drm/i915: handle FBC and self-refresh better

On 945, we need to avoid entering self-refresh if the compressor is
busy, or we may cause display FIFO underruns leading to ugly flicker.

Fixes fdo bug #24314, kernel bug #15043.

Tested-by: Alexander Lam <lambchop468@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Julien Cristau <jcristau@debian.org> (fd.o #25371)
Cc: stable@kernel.org
Signed-off-by: Eric Anholt <eric@anholt.net>

authored by Jesse Barnes and committed by Eric Anholt ee25df2b fd2e8ea5

+3
+1
drivers/gpu/drm/i915/i915_reg.h
··· 338 338 #define FBC_CTL_PERIODIC (1<<30) 339 339 #define FBC_CTL_INTERVAL_SHIFT (16) 340 340 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 341 + #define FBC_C3_IDLE (1<<13) 341 342 #define FBC_CTL_STRIDE_SHIFT (5) 342 343 #define FBC_CTL_FENCENO (1<<0) 343 344 #define FBC_COMMAND 0x0320c
+2
drivers/gpu/drm/i915/intel_display.c
··· 1031 1031 1032 1032 /* enable it... */ 1033 1033 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; 1034 + if (IS_I945GM(dev)) 1035 + fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */ 1034 1036 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; 1035 1037 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; 1036 1038 if (obj_priv->tiling_mode != I915_TILING_NONE)