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kernel
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linux
mailbox: arm_mhu: add driver for ARM MHU controller
Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
+249
+43
Documentation/devicetree/bindings/mailbox/arm-mhu.txt
+43
Documentation/devicetree/bindings/mailbox/arm-mhu.txt
···
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ARM MHU Mailbox Driver
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======================
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The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
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3 independent channels/links to communicate with remote processor(s).
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MHU links are hardwired on a platform. A link raises interrupt for any
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received data. However, there is no specified way of knowing if the sent
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data has been read by the remote. This driver assumes the sender polls
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STAT register and the remote clears it after having read the data.
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The last channel is specified to be a 'Secure' resource, hence can't be
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used by Linux running NS.
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Mailbox Device Node:
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====================
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Required properties:
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--------------------
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- compatible: Shall be "arm,mhu" & "arm,primecell"
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- reg: Contains the mailbox register address range (base
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address and length)
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- #mbox-cells Shall be 1 - the index of the channel needed.
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- interrupts: Contains the interrupt information corresponding to
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each of the 3 links of MHU.
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Example:
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--------
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mhu: mailbox@2b1f0000 {
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#mbox-cells = <1>;
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compatible = "arm,mhu", "arm,primecell";
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reg = <0 0x2b1f0000 0x1000>;
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interrupts = <0 36 4>, /* LP-NonSecure */
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<0 35 4>, /* HP-NonSecure */
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<0 37 4>; /* Secure */
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clocks = <&clock 0 2 1>;
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clock-names = "apb_pclk";
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};
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mhu_client: scb@2e000000 {
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compatible = "fujitsu,mb86s70-scb-1.0";
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reg = <0 0x2e000000 0x4000>;
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mboxes = <&mhu 1>; /* HP-NonSecure */
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};
+9
drivers/mailbox/Kconfig
+9
drivers/mailbox/Kconfig
···
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signals. Say Y if your platform supports hardware mailboxes.
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if MAILBOX
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config ARM_MHU
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tristate "ARM MHU Mailbox"
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depends on ARM_AMBA
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help
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Say Y here if you want to build the ARM MHU controller driver.
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The controller has 3 mailbox channels, the last of which can be
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used in Secure mode only.
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config PL320_MBOX
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bool "ARM PL320 Mailbox"
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depends on ARM_AMBA
+2
drivers/mailbox/Makefile
+2
drivers/mailbox/Makefile
+195
drivers/mailbox/arm_mhu.c
+195
drivers/mailbox/arm_mhu.c
···
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/*
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* Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Jassi Brar <jaswinder.singh@linaro.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/mutex.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/amba/bus.h>
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#include <linux/mailbox_controller.h>
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#define INTR_STAT_OFS 0x0
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#define INTR_SET_OFS 0x8
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#define INTR_CLR_OFS 0x10
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#define MHU_LP_OFFSET 0x0
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#define MHU_HP_OFFSET 0x20
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#define MHU_SEC_OFFSET 0x200
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#define TX_REG_OFFSET 0x100
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#define MHU_CHANS 3
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struct mhu_link {
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unsigned irq;
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void __iomem *tx_reg;
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void __iomem *rx_reg;
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};
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struct arm_mhu {
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void __iomem *base;
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struct mhu_link mlink[MHU_CHANS];
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struct mbox_chan chan[MHU_CHANS];
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struct mbox_controller mbox;
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};
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static irqreturn_t mhu_rx_interrupt(int irq, void *p)
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{
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struct mbox_chan *chan = p;
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struct mhu_link *mlink = chan->con_priv;
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u32 val;
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val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
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if (!val)
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return IRQ_NONE;
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mbox_chan_received_data(chan, (void *)&val);
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writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
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return IRQ_HANDLED;
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}
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static bool mhu_last_tx_done(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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return (val == 0);
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}
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static int mhu_send_data(struct mbox_chan *chan, void *data)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 *arg = data;
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writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
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return 0;
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}
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static int mhu_startup(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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u32 val;
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int ret;
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val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
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writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
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ret = request_irq(mlink->irq, mhu_rx_interrupt,
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IRQF_SHARED, "mhu_link", chan);
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if (ret) {
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dev_err(chan->mbox->dev,
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"Unable to aquire IRQ %d\n", mlink->irq);
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return ret;
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}
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return 0;
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}
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static void mhu_shutdown(struct mbox_chan *chan)
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{
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struct mhu_link *mlink = chan->con_priv;
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free_irq(mlink->irq, chan);
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}
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static struct mbox_chan_ops mhu_ops = {
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.send_data = mhu_send_data,
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.startup = mhu_startup,
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.shutdown = mhu_shutdown,
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.last_tx_done = mhu_last_tx_done,
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};
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static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
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{
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int i, err;
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struct arm_mhu *mhu;
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struct device *dev = &adev->dev;
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int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
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/* Allocate memory for device */
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mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
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if (!mhu)
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return -ENOMEM;
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mhu->base = devm_ioremap_resource(dev, &adev->res);
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if (IS_ERR(mhu->base)) {
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dev_err(dev, "ioremap failed\n");
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return PTR_ERR(mhu->base);
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}
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for (i = 0; i < MHU_CHANS; i++) {
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mhu->chan[i].con_priv = &mhu->mlink[i];
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mhu->mlink[i].irq = adev->irq[i];
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mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
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mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
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}
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mhu->mbox.dev = dev;
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mhu->mbox.chans = &mhu->chan[0];
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mhu->mbox.num_chans = MHU_CHANS;
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mhu->mbox.ops = &mhu_ops;
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mhu->mbox.txdone_irq = false;
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mhu->mbox.txdone_poll = true;
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mhu->mbox.txpoll_period = 10;
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amba_set_drvdata(adev, mhu);
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err = mbox_controller_register(&mhu->mbox);
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if (err) {
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dev_err(dev, "Failed to register mailboxes %d\n", err);
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return err;
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}
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dev_info(dev, "ARM MHU Mailbox registered\n");
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return 0;
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}
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static int mhu_remove(struct amba_device *adev)
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{
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struct arm_mhu *mhu = amba_get_drvdata(adev);
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mbox_controller_unregister(&mhu->mbox);
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return 0;
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}
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static struct amba_id mhu_ids[] = {
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{
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.id = 0x1bb098,
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.mask = 0xffffff,
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},
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{ 0, 0 },
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};
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MODULE_DEVICE_TABLE(amba, mhu_ids);
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static struct amba_driver arm_mhu_driver = {
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.drv = {
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.name = "mhu",
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},
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.id_table = mhu_ids,
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.probe = mhu_probe,
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.remove = mhu_remove,
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};
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module_amba_driver(arm_mhu_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("ARM MHU Driver");
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MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");