···530530 * @mc: memory controller structure holding memory informations531531 * @base: base address at which to put VRAM532532 *533533- * Function will place try to place VRAM at base address provided533533+ * Function will try to place VRAM at base address provided534534 * as parameter (which is so far either PCI aperture address or535535 * for IGP TOM base address).536536 *···557557 *558558 * Note 3: when limiting vram it's safe to overwritte real_vram_size because559559 * we are not in case where real_vram_size is inferior to mc_vram_size (ie560560- * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu560560+ * not affected by bogus hw of Novell bug 204882 + along with lots of ubuntu561561 * ones)562562 *563563 * Note 4: IGP TOM addr should be the same as the aperture addr, we don't···594594 * @rdev: radeon device structure holding all necessary informations595595 * @mc: memory controller structure holding memory informations596596 *597597- * Function will place try to place GTT before or after VRAM.597597+ * Function will try to place GTT before or after VRAM.598598 *599599 * If GTT size is bigger than space left then we ajust GTT size.600600 * Thus function will never fails.
+1-1
drivers/gpu/drm/radeon/radeon_fence.c
···840840 }841841 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);842842 rdev->fence_drv[ring].initialized = true;843843- dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx\n",843843+ dev_info(rdev->dev, "fence driver on ring %d uses gpu addr 0x%016llx\n",844844 ring, rdev->fence_drv[ring].gpu_addr);845845 return 0;846846}
+1-1
drivers/gpu/drm/radeon/si.c
···6198619861996199 if (wptr & RB_OVERFLOW) {62006200 wptr &= ~RB_OVERFLOW;62016201- /* When a ring buffer overflow happen start parsing interrupt62016201+ /* When a ring buffer overflow happens, start parsing interrupts62026202 * from the last not overwritten vector (wptr + 16). Hopefully62036203 * this should allow us to catchup.62046204 */