tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

drm/amdgpu: add header files for MP 14.0.0

This patch will add header files for MP 14.0.0.

v2: updates (Alex)

Signed-off-by: Li Ma <li.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Li Ma and committed by
Alex Deucher ed807f0c 04cef5f5

+893
+359
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_offset.h
··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * 23 + */ 24 + #ifndef _mp_14_0_0_OFFSET_HEADER 25 + #define _mp_14_0_0_OFFSET_HEADER 26 + 27 + // addressBlock: mp_SmuMp1_SmnDec 28 + // base address: 0x0 29 + #define regMP1_SMN_C2PMSG_0 0x0240 30 + #define regMP1_SMN_C2PMSG_0_BASE_IDX 0 31 + #define regMP1_SMN_C2PMSG_1 0x0241 32 + #define regMP1_SMN_C2PMSG_1_BASE_IDX 0 33 + #define regMP1_SMN_C2PMSG_2 0x0242 34 + #define regMP1_SMN_C2PMSG_2_BASE_IDX 0 35 + #define regMP1_SMN_C2PMSG_3 0x0243 36 + #define regMP1_SMN_C2PMSG_3_BASE_IDX 0 37 + #define regMP1_SMN_C2PMSG_4 0x0244 38 + #define regMP1_SMN_C2PMSG_4_BASE_IDX 0 39 + #define regMP1_SMN_C2PMSG_5 0x0245 40 + #define regMP1_SMN_C2PMSG_5_BASE_IDX 0 41 + #define regMP1_SMN_C2PMSG_6 0x0246 42 + #define regMP1_SMN_C2PMSG_6_BASE_IDX 0 43 + #define regMP1_SMN_C2PMSG_7 0x0247 44 + #define regMP1_SMN_C2PMSG_7_BASE_IDX 0 45 + #define regMP1_SMN_C2PMSG_8 0x0248 46 + #define regMP1_SMN_C2PMSG_8_BASE_IDX 0 47 + #define regMP1_SMN_C2PMSG_9 0x0249 48 + #define regMP1_SMN_C2PMSG_9_BASE_IDX 0 49 + #define regMP1_SMN_C2PMSG_10 0x024a 50 + #define regMP1_SMN_C2PMSG_10_BASE_IDX 0 51 + #define regMP1_SMN_C2PMSG_11 0x024b 52 + #define regMP1_SMN_C2PMSG_11_BASE_IDX 0 53 + #define regMP1_SMN_C2PMSG_12 0x024c 54 + #define regMP1_SMN_C2PMSG_12_BASE_IDX 0 55 + #define regMP1_SMN_C2PMSG_13 0x024d 56 + #define regMP1_SMN_C2PMSG_13_BASE_IDX 0 57 + #define regMP1_SMN_C2PMSG_14 0x024e 58 + #define regMP1_SMN_C2PMSG_14_BASE_IDX 0 59 + #define regMP1_SMN_C2PMSG_15 0x024f 60 + #define regMP1_SMN_C2PMSG_15_BASE_IDX 0 61 + #define regMP1_SMN_C2PMSG_16 0x0250 62 + #define regMP1_SMN_C2PMSG_16_BASE_IDX 0 63 + #define regMP1_SMN_C2PMSG_17 0x0251 64 + #define regMP1_SMN_C2PMSG_17_BASE_IDX 0 65 + #define regMP1_SMN_C2PMSG_18 0x0252 66 + #define regMP1_SMN_C2PMSG_18_BASE_IDX 0 67 + #define regMP1_SMN_C2PMSG_19 0x0253 68 + #define regMP1_SMN_C2PMSG_19_BASE_IDX 0 69 + #define regMP1_SMN_C2PMSG_20 0x0254 70 + #define regMP1_SMN_C2PMSG_20_BASE_IDX 0 71 + #define regMP1_SMN_C2PMSG_21 0x0255 72 + #define regMP1_SMN_C2PMSG_21_BASE_IDX 0 73 + #define regMP1_SMN_C2PMSG_22 0x0256 74 + #define regMP1_SMN_C2PMSG_22_BASE_IDX 0 75 + #define regMP1_SMN_C2PMSG_23 0x0257 76 + #define regMP1_SMN_C2PMSG_23_BASE_IDX 0 77 + #define regMP1_SMN_C2PMSG_24 0x0258 78 + #define regMP1_SMN_C2PMSG_24_BASE_IDX 0 79 + #define regMP1_SMN_C2PMSG_25 0x0259 80 + #define regMP1_SMN_C2PMSG_25_BASE_IDX 0 81 + #define regMP1_SMN_C2PMSG_26 0x025a 82 + #define regMP1_SMN_C2PMSG_26_BASE_IDX 0 83 + #define regMP1_SMN_C2PMSG_27 0x025b 84 + #define regMP1_SMN_C2PMSG_27_BASE_IDX 0 85 + #define regMP1_SMN_C2PMSG_28 0x025c 86 + #define regMP1_SMN_C2PMSG_28_BASE_IDX 0 87 + #define regMP1_SMN_C2PMSG_29 0x025d 88 + #define regMP1_SMN_C2PMSG_29_BASE_IDX 0 89 + #define regMP1_SMN_C2PMSG_30 0x025e 90 + #define regMP1_SMN_C2PMSG_30_BASE_IDX 0 91 + #define regMP1_SMN_C2PMSG_31 0x025f 92 + #define regMP1_SMN_C2PMSG_31_BASE_IDX 0 93 + #define regMP1_SMN_C2PMSG_32 0x0260 94 + #define regMP1_SMN_C2PMSG_32_BASE_IDX 0 95 + #define regMP1_SMN_C2PMSG_33 0x0261 96 + #define regMP1_SMN_C2PMSG_33_BASE_IDX 0 97 + #define regMP1_SMN_C2PMSG_34 0x0262 98 + #define regMP1_SMN_C2PMSG_34_BASE_IDX 0 99 + #define regMP1_SMN_C2PMSG_35 0x0263 100 + #define regMP1_SMN_C2PMSG_35_BASE_IDX 0 101 + #define regMP1_SMN_C2PMSG_36 0x0264 102 + #define regMP1_SMN_C2PMSG_36_BASE_IDX 0 103 + #define regMP1_SMN_C2PMSG_37 0x0265 104 + #define regMP1_SMN_C2PMSG_37_BASE_IDX 0 105 + #define regMP1_SMN_C2PMSG_38 0x0266 106 + #define regMP1_SMN_C2PMSG_38_BASE_IDX 0 107 + #define regMP1_SMN_C2PMSG_39 0x0267 108 + #define regMP1_SMN_C2PMSG_39_BASE_IDX 0 109 + #define regMP1_SMN_C2PMSG_40 0x0268 110 + #define regMP1_SMN_C2PMSG_40_BASE_IDX 0 111 + #define regMP1_SMN_C2PMSG_41 0x0269 112 + #define regMP1_SMN_C2PMSG_41_BASE_IDX 0 113 + #define regMP1_SMN_C2PMSG_42 0x026a 114 + #define regMP1_SMN_C2PMSG_42_BASE_IDX 0 115 + #define regMP1_SMN_C2PMSG_43 0x026b 116 + #define regMP1_SMN_C2PMSG_43_BASE_IDX 0 117 + #define regMP1_SMN_C2PMSG_44 0x026c 118 + #define regMP1_SMN_C2PMSG_44_BASE_IDX 0 119 + #define regMP1_SMN_C2PMSG_45 0x026d 120 + #define regMP1_SMN_C2PMSG_45_BASE_IDX 0 121 + #define regMP1_SMN_C2PMSG_46 0x026e 122 + #define regMP1_SMN_C2PMSG_46_BASE_IDX 0 123 + #define regMP1_SMN_C2PMSG_47 0x026f 124 + #define regMP1_SMN_C2PMSG_47_BASE_IDX 0 125 + #define regMP1_SMN_C2PMSG_48 0x0270 126 + #define regMP1_SMN_C2PMSG_48_BASE_IDX 0 127 + #define regMP1_SMN_C2PMSG_49 0x0271 128 + #define regMP1_SMN_C2PMSG_49_BASE_IDX 0 129 + #define regMP1_SMN_C2PMSG_50 0x0272 130 + #define regMP1_SMN_C2PMSG_50_BASE_IDX 0 131 + #define regMP1_SMN_C2PMSG_51 0x0273 132 + #define regMP1_SMN_C2PMSG_51_BASE_IDX 0 133 + #define regMP1_SMN_C2PMSG_52 0x0274 134 + #define regMP1_SMN_C2PMSG_52_BASE_IDX 0 135 + #define regMP1_SMN_C2PMSG_53 0x0275 136 + #define regMP1_SMN_C2PMSG_53_BASE_IDX 0 137 + #define regMP1_SMN_C2PMSG_54 0x0276 138 + #define regMP1_SMN_C2PMSG_54_BASE_IDX 0 139 + #define regMP1_SMN_C2PMSG_55 0x0277 140 + #define regMP1_SMN_C2PMSG_55_BASE_IDX 0 141 + #define regMP1_SMN_C2PMSG_56 0x0278 142 + #define regMP1_SMN_C2PMSG_56_BASE_IDX 0 143 + #define regMP1_SMN_C2PMSG_57 0x0279 144 + #define regMP1_SMN_C2PMSG_57_BASE_IDX 0 145 + #define regMP1_SMN_C2PMSG_58 0x027a 146 + #define regMP1_SMN_C2PMSG_58_BASE_IDX 0 147 + #define regMP1_SMN_C2PMSG_59 0x027b 148 + #define regMP1_SMN_C2PMSG_59_BASE_IDX 0 149 + #define regMP1_SMN_C2PMSG_60 0x027c 150 + #define regMP1_SMN_C2PMSG_60_BASE_IDX 0 151 + #define regMP1_SMN_C2PMSG_61 0x027d 152 + #define regMP1_SMN_C2PMSG_61_BASE_IDX 0 153 + #define regMP1_SMN_C2PMSG_62 0x027e 154 + #define regMP1_SMN_C2PMSG_62_BASE_IDX 0 155 + #define regMP1_SMN_C2PMSG_63 0x027f 156 + #define regMP1_SMN_C2PMSG_63_BASE_IDX 0 157 + #define regMP1_SMN_C2PMSG_64 0x0280 158 + #define regMP1_SMN_C2PMSG_64_BASE_IDX 0 159 + #define regMP1_SMN_C2PMSG_65 0x0281 160 + #define regMP1_SMN_C2PMSG_65_BASE_IDX 0 161 + #define regMP1_SMN_C2PMSG_66 0x0282 162 + #define regMP1_SMN_C2PMSG_66_BASE_IDX 0 163 + #define regMP1_SMN_C2PMSG_67 0x0283 164 + #define regMP1_SMN_C2PMSG_67_BASE_IDX 0 165 + #define regMP1_SMN_C2PMSG_68 0x0284 166 + #define regMP1_SMN_C2PMSG_68_BASE_IDX 0 167 + #define regMP1_SMN_C2PMSG_69 0x0285 168 + #define regMP1_SMN_C2PMSG_69_BASE_IDX 0 169 + #define regMP1_SMN_C2PMSG_70 0x0286 170 + #define regMP1_SMN_C2PMSG_70_BASE_IDX 0 171 + #define regMP1_SMN_C2PMSG_71 0x0287 172 + #define regMP1_SMN_C2PMSG_71_BASE_IDX 0 173 + #define regMP1_SMN_C2PMSG_72 0x0288 174 + #define regMP1_SMN_C2PMSG_72_BASE_IDX 0 175 + #define regMP1_SMN_C2PMSG_73 0x0289 176 + #define regMP1_SMN_C2PMSG_73_BASE_IDX 0 177 + #define regMP1_SMN_C2PMSG_74 0x028a 178 + #define regMP1_SMN_C2PMSG_74_BASE_IDX 0 179 + #define regMP1_SMN_C2PMSG_75 0x028b 180 + #define regMP1_SMN_C2PMSG_75_BASE_IDX 0 181 + #define regMP1_SMN_C2PMSG_76 0x028c 182 + #define regMP1_SMN_C2PMSG_76_BASE_IDX 0 183 + #define regMP1_SMN_C2PMSG_77 0x028d 184 + #define regMP1_SMN_C2PMSG_77_BASE_IDX 0 185 + #define regMP1_SMN_C2PMSG_78 0x028e 186 + #define regMP1_SMN_C2PMSG_78_BASE_IDX 0 187 + #define regMP1_SMN_C2PMSG_79 0x028f 188 + #define regMP1_SMN_C2PMSG_79_BASE_IDX 0 189 + #define regMP1_SMN_C2PMSG_80 0x0290 190 + #define regMP1_SMN_C2PMSG_80_BASE_IDX 0 191 + #define regMP1_SMN_C2PMSG_81 0x0291 192 + #define regMP1_SMN_C2PMSG_81_BASE_IDX 0 193 + #define regMP1_SMN_C2PMSG_82 0x0292 194 + #define regMP1_SMN_C2PMSG_82_BASE_IDX 0 195 + #define regMP1_SMN_C2PMSG_83 0x0293 196 + #define regMP1_SMN_C2PMSG_83_BASE_IDX 0 197 + #define regMP1_SMN_C2PMSG_84 0x0294 198 + #define regMP1_SMN_C2PMSG_84_BASE_IDX 0 199 + #define regMP1_SMN_C2PMSG_85 0x0295 200 + #define regMP1_SMN_C2PMSG_85_BASE_IDX 0 201 + #define regMP1_SMN_C2PMSG_86 0x0296 202 + #define regMP1_SMN_C2PMSG_86_BASE_IDX 0 203 + #define regMP1_SMN_C2PMSG_87 0x0297 204 + #define regMP1_SMN_C2PMSG_87_BASE_IDX 0 205 + #define regMP1_SMN_C2PMSG_88 0x0298 206 + #define regMP1_SMN_C2PMSG_88_BASE_IDX 0 207 + #define regMP1_SMN_C2PMSG_89 0x0299 208 + #define regMP1_SMN_C2PMSG_89_BASE_IDX 0 209 + #define regMP1_SMN_C2PMSG_90 0x029a 210 + #define regMP1_SMN_C2PMSG_90_BASE_IDX 0 211 + #define regMP1_SMN_C2PMSG_91 0x029b 212 + #define regMP1_SMN_C2PMSG_91_BASE_IDX 0 213 + #define regMP1_SMN_C2PMSG_92 0x029c 214 + #define regMP1_SMN_C2PMSG_92_BASE_IDX 0 215 + #define regMP1_SMN_C2PMSG_93 0x029d 216 + #define regMP1_SMN_C2PMSG_93_BASE_IDX 0 217 + #define regMP1_SMN_C2PMSG_94 0x029e 218 + #define regMP1_SMN_C2PMSG_94_BASE_IDX 0 219 + #define regMP1_SMN_C2PMSG_95 0x029f 220 + #define regMP1_SMN_C2PMSG_95_BASE_IDX 0 221 + #define regMP1_SMN_C2PMSG_96 0x02a0 222 + #define regMP1_SMN_C2PMSG_96_BASE_IDX 0 223 + #define regMP1_SMN_C2PMSG_97 0x02a1 224 + #define regMP1_SMN_C2PMSG_97_BASE_IDX 0 225 + #define regMP1_SMN_C2PMSG_98 0x02a2 226 + #define regMP1_SMN_C2PMSG_98_BASE_IDX 0 227 + #define regMP1_SMN_C2PMSG_99 0x02a3 228 + #define regMP1_SMN_C2PMSG_99_BASE_IDX 0 229 + #define regMP1_SMN_C2PMSG_100 0x02a4 230 + #define regMP1_SMN_C2PMSG_100_BASE_IDX 0 231 + #define regMP1_SMN_C2PMSG_101 0x02a5 232 + #define regMP1_SMN_C2PMSG_101_BASE_IDX 0 233 + #define regMP1_SMN_C2PMSG_102 0x02a6 234 + #define regMP1_SMN_C2PMSG_102_BASE_IDX 0 235 + #define regMP1_SMN_C2PMSG_103 0x02a7 236 + #define regMP1_SMN_C2PMSG_103_BASE_IDX 0 237 + #define regMP1_SMN_C2PMSG_104 0x02a8 238 + #define regMP1_SMN_C2PMSG_104_BASE_IDX 0 239 + #define regMP1_SMN_C2PMSG_105 0x02a9 240 + #define regMP1_SMN_C2PMSG_105_BASE_IDX 0 241 + #define regMP1_SMN_C2PMSG_106 0x02aa 242 + #define regMP1_SMN_C2PMSG_106_BASE_IDX 0 243 + #define regMP1_SMN_C2PMSG_107 0x02ab 244 + #define regMP1_SMN_C2PMSG_107_BASE_IDX 0 245 + #define regMP1_SMN_C2PMSG_108 0x02ac 246 + #define regMP1_SMN_C2PMSG_108_BASE_IDX 0 247 + #define regMP1_SMN_C2PMSG_109 0x02ad 248 + #define regMP1_SMN_C2PMSG_109_BASE_IDX 0 249 + #define regMP1_SMN_C2PMSG_110 0x02ae 250 + #define regMP1_SMN_C2PMSG_110_BASE_IDX 0 251 + #define regMP1_SMN_C2PMSG_111 0x02af 252 + #define regMP1_SMN_C2PMSG_111_BASE_IDX 0 253 + #define regMP1_SMN_C2PMSG_112 0x02b0 254 + #define regMP1_SMN_C2PMSG_112_BASE_IDX 0 255 + #define regMP1_SMN_C2PMSG_113 0x02b1 256 + #define regMP1_SMN_C2PMSG_113_BASE_IDX 0 257 + #define regMP1_SMN_C2PMSG_114 0x02b2 258 + #define regMP1_SMN_C2PMSG_114_BASE_IDX 0 259 + #define regMP1_SMN_C2PMSG_115 0x02b3 260 + #define regMP1_SMN_C2PMSG_115_BASE_IDX 0 261 + #define regMP1_SMN_C2PMSG_116 0x02b4 262 + #define regMP1_SMN_C2PMSG_116_BASE_IDX 0 263 + #define regMP1_SMN_C2PMSG_117 0x02b5 264 + #define regMP1_SMN_C2PMSG_117_BASE_IDX 0 265 + #define regMP1_SMN_C2PMSG_118 0x02b6 266 + #define regMP1_SMN_C2PMSG_118_BASE_IDX 0 267 + #define regMP1_SMN_C2PMSG_119 0x02b7 268 + #define regMP1_SMN_C2PMSG_119_BASE_IDX 0 269 + #define regMP1_SMN_C2PMSG_120 0x02b8 270 + #define regMP1_SMN_C2PMSG_120_BASE_IDX 0 271 + #define regMP1_SMN_C2PMSG_121 0x02b9 272 + #define regMP1_SMN_C2PMSG_121_BASE_IDX 0 273 + #define regMP1_SMN_C2PMSG_122 0x02ba 274 + #define regMP1_SMN_C2PMSG_122_BASE_IDX 0 275 + #define regMP1_SMN_C2PMSG_123 0x02bb 276 + #define regMP1_SMN_C2PMSG_123_BASE_IDX 0 277 + #define regMP1_SMN_C2PMSG_124 0x02bc 278 + #define regMP1_SMN_C2PMSG_124_BASE_IDX 0 279 + #define regMP1_SMN_C2PMSG_125 0x02bd 280 + #define regMP1_SMN_C2PMSG_125_BASE_IDX 0 281 + #define regMP1_SMN_C2PMSG_126 0x02be 282 + #define regMP1_SMN_C2PMSG_126_BASE_IDX 0 283 + #define regMP1_SMN_C2PMSG_127 0x02bf 284 + #define regMP1_SMN_C2PMSG_127_BASE_IDX 0 285 + #define regMP1_SMN_IH_CREDIT 0x0340 286 + #define regMP1_SMN_IH_CREDIT_BASE_IDX 0 287 + #define regMP1_SMN_IH_SW_INT 0x0341 288 + #define regMP1_SMN_IH_SW_INT_BASE_IDX 0 289 + #define regMP1_SMN_IH_SW_INT_CTRL 0x0342 290 + #define regMP1_SMN_IH_SW_INT_CTRL_BASE_IDX 0 291 + #define regMP1_SMN_FPS_CNT 0x0343 292 + #define regMP1_SMN_FPS_CNT_BASE_IDX 0 293 + #define regMP1_SMN_EXT_SCRATCH0 0x03c0 294 + #define regMP1_SMN_EXT_SCRATCH0_BASE_IDX 0 295 + #define regMP1_SMN_EXT_SCRATCH1 0x03c1 296 + #define regMP1_SMN_EXT_SCRATCH1_BASE_IDX 0 297 + #define regMP1_SMN_EXT_SCRATCH2 0x03c2 298 + #define regMP1_SMN_EXT_SCRATCH2_BASE_IDX 0 299 + #define regMP1_SMN_EXT_SCRATCH3 0x03c3 300 + #define regMP1_SMN_EXT_SCRATCH3_BASE_IDX 0 301 + #define regMP1_SMN_EXT_SCRATCH4 0x03c4 302 + #define regMP1_SMN_EXT_SCRATCH4_BASE_IDX 0 303 + #define regMP1_SMN_EXT_SCRATCH5 0x03c5 304 + #define regMP1_SMN_EXT_SCRATCH5_BASE_IDX 0 305 + #define regMP1_SMN_EXT_SCRATCH6 0x03c6 306 + #define regMP1_SMN_EXT_SCRATCH6_BASE_IDX 0 307 + #define regMP1_SMN_EXT_SCRATCH7 0x03c7 308 + #define regMP1_SMN_EXT_SCRATCH7_BASE_IDX 0 309 + #define regMP1_SMN_EXT_SCRATCH8 0x03c8 310 + #define regMP1_SMN_EXT_SCRATCH8_BASE_IDX 0 311 + #define regMP1_SMN_EXT_SCRATCH9 0x03c9 312 + #define regMP1_SMN_EXT_SCRATCH9_BASE_IDX 0 313 + #define regMP1_SMN_EXT_SCRATCH10 0x03ca 314 + #define regMP1_SMN_EXT_SCRATCH10_BASE_IDX 0 315 + #define regMP1_SMN_EXT_SCRATCH11 0x03cb 316 + #define regMP1_SMN_EXT_SCRATCH11_BASE_IDX 0 317 + #define regMP1_SMN_EXT_SCRATCH12 0x03cc 318 + #define regMP1_SMN_EXT_SCRATCH12_BASE_IDX 0 319 + #define regMP1_SMN_EXT_SCRATCH13 0x03cd 320 + #define regMP1_SMN_EXT_SCRATCH13_BASE_IDX 0 321 + #define regMP1_SMN_EXT_SCRATCH14 0x03ce 322 + #define regMP1_SMN_EXT_SCRATCH14_BASE_IDX 0 323 + #define regMP1_SMN_EXT_SCRATCH15 0x03cf 324 + #define regMP1_SMN_EXT_SCRATCH15_BASE_IDX 0 325 + #define regMP1_SMN_EXT_SCRATCH16 0x03d0 326 + #define regMP1_SMN_EXT_SCRATCH16_BASE_IDX 0 327 + #define regMP1_SMN_EXT_SCRATCH17 0x03d1 328 + #define regMP1_SMN_EXT_SCRATCH17_BASE_IDX 0 329 + #define regMP1_SMN_EXT_SCRATCH18 0x03d2 330 + #define regMP1_SMN_EXT_SCRATCH18_BASE_IDX 0 331 + #define regMP1_SMN_EXT_SCRATCH19 0x03d3 332 + #define regMP1_SMN_EXT_SCRATCH19_BASE_IDX 0 333 + #define regMP1_SMN_EXT_SCRATCH20 0x03d4 334 + #define regMP1_SMN_EXT_SCRATCH20_BASE_IDX 0 335 + #define regMP1_SMN_EXT_SCRATCH21 0x03d5 336 + #define regMP1_SMN_EXT_SCRATCH21_BASE_IDX 0 337 + #define regMP1_SMN_EXT_SCRATCH22 0x03d6 338 + #define regMP1_SMN_EXT_SCRATCH22_BASE_IDX 0 339 + #define regMP1_SMN_EXT_SCRATCH23 0x03d7 340 + #define regMP1_SMN_EXT_SCRATCH23_BASE_IDX 0 341 + #define regMP1_SMN_EXT_SCRATCH24 0x03d8 342 + #define regMP1_SMN_EXT_SCRATCH24_BASE_IDX 0 343 + #define regMP1_SMN_EXT_SCRATCH25 0x03d9 344 + #define regMP1_SMN_EXT_SCRATCH25_BASE_IDX 0 345 + #define regMP1_SMN_EXT_SCRATCH26 0x03da 346 + #define regMP1_SMN_EXT_SCRATCH26_BASE_IDX 0 347 + #define regMP1_SMN_EXT_SCRATCH27 0x03db 348 + #define regMP1_SMN_EXT_SCRATCH27_BASE_IDX 0 349 + #define regMP1_SMN_EXT_SCRATCH28 0x03dc 350 + #define regMP1_SMN_EXT_SCRATCH28_BASE_IDX 0 351 + #define regMP1_SMN_EXT_SCRATCH29 0x03dd 352 + #define regMP1_SMN_EXT_SCRATCH29_BASE_IDX 0 353 + #define regMP1_SMN_EXT_SCRATCH30 0x03de 354 + #define regMP1_SMN_EXT_SCRATCH30_BASE_IDX 0 355 + #define regMP1_SMN_EXT_SCRATCH31 0x03df 356 + #define regMP1_SMN_EXT_SCRATCH31_BASE_IDX 0 357 + 358 + 359 + #endif
+534
drivers/gpu/drm/amd/include/asic_reg/mp/mp_14_0_0_sh_mask.h
··· 1 + /* 2 + * Copyright 2023 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + */ 23 + #ifndef _mp_14_0_0_SH_MASK_HEADER 24 + #define _mp_14_0_0_SH_MASK_HEADER 25 + 26 + // addressBlock: mp_SmuMp1Pub_CruDec 27 + //MP1_CRU1_MP1_FIRMWARE_FLAGS 28 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 29 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 30 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L 31 + #define MP1_CRU1_MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL 32 + 33 + 34 + // addressBlock: mp_SmuMp1_SmnDec 35 + //MP1_SMN_C2PMSG_0 36 + #define MP1_SMN_C2PMSG_0__CONTENT__SHIFT 0x0 37 + #define MP1_SMN_C2PMSG_0__CONTENT_MASK 0xFFFFFFFFL 38 + //MP1_SMN_C2PMSG_1 39 + #define MP1_SMN_C2PMSG_1__CONTENT__SHIFT 0x0 40 + #define MP1_SMN_C2PMSG_1__CONTENT_MASK 0xFFFFFFFFL 41 + //MP1_SMN_C2PMSG_2 42 + #define MP1_SMN_C2PMSG_2__CONTENT__SHIFT 0x0 43 + #define MP1_SMN_C2PMSG_2__CONTENT_MASK 0xFFFFFFFFL 44 + //MP1_SMN_C2PMSG_3 45 + #define MP1_SMN_C2PMSG_3__CONTENT__SHIFT 0x0 46 + #define MP1_SMN_C2PMSG_3__CONTENT_MASK 0xFFFFFFFFL 47 + //MP1_SMN_C2PMSG_4 48 + #define MP1_SMN_C2PMSG_4__CONTENT__SHIFT 0x0 49 + #define MP1_SMN_C2PMSG_4__CONTENT_MASK 0xFFFFFFFFL 50 + //MP1_SMN_C2PMSG_5 51 + #define MP1_SMN_C2PMSG_5__CONTENT__SHIFT 0x0 52 + #define MP1_SMN_C2PMSG_5__CONTENT_MASK 0xFFFFFFFFL 53 + //MP1_SMN_C2PMSG_6 54 + #define MP1_SMN_C2PMSG_6__CONTENT__SHIFT 0x0 55 + #define MP1_SMN_C2PMSG_6__CONTENT_MASK 0xFFFFFFFFL 56 + //MP1_SMN_C2PMSG_7 57 + #define MP1_SMN_C2PMSG_7__CONTENT__SHIFT 0x0 58 + #define MP1_SMN_C2PMSG_7__CONTENT_MASK 0xFFFFFFFFL 59 + //MP1_SMN_C2PMSG_8 60 + #define MP1_SMN_C2PMSG_8__CONTENT__SHIFT 0x0 61 + #define MP1_SMN_C2PMSG_8__CONTENT_MASK 0xFFFFFFFFL 62 + //MP1_SMN_C2PMSG_9 63 + #define MP1_SMN_C2PMSG_9__CONTENT__SHIFT 0x0 64 + #define MP1_SMN_C2PMSG_9__CONTENT_MASK 0xFFFFFFFFL 65 + //MP1_SMN_C2PMSG_10 66 + #define MP1_SMN_C2PMSG_10__CONTENT__SHIFT 0x0 67 + #define MP1_SMN_C2PMSG_10__CONTENT_MASK 0xFFFFFFFFL 68 + //MP1_SMN_C2PMSG_11 69 + #define MP1_SMN_C2PMSG_11__CONTENT__SHIFT 0x0 70 + #define MP1_SMN_C2PMSG_11__CONTENT_MASK 0xFFFFFFFFL 71 + //MP1_SMN_C2PMSG_12 72 + #define MP1_SMN_C2PMSG_12__CONTENT__SHIFT 0x0 73 + #define MP1_SMN_C2PMSG_12__CONTENT_MASK 0xFFFFFFFFL 74 + //MP1_SMN_C2PMSG_13 75 + #define MP1_SMN_C2PMSG_13__CONTENT__SHIFT 0x0 76 + #define MP1_SMN_C2PMSG_13__CONTENT_MASK 0xFFFFFFFFL 77 + //MP1_SMN_C2PMSG_14 78 + #define MP1_SMN_C2PMSG_14__CONTENT__SHIFT 0x0 79 + #define MP1_SMN_C2PMSG_14__CONTENT_MASK 0xFFFFFFFFL 80 + //MP1_SMN_C2PMSG_15 81 + #define MP1_SMN_C2PMSG_15__CONTENT__SHIFT 0x0 82 + #define MP1_SMN_C2PMSG_15__CONTENT_MASK 0xFFFFFFFFL 83 + //MP1_SMN_C2PMSG_16 84 + #define MP1_SMN_C2PMSG_16__CONTENT__SHIFT 0x0 85 + #define MP1_SMN_C2PMSG_16__CONTENT_MASK 0xFFFFFFFFL 86 + //MP1_SMN_C2PMSG_17 87 + #define MP1_SMN_C2PMSG_17__CONTENT__SHIFT 0x0 88 + #define MP1_SMN_C2PMSG_17__CONTENT_MASK 0xFFFFFFFFL 89 + //MP1_SMN_C2PMSG_18 90 + #define MP1_SMN_C2PMSG_18__CONTENT__SHIFT 0x0 91 + #define MP1_SMN_C2PMSG_18__CONTENT_MASK 0xFFFFFFFFL 92 + //MP1_SMN_C2PMSG_19 93 + #define MP1_SMN_C2PMSG_19__CONTENT__SHIFT 0x0 94 + #define MP1_SMN_C2PMSG_19__CONTENT_MASK 0xFFFFFFFFL 95 + //MP1_SMN_C2PMSG_20 96 + #define MP1_SMN_C2PMSG_20__CONTENT__SHIFT 0x0 97 + #define MP1_SMN_C2PMSG_20__CONTENT_MASK 0xFFFFFFFFL 98 + //MP1_SMN_C2PMSG_21 99 + #define MP1_SMN_C2PMSG_21__CONTENT__SHIFT 0x0 100 + #define MP1_SMN_C2PMSG_21__CONTENT_MASK 0xFFFFFFFFL 101 + //MP1_SMN_C2PMSG_22 102 + #define MP1_SMN_C2PMSG_22__CONTENT__SHIFT 0x0 103 + #define MP1_SMN_C2PMSG_22__CONTENT_MASK 0xFFFFFFFFL 104 + //MP1_SMN_C2PMSG_23 105 + #define MP1_SMN_C2PMSG_23__CONTENT__SHIFT 0x0 106 + #define MP1_SMN_C2PMSG_23__CONTENT_MASK 0xFFFFFFFFL 107 + //MP1_SMN_C2PMSG_24 108 + #define MP1_SMN_C2PMSG_24__CONTENT__SHIFT 0x0 109 + #define MP1_SMN_C2PMSG_24__CONTENT_MASK 0xFFFFFFFFL 110 + //MP1_SMN_C2PMSG_25 111 + #define MP1_SMN_C2PMSG_25__CONTENT__SHIFT 0x0 112 + #define MP1_SMN_C2PMSG_25__CONTENT_MASK 0xFFFFFFFFL 113 + //MP1_SMN_C2PMSG_26 114 + #define MP1_SMN_C2PMSG_26__CONTENT__SHIFT 0x0 115 + #define MP1_SMN_C2PMSG_26__CONTENT_MASK 0xFFFFFFFFL 116 + //MP1_SMN_C2PMSG_27 117 + #define MP1_SMN_C2PMSG_27__CONTENT__SHIFT 0x0 118 + #define MP1_SMN_C2PMSG_27__CONTENT_MASK 0xFFFFFFFFL 119 + //MP1_SMN_C2PMSG_28 120 + #define MP1_SMN_C2PMSG_28__CONTENT__SHIFT 0x0 121 + #define MP1_SMN_C2PMSG_28__CONTENT_MASK 0xFFFFFFFFL 122 + //MP1_SMN_C2PMSG_29 123 + #define MP1_SMN_C2PMSG_29__CONTENT__SHIFT 0x0 124 + #define MP1_SMN_C2PMSG_29__CONTENT_MASK 0xFFFFFFFFL 125 + //MP1_SMN_C2PMSG_30 126 + #define MP1_SMN_C2PMSG_30__CONTENT__SHIFT 0x0 127 + #define MP1_SMN_C2PMSG_30__CONTENT_MASK 0xFFFFFFFFL 128 + //MP1_SMN_C2PMSG_31 129 + #define MP1_SMN_C2PMSG_31__CONTENT__SHIFT 0x0 130 + #define MP1_SMN_C2PMSG_31__CONTENT_MASK 0xFFFFFFFFL 131 + //MP1_SMN_C2PMSG_32 132 + #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 133 + #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL 134 + //MP1_SMN_C2PMSG_33 135 + #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 136 + #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL 137 + //MP1_SMN_C2PMSG_34 138 + #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 139 + #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL 140 + //MP1_SMN_C2PMSG_35 141 + #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 142 + #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL 143 + //MP1_SMN_C2PMSG_36 144 + #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 145 + #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL 146 + //MP1_SMN_C2PMSG_37 147 + #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 148 + #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL 149 + //MP1_SMN_C2PMSG_38 150 + #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 151 + #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL 152 + //MP1_SMN_C2PMSG_39 153 + #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 154 + #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL 155 + //MP1_SMN_C2PMSG_40 156 + #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 157 + #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL 158 + //MP1_SMN_C2PMSG_41 159 + #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 160 + #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL 161 + //MP1_SMN_C2PMSG_42 162 + #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 163 + #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL 164 + //MP1_SMN_C2PMSG_43 165 + #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 166 + #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL 167 + //MP1_SMN_C2PMSG_44 168 + #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 169 + #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL 170 + //MP1_SMN_C2PMSG_45 171 + #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 172 + #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL 173 + //MP1_SMN_C2PMSG_46 174 + #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 175 + #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL 176 + //MP1_SMN_C2PMSG_47 177 + #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 178 + #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL 179 + //MP1_SMN_C2PMSG_48 180 + #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 181 + #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL 182 + //MP1_SMN_C2PMSG_49 183 + #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 184 + #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL 185 + //MP1_SMN_C2PMSG_50 186 + #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 187 + #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL 188 + //MP1_SMN_C2PMSG_51 189 + #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 190 + #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL 191 + //MP1_SMN_C2PMSG_52 192 + #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 193 + #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL 194 + //MP1_SMN_C2PMSG_53 195 + #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 196 + #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL 197 + //MP1_SMN_C2PMSG_54 198 + #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 199 + #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL 200 + //MP1_SMN_C2PMSG_55 201 + #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 202 + #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL 203 + //MP1_SMN_C2PMSG_56 204 + #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 205 + #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL 206 + //MP1_SMN_C2PMSG_57 207 + #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 208 + #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL 209 + //MP1_SMN_C2PMSG_58 210 + #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 211 + #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL 212 + //MP1_SMN_C2PMSG_59 213 + #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 214 + #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL 215 + //MP1_SMN_C2PMSG_60 216 + #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 217 + #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL 218 + //MP1_SMN_C2PMSG_61 219 + #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 220 + #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL 221 + //MP1_SMN_C2PMSG_62 222 + #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 223 + #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL 224 + //MP1_SMN_C2PMSG_63 225 + #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 226 + #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL 227 + //MP1_SMN_C2PMSG_64 228 + #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 229 + #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL 230 + //MP1_SMN_C2PMSG_65 231 + #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 232 + #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL 233 + //MP1_SMN_C2PMSG_66 234 + #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 235 + #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL 236 + //MP1_SMN_C2PMSG_67 237 + #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 238 + #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL 239 + //MP1_SMN_C2PMSG_68 240 + #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 241 + #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL 242 + //MP1_SMN_C2PMSG_69 243 + #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 244 + #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL 245 + //MP1_SMN_C2PMSG_70 246 + #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 247 + #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL 248 + //MP1_SMN_C2PMSG_71 249 + #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 250 + #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL 251 + //MP1_SMN_C2PMSG_72 252 + #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 253 + #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL 254 + //MP1_SMN_C2PMSG_73 255 + #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 256 + #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL 257 + //MP1_SMN_C2PMSG_74 258 + #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 259 + #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL 260 + //MP1_SMN_C2PMSG_75 261 + #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 262 + #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL 263 + //MP1_SMN_C2PMSG_76 264 + #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 265 + #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL 266 + //MP1_SMN_C2PMSG_77 267 + #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 268 + #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL 269 + //MP1_SMN_C2PMSG_78 270 + #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 271 + #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL 272 + //MP1_SMN_C2PMSG_79 273 + #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 274 + #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL 275 + //MP1_SMN_C2PMSG_80 276 + #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 277 + #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL 278 + //MP1_SMN_C2PMSG_81 279 + #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 280 + #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL 281 + //MP1_SMN_C2PMSG_82 282 + #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 283 + #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL 284 + //MP1_SMN_C2PMSG_83 285 + #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 286 + #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL 287 + //MP1_SMN_C2PMSG_84 288 + #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 289 + #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL 290 + //MP1_SMN_C2PMSG_85 291 + #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 292 + #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL 293 + //MP1_SMN_C2PMSG_86 294 + #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 295 + #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL 296 + //MP1_SMN_C2PMSG_87 297 + #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 298 + #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL 299 + //MP1_SMN_C2PMSG_88 300 + #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 301 + #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL 302 + //MP1_SMN_C2PMSG_89 303 + #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 304 + #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL 305 + //MP1_SMN_C2PMSG_90 306 + #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 307 + #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL 308 + //MP1_SMN_C2PMSG_91 309 + #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 310 + #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL 311 + //MP1_SMN_C2PMSG_92 312 + #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 313 + #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL 314 + //MP1_SMN_C2PMSG_93 315 + #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 316 + #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL 317 + //MP1_SMN_C2PMSG_94 318 + #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 319 + #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL 320 + //MP1_SMN_C2PMSG_95 321 + #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 322 + #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL 323 + //MP1_SMN_C2PMSG_96 324 + #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 325 + #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL 326 + //MP1_SMN_C2PMSG_97 327 + #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 328 + #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL 329 + //MP1_SMN_C2PMSG_98 330 + #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 331 + #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL 332 + //MP1_SMN_C2PMSG_99 333 + #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 334 + #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL 335 + //MP1_SMN_C2PMSG_100 336 + #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 337 + #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL 338 + //MP1_SMN_C2PMSG_101 339 + #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 340 + #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL 341 + //MP1_SMN_C2PMSG_102 342 + #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 343 + #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL 344 + //MP1_SMN_C2PMSG_103 345 + #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 346 + #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL 347 + //MP1_SMN_C2PMSG_104 348 + #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 349 + #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL 350 + //MP1_SMN_C2PMSG_105 351 + #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 352 + #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL 353 + //MP1_SMN_C2PMSG_106 354 + #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 355 + #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL 356 + //MP1_SMN_C2PMSG_107 357 + #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 358 + #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL 359 + //MP1_SMN_C2PMSG_108 360 + #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 361 + #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL 362 + //MP1_SMN_C2PMSG_109 363 + #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 364 + #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL 365 + //MP1_SMN_C2PMSG_110 366 + #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 367 + #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL 368 + //MP1_SMN_C2PMSG_111 369 + #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 370 + #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL 371 + //MP1_SMN_C2PMSG_112 372 + #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 373 + #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL 374 + //MP1_SMN_C2PMSG_113 375 + #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 376 + #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL 377 + //MP1_SMN_C2PMSG_114 378 + #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 379 + #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL 380 + //MP1_SMN_C2PMSG_115 381 + #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 382 + #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL 383 + //MP1_SMN_C2PMSG_116 384 + #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 385 + #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL 386 + //MP1_SMN_C2PMSG_117 387 + #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 388 + #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL 389 + //MP1_SMN_C2PMSG_118 390 + #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 391 + #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL 392 + //MP1_SMN_C2PMSG_119 393 + #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 394 + #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL 395 + //MP1_SMN_C2PMSG_120 396 + #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 397 + #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL 398 + //MP1_SMN_C2PMSG_121 399 + #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 400 + #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL 401 + //MP1_SMN_C2PMSG_122 402 + #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 403 + #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL 404 + //MP1_SMN_C2PMSG_123 405 + #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 406 + #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL 407 + //MP1_SMN_C2PMSG_124 408 + #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 409 + #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL 410 + //MP1_SMN_C2PMSG_125 411 + #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 412 + #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL 413 + //MP1_SMN_C2PMSG_126 414 + #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 415 + #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL 416 + //MP1_SMN_C2PMSG_127 417 + #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 418 + #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL 419 + //MP1_SMN_IH_CREDIT 420 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 421 + #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 422 + #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L 423 + #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L 424 + //MP1_SMN_IH_SW_INT 425 + #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 426 + #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 427 + #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL 428 + #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L 429 + //MP1_SMN_IH_SW_INT_CTRL 430 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 431 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 432 + #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L 433 + #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L 434 + //MP1_SMN_FPS_CNT 435 + #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 436 + #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL 437 + //MP1_SMN_EXT_SCRATCH0 438 + #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 439 + #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL 440 + //MP1_SMN_EXT_SCRATCH1 441 + #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 442 + #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL 443 + //MP1_SMN_EXT_SCRATCH2 444 + #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 445 + #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL 446 + //MP1_SMN_EXT_SCRATCH3 447 + #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 448 + #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL 449 + //MP1_SMN_EXT_SCRATCH4 450 + #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 451 + #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL 452 + //MP1_SMN_EXT_SCRATCH5 453 + #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 454 + #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL 455 + //MP1_SMN_EXT_SCRATCH6 456 + #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 457 + #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL 458 + //MP1_SMN_EXT_SCRATCH7 459 + #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 460 + #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL 461 + //MP1_SMN_EXT_SCRATCH8 462 + #define MP1_SMN_EXT_SCRATCH8__DATA__SHIFT 0x0 463 + #define MP1_SMN_EXT_SCRATCH8__DATA_MASK 0xFFFFFFFFL 464 + //MP1_SMN_EXT_SCRATCH9 465 + #define MP1_SMN_EXT_SCRATCH9__DATA__SHIFT 0x0 466 + #define MP1_SMN_EXT_SCRATCH9__DATA_MASK 0xFFFFFFFFL 467 + //MP1_SMN_EXT_SCRATCH10 468 + #define MP1_SMN_EXT_SCRATCH10__DATA__SHIFT 0x0 469 + #define MP1_SMN_EXT_SCRATCH10__DATA_MASK 0xFFFFFFFFL 470 + //MP1_SMN_EXT_SCRATCH11 471 + #define MP1_SMN_EXT_SCRATCH11__DATA__SHIFT 0x0 472 + #define MP1_SMN_EXT_SCRATCH11__DATA_MASK 0xFFFFFFFFL 473 + //MP1_SMN_EXT_SCRATCH12 474 + #define MP1_SMN_EXT_SCRATCH12__DATA__SHIFT 0x0 475 + #define MP1_SMN_EXT_SCRATCH12__DATA_MASK 0xFFFFFFFFL 476 + //MP1_SMN_EXT_SCRATCH13 477 + #define MP1_SMN_EXT_SCRATCH13__DATA__SHIFT 0x0 478 + #define MP1_SMN_EXT_SCRATCH13__DATA_MASK 0xFFFFFFFFL 479 + //MP1_SMN_EXT_SCRATCH14 480 + #define MP1_SMN_EXT_SCRATCH14__DATA__SHIFT 0x0 481 + #define MP1_SMN_EXT_SCRATCH14__DATA_MASK 0xFFFFFFFFL 482 + //MP1_SMN_EXT_SCRATCH15 483 + #define MP1_SMN_EXT_SCRATCH15__DATA__SHIFT 0x0 484 + #define MP1_SMN_EXT_SCRATCH15__DATA_MASK 0xFFFFFFFFL 485 + //MP1_SMN_EXT_SCRATCH16 486 + #define MP1_SMN_EXT_SCRATCH16__DATA__SHIFT 0x0 487 + #define MP1_SMN_EXT_SCRATCH16__DATA_MASK 0xFFFFFFFFL 488 + //MP1_SMN_EXT_SCRATCH17 489 + #define MP1_SMN_EXT_SCRATCH17__DATA__SHIFT 0x0 490 + #define MP1_SMN_EXT_SCRATCH17__DATA_MASK 0xFFFFFFFFL 491 + //MP1_SMN_EXT_SCRATCH18 492 + #define MP1_SMN_EXT_SCRATCH18__DATA__SHIFT 0x0 493 + #define MP1_SMN_EXT_SCRATCH18__DATA_MASK 0xFFFFFFFFL 494 + //MP1_SMN_EXT_SCRATCH19 495 + #define MP1_SMN_EXT_SCRATCH19__DATA__SHIFT 0x0 496 + #define MP1_SMN_EXT_SCRATCH19__DATA_MASK 0xFFFFFFFFL 497 + //MP1_SMN_EXT_SCRATCH20 498 + #define MP1_SMN_EXT_SCRATCH20__DATA__SHIFT 0x0 499 + #define MP1_SMN_EXT_SCRATCH20__DATA_MASK 0xFFFFFFFFL 500 + //MP1_SMN_EXT_SCRATCH21 501 + #define MP1_SMN_EXT_SCRATCH21__DATA__SHIFT 0x0 502 + #define MP1_SMN_EXT_SCRATCH21__DATA_MASK 0xFFFFFFFFL 503 + //MP1_SMN_EXT_SCRATCH22 504 + #define MP1_SMN_EXT_SCRATCH22__DATA__SHIFT 0x0 505 + #define MP1_SMN_EXT_SCRATCH22__DATA_MASK 0xFFFFFFFFL 506 + //MP1_SMN_EXT_SCRATCH23 507 + #define MP1_SMN_EXT_SCRATCH23__DATA__SHIFT 0x0 508 + #define MP1_SMN_EXT_SCRATCH23__DATA_MASK 0xFFFFFFFFL 509 + //MP1_SMN_EXT_SCRATCH24 510 + #define MP1_SMN_EXT_SCRATCH24__DATA__SHIFT 0x0 511 + #define MP1_SMN_EXT_SCRATCH24__DATA_MASK 0xFFFFFFFFL 512 + //MP1_SMN_EXT_SCRATCH25 513 + #define MP1_SMN_EXT_SCRATCH25__DATA__SHIFT 0x0 514 + #define MP1_SMN_EXT_SCRATCH25__DATA_MASK 0xFFFFFFFFL 515 + //MP1_SMN_EXT_SCRATCH26 516 + #define MP1_SMN_EXT_SCRATCH26__DATA__SHIFT 0x0 517 + #define MP1_SMN_EXT_SCRATCH26__DATA_MASK 0xFFFFFFFFL 518 + //MP1_SMN_EXT_SCRATCH27 519 + #define MP1_SMN_EXT_SCRATCH27__DATA__SHIFT 0x0 520 + #define MP1_SMN_EXT_SCRATCH27__DATA_MASK 0xFFFFFFFFL 521 + //MP1_SMN_EXT_SCRATCH28 522 + #define MP1_SMN_EXT_SCRATCH28__DATA__SHIFT 0x0 523 + #define MP1_SMN_EXT_SCRATCH28__DATA_MASK 0xFFFFFFFFL 524 + //MP1_SMN_EXT_SCRATCH29 525 + #define MP1_SMN_EXT_SCRATCH29__DATA__SHIFT 0x0 526 + #define MP1_SMN_EXT_SCRATCH29__DATA_MASK 0xFFFFFFFFL 527 + //MP1_SMN_EXT_SCRATCH30 528 + #define MP1_SMN_EXT_SCRATCH30__DATA__SHIFT 0x0 529 + #define MP1_SMN_EXT_SCRATCH30__DATA_MASK 0xFFFFFFFFL 530 + //MP1_SMN_EXT_SCRATCH31 531 + #define MP1_SMN_EXT_SCRATCH31__DATA__SHIFT 0x0 532 + #define MP1_SMN_EXT_SCRATCH31__DATA_MASK 0xFFFFFFFFL 533 + 534 + #endif