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[ARM] 4479/1: AT91: Define new MMC register bits
Add definitions for RDPROOF, WRPROOF and PDCFBYTE bits of the Mode
Register in the updated MMC controller found on the AT91SAM9260 and
AT91SAM9263 processors.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
authored by Andrew Victor and committed by Russell King ed54fcfd c06911c0
+3
include/asm-arm/arch-at91/at91_mci.h
+3
include/asm-arm/arch-at91/at91_mci.h
···
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#define AT91_MCI_MR 0x04 /* Mode Register */
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#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
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#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
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#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
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#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
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#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
···
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#define AT91_MCI_MR 0x04 /* Mode Register */
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#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
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#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
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+
#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
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+
#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
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+
#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
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#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
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#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
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#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */