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ARM: vexpress: Add Cortex-R Series UART, selectable via DEBUG_LL

The Cortex-R series processors on Versatile Express have a different memory
map to the RS1 and CA9X4 tiles. Most of the platform difference can be
expressed in device-trees, but the UART definitions for LL_DEBUG cannot.

This patch defines the UART location for R-Series processors on
versatile-express, allowing low-level debug and output from the decompressor.
These definitions are selectable via Kconfig

Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
CC: Pawel Moll <pawel.moll@arm.com>

Jonathan Austin ed18bdc8 c90ad5c9

+19 -1
+9 -1
arch/arm/Kconfig.debug
··· 476 476 of the tiles using the RS1 memory map, including all new A-class 477 477 core tiles, FPGA-based SMMs and software models. 478 478 479 + config DEBUG_VEXPRESS_UART0_CRX 480 + bool "Use PL011 UART0 at 0xb0090000 (Cortex-R compliant tiles)" 481 + depends on ARCH_VEXPRESS && !MMU 482 + help 483 + This option selects UART0 at 0xb0090000. This is appropriate for 484 + Cortex-R series tiles and SMMs, such as Cortex-R5 and Cortex-R7 485 + 479 486 config DEBUG_VT8500_UART0 480 487 bool "Use UART0 on VIA/Wondermedia SoCs" 481 488 depends on ARCH_VT8500 ··· 652 645 default "debug/tegra.S" if DEBUG_TEGRA_UART 653 646 default "debug/ux500.S" if DEBUG_UX500_UART 654 647 default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ 655 - DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 648 + DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1 || \ 649 + DEBUG_VEXPRESS_UART0_CRX 656 650 default "debug/vt8500.S" if DEBUG_VT8500_UART0 657 651 default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1 658 652 default "mach/debug-macro.S"
+10
arch/arm/include/debug/vexpress.S
··· 16 16 #define DEBUG_LL_PHYS_BASE_RS1 0x1c000000 17 17 #define DEBUG_LL_UART_OFFSET_RS1 0x00090000 18 18 19 + #define DEBUG_LL_UART_PHYS_CRX 0xb0090000 20 + 19 21 #define DEBUG_LL_VIRT_BASE 0xf8000000 20 22 21 23 #if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT) ··· 65 63 mov \rp, #DEBUG_LL_UART_OFFSET_RS1 66 64 orr \rv, \rp, #DEBUG_LL_VIRT_BASE 67 65 orr \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1 66 + .endm 67 + 68 + #include <asm/hardware/debug-pl01x.S> 69 + 70 + #elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CRX) 71 + 72 + .macro addruart,rp,tmp,tmp2 73 + ldr \rp, =DEBUG_LL_UART_PHYS_CRX 68 74 .endm 69 75 70 76 #include <asm/hardware/debug-pl01x.S>