Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

Merge branch '4.8/omapdrm-pll' (omapdrm PLL work)

Merge omapdrm PLL work, which makes it possible to use the DSS PLLs in a
versatile manner, for example, HDMI PLL can be used for LCDs.

+509 -373
+37 -60
drivers/gpu/drm/omapdrm/dss/dispc.c
··· 3299 3299 3300 3300 static unsigned long dispc_fclk_rate(void) 3301 3301 { 3302 - struct dss_pll *pll; 3303 - unsigned long r = 0; 3302 + unsigned long r; 3303 + enum dss_clk_source src; 3304 3304 3305 - switch (dss_get_dispc_clk_source()) { 3306 - case OMAP_DSS_CLK_SRC_FCK: 3305 + src = dss_get_dispc_clk_source(); 3306 + 3307 + if (src == DSS_CLK_SRC_FCK) { 3307 3308 r = dss_get_dispc_clk_rate(); 3308 - break; 3309 - case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3310 - pll = dss_pll_find("dsi0"); 3311 - if (!pll) 3312 - pll = dss_pll_find("video0"); 3309 + } else { 3310 + struct dss_pll *pll; 3311 + unsigned clkout_idx; 3313 3312 3314 - r = pll->cinfo.clkout[0]; 3315 - break; 3316 - case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3317 - pll = dss_pll_find("dsi1"); 3318 - if (!pll) 3319 - pll = dss_pll_find("video1"); 3313 + pll = dss_pll_find_by_src(src); 3314 + clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3320 3315 3321 - r = pll->cinfo.clkout[0]; 3322 - break; 3323 - default: 3324 - BUG(); 3325 - return 0; 3316 + r = pll->cinfo.clkout[clkout_idx]; 3326 3317 } 3327 3318 3328 3319 return r; ··· 3321 3330 3322 3331 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) 3323 3332 { 3324 - struct dss_pll *pll; 3325 3333 int lcd; 3326 3334 unsigned long r; 3327 - u32 l; 3335 + enum dss_clk_source src; 3328 3336 3329 - if (dss_mgr_is_lcd(channel)) { 3330 - l = dispc_read_reg(DISPC_DIVISORo(channel)); 3331 - 3332 - lcd = FLD_GET(l, 23, 16); 3333 - 3334 - switch (dss_get_lcd_clk_source(channel)) { 3335 - case OMAP_DSS_CLK_SRC_FCK: 3336 - r = dss_get_dispc_clk_rate(); 3337 - break; 3338 - case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 3339 - pll = dss_pll_find("dsi0"); 3340 - if (!pll) 3341 - pll = dss_pll_find("video0"); 3342 - 3343 - r = pll->cinfo.clkout[0]; 3344 - break; 3345 - case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 3346 - pll = dss_pll_find("dsi1"); 3347 - if (!pll) 3348 - pll = dss_pll_find("video1"); 3349 - 3350 - r = pll->cinfo.clkout[0]; 3351 - break; 3352 - default: 3353 - BUG(); 3354 - return 0; 3355 - } 3356 - 3357 - return r / lcd; 3358 - } else { 3337 + /* for TV, LCLK rate is the FCLK rate */ 3338 + if (!dss_mgr_is_lcd(channel)) 3359 3339 return dispc_fclk_rate(); 3340 + 3341 + src = dss_get_lcd_clk_source(channel); 3342 + 3343 + if (src == DSS_CLK_SRC_FCK) { 3344 + r = dss_get_dispc_clk_rate(); 3345 + } else { 3346 + struct dss_pll *pll; 3347 + unsigned clkout_idx; 3348 + 3349 + pll = dss_pll_find_by_src(src); 3350 + clkout_idx = dss_pll_get_clkout_idx_for_src(src); 3351 + 3352 + r = pll->cinfo.clkout[clkout_idx]; 3360 3353 } 3354 + 3355 + lcd = REG_GET(DISPC_DIVISORo(channel), 23, 16); 3356 + 3357 + return r / lcd; 3361 3358 } 3362 3359 3363 3360 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) ··· 3405 3426 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) 3406 3427 { 3407 3428 int lcd, pcd; 3408 - enum omap_dss_clk_source lcd_clk_src; 3429 + enum dss_clk_source lcd_clk_src; 3409 3430 3410 3431 seq_printf(s, "- %s -\n", mgr_desc[channel].name); 3411 3432 3412 3433 lcd_clk_src = dss_get_lcd_clk_source(channel); 3413 3434 3414 - seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, 3415 - dss_get_generic_clk_source_name(lcd_clk_src), 3416 - dss_feat_get_clk_source_name(lcd_clk_src)); 3435 + seq_printf(s, "%s clk source = %s\n", mgr_desc[channel].name, 3436 + dss_get_clk_source_name(lcd_clk_src)); 3417 3437 3418 3438 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); 3419 3439 ··· 3426 3448 { 3427 3449 int lcd; 3428 3450 u32 l; 3429 - enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3451 + enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); 3430 3452 3431 3453 if (dispc_runtime_get()) 3432 3454 return; 3433 3455 3434 3456 seq_printf(s, "- DISPC -\n"); 3435 3457 3436 - seq_printf(s, "dispc fclk source = %s (%s)\n", 3437 - dss_get_generic_clk_source_name(dispc_clk_src), 3438 - dss_feat_get_clk_source_name(dispc_clk_src)); 3458 + seq_printf(s, "dispc fclk source = %s\n", 3459 + dss_get_clk_source_name(dispc_clk_src)); 3439 3460 3440 3461 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); 3441 3462
+65 -68
drivers/gpu/drm/omapdrm/dss/dpi.c
··· 39 39 #include "dss.h" 40 40 #include "dss_features.h" 41 41 42 - #define HSDIV_DISPC 0 43 - 44 42 struct dpi_data { 45 43 struct platform_device *pdev; 46 44 47 45 struct regulator *vdds_dsi_reg; 46 + enum dss_clk_source clk_src; 48 47 struct dss_pll *pll; 49 48 50 49 struct mutex lock; ··· 68 69 return dev_get_drvdata(&pdev->dev); 69 70 } 70 71 71 - static struct dss_pll *dpi_get_pll(enum omap_channel channel) 72 + static enum dss_clk_source dpi_get_clk_src(enum omap_channel channel) 72 73 { 73 74 /* 74 75 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL ··· 82 83 case OMAPDSS_VER_OMAP3630: 83 84 case OMAPDSS_VER_AM35xx: 84 85 case OMAPDSS_VER_AM43xx: 85 - return NULL; 86 + return DSS_CLK_SRC_FCK; 86 87 87 88 case OMAPDSS_VER_OMAP4430_ES1: 88 89 case OMAPDSS_VER_OMAP4430_ES2: 89 90 case OMAPDSS_VER_OMAP4: 90 91 switch (channel) { 91 92 case OMAP_DSS_CHANNEL_LCD: 92 - return dss_pll_find("dsi0"); 93 + return DSS_CLK_SRC_PLL1_1; 93 94 case OMAP_DSS_CHANNEL_LCD2: 94 - return dss_pll_find("dsi1"); 95 + return DSS_CLK_SRC_PLL2_1; 95 96 default: 96 - return NULL; 97 + return DSS_CLK_SRC_FCK; 97 98 } 98 99 99 100 case OMAPDSS_VER_OMAP5: 100 101 switch (channel) { 101 102 case OMAP_DSS_CHANNEL_LCD: 102 - return dss_pll_find("dsi0"); 103 + return DSS_CLK_SRC_PLL1_1; 103 104 case OMAP_DSS_CHANNEL_LCD3: 104 - return dss_pll_find("dsi1"); 105 + return DSS_CLK_SRC_PLL2_1; 106 + case OMAP_DSS_CHANNEL_LCD2: 105 107 default: 106 - return NULL; 108 + return DSS_CLK_SRC_FCK; 107 109 } 108 110 109 111 case OMAPDSS_VER_DRA7xx: 110 112 switch (channel) { 111 113 case OMAP_DSS_CHANNEL_LCD: 114 + return DSS_CLK_SRC_PLL1_1; 112 115 case OMAP_DSS_CHANNEL_LCD2: 113 - return dss_pll_find("video0"); 116 + return DSS_CLK_SRC_PLL1_3; 114 117 case OMAP_DSS_CHANNEL_LCD3: 115 - return dss_pll_find("video1"); 118 + return DSS_CLK_SRC_PLL2_1; 116 119 default: 117 - return NULL; 120 + return DSS_CLK_SRC_FCK; 118 121 } 119 122 120 123 default: 121 - return NULL; 122 - } 123 - } 124 - 125 - static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel) 126 - { 127 - switch (channel) { 128 - case OMAP_DSS_CHANNEL_LCD: 129 - return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC; 130 - case OMAP_DSS_CHANNEL_LCD2: 131 - return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; 132 - case OMAP_DSS_CHANNEL_LCD3: 133 - return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC; 134 - default: 135 - /* this shouldn't happen */ 136 - WARN_ON(1); 137 - return OMAP_DSS_CLK_SRC_FCK; 124 + return DSS_CLK_SRC_FCK; 138 125 } 139 126 } 140 127 141 128 struct dpi_clk_calc_ctx { 142 129 struct dss_pll *pll; 130 + unsigned clkout_idx; 143 131 144 132 /* inputs */ 145 133 ··· 134 148 135 149 /* outputs */ 136 150 137 - struct dss_pll_clock_info dsi_cinfo; 151 + struct dss_pll_clock_info pll_cinfo; 138 152 unsigned long fck; 139 153 struct dispc_clock_info dispc_cinfo; 140 154 }; ··· 179 193 if (m_dispc > 1 && m_dispc % 2 != 0 && ctx->pck_min >= 100000000) 180 194 return false; 181 195 182 - ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 183 - ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 196 + ctx->pll_cinfo.mX[ctx->clkout_idx] = m_dispc; 197 + ctx->pll_cinfo.clkout[ctx->clkout_idx] = dispc; 184 198 185 199 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max, 186 200 dpi_calc_dispc_cb, ctx); ··· 193 207 { 194 208 struct dpi_clk_calc_ctx *ctx = data; 195 209 196 - ctx->dsi_cinfo.n = n; 197 - ctx->dsi_cinfo.m = m; 198 - ctx->dsi_cinfo.fint = fint; 199 - ctx->dsi_cinfo.clkdco = clkdco; 210 + ctx->pll_cinfo.n = n; 211 + ctx->pll_cinfo.m = m; 212 + ctx->pll_cinfo.fint = fint; 213 + ctx->pll_cinfo.clkdco = clkdco; 200 214 201 - return dss_pll_hsdiv_calc(ctx->pll, clkdco, 215 + return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, 202 216 ctx->pck_min, dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 203 217 dpi_calc_hsdiv_cb, ctx); 204 218 } ··· 213 227 dpi_calc_dispc_cb, ctx); 214 228 } 215 229 216 - static bool dpi_dsi_clk_calc(struct dpi_data *dpi, unsigned long pck, 230 + static bool dpi_pll_clk_calc(struct dpi_data *dpi, unsigned long pck, 217 231 struct dpi_clk_calc_ctx *ctx) 218 232 { 219 233 unsigned long clkin; 220 - unsigned long pll_min, pll_max; 221 234 222 235 memset(ctx, 0, sizeof(*ctx)); 223 236 ctx->pll = dpi->pll; 224 - ctx->pck_min = pck - 1000; 225 - ctx->pck_max = pck + 1000; 237 + ctx->clkout_idx = dss_pll_get_clkout_idx_for_src(dpi->clk_src); 226 238 227 - pll_min = 0; 228 - pll_max = 0; 239 + clkin = clk_get_rate(dpi->pll->clkin); 229 240 230 - clkin = clk_get_rate(ctx->pll->clkin); 241 + if (dpi->pll->hw->type == DSS_PLL_TYPE_A) { 242 + unsigned long pll_min, pll_max; 231 243 232 - return dss_pll_calc(ctx->pll, clkin, 233 - pll_min, pll_max, 234 - dpi_calc_pll_cb, ctx); 244 + ctx->pck_min = pck - 1000; 245 + ctx->pck_max = pck + 1000; 246 + 247 + pll_min = 0; 248 + pll_max = 0; 249 + 250 + return dss_pll_calc_a(ctx->pll, clkin, 251 + pll_min, pll_max, 252 + dpi_calc_pll_cb, ctx); 253 + } else { /* DSS_PLL_TYPE_B */ 254 + dss_pll_calc_b(dpi->pll, clkin, pck, &ctx->pll_cinfo); 255 + 256 + ctx->dispc_cinfo.lck_div = 1; 257 + ctx->dispc_cinfo.pck_div = 1; 258 + ctx->dispc_cinfo.lck = ctx->pll_cinfo.clkout[0]; 259 + ctx->dispc_cinfo.pck = ctx->dispc_cinfo.lck; 260 + 261 + return true; 262 + } 235 263 } 236 264 237 265 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx) ··· 279 279 280 280 281 281 282 - static int dpi_set_dsi_clk(struct dpi_data *dpi, enum omap_channel channel, 282 + static int dpi_set_pll_clk(struct dpi_data *dpi, enum omap_channel channel, 283 283 unsigned long pck_req, unsigned long *fck, int *lck_div, 284 284 int *pck_div) 285 285 { ··· 287 287 int r; 288 288 bool ok; 289 289 290 - ok = dpi_dsi_clk_calc(dpi, pck_req, &ctx); 290 + ok = dpi_pll_clk_calc(dpi, pck_req, &ctx); 291 291 if (!ok) 292 292 return -EINVAL; 293 293 294 - r = dss_pll_set_config(dpi->pll, &ctx.dsi_cinfo); 294 + r = dss_pll_set_config(dpi->pll, &ctx.pll_cinfo); 295 295 if (r) 296 296 return r; 297 297 298 - dss_select_lcd_clk_source(channel, 299 - dpi_get_alt_clk_src(channel)); 298 + dss_select_lcd_clk_source(channel, dpi->clk_src); 300 299 301 300 dpi->mgr_config.clock_info = ctx.dispc_cinfo; 302 301 303 - *fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC]; 302 + *fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 304 303 *lck_div = ctx.dispc_cinfo.lck_div; 305 304 *pck_div = ctx.dispc_cinfo.pck_div; 306 305 ··· 341 342 int r = 0; 342 343 343 344 if (dpi->pll) 344 - r = dpi_set_dsi_clk(dpi, channel, t->pixelclock, &fck, 345 + r = dpi_set_pll_clk(dpi, channel, t->pixelclock, &fck, 345 346 &lck_div, &pck_div); 346 347 else 347 348 r = dpi_set_dispc_clk(dpi, t->pixelclock, &fck, ··· 418 419 if (dpi->pll) { 419 420 r = dss_pll_enable(dpi->pll); 420 421 if (r) 421 - goto err_dsi_pll_init; 422 + goto err_pll_init; 422 423 } 423 424 424 425 r = dpi_set_mode(dpi); ··· 441 442 err_set_mode: 442 443 if (dpi->pll) 443 444 dss_pll_disable(dpi->pll); 444 - err_dsi_pll_init: 445 + err_pll_init: 445 446 err_src_sel: 446 447 dispc_runtime_put(); 447 448 err_get_dispc: ··· 464 465 dss_mgr_disable(channel); 465 466 466 467 if (dpi->pll) { 467 - dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); 468 + dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 468 469 dss_pll_disable(dpi->pll); 469 470 } 470 471 ··· 523 524 return -EINVAL; 524 525 525 526 if (dpi->pll) { 526 - ok = dpi_dsi_clk_calc(dpi, timings->pixelclock, &ctx); 527 + ok = dpi_pll_clk_calc(dpi, timings->pixelclock, &ctx); 527 528 if (!ok) 528 529 return -EINVAL; 529 530 530 - fck = ctx.dsi_cinfo.clkout[HSDIV_DISPC]; 531 + fck = ctx.pll_cinfo.clkout[ctx.clkout_idx]; 531 532 } else { 532 533 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx); 533 534 if (!ok) ··· 557 558 mutex_unlock(&dpi->lock); 558 559 } 559 560 560 - static int dpi_verify_dsi_pll(struct dss_pll *pll) 561 + static int dpi_verify_pll(struct dss_pll *pll) 561 562 { 562 563 int r; 563 564 ··· 601 602 if (dpi->pll) 602 603 return; 603 604 604 - pll = dpi_get_pll(dpi->output.dispc_channel); 605 + dpi->clk_src = dpi_get_clk_src(dpi->output.dispc_channel); 606 + 607 + pll = dss_pll_find_by_src(dpi->clk_src); 605 608 if (!pll) 606 609 return; 607 610 608 - /* On DRA7 we need to set a mux to use the PLL */ 609 - if (omapdss_get_version() == OMAPDSS_VER_DRA7xx) 610 - dss_ctrl_pll_set_control_mux(pll->id, dpi->output.dispc_channel); 611 - 612 - if (dpi_verify_dsi_pll(pll)) { 613 - DSSWARN("DSI PLL not operational\n"); 611 + if (dpi_verify_pll(pll)) { 612 + DSSWARN("PLL not operational\n"); 614 613 return; 615 614 } 616 615
+30 -25
drivers/gpu/drm/omapdrm/dss/dsi.c
··· 1262 1262 unsigned long r; 1263 1263 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1264 1264 1265 - if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { 1265 + if (dss_get_dsi_clk_source(dsi->module_id) == DSS_CLK_SRC_FCK) { 1266 1266 /* DSI FCLK source is DSS_CLK_FCK */ 1267 1267 r = clk_get_rate(dsi->dss_clk); 1268 1268 } else { ··· 1475 1475 { 1476 1476 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); 1477 1477 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1478 - enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; 1478 + enum dss_clk_source dispc_clk_src, dsi_clk_src; 1479 1479 int dsi_module = dsi->module_id; 1480 1480 struct dss_pll *pll = &dsi->pll; 1481 1481 ··· 1495 1495 cinfo->clkdco, cinfo->m); 1496 1496 1497 1497 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1498 - dss_feat_get_clk_source_name(dsi_module == 0 ? 1499 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 1500 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), 1498 + dss_get_clk_source_name(dsi_module == 0 ? 1499 + DSS_CLK_SRC_PLL1_1 : 1500 + DSS_CLK_SRC_PLL2_1), 1501 1501 cinfo->clkout[HSDIV_DISPC], 1502 1502 cinfo->mX[HSDIV_DISPC], 1503 - dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1503 + dispc_clk_src == DSS_CLK_SRC_FCK ? 1504 1504 "off" : "on"); 1505 1505 1506 1506 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1507 - dss_feat_get_clk_source_name(dsi_module == 0 ? 1508 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 1509 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), 1507 + dss_get_clk_source_name(dsi_module == 0 ? 1508 + DSS_CLK_SRC_PLL1_2 : 1509 + DSS_CLK_SRC_PLL2_2), 1510 1510 cinfo->clkout[HSDIV_DSI], 1511 1511 cinfo->mX[HSDIV_DSI], 1512 - dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? 1512 + dsi_clk_src == DSS_CLK_SRC_FCK ? 1513 1513 "off" : "on"); 1514 1514 1515 1515 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1516 1516 1517 - seq_printf(s, "dsi fclk source = %s (%s)\n", 1518 - dss_get_generic_clk_source_name(dsi_clk_src), 1519 - dss_feat_get_clk_source_name(dsi_clk_src)); 1517 + seq_printf(s, "dsi fclk source = %s\n", 1518 + dss_get_clk_source_name(dsi_clk_src)); 1520 1519 1521 1520 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); 1522 1521 ··· 4101 4102 int r; 4102 4103 4103 4104 dss_select_lcd_clk_source(channel, dsi->module_id == 0 ? 4104 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : 4105 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC); 4105 + DSS_CLK_SRC_PLL1_1 : 4106 + DSS_CLK_SRC_PLL2_1); 4106 4107 4107 4108 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4108 4109 r = dss_mgr_register_framedone_handler(channel, ··· 4149 4150 dss_mgr_unregister_framedone_handler(channel, 4150 4151 dsi_framedone_irq_callback, dsidev); 4151 4152 err: 4152 - dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); 4153 + dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4153 4154 return r; 4154 4155 } 4155 4156 ··· 4162 4163 dss_mgr_unregister_framedone_handler(channel, 4163 4164 dsi_framedone_irq_callback, dsidev); 4164 4165 4165 - dss_select_lcd_clk_source(channel, OMAP_DSS_CLK_SRC_FCK); 4166 + dss_select_lcd_clk_source(channel, DSS_CLK_SRC_FCK); 4166 4167 } 4167 4168 4168 4169 static int dsi_configure_dsi_clocks(struct platform_device *dsidev) ··· 4196 4197 goto err1; 4197 4198 4198 4199 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ? 4199 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : 4200 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI); 4200 + DSS_CLK_SRC_PLL1_2 : 4201 + DSS_CLK_SRC_PLL2_2); 4201 4202 4202 4203 DSSDBG("PLL OK\n"); 4203 4204 ··· 4229 4230 err3: 4230 4231 dsi_cio_uninit(dsidev); 4231 4232 err2: 4232 - dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4233 + dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4233 4234 err1: 4234 4235 dss_pll_disable(&dsi->pll); 4235 4236 err0: ··· 4251 4252 dsi_vc_enable(dsidev, 2, 0); 4252 4253 dsi_vc_enable(dsidev, 3, 0); 4253 4254 4254 - dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); 4255 + dss_select_dsi_clk_source(dsi->module_id, DSS_CLK_SRC_FCK); 4255 4256 dsi_cio_uninit(dsidev); 4256 4257 dsi_pll_uninit(dsidev, disconnect_lanes); 4257 4258 } ··· 4452 4453 ctx->dsi_cinfo.fint = fint; 4453 4454 ctx->dsi_cinfo.clkdco = clkdco; 4454 4455 4455 - return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4456 + return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4456 4457 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4457 4458 dsi_cm_calc_hsdiv_cb, ctx); 4458 4459 } ··· 4491 4492 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4492 4493 pll_max = cfg->hs_clk_max * 4; 4493 4494 4494 - return dss_pll_calc(ctx->pll, clkin, 4495 + return dss_pll_calc_a(ctx->pll, clkin, 4495 4496 pll_min, pll_max, 4496 4497 dsi_cm_calc_pll_cb, ctx); 4497 4498 } ··· 4750 4751 ctx->dsi_cinfo.fint = fint; 4751 4752 ctx->dsi_cinfo.clkdco = clkdco; 4752 4753 4753 - return dss_pll_hsdiv_calc(ctx->pll, clkdco, ctx->req_pck_min, 4754 + return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4754 4755 dss_feat_get_param_max(FEAT_PARAM_DSS_FCK), 4755 4756 dsi_vm_calc_hsdiv_cb, ctx); 4756 4757 } ··· 4792 4793 pll_max = byteclk_max * 4 * 4; 4793 4794 } 4794 4795 4795 - return dss_pll_calc(ctx->pll, clkin, 4796 + return dss_pll_calc_a(ctx->pll, clkin, 4796 4797 pll_min, pll_max, 4797 4798 dsi_vm_calc_pll_cb, ctx); 4798 4799 } ··· 5138 5139 }; 5139 5140 5140 5141 static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 5142 + .type = DSS_PLL_TYPE_A, 5143 + 5141 5144 .n_max = (1 << 7) - 1, 5142 5145 .m_max = (1 << 11) - 1, 5143 5146 .mX_max = (1 << 4) - 1, ··· 5165 5164 }; 5166 5165 5167 5166 static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 5167 + .type = DSS_PLL_TYPE_A, 5168 + 5168 5169 .n_max = (1 << 8) - 1, 5169 5170 .m_max = (1 << 12) - 1, 5170 5171 .mX_max = (1 << 5) - 1, ··· 5192 5189 }; 5193 5190 5194 5191 static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 5192 + .type = DSS_PLL_TYPE_A, 5193 + 5195 5194 .n_max = (1 << 8) - 1, 5196 5195 .m_max = (1 << 12) - 1, 5197 5196 .mX_max = (1 << 5) - 1,
+176 -78
drivers/gpu/drm/omapdrm/dss/dss.c
··· 76 76 const enum omap_display_type *ports; 77 77 int num_ports; 78 78 int (*dpi_select_source)(int port, enum omap_channel channel); 79 + int (*select_lcd_source)(enum omap_channel channel, 80 + enum dss_clk_source clk_src); 79 81 }; 80 82 81 83 static struct { ··· 94 92 unsigned long cache_prate; 95 93 struct dispc_clock_info cache_dispc_cinfo; 96 94 97 - enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 98 - enum omap_dss_clk_source dispc_clk_source; 99 - enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 95 + enum dss_clk_source dsi_clk_source[MAX_NUM_DSI]; 96 + enum dss_clk_source dispc_clk_source; 97 + enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS]; 100 98 101 99 bool ctx_valid; 102 100 u32 ctx[DSS_SZ_REGS / sizeof(u32)]; ··· 108 106 } dss; 109 107 110 108 static const char * const dss_generic_clk_source_names[] = { 111 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC", 112 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI", 113 - [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK", 114 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DSI_PLL2_HSDIV_DISPC", 115 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DSI_PLL2_HSDIV_DSI", 109 + [DSS_CLK_SRC_FCK] = "FCK", 110 + [DSS_CLK_SRC_PLL1_1] = "PLL1:1", 111 + [DSS_CLK_SRC_PLL1_2] = "PLL1:2", 112 + [DSS_CLK_SRC_PLL1_3] = "PLL1:3", 113 + [DSS_CLK_SRC_PLL2_1] = "PLL2:1", 114 + [DSS_CLK_SRC_PLL2_2] = "PLL2:2", 115 + [DSS_CLK_SRC_PLL2_3] = "PLL2:3", 116 + [DSS_CLK_SRC_HDMI_PLL] = "HDMI PLL", 116 117 }; 117 118 118 119 static bool dss_initialized; ··· 208 203 1 << shift, val << shift); 209 204 } 210 205 211 - void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id, 206 + static int dss_ctrl_pll_set_control_mux(enum dss_clk_source clk_src, 212 207 enum omap_channel channel) 213 208 { 214 209 unsigned shift, val; 215 210 216 211 if (!dss.syscon_pll_ctrl) 217 - return; 212 + return -EINVAL; 218 213 219 214 switch (channel) { 220 215 case OMAP_DSS_CHANNEL_LCD: 221 216 shift = 3; 222 217 223 - switch (pll_id) { 224 - case DSS_PLL_VIDEO1: 218 + switch (clk_src) { 219 + case DSS_CLK_SRC_PLL1_1: 225 220 val = 0; break; 226 - case DSS_PLL_HDMI: 221 + case DSS_CLK_SRC_HDMI_PLL: 227 222 val = 1; break; 228 223 default: 229 224 DSSERR("error in PLL mux config for LCD\n"); 230 - return; 225 + return -EINVAL; 231 226 } 232 227 233 228 break; 234 229 case OMAP_DSS_CHANNEL_LCD2: 235 230 shift = 5; 236 231 237 - switch (pll_id) { 238 - case DSS_PLL_VIDEO1: 232 + switch (clk_src) { 233 + case DSS_CLK_SRC_PLL1_3: 239 234 val = 0; break; 240 - case DSS_PLL_VIDEO2: 235 + case DSS_CLK_SRC_PLL2_3: 241 236 val = 1; break; 242 - case DSS_PLL_HDMI: 237 + case DSS_CLK_SRC_HDMI_PLL: 243 238 val = 2; break; 244 239 default: 245 240 DSSERR("error in PLL mux config for LCD2\n"); 246 - return; 241 + return -EINVAL; 247 242 } 248 243 249 244 break; 250 245 case OMAP_DSS_CHANNEL_LCD3: 251 246 shift = 7; 252 247 253 - switch (pll_id) { 254 - case DSS_PLL_VIDEO1: 255 - val = 1; break; 256 - case DSS_PLL_VIDEO2: 248 + switch (clk_src) { 249 + case DSS_CLK_SRC_PLL2_1: 257 250 val = 0; break; 258 - case DSS_PLL_HDMI: 251 + case DSS_CLK_SRC_PLL1_3: 252 + val = 1; break; 253 + case DSS_CLK_SRC_HDMI_PLL: 259 254 val = 2; break; 260 255 default: 261 256 DSSERR("error in PLL mux config for LCD3\n"); 262 - return; 257 + return -EINVAL; 263 258 } 264 259 265 260 break; 266 261 default: 267 262 DSSERR("error in PLL mux config\n"); 268 - return; 263 + return -EINVAL; 269 264 } 270 265 271 266 regmap_update_bits(dss.syscon_pll_ctrl, dss.syscon_pll_ctrl_offset, 272 267 0x3 << shift, val << shift); 268 + 269 + return 0; 273 270 } 274 271 275 272 void dss_sdi_init(int datapairs) ··· 361 354 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ 362 355 } 363 356 364 - const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src) 357 + const char *dss_get_clk_source_name(enum dss_clk_source clk_src) 365 358 { 366 359 return dss_generic_clk_source_names[clk_src]; 367 360 } 368 361 369 362 void dss_dump_clocks(struct seq_file *s) 370 363 { 371 - const char *fclk_name, *fclk_real_name; 364 + const char *fclk_name; 372 365 unsigned long fclk_rate; 373 366 374 367 if (dss_runtime_get()) ··· 376 369 377 370 seq_printf(s, "- DSS -\n"); 378 371 379 - fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK); 380 - fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK); 372 + fclk_name = dss_get_clk_source_name(DSS_CLK_SRC_FCK); 381 373 fclk_rate = clk_get_rate(dss.dss_clk); 382 374 383 - seq_printf(s, "%s (%s) = %lu\n", 384 - fclk_name, fclk_real_name, 375 + seq_printf(s, "%s = %lu\n", 376 + fclk_name, 385 377 fclk_rate); 386 378 387 379 dss_runtime_put(); ··· 409 403 #undef DUMPREG 410 404 } 411 405 412 - static void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src) 406 + static int dss_get_channel_index(enum omap_channel channel) 407 + { 408 + switch (channel) { 409 + case OMAP_DSS_CHANNEL_LCD: 410 + return 0; 411 + case OMAP_DSS_CHANNEL_LCD2: 412 + return 1; 413 + case OMAP_DSS_CHANNEL_LCD3: 414 + return 2; 415 + default: 416 + WARN_ON(1); 417 + return 0; 418 + } 419 + } 420 + 421 + static void dss_select_dispc_clk_source(enum dss_clk_source clk_src) 413 422 { 414 423 int b; 415 424 u8 start, end; 416 425 426 + /* 427 + * We always use PRCM clock as the DISPC func clock, except on DSS3, 428 + * where we don't have separate DISPC and LCD clock sources. 429 + */ 430 + if (WARN_ON(dss_has_feature(FEAT_LCD_CLK_SRC) && 431 + clk_src != DSS_CLK_SRC_FCK)) 432 + return; 433 + 417 434 switch (clk_src) { 418 - case OMAP_DSS_CLK_SRC_FCK: 435 + case DSS_CLK_SRC_FCK: 419 436 b = 0; 420 437 break; 421 - case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 438 + case DSS_CLK_SRC_PLL1_1: 422 439 b = 1; 423 440 break; 424 - case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 441 + case DSS_CLK_SRC_PLL2_1: 425 442 b = 2; 426 443 break; 427 444 default: ··· 460 431 } 461 432 462 433 void dss_select_dsi_clk_source(int dsi_module, 463 - enum omap_dss_clk_source clk_src) 434 + enum dss_clk_source clk_src) 464 435 { 465 436 int b, pos; 466 437 467 438 switch (clk_src) { 468 - case OMAP_DSS_CLK_SRC_FCK: 439 + case DSS_CLK_SRC_FCK: 469 440 b = 0; 470 441 break; 471 - case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI: 442 + case DSS_CLK_SRC_PLL1_2: 472 443 BUG_ON(dsi_module != 0); 473 444 b = 1; 474 445 break; 475 - case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI: 446 + case DSS_CLK_SRC_PLL2_2: 476 447 BUG_ON(dsi_module != 1); 477 448 b = 1; 478 449 break; ··· 487 458 dss.dsi_clk_source[dsi_module] = clk_src; 488 459 } 489 460 490 - void dss_select_lcd_clk_source(enum omap_channel channel, 491 - enum omap_dss_clk_source clk_src) 461 + static int dss_lcd_clk_mux_dra7(enum omap_channel channel, 462 + enum dss_clk_source clk_src) 492 463 { 493 - int b, ix, pos; 464 + const u8 ctrl_bits[] = { 465 + [OMAP_DSS_CHANNEL_LCD] = 0, 466 + [OMAP_DSS_CHANNEL_LCD2] = 12, 467 + [OMAP_DSS_CHANNEL_LCD3] = 19, 468 + }; 469 + 470 + u8 ctrl_bit = ctrl_bits[channel]; 471 + int r; 472 + 473 + if (clk_src == DSS_CLK_SRC_FCK) { 474 + /* LCDx_CLK_SWITCH */ 475 + REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 476 + return -EINVAL; 477 + } 478 + 479 + r = dss_ctrl_pll_set_control_mux(clk_src, channel); 480 + if (r) 481 + return r; 482 + 483 + REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 484 + 485 + return 0; 486 + } 487 + 488 + static int dss_lcd_clk_mux_omap5(enum omap_channel channel, 489 + enum dss_clk_source clk_src) 490 + { 491 + const u8 ctrl_bits[] = { 492 + [OMAP_DSS_CHANNEL_LCD] = 0, 493 + [OMAP_DSS_CHANNEL_LCD2] = 12, 494 + [OMAP_DSS_CHANNEL_LCD3] = 19, 495 + }; 496 + const enum dss_clk_source allowed_plls[] = { 497 + [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 498 + [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_FCK, 499 + [OMAP_DSS_CHANNEL_LCD3] = DSS_CLK_SRC_PLL2_1, 500 + }; 501 + 502 + u8 ctrl_bit = ctrl_bits[channel]; 503 + 504 + if (clk_src == DSS_CLK_SRC_FCK) { 505 + /* LCDx_CLK_SWITCH */ 506 + REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 507 + return -EINVAL; 508 + } 509 + 510 + if (WARN_ON(allowed_plls[channel] != clk_src)) 511 + return -EINVAL; 512 + 513 + REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 514 + 515 + return 0; 516 + } 517 + 518 + static int dss_lcd_clk_mux_omap4(enum omap_channel channel, 519 + enum dss_clk_source clk_src) 520 + { 521 + const u8 ctrl_bits[] = { 522 + [OMAP_DSS_CHANNEL_LCD] = 0, 523 + [OMAP_DSS_CHANNEL_LCD2] = 12, 524 + }; 525 + const enum dss_clk_source allowed_plls[] = { 526 + [OMAP_DSS_CHANNEL_LCD] = DSS_CLK_SRC_PLL1_1, 527 + [OMAP_DSS_CHANNEL_LCD2] = DSS_CLK_SRC_PLL2_1, 528 + }; 529 + 530 + u8 ctrl_bit = ctrl_bits[channel]; 531 + 532 + if (clk_src == DSS_CLK_SRC_FCK) { 533 + /* LCDx_CLK_SWITCH */ 534 + REG_FLD_MOD(DSS_CONTROL, 0, ctrl_bit, ctrl_bit); 535 + return 0; 536 + } 537 + 538 + if (WARN_ON(allowed_plls[channel] != clk_src)) 539 + return -EINVAL; 540 + 541 + REG_FLD_MOD(DSS_CONTROL, 1, ctrl_bit, ctrl_bit); 542 + 543 + return 0; 544 + } 545 + 546 + void dss_select_lcd_clk_source(enum omap_channel channel, 547 + enum dss_clk_source clk_src) 548 + { 549 + int idx = dss_get_channel_index(channel); 550 + int r; 494 551 495 552 if (!dss_has_feature(FEAT_LCD_CLK_SRC)) { 496 553 dss_select_dispc_clk_source(clk_src); 554 + dss.lcd_clk_source[idx] = clk_src; 497 555 return; 498 556 } 499 557 500 - switch (clk_src) { 501 - case OMAP_DSS_CLK_SRC_FCK: 502 - b = 0; 503 - break; 504 - case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: 505 - BUG_ON(channel != OMAP_DSS_CHANNEL_LCD); 506 - b = 1; 507 - break; 508 - case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: 509 - BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2 && 510 - channel != OMAP_DSS_CHANNEL_LCD3); 511 - b = 1; 512 - break; 513 - default: 514 - BUG(); 558 + r = dss.feat->select_lcd_source(channel, clk_src); 559 + if (r) 515 560 return; 516 - } 517 561 518 - pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 519 - (channel == OMAP_DSS_CHANNEL_LCD2 ? 12 : 19); 520 - REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ 521 - 522 - ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 523 - (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); 524 - dss.lcd_clk_source[ix] = clk_src; 562 + dss.lcd_clk_source[idx] = clk_src; 525 563 } 526 564 527 - enum omap_dss_clk_source dss_get_dispc_clk_source(void) 565 + enum dss_clk_source dss_get_dispc_clk_source(void) 528 566 { 529 567 return dss.dispc_clk_source; 530 568 } 531 569 532 - enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module) 570 + enum dss_clk_source dss_get_dsi_clk_source(int dsi_module) 533 571 { 534 572 return dss.dsi_clk_source[dsi_module]; 535 573 } 536 574 537 - enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 575 + enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel) 538 576 { 539 577 if (dss_has_feature(FEAT_LCD_CLK_SRC)) { 540 - int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 541 - (channel == OMAP_DSS_CHANNEL_LCD2 ? 1 : 2); 542 - return dss.lcd_clk_source[ix]; 578 + int idx = dss_get_channel_index(channel); 579 + return dss.lcd_clk_source[idx]; 543 580 } else { 544 581 /* LCD_CLK source is the same as DISPC_FCLK source for 545 582 * OMAP2 and OMAP3 */ ··· 954 859 .dpi_select_source = &dss_dpi_select_source_omap4, 955 860 .ports = omap2plus_ports, 956 861 .num_ports = ARRAY_SIZE(omap2plus_ports), 862 + .select_lcd_source = &dss_lcd_clk_mux_omap4, 957 863 }; 958 864 959 865 static const struct dss_features omap54xx_dss_feats = { ··· 964 868 .dpi_select_source = &dss_dpi_select_source_omap5, 965 869 .ports = omap2plus_ports, 966 870 .num_ports = ARRAY_SIZE(omap2plus_ports), 871 + .select_lcd_source = &dss_lcd_clk_mux_omap5, 967 872 }; 968 873 969 874 static const struct dss_features am43xx_dss_feats = { ··· 983 886 .dpi_select_source = &dss_dpi_select_source_dra7xx, 984 887 .ports = dra7xx_ports, 985 888 .num_ports = ARRAY_SIZE(dra7xx_ports), 889 + .select_lcd_source = &dss_lcd_clk_mux_dra7, 986 890 }; 987 891 988 892 static int dss_init_features(struct platform_device *pdev) ··· 1241 1143 /* Select DPLL */ 1242 1144 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0); 1243 1145 1244 - dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); 1146 + dss_select_dispc_clk_source(DSS_CLK_SRC_FCK); 1245 1147 1246 1148 #ifdef CONFIG_OMAP2_DSS_VENC 1247 1149 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */ 1248 1150 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */ 1249 1151 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */ 1250 1152 #endif 1251 - dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; 1252 - dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; 1253 - dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK; 1254 - dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK; 1255 - dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK; 1153 + dss.dsi_clk_source[0] = DSS_CLK_SRC_FCK; 1154 + dss.dsi_clk_source[1] = DSS_CLK_SRC_FCK; 1155 + dss.dispc_clk_source = DSS_CLK_SRC_FCK; 1156 + dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK; 1157 + dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK; 1256 1158 1257 1159 rev = dss_read_reg(DSS_REVISION); 1258 1160 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
+35 -10
drivers/gpu/drm/omapdrm/dss/dss.h
··· 102 102 DSS_WB_LCD3_MGR = 7, 103 103 }; 104 104 105 + enum dss_clk_source { 106 + DSS_CLK_SRC_FCK = 0, 107 + 108 + DSS_CLK_SRC_PLL1_1, 109 + DSS_CLK_SRC_PLL1_2, 110 + DSS_CLK_SRC_PLL1_3, 111 + 112 + DSS_CLK_SRC_PLL2_1, 113 + DSS_CLK_SRC_PLL2_2, 114 + DSS_CLK_SRC_PLL2_3, 115 + 116 + DSS_CLK_SRC_HDMI_PLL, 117 + }; 118 + 105 119 enum dss_pll_id { 106 120 DSS_PLL_DSI1, 107 121 DSS_PLL_DSI2, ··· 127 113 struct dss_pll; 128 114 129 115 #define DSS_PLL_MAX_HSDIVS 4 116 + 117 + enum dss_pll_type { 118 + DSS_PLL_TYPE_A, 119 + DSS_PLL_TYPE_B, 120 + }; 130 121 131 122 /* 132 123 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7. ··· 159 140 }; 160 141 161 142 struct dss_pll_hw { 143 + enum dss_pll_type type; 144 + 162 145 unsigned n_max; 163 146 unsigned m_min; 164 147 unsigned m_max; ··· 248 227 int dss_dpi_select_source(int port, enum omap_channel channel); 249 228 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select); 250 229 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void); 251 - const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src); 230 + const char *dss_get_clk_source_name(enum dss_clk_source clk_src); 252 231 void dss_dump_clocks(struct seq_file *s); 253 232 254 233 /* DSS VIDEO PLL */ ··· 265 244 #endif 266 245 267 246 void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable); 268 - void dss_ctrl_pll_set_control_mux(enum dss_pll_id pll_id, 269 - enum omap_channel channel); 270 247 271 248 void dss_sdi_init(int datapairs); 272 249 int dss_sdi_enable(void); 273 250 void dss_sdi_disable(void); 274 251 275 252 void dss_select_dsi_clk_source(int dsi_module, 276 - enum omap_dss_clk_source clk_src); 253 + enum dss_clk_source clk_src); 277 254 void dss_select_lcd_clk_source(enum omap_channel channel, 278 - enum omap_dss_clk_source clk_src); 279 - enum omap_dss_clk_source dss_get_dispc_clk_source(void); 280 - enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module); 281 - enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 255 + enum dss_clk_source clk_src); 256 + enum dss_clk_source dss_get_dispc_clk_source(void); 257 + enum dss_clk_source dss_get_dsi_clk_source(int dsi_module); 258 + enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel); 282 259 283 260 void dss_set_venc_output(enum omap_dss_venc_type type); 284 261 void dss_set_dac_pwrdn_bgz(bool enable); ··· 428 409 int dss_pll_register(struct dss_pll *pll); 429 410 void dss_pll_unregister(struct dss_pll *pll); 430 411 struct dss_pll *dss_pll_find(const char *name); 412 + struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src); 413 + unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src); 431 414 int dss_pll_enable(struct dss_pll *pll); 432 415 void dss_pll_disable(struct dss_pll *pll); 433 416 int dss_pll_set_config(struct dss_pll *pll, 434 417 const struct dss_pll_clock_info *cinfo); 435 418 436 - bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, 419 + bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 437 420 unsigned long out_min, unsigned long out_max, 438 421 dss_hsdiv_calc_func func, void *data); 439 - bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, 422 + bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 440 423 unsigned long pll_min, unsigned long pll_max, 441 424 dss_pll_calc_func func, void *data); 425 + 426 + bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 427 + unsigned long target_clkout, struct dss_pll_clock_info *cinfo); 428 + 442 429 int dss_pll_write_config_type_a(struct dss_pll *pll, 443 430 const struct dss_pll_clock_info *cinfo); 444 431 int dss_pll_write_config_type_b(struct dss_pll *pll,
-43
drivers/gpu/drm/omapdrm/dss/dss_features.c
··· 50 50 const enum omap_dss_output_id *supported_outputs; 51 51 const enum omap_color_mode *supported_color_modes; 52 52 const enum omap_overlay_caps *overlay_caps; 53 - const char * const *clksrc_names; 54 53 const struct dss_param_range *dss_params; 55 54 56 55 const enum omap_dss_rotation_type supported_rotation_types; ··· 388 389 OMAP_DSS_OVL_CAP_POS | OMAP_DSS_OVL_CAP_REPLICATION, 389 390 }; 390 391 391 - static const char * const omap2_dss_clk_source_names[] = { 392 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A", 393 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A", 394 - [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1", 395 - }; 396 - 397 - static const char * const omap3_dss_clk_source_names[] = { 398 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK", 399 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK", 400 - [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK", 401 - }; 402 - 403 - static const char * const omap4_dss_clk_source_names[] = { 404 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1", 405 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2", 406 - [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK", 407 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1", 408 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2", 409 - }; 410 - 411 - static const char * const omap5_dss_clk_source_names[] = { 412 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DPLL_DSI1_A_CLK1", 413 - [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DPLL_DSI1_A_CLK2", 414 - [OMAP_DSS_CLK_SRC_FCK] = "DSS_CLK", 415 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "DPLL_DSI1_C_CLK1", 416 - [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "DPLL_DSI1_C_CLK2", 417 - }; 418 - 419 392 static const struct dss_param_range omap2_dss_param_range[] = { 420 393 [FEAT_PARAM_DSS_FCK] = { 0, 133000000 }, 421 394 [FEAT_PARAM_DSS_PCD] = { 2, 255 }, ··· 602 631 .supported_outputs = omap2_dss_supported_outputs, 603 632 .supported_color_modes = omap2_dss_supported_color_modes, 604 633 .overlay_caps = omap2_dss_overlay_caps, 605 - .clksrc_names = omap2_dss_clk_source_names, 606 634 .dss_params = omap2_dss_param_range, 607 635 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, 608 636 .buffer_size_unit = 1, ··· 622 652 .supported_outputs = omap3430_dss_supported_outputs, 623 653 .supported_color_modes = omap3_dss_supported_color_modes, 624 654 .overlay_caps = omap3430_dss_overlay_caps, 625 - .clksrc_names = omap3_dss_clk_source_names, 626 655 .dss_params = omap3_dss_param_range, 627 656 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, 628 657 .buffer_size_unit = 1, ··· 645 676 .supported_outputs = omap3430_dss_supported_outputs, 646 677 .supported_color_modes = omap3_dss_supported_color_modes, 647 678 .overlay_caps = omap3430_dss_overlay_caps, 648 - .clksrc_names = omap3_dss_clk_source_names, 649 679 .dss_params = omap3_dss_param_range, 650 680 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, 651 681 .buffer_size_unit = 1, ··· 664 696 .supported_outputs = am43xx_dss_supported_outputs, 665 697 .supported_color_modes = omap3_dss_supported_color_modes, 666 698 .overlay_caps = omap3430_dss_overlay_caps, 667 - .clksrc_names = omap2_dss_clk_source_names, 668 699 .dss_params = am43xx_dss_param_range, 669 700 .supported_rotation_types = OMAP_DSS_ROT_DMA, 670 701 .buffer_size_unit = 1, ··· 683 716 .supported_outputs = omap3630_dss_supported_outputs, 684 717 .supported_color_modes = omap3_dss_supported_color_modes, 685 718 .overlay_caps = omap3630_dss_overlay_caps, 686 - .clksrc_names = omap3_dss_clk_source_names, 687 719 .dss_params = omap3_dss_param_range, 688 720 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_VRFB, 689 721 .buffer_size_unit = 1, ··· 704 738 .supported_outputs = omap4_dss_supported_outputs, 705 739 .supported_color_modes = omap4_dss_supported_color_modes, 706 740 .overlay_caps = omap4_dss_overlay_caps, 707 - .clksrc_names = omap4_dss_clk_source_names, 708 741 .dss_params = omap4_dss_param_range, 709 742 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, 710 743 .buffer_size_unit = 16, ··· 724 759 .supported_outputs = omap4_dss_supported_outputs, 725 760 .supported_color_modes = omap4_dss_supported_color_modes, 726 761 .overlay_caps = omap4_dss_overlay_caps, 727 - .clksrc_names = omap4_dss_clk_source_names, 728 762 .dss_params = omap4_dss_param_range, 729 763 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, 730 764 .buffer_size_unit = 16, ··· 744 780 .supported_outputs = omap4_dss_supported_outputs, 745 781 .supported_color_modes = omap4_dss_supported_color_modes, 746 782 .overlay_caps = omap4_dss_overlay_caps, 747 - .clksrc_names = omap4_dss_clk_source_names, 748 783 .dss_params = omap4_dss_param_range, 749 784 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, 750 785 .buffer_size_unit = 16, ··· 764 801 .supported_outputs = omap5_dss_supported_outputs, 765 802 .supported_color_modes = omap4_dss_supported_color_modes, 766 803 .overlay_caps = omap4_dss_overlay_caps, 767 - .clksrc_names = omap5_dss_clk_source_names, 768 804 .dss_params = omap5_dss_param_range, 769 805 .supported_rotation_types = OMAP_DSS_ROT_DMA | OMAP_DSS_ROT_TILER, 770 806 .buffer_size_unit = 16, ··· 819 857 { 820 858 return omap_current_dss_features->supported_color_modes[plane] & 821 859 color_mode; 822 - } 823 - 824 - const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id) 825 - { 826 - return omap_current_dss_features->clksrc_names[id]; 827 860 } 828 861 829 862 u32 dss_feat_get_buffer_size_unit(void)
-1
drivers/gpu/drm/omapdrm/dss/dss_features.h
··· 91 91 enum omap_overlay_caps dss_feat_get_overlay_caps(enum omap_plane plane); 92 92 bool dss_feat_color_mode_supported(enum omap_plane plane, 93 93 enum omap_color_mode color_mode); 94 - const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id); 95 94 96 95 u32 dss_feat_get_buffer_size_unit(void); /* in bytes */ 97 96 u32 dss_feat_get_burst_size_unit(void); /* in bytes */
+1 -2
drivers/gpu/drm/omapdrm/dss/hdmi.h
··· 240 240 241 241 void __iomem *base; 242 242 243 + struct platform_device *pdev; 243 244 struct hdmi_wp_data *wp; 244 245 }; 245 246 ··· 307 306 308 307 /* HDMI PLL funcs */ 309 308 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s); 310 - void hdmi_pll_compute(struct hdmi_pll_data *pll, 311 - unsigned long target_tmds, struct dss_pll_clock_info *pi); 312 309 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll, 313 310 struct hdmi_wp_data *wp); 314 311 void hdmi_pll_uninit(struct hdmi_pll_data *hpll);
+5 -1
drivers/gpu/drm/omapdrm/dss/hdmi4.c
··· 177 177 if (p->double_pixel) 178 178 pc *= 2; 179 179 180 - hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo); 180 + /* DSS_HDMI_TCLK is bitclk / 10 */ 181 + pc *= 10; 182 + 183 + dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), 184 + pc, &hdmi_cinfo); 181 185 182 186 r = dss_pll_enable(&hdmi.pll.pll); 183 187 if (r) {
+5 -1
drivers/gpu/drm/omapdrm/dss/hdmi5.c
··· 190 190 if (p->double_pixel) 191 191 pc *= 2; 192 192 193 - hdmi_pll_compute(&hdmi.pll, pc, &hdmi_cinfo); 193 + /* DSS_HDMI_TCLK is bitclk / 10 */ 194 + pc *= 10; 195 + 196 + dss_pll_calc_b(&hdmi.pll.pll, clk_get_rate(hdmi.pll.pll.clkin), 197 + pc, &hdmi_cinfo); 194 198 195 199 /* disable and clear irqs */ 196 200 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
+14 -61
drivers/gpu/drm/omapdrm/dss/hdmi_pll.c
··· 17 17 #include <linux/platform_device.h> 18 18 #include <linux/clk.h> 19 19 #include <linux/seq_file.h> 20 + #include <linux/pm_runtime.h> 20 21 21 22 #include <video/omapdss.h> 22 23 ··· 40 39 DUMPPLL(PLLCTRL_CFG4); 41 40 } 42 41 43 - void hdmi_pll_compute(struct hdmi_pll_data *pll, 44 - unsigned long target_tmds, struct dss_pll_clock_info *pi) 45 - { 46 - unsigned long fint, clkdco, clkout; 47 - unsigned long target_bitclk, target_clkdco; 48 - unsigned long min_dco; 49 - unsigned n, m, mf, m2, sd; 50 - unsigned long clkin; 51 - const struct dss_pll_hw *hw = pll->pll.hw; 52 - 53 - clkin = clk_get_rate(pll->pll.clkin); 54 - 55 - DSSDBG("clkin %lu, target tmds %lu\n", clkin, target_tmds); 56 - 57 - target_bitclk = target_tmds * 10; 58 - 59 - /* Fint */ 60 - n = DIV_ROUND_UP(clkin, hw->fint_max); 61 - fint = clkin / n; 62 - 63 - /* adjust m2 so that the clkdco will be high enough */ 64 - min_dco = roundup(hw->clkdco_min, fint); 65 - m2 = DIV_ROUND_UP(min_dco, target_bitclk); 66 - if (m2 == 0) 67 - m2 = 1; 68 - 69 - target_clkdco = target_bitclk * m2; 70 - m = target_clkdco / fint; 71 - 72 - clkdco = fint * m; 73 - 74 - /* adjust clkdco with fractional mf */ 75 - if (WARN_ON(target_clkdco - clkdco > fint)) 76 - mf = 0; 77 - else 78 - mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); 79 - 80 - if (mf > 0) 81 - clkdco += (u32)div_u64((u64)mf * fint, 262144); 82 - 83 - clkout = clkdco / m2; 84 - 85 - /* sigma-delta */ 86 - sd = DIV_ROUND_UP(fint * m, 250000000); 87 - 88 - DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", 89 - n, m, mf, m2, sd); 90 - DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); 91 - 92 - pi->n = n; 93 - pi->m = m; 94 - pi->mf = mf; 95 - pi->mX[0] = m2; 96 - pi->sd = sd; 97 - 98 - pi->fint = fint; 99 - pi->clkdco = clkdco; 100 - pi->clkout[0] = clkout; 101 - } 102 - 103 42 static int hdmi_pll_enable(struct dss_pll *dsspll) 104 43 { 105 44 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); 106 45 struct hdmi_wp_data *wp = pll->wp; 107 - u16 r = 0; 46 + int r; 47 + 48 + r = pm_runtime_get_sync(&pll->pdev->dev); 49 + WARN_ON(r < 0); 108 50 109 51 dss_ctrl_pll_enable(DSS_PLL_HDMI, true); 110 52 ··· 62 118 { 63 119 struct hdmi_pll_data *pll = container_of(dsspll, struct hdmi_pll_data, pll); 64 120 struct hdmi_wp_data *wp = pll->wp; 121 + int r; 65 122 66 123 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); 67 124 68 125 dss_ctrl_pll_enable(DSS_PLL_HDMI, false); 126 + 127 + r = pm_runtime_put_sync(&pll->pdev->dev); 128 + WARN_ON(r < 0 && r != -ENOSYS); 69 129 } 70 130 71 131 static const struct dss_pll_ops dsi_pll_ops = { ··· 79 131 }; 80 132 81 133 static const struct dss_pll_hw dss_omap4_hdmi_pll_hw = { 134 + .type = DSS_PLL_TYPE_B, 135 + 82 136 .n_max = 255, 83 137 .m_min = 20, 84 138 .m_max = 4095, ··· 104 154 }; 105 155 106 156 static const struct dss_pll_hw dss_omap5_hdmi_pll_hw = { 157 + .type = DSS_PLL_TYPE_B, 158 + 107 159 .n_max = 255, 108 160 .m_min = 20, 109 161 .m_max = 2045, ··· 177 225 int r; 178 226 struct resource *res; 179 227 228 + pll->pdev = pdev; 180 229 pll->wp = wp; 181 230 182 231 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
+124 -2
drivers/gpu/drm/omapdrm/dss/pll.c
··· 76 76 return NULL; 77 77 } 78 78 79 + struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src) 80 + { 81 + struct dss_pll *pll; 82 + 83 + switch (src) { 84 + default: 85 + case DSS_CLK_SRC_FCK: 86 + return NULL; 87 + 88 + case DSS_CLK_SRC_HDMI_PLL: 89 + return dss_pll_find("hdmi"); 90 + 91 + case DSS_CLK_SRC_PLL1_1: 92 + case DSS_CLK_SRC_PLL1_2: 93 + case DSS_CLK_SRC_PLL1_3: 94 + pll = dss_pll_find("dsi0"); 95 + if (!pll) 96 + pll = dss_pll_find("video0"); 97 + return pll; 98 + 99 + case DSS_CLK_SRC_PLL2_1: 100 + case DSS_CLK_SRC_PLL2_2: 101 + case DSS_CLK_SRC_PLL2_3: 102 + pll = dss_pll_find("dsi1"); 103 + if (!pll) 104 + pll = dss_pll_find("video1"); 105 + return pll; 106 + } 107 + } 108 + 109 + unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src) 110 + { 111 + switch (src) { 112 + case DSS_CLK_SRC_HDMI_PLL: 113 + return 0; 114 + 115 + case DSS_CLK_SRC_PLL1_1: 116 + case DSS_CLK_SRC_PLL2_1: 117 + return 0; 118 + 119 + case DSS_CLK_SRC_PLL1_2: 120 + case DSS_CLK_SRC_PLL2_2: 121 + return 1; 122 + 123 + case DSS_CLK_SRC_PLL1_3: 124 + case DSS_CLK_SRC_PLL2_3: 125 + return 2; 126 + 127 + default: 128 + return 0; 129 + } 130 + } 131 + 79 132 int dss_pll_enable(struct dss_pll *pll) 80 133 { 81 134 int r; ··· 182 129 return 0; 183 130 } 184 131 185 - bool dss_pll_hsdiv_calc(const struct dss_pll *pll, unsigned long clkdco, 132 + bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco, 186 133 unsigned long out_min, unsigned long out_max, 187 134 dss_hsdiv_calc_func func, void *data) 188 135 { ··· 207 154 return false; 208 155 } 209 156 210 - bool dss_pll_calc(const struct dss_pll *pll, unsigned long clkin, 157 + /* 158 + * clkdco = clkin / n * m * 2 159 + * clkoutX = clkdco / mX 160 + */ 161 + bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin, 211 162 unsigned long pll_min, unsigned long pll_max, 212 163 dss_pll_calc_func func, void *data) 213 164 { ··· 250 193 } 251 194 252 195 return false; 196 + } 197 + 198 + /* 199 + * This calculates a PLL config that will provide the target_clkout rate 200 + * for clkout. Additionally clkdco rate will be the same as clkout rate 201 + * when clkout rate is >= min_clkdco. 202 + * 203 + * clkdco = clkin / n * m + clkin / n * mf / 262144 204 + * clkout = clkdco / m2 205 + */ 206 + bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin, 207 + unsigned long target_clkout, struct dss_pll_clock_info *cinfo) 208 + { 209 + unsigned long fint, clkdco, clkout; 210 + unsigned long target_clkdco; 211 + unsigned long min_dco; 212 + unsigned n, m, mf, m2, sd; 213 + const struct dss_pll_hw *hw = pll->hw; 214 + 215 + DSSDBG("clkin %lu, target clkout %lu\n", clkin, target_clkout); 216 + 217 + /* Fint */ 218 + n = DIV_ROUND_UP(clkin, hw->fint_max); 219 + fint = clkin / n; 220 + 221 + /* adjust m2 so that the clkdco will be high enough */ 222 + min_dco = roundup(hw->clkdco_min, fint); 223 + m2 = DIV_ROUND_UP(min_dco, target_clkout); 224 + if (m2 == 0) 225 + m2 = 1; 226 + 227 + target_clkdco = target_clkout * m2; 228 + m = target_clkdco / fint; 229 + 230 + clkdco = fint * m; 231 + 232 + /* adjust clkdco with fractional mf */ 233 + if (WARN_ON(target_clkdco - clkdco > fint)) 234 + mf = 0; 235 + else 236 + mf = (u32)div_u64(262144ull * (target_clkdco - clkdco), fint); 237 + 238 + if (mf > 0) 239 + clkdco += (u32)div_u64((u64)mf * fint, 262144); 240 + 241 + clkout = clkdco / m2; 242 + 243 + /* sigma-delta */ 244 + sd = DIV_ROUND_UP(fint * m, 250000000); 245 + 246 + DSSDBG("N = %u, M = %u, M.f = %u, M2 = %u, SD = %u\n", 247 + n, m, mf, m2, sd); 248 + DSSDBG("Fint %lu, clkdco %lu, clkout %lu\n", fint, clkdco, clkout); 249 + 250 + cinfo->n = n; 251 + cinfo->m = m; 252 + cinfo->mf = mf; 253 + cinfo->mX[0] = m2; 254 + cinfo->sd = sd; 255 + 256 + cinfo->fint = fint; 257 + cinfo->clkdco = clkdco; 258 + cinfo->clkout[0] = clkout; 259 + 260 + return true; 253 261 } 254 262 255 263 static int wait_for_bit_change(void __iomem *reg, int bitnum, int value)
+6
drivers/gpu/drm/omapdrm/dss/video-pll.c
··· 108 108 }; 109 109 110 110 static const struct dss_pll_hw dss_dra7_video_pll_hw = { 111 + .type = DSS_PLL_TYPE_A, 112 + 111 113 .n_max = (1 << 8) - 1, 112 114 .m_max = (1 << 12) - 1, 113 115 .mX_max = (1 << 5) - 1, ··· 126 124 .mX_lsb[0] = 21, 127 125 .mX_msb[1] = 30, 128 126 .mX_lsb[1] = 26, 127 + .mX_msb[2] = 4, 128 + .mX_lsb[2] = 0, 129 + .mX_msb[3] = 9, 130 + .mX_lsb[3] = 5, 129 131 130 132 .has_refsel = true, 131 133 };
+11
drivers/video/fbdev/omap2/omapfb/dss/dss.h
··· 73 73 #define FLD_MOD(orig, val, start, end) \ 74 74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end)) 75 75 76 + enum omap_dss_clk_source { 77 + OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 78 + * OMAP4: DSS_FCLK */ 79 + OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 80 + * OMAP4: PLL1_CLK1 */ 81 + OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 82 + * OMAP4: PLL1_CLK2 */ 83 + OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 84 + OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 85 + }; 86 + 76 87 enum dss_io_pad_mode { 77 88 DSS_IO_PAD_MODE_RESET, 78 89 DSS_IO_PAD_MODE_RFBI,
-1
drivers/video/fbdev/omap2/omapfb/dss/manager.c
··· 69 69 break; 70 70 } 71 71 72 - mgr->caps = 0; 73 72 mgr->supported_displays = 74 73 dss_feat_get_supported_displays(mgr->id); 75 74 mgr->supported_outputs =
-20
include/video/omapdss.h
··· 195 195 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5, 196 196 }; 197 197 198 - enum omap_overlay_manager_caps { 199 - OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */ 200 - }; 201 - 202 - enum omap_dss_clk_source { 203 - OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK 204 - * OMAP4: DSS_FCLK */ 205 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK 206 - * OMAP4: PLL1_CLK1 */ 207 - OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK 208 - * OMAP4: PLL1_CLK2 */ 209 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */ 210 - OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */ 211 - }; 212 - 213 - enum omap_hdmi_flags { 214 - OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0, 215 - }; 216 - 217 198 enum omap_dss_output_id { 218 199 OMAP_DSS_OUTPUT_DPI = 1 << 0, 219 200 OMAP_DSS_OUTPUT_DBI = 1 << 1, ··· 444 463 /* static fields */ 445 464 const char *name; 446 465 enum omap_channel id; 447 - enum omap_overlay_manager_caps caps; 448 466 struct list_head overlays; 449 467 enum omap_display_type supported_displays; 450 468 enum omap_dss_output_id supported_outputs;