tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
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MIPS: Alchemy: au1200fb: use clk framework

minimal patch to replace direct clock register hackery with clock
framework calls.

Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Patchwork: https://patchwork.linux-mips.org/patch/7472/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

authored by

Manuel Lauss and committed by
Ralf Baechle ecc2ea3b 6b1889c1

+23 -27
+23 -27
drivers/video/fbdev/au1200fb.c
··· 30 30 * 675 Mass Ave, Cambridge, MA 02139, USA. 31 31 */ 32 32 33 + #include <linux/clk.h> 33 34 #include <linux/module.h> 34 35 #include <linux/platform_device.h> 35 36 #include <linux/kernel.h> ··· 331 330 uint32 mode_pwmhi; 332 331 uint32 mode_outmask; 333 332 uint32 mode_fifoctrl; 334 - uint32 mode_toyclksrc; 335 333 uint32 mode_backlight; 336 - uint32 mode_auxpll; 334 + uint32 lcdclk; 337 335 #define Xres min_xres 338 336 #define Yres min_yres 339 337 u32 min_xres; /* Minimum horizontal resolution */ ··· 379 379 .mode_pwmhi = 0x00000000, 380 380 .mode_outmask = 0x00FFFFFF, 381 381 .mode_fifoctrl = 0x2f2f2f2f, 382 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 383 382 .mode_backlight = 0x00000000, 384 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 383 + .lcdclk = 96, 385 384 320, 320, 386 385 240, 240, 387 386 }, ··· 406 407 .mode_pwmhi = 0x00000000, 407 408 .mode_outmask = 0x00FFFFFF, 408 409 .mode_fifoctrl = 0x2f2f2f2f, 409 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 410 410 .mode_backlight = 0x00000000, 411 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 411 + .lcdclk = 96, 412 412 640, 480, 413 413 640, 480, 414 414 }, ··· 433 435 .mode_pwmhi = 0x00000000, 434 436 .mode_outmask = 0x00FFFFFF, 435 437 .mode_fifoctrl = 0x2f2f2f2f, 436 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 437 438 .mode_backlight = 0x00000000, 438 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 439 + .lcdclk = 96, 439 440 800, 800, 440 441 600, 600, 441 442 }, ··· 460 463 .mode_pwmhi = 0x00000000, 461 464 .mode_outmask = 0x00FFFFFF, 462 465 .mode_fifoctrl = 0x2f2f2f2f, 463 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 464 466 .mode_backlight = 0x00000000, 465 - .mode_auxpll = 6, /* 72MHz AUXPLL */ 467 + .lcdclk = 72, 466 468 1024, 1024, 467 469 768, 768, 468 470 }, ··· 487 491 .mode_pwmhi = 0x00000000, 488 492 .mode_outmask = 0x00FFFFFF, 489 493 .mode_fifoctrl = 0x2f2f2f2f, 490 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 491 494 .mode_backlight = 0x00000000, 492 - .mode_auxpll = 10, /* 120MHz AUXPLL */ 495 + .lcdclk = 120, 493 496 1280, 1280, 494 497 1024, 1024, 495 498 }, ··· 514 519 .mode_pwmhi = 0x03400000, /* SCB 0x0 */ 515 520 .mode_outmask = 0x00FFFFFF, 516 521 .mode_fifoctrl = 0x2f2f2f2f, 517 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 518 522 .mode_backlight = 0x00000000, 519 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 523 + .lcdclk = 96, 520 524 1024, 1024, 521 525 768, 768, 522 526 }, ··· 544 550 .mode_pwmhi = 0x03400000, 545 551 .mode_outmask = 0x00fcfcfc, 546 552 .mode_fifoctrl = 0x2f2f2f2f, 547 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 548 553 .mode_backlight = 0x00000000, 549 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 554 + .lcdclk = 96, 550 555 640, 480, 551 556 640, 480, 552 557 }, ··· 574 581 .mode_pwmhi = 0x03400000, 575 582 .mode_outmask = 0x00fcfcfc, 576 583 .mode_fifoctrl = 0x2f2f2f2f, 577 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 578 584 .mode_backlight = 0x00000000, 579 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 585 + .lcdclk = 96, /* 96MHz AUXPLL */ 580 586 320, 320, 581 587 240, 240, 582 588 }, ··· 604 612 .mode_pwmhi = 0x03400000, 605 613 .mode_outmask = 0x00fcfcfc, 606 614 .mode_fifoctrl = 0x2f2f2f2f, 607 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 608 615 .mode_backlight = 0x00000000, 609 - .mode_auxpll = 8, /* 96MHz AUXPLL */ 616 + .lcdclk = 96, 610 617 856, 856, 611 618 480, 480, 612 619 }, ··· 637 646 .mode_pwmhi = 0x00000000, 638 647 .mode_outmask = 0x00FFFFFF, 639 648 .mode_fifoctrl = 0x2f2f2f2f, 640 - .mode_toyclksrc = 0x00000004, /* AUXPLL directly */ 641 649 .mode_backlight = 0x00000000, 642 - .mode_auxpll = (48/12) * 2, 650 + .lcdclk = 96, 643 651 800, 800, 644 652 480, 480, 645 653 }, ··· 818 828 */ 819 829 if (!(panel->mode_clkcontrol & LCD_CLKCONTROL_EXT)) 820 830 { 821 - uint32 sys_clksrc; 822 - alchemy_wrsys(panel->mode_auxpll, AU1000_SYS_AUXPLL); 823 - sys_clksrc = alchemy_rdsys(AU1000_SYS_CLKSRC) & ~0x0000001f; 824 - sys_clksrc |= panel->mode_toyclksrc; 825 - alchemy_wrsys(sys_clksrc, AU1000_SYS_CLKSRC); 831 + struct clk *c = clk_get(NULL, "lcd_intclk"); 832 + long r, pc = panel->lcdclk * 1000000; 833 + 834 + if (!IS_ERR(c)) { 835 + r = clk_round_rate(c, pc); 836 + if ((pc - r) < (pc / 10)) { /* 10% slack */ 837 + clk_set_rate(c, r); 838 + clk_prepare_enable(c); 839 + } 840 + clk_put(c); 841 + } 826 842 } 827 843 828 844 /*