tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: mediatek: add mt7986 clock support
Add MT7986 clock support, include topckgen, apmixedsys,
infracfg, and ethernet subsystem clocks.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20211217121148.6753-4-sam.shih@mediatek.com
Reviewed-by: Ryder Lee <ryder.lee@kernel.org>
[sboyd@kernel.org: Fix typos in Kconfig, there are more existing typos
from where they were copied from of but whatever]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
authored by
Sam Shih
and committed by
Stephen Boyd
ec97d23c
4470c830
+819
+17
drivers/clk/mediatek/Kconfig
+17
drivers/clk/mediatek/Kconfig
···
344
344
This driver supports MediaTek MT7629 HIFSYS clocks providing
345
345
to PCI-E and USB.
346
346
347
+
config COMMON_CLK_MT7986
348
+
bool "Clock driver for MediaTek MT7986"
349
+
depends on ARCH_MEDIATEK || COMPILE_TEST
350
+
select COMMON_CLK_MEDIATEK
351
+
default ARCH_MEDIATEK
352
+
help
353
+
This driver supports MediaTek MT7986 basic clocks and clocks
354
+
required for various peripherals found on MediaTek.
355
+
356
+
config COMMON_CLK_MT7986_ETHSYS
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bool "Clock driver for MediaTek MT7986 ETHSYS"
358
+
depends on COMMON_CLK_MT7986
359
+
default COMMON_CLK_MT7986
360
+
help
361
+
This driver adds support for clocks for Ethernet and SGMII
362
+
required on MediaTek MT7986 SoC.
363
+
347
364
config COMMON_CLK_MT8135
348
365
bool "Clock driver for MediaTek MT8135"
349
366
depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST
+4
drivers/clk/mediatek/Makefile
+4
drivers/clk/mediatek/Makefile
···
46
46
obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o
47
47
obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
48
48
obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
49
+
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
50
+
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
51
+
obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
52
+
obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
49
53
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
50
54
obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167.o
51
55
obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o
+100
drivers/clk/mediatek/clk-mt7986-apmixed.c
+100
drivers/clk/mediatek/clk-mt7986-apmixed.c
···
1
+
// SPDX-License-Identifier: GPL-1.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Author: Sam Shih <sam.shih@mediatek.com>
5
+
* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_address.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/platform_device.h>
13
+
#include "clk-mtk.h"
14
+
#include "clk-gate.h"
15
+
#include "clk-mux.h"
16
+
17
+
#include <dt-bindings/clock/mt7986-clk.h>
18
+
#include <linux/clk.h>
19
+
20
+
#define MT7986_PLL_FMAX (2500UL * MHZ)
21
+
#define CON0_MT7986_RST_BAR BIT(27)
22
+
23
+
#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
24
+
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, \
25
+
_div_table, _parent_name) \
26
+
{ \
27
+
.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg, \
28
+
.en_mask = _en_mask, .flags = _flags, \
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+
.rst_bar_mask = CON0_MT7986_RST_BAR, .fmax = MT7986_PLL_FMAX, \
30
+
.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \
31
+
.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg, \
32
+
.pcw_shift = _pcw_shift, .div_table = _div_table, \
33
+
.parent_name = _parent_name, \
34
+
}
35
+
36
+
#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
37
+
_pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) \
38
+
PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \
39
+
_pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL, \
40
+
"clkxtal")
41
+
42
+
static const struct mtk_pll_data plls[] = {
43
+
PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, 0, 32,
44
+
0x0200, 4, 0, 0x0204, 0),
45
+
PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,
46
+
0x0210, 4, 0, 0x0214, 0),
47
+
PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,
48
+
0x0220, 4, 0, 0x0224, 0),
49
+
PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023c, 0x00000001, 0, 32,
50
+
0x0230, 4, 0, 0x0234, 0),
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+
PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024c, 0x00000001, 0,
52
+
32, 0x0240, 4, 0, 0x0244, 0),
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+
PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025c, 0x00000001, 0, 32,
54
+
0x0250, 4, 0, 0x0254, 0),
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+
PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32, 0x0260,
56
+
4, 0, 0x0264, 0),
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+
PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,
58
+
0x0278, 4, 0, 0x027c, 0),
59
+
};
60
+
61
+
static const struct of_device_id of_match_clk_mt7986_apmixed[] = {
62
+
{ .compatible = "mediatek,mt7986-apmixedsys", },
63
+
{}
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+
};
65
+
66
+
static int clk_mt7986_apmixed_probe(struct platform_device *pdev)
67
+
{
68
+
struct clk_onecell_data *clk_data;
69
+
struct device_node *node = pdev->dev.of_node;
70
+
int r;
71
+
72
+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
73
+
if (!clk_data)
74
+
return -ENOMEM;
75
+
76
+
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
77
+
78
+
clk_prepare_enable(clk_data->clks[CLK_APMIXED_ARMPLL]);
79
+
80
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
81
+
if (r) {
82
+
pr_err("%s(): could not register clock provider: %d\n",
83
+
__func__, r);
84
+
goto free_apmixed_data;
85
+
}
86
+
return r;
87
+
88
+
free_apmixed_data:
89
+
mtk_free_clk_data(clk_data);
90
+
return r;
91
+
}
92
+
93
+
static struct platform_driver clk_mt7986_apmixed_drv = {
94
+
.probe = clk_mt7986_apmixed_probe,
95
+
.driver = {
96
+
.name = "clk-mt7986-apmixed",
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+
.of_match_table = of_match_clk_mt7986_apmixed,
98
+
},
99
+
};
100
+
builtin_platform_driver(clk_mt7986_apmixed_drv);
+132
drivers/clk/mediatek/clk-mt7986-eth.c
+132
drivers/clk/mediatek/clk-mt7986-eth.c
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Author: Sam Shih <sam.shih@mediatek.com>
5
+
* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_address.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/platform_device.h>
13
+
14
+
#include "clk-mtk.h"
15
+
#include "clk-gate.h"
16
+
17
+
#include <dt-bindings/clock/mt7986-clk.h>
18
+
19
+
static const struct mtk_gate_regs sgmii0_cg_regs = {
20
+
.set_ofs = 0xe4,
21
+
.clr_ofs = 0xe4,
22
+
.sta_ofs = 0xe4,
23
+
};
24
+
25
+
#define GATE_SGMII0(_id, _name, _parent, _shift) \
26
+
{ \
27
+
.id = _id, .name = _name, .parent_name = _parent, \
28
+
.regs = &sgmii0_cg_regs, .shift = _shift, \
29
+
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
30
+
}
31
+
32
+
static const struct mtk_gate sgmii0_clks[] __initconst = {
33
+
GATE_SGMII0(CLK_SGMII0_TX250M_EN, "sgmii0_tx250m_en", "top_xtal", 2),
34
+
GATE_SGMII0(CLK_SGMII0_RX250M_EN, "sgmii0_rx250m_en", "top_xtal", 3),
35
+
GATE_SGMII0(CLK_SGMII0_CDR_REF, "sgmii0_cdr_ref", "top_xtal", 4),
36
+
GATE_SGMII0(CLK_SGMII0_CDR_FB, "sgmii0_cdr_fb", "top_xtal", 5),
37
+
};
38
+
39
+
static const struct mtk_gate_regs sgmii1_cg_regs = {
40
+
.set_ofs = 0xe4,
41
+
.clr_ofs = 0xe4,
42
+
.sta_ofs = 0xe4,
43
+
};
44
+
45
+
#define GATE_SGMII1(_id, _name, _parent, _shift) \
46
+
{ \
47
+
.id = _id, .name = _name, .parent_name = _parent, \
48
+
.regs = &sgmii1_cg_regs, .shift = _shift, \
49
+
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
50
+
}
51
+
52
+
static const struct mtk_gate sgmii1_clks[] __initconst = {
53
+
GATE_SGMII1(CLK_SGMII1_TX250M_EN, "sgmii1_tx250m_en", "top_xtal", 2),
54
+
GATE_SGMII1(CLK_SGMII1_RX250M_EN, "sgmii1_rx250m_en", "top_xtal", 3),
55
+
GATE_SGMII1(CLK_SGMII1_CDR_REF, "sgmii1_cdr_ref", "top_xtal", 4),
56
+
GATE_SGMII1(CLK_SGMII1_CDR_FB, "sgmii1_cdr_fb", "top_xtal", 5),
57
+
};
58
+
59
+
static const struct mtk_gate_regs eth_cg_regs = {
60
+
.set_ofs = 0x30,
61
+
.clr_ofs = 0x30,
62
+
.sta_ofs = 0x30,
63
+
};
64
+
65
+
#define GATE_ETH(_id, _name, _parent, _shift) \
66
+
{ \
67
+
.id = _id, .name = _name, .parent_name = _parent, \
68
+
.regs = ð_cg_regs, .shift = _shift, \
69
+
.ops = &mtk_clk_gate_ops_no_setclr_inv, \
70
+
}
71
+
72
+
static const struct mtk_gate eth_clks[] __initconst = {
73
+
GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x_sel", 6),
74
+
GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m_sel", 7),
75
+
GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m_sel", 8),
76
+
GATE_ETH(CLK_ETH_WOCPU1_EN, "eth_wocpu1_en", "netsys_mcu_sel", 14),
77
+
GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_mcu_sel", 15),
78
+
};
79
+
80
+
static void __init mtk_sgmiisys_0_init(struct device_node *node)
81
+
{
82
+
struct clk_onecell_data *clk_data;
83
+
int r;
84
+
85
+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii0_clks));
86
+
87
+
mtk_clk_register_gates(node, sgmii0_clks, ARRAY_SIZE(sgmii0_clks),
88
+
clk_data);
89
+
90
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
91
+
if (r)
92
+
pr_err("%s(): could not register clock provider: %d\n",
93
+
__func__, r);
94
+
}
95
+
CLK_OF_DECLARE(mtk_sgmiisys_0, "mediatek,mt7986-sgmiisys_0",
96
+
mtk_sgmiisys_0_init);
97
+
98
+
static void __init mtk_sgmiisys_1_init(struct device_node *node)
99
+
{
100
+
struct clk_onecell_data *clk_data;
101
+
int r;
102
+
103
+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(sgmii1_clks));
104
+
105
+
mtk_clk_register_gates(node, sgmii1_clks, ARRAY_SIZE(sgmii1_clks),
106
+
clk_data);
107
+
108
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
109
+
110
+
if (r)
111
+
pr_err("%s(): could not register clock provider: %d\n",
112
+
__func__, r);
113
+
}
114
+
CLK_OF_DECLARE(mtk_sgmiisys_1, "mediatek,mt7986-sgmiisys_1",
115
+
mtk_sgmiisys_1_init);
116
+
117
+
static void __init mtk_ethsys_init(struct device_node *node)
118
+
{
119
+
struct clk_onecell_data *clk_data;
120
+
int r;
121
+
122
+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(eth_clks));
123
+
124
+
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks), clk_data);
125
+
126
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
127
+
128
+
if (r)
129
+
pr_err("%s(): could not register clock provider: %d\n",
130
+
__func__, r);
131
+
}
132
+
CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt7986-ethsys_ck", mtk_ethsys_init);
+224
drivers/clk/mediatek/clk-mt7986-infracfg.c
+224
drivers/clk/mediatek/clk-mt7986-infracfg.c
···
1
+
// SPDX-License-Identifier: GPL-1.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Author: Sam Shih <sam.shih@mediatek.com>
5
+
* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_address.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/platform_device.h>
13
+
#include "clk-mtk.h"
14
+
#include "clk-gate.h"
15
+
#include "clk-mux.h"
16
+
17
+
#include <dt-bindings/clock/mt7986-clk.h>
18
+
#include <linux/clk.h>
19
+
20
+
static DEFINE_SPINLOCK(mt7986_clk_lock);
21
+
22
+
static const struct mtk_fixed_factor infra_divs[] = {
23
+
FACTOR(CLK_INFRA_SYSAXI_D2, "infra_sysaxi_d2", "sysaxi_sel", 1, 2),
24
+
};
25
+
26
+
static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",
27
+
"uart_sel" };
28
+
29
+
static const char *const infra_spi_parents[] __initconst = { "i2c_sel",
30
+
"spi_sel" };
31
+
32
+
static const char *const infra_pwm_bsel_parents[] __initconst = {
33
+
"top_rtc_32p7k", "csw_f26m_sel", "infra_sysaxi_d2", "pwm_sel"
34
+
};
35
+
36
+
static const char *const infra_pcie_parents[] __initconst = {
37
+
"top_rtc_32p7k", "csw_f26m_sel", "top_xtal", "pextp_tl_ck_sel"
38
+
};
39
+
40
+
static const struct mtk_mux infra_muxes[] = {
41
+
/* MODULE_CLK_SEL_0 */
42
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",
43
+
infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,
44
+
-1, -1, -1),
45
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",
46
+
infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,
47
+
-1, -1, -1),
48
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",
49
+
infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,
50
+
-1, -1, -1),
51
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",
52
+
infra_spi_parents, 0x0018, 0x0010, 0x0014, 4, 1,
53
+
-1, -1, -1),
54
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",
55
+
infra_spi_parents, 0x0018, 0x0010, 0x0014, 5, 1,
56
+
-1, -1, -1),
57
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",
58
+
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 9,
59
+
2, -1, -1, -1),
60
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",
61
+
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 11,
62
+
2, -1, -1, -1),
63
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",
64
+
infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,
65
+
2, -1, -1, -1),
66
+
/* MODULE_CLK_SEL_1 */
67
+
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",
68
+
infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,
69
+
-1, -1, -1),
70
+
};
71
+
72
+
static const struct mtk_gate_regs infra0_cg_regs = {
73
+
.set_ofs = 0x40,
74
+
.clr_ofs = 0x44,
75
+
.sta_ofs = 0x48,
76
+
};
77
+
78
+
static const struct mtk_gate_regs infra1_cg_regs = {
79
+
.set_ofs = 0x50,
80
+
.clr_ofs = 0x54,
81
+
.sta_ofs = 0x58,
82
+
};
83
+
84
+
static const struct mtk_gate_regs infra2_cg_regs = {
85
+
.set_ofs = 0x60,
86
+
.clr_ofs = 0x64,
87
+
.sta_ofs = 0x68,
88
+
};
89
+
90
+
#define GATE_INFRA0(_id, _name, _parent, _shift) \
91
+
{ \
92
+
.id = _id, .name = _name, .parent_name = _parent, \
93
+
.regs = &infra0_cg_regs, .shift = _shift, \
94
+
.ops = &mtk_clk_gate_ops_setclr, \
95
+
}
96
+
97
+
#define GATE_INFRA1(_id, _name, _parent, _shift) \
98
+
{ \
99
+
.id = _id, .name = _name, .parent_name = _parent, \
100
+
.regs = &infra1_cg_regs, .shift = _shift, \
101
+
.ops = &mtk_clk_gate_ops_setclr, \
102
+
}
103
+
104
+
#define GATE_INFRA2(_id, _name, _parent, _shift) \
105
+
{ \
106
+
.id = _id, .name = _name, .parent_name = _parent, \
107
+
.regs = &infra2_cg_regs, .shift = _shift, \
108
+
.ops = &mtk_clk_gate_ops_setclr, \
109
+
}
110
+
111
+
static const struct mtk_gate infra_clks[] = {
112
+
/* INFRA0 */
113
+
GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_sysaxi_d2", 0),
114
+
GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_sysaxi_d2", 1),
115
+
GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),
116
+
GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),
117
+
GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),
118
+
GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi_sel", 6),
119
+
GATE_INFRA0(CLK_INFRA_EIP97_CK, "infra_eip97", "eip_b_sel", 7),
120
+
GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi_sel", 8),
121
+
GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),
122
+
GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l_sel", 10),
123
+
GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys_sel", 11),
124
+
GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner_sel", 13),
125
+
GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",
126
+
14),
127
+
GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_sysaxi_d2", 15),
128
+
GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_sysaxi_d2", 16),
129
+
GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_sysaxi_d2", 24),
130
+
GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),
131
+
GATE_INFRA0(CLK_INFRA_TRNG_CK, "infra_trng", "sysaxi_sel", 26),
132
+
/* INFRA1 */
133
+
GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),
134
+
GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_sel", 1),
135
+
GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),
136
+
GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),
137
+
GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),
138
+
GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x_sel", 8),
139
+
GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_sel", 9),
140
+
GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_sysaxi_d2",
141
+
10),
142
+
GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),
143
+
GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),
144
+
GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_sysaxi_d2",
145
+
13),
146
+
GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_sysaxi_d2",
147
+
14),
148
+
GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "top_rtc_32k", 15),
149
+
GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_416m_sel", 16),
150
+
GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_250m_sel",
151
+
17),
152
+
GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi_sel",
153
+
18),
154
+
GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "infra_sysaxi_d2",
155
+
19),
156
+
GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "csw_f26m_sel", 20),
157
+
GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m_sel", 21),
158
+
GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x_sel", 23),
159
+
/* INFRA2 */
160
+
GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi_sel", 0),
161
+
GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "infra_sysaxi_d2",
162
+
1),
163
+
GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys_sel", 2),
164
+
GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_sel", 3),
165
+
GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl_ck_sel", 12),
166
+
GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "top_xtal",
167
+
13),
168
+
GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m_sel", 14),
169
+
GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi_sel", 15),
170
+
};
171
+
172
+
static int clk_mt7986_infracfg_probe(struct platform_device *pdev)
173
+
{
174
+
struct clk_onecell_data *clk_data;
175
+
struct device_node *node = pdev->dev.of_node;
176
+
int r;
177
+
void __iomem *base;
178
+
int nr = ARRAY_SIZE(infra_divs) + ARRAY_SIZE(infra_muxes) +
179
+
ARRAY_SIZE(infra_clks);
180
+
181
+
base = of_iomap(node, 0);
182
+
if (!base) {
183
+
pr_err("%s(): ioremap failed\n", __func__);
184
+
return -ENOMEM;
185
+
}
186
+
187
+
clk_data = mtk_alloc_clk_data(nr);
188
+
189
+
if (!clk_data)
190
+
return -ENOMEM;
191
+
192
+
mtk_clk_register_factors(infra_divs, ARRAY_SIZE(infra_divs), clk_data);
193
+
mtk_clk_register_muxes(infra_muxes, ARRAY_SIZE(infra_muxes), node,
194
+
&mt7986_clk_lock, clk_data);
195
+
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
196
+
clk_data);
197
+
198
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
199
+
if (r) {
200
+
pr_err("%s(): could not register clock provider: %d\n",
201
+
__func__, r);
202
+
goto free_infracfg_data;
203
+
}
204
+
return r;
205
+
206
+
free_infracfg_data:
207
+
mtk_free_clk_data(clk_data);
208
+
return r;
209
+
210
+
}
211
+
212
+
static const struct of_device_id of_match_clk_mt7986_infracfg[] = {
213
+
{ .compatible = "mediatek,mt7986-infracfg", },
214
+
{}
215
+
};
216
+
217
+
static struct platform_driver clk_mt7986_infracfg_drv = {
218
+
.probe = clk_mt7986_infracfg_probe,
219
+
.driver = {
220
+
.name = "clk-mt7986-infracfg",
221
+
.of_match_table = of_match_clk_mt7986_infracfg,
222
+
},
223
+
};
224
+
builtin_platform_driver(clk_mt7986_infracfg_drv);
+342
drivers/clk/mediatek/clk-mt7986-topckgen.c
+342
drivers/clk/mediatek/clk-mt7986-topckgen.c
···
1
+
// SPDX-License-Identifier: GPL-1.0
2
+
/*
3
+
* Copyright (c) 2021 MediaTek Inc.
4
+
* Author: Sam Shih <sam.shih@mediatek.com>
5
+
* Author: Wenzhen Yu <wenzhen.yu@mediatek.com>
6
+
*/
7
+
8
+
#include <linux/clk-provider.h>
9
+
#include <linux/of.h>
10
+
#include <linux/of_address.h>
11
+
#include <linux/of_device.h>
12
+
#include <linux/platform_device.h>
13
+
#include "clk-mtk.h"
14
+
#include "clk-gate.h"
15
+
#include "clk-mux.h"
16
+
17
+
#include <dt-bindings/clock/mt7986-clk.h>
18
+
#include <linux/clk.h>
19
+
20
+
static DEFINE_SPINLOCK(mt7986_clk_lock);
21
+
22
+
static const struct mtk_fixed_clk top_fixed_clks[] = {
23
+
FIXED_CLK(CLK_TOP_XTAL, "top_xtal", "clkxtal", 40000000),
24
+
FIXED_CLK(CLK_TOP_JTAG, "top_jtag", "clkxtal", 50000000),
25
+
};
26
+
27
+
static const struct mtk_fixed_factor top_divs[] = {
28
+
/* XTAL */
29
+
FACTOR(CLK_TOP_XTAL_D2, "top_xtal_d2", "top_xtal", 1, 2),
30
+
FACTOR(CLK_TOP_RTC_32K, "top_rtc_32k", "top_xtal", 1, 1250),
31
+
FACTOR(CLK_TOP_RTC_32P7K, "top_rtc_32p7k", "top_xtal", 1, 1220),
32
+
/* MPLL */
33
+
FACTOR(CLK_TOP_MPLL_D2, "top_mpll_d2", "mpll", 1, 2),
34
+
FACTOR(CLK_TOP_MPLL_D4, "top_mpll_d4", "mpll", 1, 4),
35
+
FACTOR(CLK_TOP_MPLL_D8, "top_mpll_d8", "mpll", 1, 8),
36
+
FACTOR(CLK_TOP_MPLL_D8_D2, "top_mpll_d8_d2", "mpll", 1, 16),
37
+
FACTOR(CLK_TOP_MPLL_D3_D2, "top_mpll_d3_d2", "mpll", 1, 6),
38
+
/* MMPLL */
39
+
FACTOR(CLK_TOP_MMPLL_D2, "top_mmpll_d2", "mmpll", 1, 2),
40
+
FACTOR(CLK_TOP_MMPLL_D4, "top_mmpll_d4", "mmpll", 1, 4),
41
+
FACTOR(CLK_TOP_MMPLL_D8, "top_mmpll_d8", "mmpll", 1, 8),
42
+
FACTOR(CLK_TOP_MMPLL_D8_D2, "top_mmpll_d8_d2", "mmpll", 1, 16),
43
+
FACTOR(CLK_TOP_MMPLL_D3_D8, "top_mmpll_d3_d8", "mmpll", 1, 24),
44
+
FACTOR(CLK_TOP_MMPLL_U2PHY, "top_mmpll_u2phy", "mmpll", 1, 30),
45
+
/* APLL2 */
46
+
FACTOR(CLK_TOP_APLL2_D4, "top_apll2_d4", "apll2", 1, 4),
47
+
/* NET1PLL */
48
+
FACTOR(CLK_TOP_NET1PLL_D4, "top_net1pll_d4", "net1pll", 1, 4),
49
+
FACTOR(CLK_TOP_NET1PLL_D5, "top_net1pll_d5", "net1pll", 1, 5),
50
+
FACTOR(CLK_TOP_NET1PLL_D5_D2, "top_net1pll_d5_d2", "net1pll", 1, 10),
51
+
FACTOR(CLK_TOP_NET1PLL_D5_D4, "top_net1pll_d5_d4", "net1pll", 1, 20),
52
+
FACTOR(CLK_TOP_NET1PLL_D8_D2, "top_net1pll_d8_d2", "net1pll", 1, 16),
53
+
FACTOR(CLK_TOP_NET1PLL_D8_D4, "top_net1pll_d8_d4", "net1pll", 1, 32),
54
+
/* NET2PLL */
55
+
FACTOR(CLK_TOP_NET2PLL_D4, "top_net2pll_d4", "net2pll", 1, 4),
56
+
FACTOR(CLK_TOP_NET2PLL_D4_D2, "top_net2pll_d4_d2", "net2pll", 1, 8),
57
+
FACTOR(CLK_TOP_NET2PLL_D3_D2, "top_net2pll_d3_d2", "net2pll", 1, 2),
58
+
/* WEDMCUPLL */
59
+
FACTOR(CLK_TOP_WEDMCUPLL_D5_D2, "top_wedmcupll_d5_d2", "wedmcupll", 1,
60
+
10),
61
+
};
62
+
63
+
static const char *const nfi1x_parents[] __initconst = { "top_xtal",
64
+
"top_mmpll_d8",
65
+
"top_net1pll_d8_d2",
66
+
"top_net2pll_d3_d2",
67
+
"top_mpll_d4",
68
+
"top_mmpll_d8_d2",
69
+
"top_wedmcupll_d5_d2",
70
+
"top_mpll_d8" };
71
+
72
+
static const char *const spinfi_parents[] __initconst = {
73
+
"top_xtal_d2", "top_xtal", "top_net1pll_d5_d4",
74
+
"top_mpll_d4", "top_mmpll_d8_d2", "top_wedmcupll_d5_d2",
75
+
"top_mmpll_d3_d8", "top_mpll_d8"
76
+
};
77
+
78
+
static const char *const spi_parents[] __initconst = {
79
+
"top_xtal", "top_mpll_d2", "top_mmpll_d8",
80
+
"top_net1pll_d8_d2", "top_net2pll_d3_d2", "top_net1pll_d5_d4",
81
+
"top_mpll_d4", "top_wedmcupll_d5_d2"
82
+
};
83
+
84
+
static const char *const uart_parents[] __initconst = { "top_xtal",
85
+
"top_mpll_d8",
86
+
"top_mpll_d8_d2" };
87
+
88
+
static const char *const pwm_parents[] __initconst = {
89
+
"top_xtal", "top_net1pll_d8_d2", "top_net1pll_d5_d4", "top_mpll_d4"
90
+
};
91
+
92
+
static const char *const i2c_parents[] __initconst = {
93
+
"top_xtal", "top_net1pll_d5_d4", "top_mpll_d4", "top_net1pll_d8_d4"
94
+
};
95
+
96
+
static const char *const pextp_tl_ck_parents[] __initconst = {
97
+
"top_xtal", "top_net1pll_d5_d4", "top_net2pll_d4_d2", "top_rtc_32k"
98
+
};
99
+
100
+
static const char *const emmc_250m_parents[] __initconst = {
101
+
"top_xtal", "top_net1pll_d5_d2"
102
+
};
103
+
104
+
static const char *const emmc_416m_parents[] __initconst = { "top_xtal",
105
+
"mpll" };
106
+
107
+
static const char *const f_26m_adc_parents[] __initconst = { "top_xtal",
108
+
"top_mpll_d8_d2" };
109
+
110
+
static const char *const dramc_md32_parents[] __initconst = { "top_xtal",
111
+
"top_mpll_d2" };
112
+
113
+
static const char *const sysaxi_parents[] __initconst = { "top_xtal",
114
+
"top_net1pll_d8_d2",
115
+
"top_net2pll_d4" };
116
+
117
+
static const char *const sysapb_parents[] __initconst = { "top_xtal",
118
+
"top_mpll_d3_d2",
119
+
"top_net2pll_d4_d2" };
120
+
121
+
static const char *const arm_db_main_parents[] __initconst = {
122
+
"top_xtal", "top_net2pll_d3_d2"
123
+
};
124
+
125
+
static const char *const arm_db_jtsel_parents[] __initconst = { "top_jtag",
126
+
"top_xtal" };
127
+
128
+
static const char *const netsys_parents[] __initconst = { "top_xtal",
129
+
"top_mmpll_d4" };
130
+
131
+
static const char *const netsys_500m_parents[] __initconst = {
132
+
"top_xtal", "top_net1pll_d5"
133
+
};
134
+
135
+
static const char *const netsys_mcu_parents[] __initconst = {
136
+
"top_xtal", "wedmcupll", "top_mmpll_d2", "top_net1pll_d4",
137
+
"top_net1pll_d5"
138
+
};
139
+
140
+
static const char *const netsys_2x_parents[] __initconst = {
141
+
"top_xtal", "net2pll", "wedmcupll", "top_mmpll_d2"
142
+
};
143
+
144
+
static const char *const sgm_325m_parents[] __initconst = { "top_xtal",
145
+
"sgmpll" };
146
+
147
+
static const char *const sgm_reg_parents[] __initconst = {
148
+
"top_xtal", "top_net1pll_d8_d4"
149
+
};
150
+
151
+
static const char *const a1sys_parents[] __initconst = { "top_xtal",
152
+
"top_apll2_d4" };
153
+
154
+
static const char *const conn_mcusys_parents[] __initconst = { "top_xtal",
155
+
"top_mmpll_d2" };
156
+
157
+
static const char *const eip_b_parents[] __initconst = { "top_xtal",
158
+
"net2pll" };
159
+
160
+
static const char *const aud_l_parents[] __initconst = { "top_xtal", "apll2",
161
+
"top_mpll_d8_d2" };
162
+
163
+
static const char *const a_tuner_parents[] __initconst = { "top_xtal",
164
+
"top_apll2_d4",
165
+
"top_mpll_d8_d2" };
166
+
167
+
static const char *const u2u3_sys_parents[] __initconst = {
168
+
"top_xtal", "top_net1pll_d5_d4"
169
+
};
170
+
171
+
static const char *const da_u2_refsel_parents[] __initconst = {
172
+
"top_xtal", "top_mmpll_u2phy"
173
+
};
174
+
175
+
static const struct mtk_mux top_muxes[] = {
176
+
/* CLK_CFG_0 */
177
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_NFI1X_SEL, "nfi1x_sel", nfi1x_parents,
178
+
0x000, 0x004, 0x008, 0, 3, 7, 0x1C0, 0),
179
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPINFI_SEL, "spinfi_sel", spinfi_parents,
180
+
0x000, 0x004, 0x008, 8, 3, 15, 0x1C0, 1),
181
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI_SEL, "spi_sel", spi_parents, 0x000,
182
+
0x004, 0x008, 16, 3, 23, 0x1C0, 2),
183
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SPIM_MST_SEL, "spim_mst_sel", spi_parents,
184
+
0x000, 0x004, 0x008, 24, 3, 31, 0x1C0, 3),
185
+
/* CLK_CFG_1 */
186
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
187
+
0x014, 0x018, 0, 2, 7, 0x1C0, 4),
188
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x010,
189
+
0x014, 0x018, 8, 2, 15, 0x1C0, 5),
190
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel", i2c_parents, 0x010,
191
+
0x014, 0x018, 16, 2, 23, 0x1C0, 6),
192
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_PEXTP_TL_SEL, "pextp_tl_ck_sel",
193
+
pextp_tl_ck_parents, 0x010, 0x014, 0x018, 24, 2,
194
+
31, 0x1C0, 7),
195
+
/* CLK_CFG_2 */
196
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_250M_SEL, "emmc_250m_sel",
197
+
emmc_250m_parents, 0x020, 0x024, 0x028, 0, 1, 7,
198
+
0x1C0, 8),
199
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_EMMC_416M_SEL, "emmc_416m_sel",
200
+
emmc_416m_parents, 0x020, 0x024, 0x028, 8, 1, 15,
201
+
0x1C0, 9),
202
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
203
+
f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
204
+
0x1C0, 10),
205
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
206
+
0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
207
+
/* CLK_CFG_3 */
208
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
209
+
dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
210
+
0x1C0, 12),
211
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
212
+
0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
213
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
214
+
0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
215
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
216
+
arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
217
+
31, 0x1C0, 15),
218
+
/* CLK_CFG_4 */
219
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_JTSEL, "arm_db_jtsel",
220
+
arm_db_jtsel_parents, 0x040, 0x044, 0x048, 0, 1, 7,
221
+
0x1C0, 16),
222
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_SEL, "netsys_sel", netsys_parents,
223
+
0x040, 0x044, 0x048, 8, 1, 15, 0x1C0, 17),
224
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_500M_SEL, "netsys_500m_sel",
225
+
netsys_500m_parents, 0x040, 0x044, 0x048, 16, 1,
226
+
23, 0x1C0, 18),
227
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_MCU_SEL, "netsys_mcu_sel",
228
+
netsys_mcu_parents, 0x040, 0x044, 0x048, 24, 3, 31,
229
+
0x1C0, 19),
230
+
/* CLK_CFG_5 */
231
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_NETSYS_2X_SEL, "netsys_2x_sel",
232
+
netsys_2x_parents, 0x050, 0x054, 0x058, 0, 2, 7,
233
+
0x1C0, 20),
234
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
235
+
sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
236
+
0x1C0, 21),
237
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
238
+
sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
239
+
0x1C0, 22),
240
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
241
+
0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
242
+
/* CLK_CFG_6 */
243
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_CONN_MCUSYS_SEL, "conn_mcusys_sel",
244
+
conn_mcusys_parents, 0x060, 0x064, 0x068, 0, 1, 7,
245
+
0x1C0, 24),
246
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_EIP_B_SEL, "eip_b_sel", eip_b_parents,
247
+
0x060, 0x064, 0x068, 8, 1, 15, 0x1C0, 25),
248
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_PCIE_PHY_SEL, "pcie_phy_sel",
249
+
f_26m_adc_parents, 0x060, 0x064, 0x068, 16, 1, 23,
250
+
0x1C0, 26),
251
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_USB3_PHY_SEL, "usb3_phy_sel",
252
+
f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
253
+
0x1C0, 27),
254
+
/* CLK_CFG_7 */
255
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
256
+
f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
257
+
0x1C0, 28),
258
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
259
+
0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
260
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
261
+
a_tuner_parents, 0x070, 0x074, 0x078, 16, 2, 23,
262
+
0x1C0, 30),
263
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SEL, "u2u3_sel", f_26m_adc_parents,
264
+
0x070, 0x074, 0x078, 24, 1, 31, 0x1C4, 0),
265
+
/* CLK_CFG_8 */
266
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_SYS_SEL, "u2u3_sys_sel",
267
+
u2u3_sys_parents, 0x080, 0x084, 0x088, 0, 1, 7,
268
+
0x1C4, 1),
269
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_U2U3_XHCI_SEL, "u2u3_xhci_sel",
270
+
u2u3_sys_parents, 0x080, 0x084, 0x088, 8, 1, 15,
271
+
0x1C4, 2),
272
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_REFSEL, "da_u2_refsel",
273
+
da_u2_refsel_parents, 0x080, 0x084, 0x088, 16, 1,
274
+
23, 0x1C4, 3),
275
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_DA_U2_CK_1P_SEL, "da_u2_ck_1p_sel",
276
+
da_u2_refsel_parents, 0x080, 0x084, 0x088, 24, 1,
277
+
31, 0x1C4, 4),
278
+
/* CLK_CFG_9 */
279
+
MUX_GATE_CLR_SET_UPD(CLK_TOP_AP2CNN_HOST_SEL, "ap2cnn_host_sel",
280
+
sgm_reg_parents, 0x090, 0x094, 0x098, 0, 1, 7,
281
+
0x1C4, 5),
282
+
};
283
+
284
+
static int clk_mt7986_topckgen_probe(struct platform_device *pdev)
285
+
{
286
+
struct clk_onecell_data *clk_data;
287
+
struct device_node *node = pdev->dev.of_node;
288
+
int r;
289
+
void __iomem *base;
290
+
int nr = ARRAY_SIZE(top_fixed_clks) + ARRAY_SIZE(top_divs) +
291
+
ARRAY_SIZE(top_muxes);
292
+
293
+
base = of_iomap(node, 0);
294
+
if (!base) {
295
+
pr_err("%s(): ioremap failed\n", __func__);
296
+
return -ENOMEM;
297
+
}
298
+
299
+
clk_data = mtk_alloc_clk_data(nr);
300
+
if (!clk_data)
301
+
return -ENOMEM;
302
+
303
+
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
304
+
clk_data);
305
+
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
306
+
mtk_clk_register_muxes(top_muxes, ARRAY_SIZE(top_muxes), node,
307
+
&mt7986_clk_lock, clk_data);
308
+
309
+
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAXI_SEL]);
310
+
clk_prepare_enable(clk_data->clks[CLK_TOP_SYSAPB_SEL]);
311
+
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_SEL]);
312
+
clk_prepare_enable(clk_data->clks[CLK_TOP_DRAMC_MD32_SEL]);
313
+
clk_prepare_enable(clk_data->clks[CLK_TOP_F26M_SEL]);
314
+
clk_prepare_enable(clk_data->clks[CLK_TOP_SGM_REG_SEL]);
315
+
316
+
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
317
+
318
+
if (r) {
319
+
pr_err("%s(): could not register clock provider: %d\n",
320
+
__func__, r);
321
+
goto free_topckgen_data;
322
+
}
323
+
return r;
324
+
325
+
free_topckgen_data:
326
+
mtk_free_clk_data(clk_data);
327
+
return r;
328
+
}
329
+
330
+
static const struct of_device_id of_match_clk_mt7986_topckgen[] = {
331
+
{ .compatible = "mediatek,mt7986-topckgen", },
332
+
{}
333
+
};
334
+
335
+
static struct platform_driver clk_mt7986_topckgen_drv = {
336
+
.probe = clk_mt7986_topckgen_probe,
337
+
.driver = {
338
+
.name = "clk-mt7986-topckgen",
339
+
.of_match_table = of_match_clk_mt7986_topckgen,
340
+
},
341
+
};
342
+
builtin_platform_driver(clk_mt7986_topckgen_drv);