tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge tag 'renesas-pinctrl-for-v6.19-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: renesas: Updates for v6.19 (take two)

- Remove removed signals on R-Car V4H and V4M,
- Refactor OEN register PWPR handling on RZ/G2L.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>

Linus Walleij ec8e1f41 f2596d9f

+68 -91
+33 -67
drivers/pinctrl/renesas/pfc-r8a779g0.c
··· 352 352 #define IP1SR2_3_0 FM(TPU0TO0_A) FM(CANFD6_RX) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 353 353 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 354 354 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 - #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 355 + #define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 356 356 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 357 357 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 358 358 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ··· 471 471 #define IP0SR6_7_4 FM(AVB1_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 472 472 #define IP0SR6_11_8 FM(AVB1_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 473 473 #define IP0SR6_15_12 FM(AVB1_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 474 - #define IP0SR6_19_16 FM(AVB1_LINK) FM(AVB1_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 475 - #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) FM(AVB1_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 476 - #define IP0SR6_27_24 FM(AVB1_TXC) FM(AVB1_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 477 - #define IP0SR6_31_28 FM(AVB1_TX_CTL) FM(AVB1_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 474 + #define IP0SR6_19_16 FM(AVB1_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 475 + #define IP0SR6_23_20 FM(AVB1_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 476 + #define IP0SR6_27_24 FM(AVB1_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 477 + #define IP0SR6_31_28 FM(AVB1_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 478 478 479 479 /* IP1SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 480 - #define IP1SR6_3_0 FM(AVB1_RXC) FM(AVB1_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 - #define IP1SR6_7_4 FM(AVB1_RX_CTL) FM(AVB1_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482 - #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) FM(AVB1_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483 - #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) FM(AVB1_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 - #define IP1SR6_19_16 FM(AVB1_TD1) FM(AVB1_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 485 - #define IP1SR6_23_20 FM(AVB1_TD0) FM(AVB1_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 486 - #define IP1SR6_27_24 FM(AVB1_RD1) FM(AVB1_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 487 - #define IP1SR6_31_28 FM(AVB1_RD0) FM(AVB1_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 480 + #define IP1SR6_3_0 FM(AVB1_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 + #define IP1SR6_7_4 FM(AVB1_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482 + #define IP1SR6_11_8 FM(AVB1_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483 + #define IP1SR6_15_12 FM(AVB1_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 + #define IP1SR6_19_16 FM(AVB1_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 485 + #define IP1SR6_23_20 FM(AVB1_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 486 + #define IP1SR6_27_24 FM(AVB1_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 487 + #define IP1SR6_31_28 FM(AVB1_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 488 488 489 489 /* IP2SR6 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 490 - #define IP2SR6_3_0 FM(AVB1_TD2) FM(AVB1_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 491 - #define IP2SR6_7_4 FM(AVB1_RD2) FM(AVB1_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 492 - #define IP2SR6_11_8 FM(AVB1_TD3) FM(AVB1_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 493 - #define IP2SR6_15_12 FM(AVB1_RD3) FM(AVB1_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 490 + #define IP2SR6_3_0 FM(AVB1_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 491 + #define IP2SR6_7_4 FM(AVB1_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 492 + #define IP2SR6_11_8 FM(AVB1_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 493 + #define IP2SR6_15_12 FM(AVB1_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 494 494 #define IP2SR6_19_16 FM(AVB1_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 495 495 496 496 /* SR7 */ 497 497 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 498 - #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 499 - #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 500 - #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 501 - #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 502 - #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 498 + #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 499 + #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 500 + #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 501 + #define IP0SR7_15_12 FM(AVB0_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 502 + #define IP0SR7_19_16 FM(AVB0_LINK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 503 503 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 504 - #define IP0SR7_27_24 FM(AVB0_TD2) FM(AVB0_MII_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 505 - #define IP0SR7_31_28 FM(AVB0_TD1) FM(AVB0_MII_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 504 + #define IP0SR7_27_24 FM(AVB0_TD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 505 + #define IP0SR7_31_28 FM(AVB0_TD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 506 506 507 507 /* IP1SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 508 - #define IP1SR7_3_0 FM(AVB0_RD3) FM(AVB0_MII_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 508 + #define IP1SR7_3_0 FM(AVB0_RD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 509 509 #define IP1SR7_7_4 FM(AVB0_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 510 510 #define IP1SR7_11_8 FM(AVB0_MAGIC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 511 - #define IP1SR7_15_12 FM(AVB0_TD0) FM(AVB0_MII_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 512 - #define IP1SR7_19_16 FM(AVB0_RD2) FM(AVB0_MII_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 511 + #define IP1SR7_15_12 FM(AVB0_TD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 512 + #define IP1SR7_19_16 FM(AVB0_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 513 513 #define IP1SR7_23_20 FM(AVB0_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 514 514 #define IP1SR7_27_24 FM(AVB0_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 515 - #define IP1SR7_31_28 FM(AVB0_TXC) FM(AVB0_MII_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 515 + #define IP1SR7_31_28 FM(AVB0_TXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 516 516 517 517 /* IP2SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 518 - #define IP2SR7_3_0 FM(AVB0_TX_CTL) FM(AVB0_MII_TX_EN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 519 - #define IP2SR7_7_4 FM(AVB0_RD1) FM(AVB0_MII_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 520 - #define IP2SR7_11_8 FM(AVB0_RD0) FM(AVB0_MII_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 521 - #define IP2SR7_15_12 FM(AVB0_RXC) FM(AVB0_MII_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 522 - #define IP2SR7_19_16 FM(AVB0_RX_CTL) FM(AVB0_MII_RX_DV) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 518 + #define IP2SR7_3_0 FM(AVB0_TX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 519 + #define IP2SR7_7_4 FM(AVB0_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 520 + #define IP2SR7_11_8 FM(AVB0_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 521 + #define IP2SR7_15_12 FM(AVB0_RXC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 522 + #define IP2SR7_19_16 FM(AVB0_RX_CTL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 523 523 524 524 /* SR8 */ 525 525 /* IP0SR8 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ ··· 925 925 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), 926 926 927 927 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), 928 - PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), 929 928 930 929 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), 931 930 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), ··· 1075 1076 PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT), 1076 1077 1077 1078 PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK), 1078 - PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER), 1079 1079 1080 1080 PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH), 1081 - PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER), 1082 1081 1083 1082 PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC), 1084 - PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC), 1085 1083 1086 1084 PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL), 1087 - PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN), 1088 1085 1089 1086 /* IP1SR6 */ 1090 1087 PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC), 1091 - PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_MII_RXC), 1092 1088 1093 1089 PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL), 1094 - PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV), 1095 1090 1096 1091 PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS), 1097 - PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL), 1098 1092 1099 1093 PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE), 1100 - PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS), 1101 1094 1102 1095 PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1), 1103 - PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1), 1104 1096 1105 1097 PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0), 1106 - PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0), 1107 1098 1108 1099 PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1), 1109 - PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1), 1110 1100 1111 1101 PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_RD0), 1112 - PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0), 1113 1102 1114 1103 /* IP2SR6 */ 1115 1104 PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2), 1116 - PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2), 1117 1105 1118 1106 PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2), 1119 - PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2), 1120 1107 1121 1108 PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3), 1122 - PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3), 1123 1109 1124 1110 PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3), 1125 - PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3), 1126 1111 1127 1112 PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK), 1128 1113 1129 1114 /* IP0SR7 */ 1130 1115 PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS), 1131 - PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL), 1132 1116 1133 1117 PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE), 1134 - PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS), 1135 1118 1136 1119 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), 1137 - PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), 1138 - PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), 1139 1120 1140 1121 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), 1141 - PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3), 1142 1122 1143 1123 PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK), 1144 - PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER), 1145 1124 1146 1125 PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT), 1147 1126 1148 1127 PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2), 1149 - PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2), 1150 1128 1151 1129 PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1), 1152 - PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1), 1153 1130 1154 1131 /* IP1SR7 */ 1155 1132 PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3), 1156 - PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3), 1157 1133 1158 1134 PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK), 1159 1135 1160 1136 PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC), 1161 1137 1162 1138 PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0), 1163 - PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0), 1164 1139 1165 1140 PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2), 1166 - PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2), 1167 1141 1168 1142 PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC), 1169 1143 1170 1144 PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO), 1171 1145 1172 1146 PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC), 1173 - PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC), 1174 1147 1175 1148 /* IP2SR7 */ 1176 1149 PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL), 1177 - PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN), 1178 1150 1179 1151 PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1), 1180 - PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1), 1181 1152 1182 1153 PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_RD0), 1183 - PINMUX_IPSR_GPSR(IP2SR7_11_8, AVB0_MII_RD0), 1184 1154 1185 1155 PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_RXC), 1186 - PINMUX_IPSR_GPSR(IP2SR7_15_12, AVB0_MII_RXC), 1187 1156 1188 1157 PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_RX_CTL), 1189 - PINMUX_IPSR_GPSR(IP2SR7_19_16, AVB0_MII_RX_DV), 1190 1158 1191 1159 /* IP0SR8 */ 1192 1160 PINMUX_IPSR_MSEL(IP0SR8_3_0, SCL0, SEL_SCL0_0),
+2 -4
drivers/pinctrl/renesas/pfc-r8a779h0.c
··· 339 339 #define IP1SR2_3_0 FM(TPU0TO0_A) F_(0, 0) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 340 340 #define IP1SR2_7_4 FM(CAN_CLK) FM(FXR_TXENA_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 341 341 #define IP1SR2_11_8 FM(CANFD0_TX) FM(FXR_TXENB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 - #define IP1SR2_15_12 FM(CANFD0_RX) FM(STPWT_EXTFXR) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 342 + #define IP1SR2_15_12 FM(CANFD0_RX) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 343 343 #define IP1SR2_19_16 FM(CANFD2_TX) FM(TPU0TO2_A) F_(0, 0) FM(TCLK3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 344 344 #define IP1SR2_23_20 FM(CANFD2_RX) FM(TPU0TO3_A) FM(PWM1_B) FM(TCLK4_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 345 345 #define IP1SR2_27_24 FM(CANFD3_TX) F_(0, 0) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ··· 478 478 /* IP0SR7 */ /* 0 */ /* 1 */ /* 2 */ /* 3 4 5 6 7 8 9 A B C D E F */ 479 479 #define IP0SR7_3_0 FM(AVB0_AVTP_PPS) FM(AVB0_MII_COL) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 480 480 #define IP0SR7_7_4 FM(AVB0_AVTP_CAPTURE) FM(AVB0_MII_CRS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 - #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 481 + #define IP0SR7_11_8 FM(AVB0_AVTP_MATCH) FM(AVB0_MII_RX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 482 482 #define IP0SR7_15_12 FM(AVB0_TD3) FM(AVB0_MII_TD3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 483 483 #define IP0SR7_19_16 FM(AVB0_LINK) FM(AVB0_MII_TX_ER) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) 484 484 #define IP0SR7_23_20 FM(AVB0_PHY_INT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) ··· 865 865 PINMUX_IPSR_GPSR(IP1SR2_11_8, FXR_TXENB_N_B), 866 866 867 867 PINMUX_IPSR_GPSR(IP1SR2_15_12, CANFD0_RX), 868 - PINMUX_IPSR_GPSR(IP1SR2_15_12, STPWT_EXTFXR), 869 868 870 869 PINMUX_IPSR_GPSR(IP1SR2_19_16, CANFD2_TX), 871 870 PINMUX_IPSR_GPSR(IP1SR2_19_16, TPU0TO2_A), ··· 1122 1123 1123 1124 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH), 1124 1125 PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER), 1125 - PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT), 1126 1126 1127 1127 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3), 1128 1128 PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
+33 -20
drivers/pinctrl/renesas/pinctrl-rzg2l.c
··· 1112 1112 return !(readb(pctrl->base + pctrl->data->hwcfg->regs.oen) & BIT(bit)); 1113 1113 } 1114 1114 1115 - static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1115 + /** 1116 + * rzg2l_oen_write_with_pwpr - Write to OEN register with PWPR protection 1117 + * @pctrl: pinctrl driver data 1118 + * @val: value to write to OEN register 1119 + * 1120 + * Writes to the OEN register, handling PWPR write protection if required 1121 + * by the hardware configuration. Must be called with pctrl->lock held. 1122 + */ 1123 + static void rzg2l_oen_write_with_pwpr(struct rzg2l_pinctrl *pctrl, u8 val) 1116 1124 { 1117 1125 const struct rzg2l_register_offsets *regs = &pctrl->data->hwcfg->regs; 1118 1126 u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1127 + u8 pwpr; 1128 + 1129 + if (pctrl->data->hwcfg->oen_pwpr_lock) { 1130 + pwpr = readb(pctrl->base + regs->pwpr); 1131 + writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1132 + } 1133 + 1134 + writeb(val, pctrl->base + oen_offset); 1135 + 1136 + if (pctrl->data->hwcfg->oen_pwpr_lock) 1137 + writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1138 + } 1139 + 1140 + static int rzg2l_write_oen(struct rzg2l_pinctrl *pctrl, unsigned int _pin, u8 oen) 1141 + { 1142 + u16 oen_offset = pctrl->data->hwcfg->regs.oen; 1119 1143 unsigned long flags; 1120 - u8 val, pwpr; 1121 1144 int bit; 1145 + u8 val; 1122 1146 1123 1147 if (!pctrl->data->pin_to_oen_bit) 1124 1148 return -EOPNOTSUPP; ··· 1157 1133 val &= ~BIT(bit); 1158 1134 else 1159 1135 val |= BIT(bit); 1160 - if (pctrl->data->hwcfg->oen_pwpr_lock) { 1161 - pwpr = readb(pctrl->base + regs->pwpr); 1162 - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 1163 - } 1164 - writeb(val, pctrl->base + oen_offset); 1165 - if (pctrl->data->hwcfg->oen_pwpr_lock) 1166 - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 1136 + 1137 + rzg2l_oen_write_with_pwpr(pctrl, val); 1167 1138 raw_spin_unlock_irqrestore(&pctrl->lock, flags); 1168 1139 1169 1140 return 0; ··· 3219 3200 const struct rzg2l_register_offsets *regs = &hwcfg->regs; 3220 3201 struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache; 3221 3202 unsigned long flags; 3222 - u8 pwpr; 3223 3203 int ret; 3224 3204 3225 3205 if (!atomic_read(&pctrl->wakeup_path)) { ··· 3228 3210 } 3229 3211 3230 3212 writeb(cache->qspi, pctrl->base + QSPI); 3231 - if (pctrl->data->hwcfg->oen_pwpr_lock) { 3232 - raw_spin_lock_irqsave(&pctrl->lock, flags); 3233 - pwpr = readb(pctrl->base + regs->pwpr); 3234 - writeb(pwpr | PWPR_REGWE_B, pctrl->base + regs->pwpr); 3235 - } 3236 - writeb(cache->oen, pctrl->base + pctrl->data->hwcfg->regs.oen); 3237 - if (pctrl->data->hwcfg->oen_pwpr_lock) { 3238 - writeb(pwpr & ~PWPR_REGWE_B, pctrl->base + regs->pwpr); 3239 - raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3240 - } 3213 + 3214 + raw_spin_lock_irqsave(&pctrl->lock, flags); 3215 + rzg2l_oen_write_with_pwpr(pctrl, cache->oen); 3216 + raw_spin_unlock_irqrestore(&pctrl->lock, flags); 3217 + 3241 3218 for (u8 i = 0; i < 2; i++) { 3242 3219 if (regs->sd_ch) 3243 3220 writeb(cache->sd_ch[i], pctrl->base + SD_CH(regs->sd_ch, i));