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dt-bindings: clock: drop useless consumer example

Consumer examples in the bindings of resource providers are trivial,
useless and duplication of code. Remove the example code for consumer

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220316130858.93455-2-krzysztof.kozlowski@canonical.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

authored by

Krzysztof Kozlowski and committed by
Stephen Boyd
ec8b5578 7a74e1e4

-143
-12
Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
··· 61 61 #clock-cells = <1>; 62 62 }; 63 63 64 - # Example UART controller node that consumes clock generated by the clock controller: 65 - - | 66 - uart0: serial@58018000 { 67 - compatible = "snps,dw-apb-uart"; 68 - reg = <0x58018000 0x2000>; 69 - clocks = <&clk 45>, <&clk 46>; 70 - clock-names = "baudclk", "apb_pclk"; 71 - interrupts = <0 9 4>; 72 - reg-shift = <2>; 73 - reg-io-width = <4>; 74 - }; 75 - 76 64 ...
-7
Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
··· 191 191 }; 192 192 }; 193 193 194 - /* Consumer referencing the 5P49V5923 pin OUT1 */ 195 - consumer { 196 - /* ... */ 197 - clocks = <&vc5 1>; 198 - /* ... */ 199 - }; 200 - 201 194 ...
-9
Documentation/devicetree/bindings/clock/imx1-clock.yaml
··· 40 40 compatible = "fsl,imx1-ccm"; 41 41 reg = <0x0021b000 0x1000>; 42 42 }; 43 - 44 - pwm@208000 { 45 - #pwm-cells = <2>; 46 - compatible = "fsl,imx1-pwm"; 47 - reg = <0x00208000 0x1000>; 48 - interrupts = <34>; 49 - clocks = <&clks IMX1_CLK_DUMMY>, <&clks IMX1_CLK_PER1>; 50 - clock-names = "ipg", "per"; 51 - };
-9
Documentation/devicetree/bindings/clock/imx21-clock.yaml
··· 40 40 reg = <0x10027000 0x800>; 41 41 #clock-cells = <1>; 42 42 }; 43 - 44 - serial@1000a000 { 45 - compatible = "fsl,imx21-uart"; 46 - reg = <0x1000a000 0x1000>; 47 - interrupts = <20>; 48 - clocks = <&clks IMX21_CLK_UART1_IPG_GATE>, 49 - <&clks IMX21_CLK_PER1>; 50 - clock-names = "ipg", "per"; 51 - };
-9
Documentation/devicetree/bindings/clock/imx23-clock.yaml
··· 83 83 reg = <0x80040000 0x2000>; 84 84 #clock-cells = <1>; 85 85 }; 86 - 87 - serial@8006c000 { 88 - compatible = "fsl,imx23-auart"; 89 - reg = <0x8006c000 0x2000>; 90 - interrupts = <24>; 91 - clocks = <&clks 32>; 92 - dmas = <&dma_apbx 6>, <&dma_apbx 7>; 93 - dma-names = "rx", "tx"; 94 - };
-8
Documentation/devicetree/bindings/clock/imx25-clock.yaml
··· 176 176 interrupts = <31>; 177 177 #clock-cells = <1>; 178 178 }; 179 - 180 - serial@43f90000 { 181 - compatible = "fsl,imx25-uart", "fsl,imx21-uart"; 182 - reg = <0x43f90000 0x4000>; 183 - interrupts = <45>; 184 - clocks = <&clks 79>, <&clks 50>; 185 - clock-names = "ipg", "per"; 186 - };
-9
Documentation/devicetree/bindings/clock/imx27-clock.yaml
··· 44 44 interrupts = <31>; 45 45 #clock-cells = <1>; 46 46 }; 47 - 48 - serial@1000a000 { 49 - compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 50 - reg = <0x1000a000 0x1000>; 51 - interrupts = <20>; 52 - clocks = <&clks IMX27_CLK_UART1_IPG_GATE>, 53 - <&clks IMX27_CLK_PER1_GATE>; 54 - clock-names = "ipg", "per"; 55 - };
-9
Documentation/devicetree/bindings/clock/imx28-clock.yaml
··· 106 106 reg = <0x80040000 0x2000>; 107 107 #clock-cells = <1>; 108 108 }; 109 - 110 - serial@8006a000 { 111 - compatible = "fsl,imx28-auart"; 112 - reg = <0x8006a000 0x2000>; 113 - interrupts = <112>; 114 - dmas = <&dma_apbx 8>, <&dma_apbx 9>; 115 - dma-names = "rx", "tx"; 116 - clocks = <&clks 45>; 117 - };
-8
Documentation/devicetree/bindings/clock/imx31-clock.yaml
··· 110 110 interrupts = <31>, <53>; 111 111 #clock-cells = <1>; 112 112 }; 113 - 114 - serial@43f90000 { 115 - compatible = "fsl,imx31-uart", "fsl,imx21-uart"; 116 - reg = <0x43f90000 0x4000>; 117 - interrupts = <45>; 118 - clocks = <&clks 10>, <&clks 30>; 119 - clock-names = "ipg", "per"; 120 - };
-8
Documentation/devicetree/bindings/clock/imx35-clock.yaml
··· 129 129 interrupts = <31>; 130 130 #clock-cells = <1>; 131 131 }; 132 - 133 - mmc@53fb4000 { 134 - compatible = "fsl,imx35-esdhc"; 135 - reg = <0x53fb4000 0x4000>; 136 - interrupts = <7>; 137 - clocks = <&clks 9>, <&clks 8>, <&clks 43>; 138 - clock-names = "ipg", "ahb", "per"; 139 - };
-11
Documentation/devicetree/bindings/clock/imx7ulp-pcc-clock.yaml
··· 108 108 "upll", "sosc_bus_clk", "firc_bus_clk", 109 109 "rosc", "spll_bus_clk"; 110 110 }; 111 - 112 - mmc@40380000 { 113 - compatible = "fsl,imx7ulp-usdhc"; 114 - reg = <0x40380000 0x10000>; 115 - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 116 - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 117 - <&scg1 IMX7ULP_CLK_NIC1_DIV>, 118 - <&pcc2 IMX7ULP_CLK_USDHC1>; 119 - clock-names ="ipg", "ahb", "per"; 120 - bus-width = <4>; 121 - };
-11
Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml
··· 86 86 "firc", "upll"; 87 87 #clock-cells = <1>; 88 88 }; 89 - 90 - mmc@40380000 { 91 - compatible = "fsl,imx7ulp-usdhc"; 92 - reg = <0x40380000 0x10000>; 93 - interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 94 - clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 95 - <&scg1 IMX7ULP_CLK_NIC1_DIV>, 96 - <&pcc2 IMX7ULP_CLK_USDHC1>; 97 - clock-names ="ipg", "ahb", "per"; 98 - bus-width = <4>; 99 - };
-11
Documentation/devicetree/bindings/clock/imx8qxp-lpcg.yaml
··· 101 101 "sdhc0_lpcg_ahb_clk"; 102 102 power-domains = <&pd IMX_SC_R_SDHC_0>; 103 103 }; 104 - 105 - mmc@5b010000 { 106 - compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc"; 107 - interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 108 - reg = <0x5b010000 0x10000>; 109 - clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>, 110 - <&sdhc0_lpcg IMX_LPCG_CLK_5>, 111 - <&sdhc0_lpcg IMX_LPCG_CLK_0>; 112 - clock-names = "ipg", "ahb", "per"; 113 - power-domains = <&pd IMX_SC_R_SDHC_0>; 114 - };
-8
Documentation/devicetree/bindings/clock/imxrt1050-clock.yaml
··· 57 57 clock-names = "osc"; 58 58 #clock-cells = <1>; 59 59 }; 60 - 61 - lpuart1: serial@40184000 { 62 - compatible = "fsl,imxrt1050-lpuart"; 63 - reg = <0x40184000 0x4000>; 64 - interrupts = <20>; 65 - clocks = <&clks IMXRT1050_CLK_LPUART1>; 66 - clock-names = "ipg"; 67 - };
-7
Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
··· 106 106 #clock-cells = <1>; 107 107 #reset-cells = <1>; 108 108 }; 109 - 110 - usb-controller@c5004000 { 111 - compatible = "nvidia,tegra20-ehci"; 112 - reg = <0xc5004000 0x4000>; 113 - clocks = <&car TEGRA124_CLK_USB2>; 114 - resets = <&car TEGRA124_CLK_USB2>; 115 - };
-7
Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
··· 97 97 power-domains = <&domain>; 98 98 }; 99 99 }; 100 - 101 - usb-controller@c5004000 { 102 - compatible = "nvidia,tegra20-ehci"; 103 - reg = <0xc5004000 0x4000>; 104 - clocks = <&car TEGRA20_CLK_USB2>; 105 - resets = <&car TEGRA20_CLK_USB2>; 106 - };