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ARM: tegra: Add DT binding for Tegra186 GPIO controllers
Tegra186 contains two separate but mostly similar GPIO controllers.
Register layout differs significantly from previous Tegra generations,
and so a new binding is required to describe them in device tree. This
patch adds that binding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
authored by
Stephen Warren
and committed by
Thierry Reding
ec6b9255
1e48b695
+217
+161
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt
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Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.txt
···
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NVIDIA Tegra186 GPIO controllers
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Tegra186 contains two GPIO controllers; a main controller and an "AON"
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controller. This binding document applies to both controllers. The register
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layouts for the controllers share many similarities, but also some significant
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differences. Hence, this document describes closely related but different
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bindings and compatible values.
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The Tegra186 GPIO controller allows software to set the IO direction of, and
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read/write the value of, numerous GPIO signals. Routing of GPIO signals to
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package balls is under the control of a separate pin controller HW block. Two
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major sets of registers exist:
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a) Security registers, which allow configuration of allowed access to the GPIO
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register set. These registers exist in a single contiguous block of physical
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address space. The size of this block, and the security features available,
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varies between the different GPIO controllers.
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Access to this set of registers is not necessary in all circumstances. Code
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that wishes to configure access to the GPIO registers needs access to these
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registers to do so. Code which simply wishes to read or write GPIO data does not
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need access to these registers.
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b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO
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controllers, these registers are exposed via multiple "physical aliases" in
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address space, each of which access the same underlying state. See the hardware
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documentation for rationale. Any particular GPIO client is expected to access
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just one of these physical aliases.
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Tegra HW documentation describes a unified naming convention for all GPIOs
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implemented by the SoC. Each GPIO is assigned to a port, and a port may control
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a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
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name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6,
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or GPIO_PCC3.
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The number of ports implemented by each GPIO controller varies. The number of
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implemented GPIOs within each port varies. GPIO registers within a controller
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are grouped and laid out according to the port they affect.
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The mapping from port name to the GPIO controller that implements that port, and
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the mapping from port name to register offset within a controller, are both
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extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h>
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describes the port-level mapping. In that file, the naming convention for ports
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matches the HW documentation. The values chosen for the names are alphabetically
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sorted within a particular controller. Drivers need to map between the DT GPIO
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IDs and HW register offsets using a lookup table.
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Each GPIO controller can generate a number of interrupt signals. Each signal
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represents the aggregate status for all GPIOs within a set of ports. Thus, the
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number of interrupt signals generated by a controller varies as a rough function
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of the number of ports it implements. Note that the HW documentation refers to
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both the overall controller HW module and the sets-of-ports as "controllers".
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Each GPIO controller in fact generates multiple interrupts signals for each set
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of ports. Each GPIO may be configured to feed into a specific one of the
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interrupt signals generated by a set-of-ports. The intent is for each generated
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signal to be routed to a different CPU, thus allowing different CPUs to each
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handle subsets of the interrupts within a port. The status of each of these
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per-port-set signals is reported via a separate register. Thus, a driver needs
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to know which status register to observe. This binding currently defines no
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configuration mechanism for this. By default, drivers should use register
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GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
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define a property to configure this.
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Required properties:
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- compatible
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Array of strings.
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One of:
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- "nvidia,tegra186-gpio".
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- "nvidia,tegra186-gpio-aon".
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- reg-names
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Array of strings.
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Contains a list of names for the register spaces described by the reg
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property. May contain the following entries, in any order:
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- "gpio": Mandatory. GPIO control registers. This may cover either:
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a) The single physical alias that this OS should use.
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b) All physical aliases that exist in the controller. This is
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appropriate when the OS is responsible for managing assignment of
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the physical aliases.
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- "security": Optional. Security configuration registers.
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Users of this binding MUST look up entries in the reg property by name,
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using this reg-names property to do so.
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- reg
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Array of (physical base address, length) tuples.
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Must contain one entry per entry in the reg-names property, in a matching
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order.
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- interrupts
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Array of interrupt specifiers.
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The interrupt outputs from the HW block, one per set of ports, in the
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order the HW manual describes them. The number of entries required varies
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depending on compatible value:
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- "nvidia,tegra186-gpio": 6 entries.
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- "nvidia,tegra186-gpio-aon": 1 entry.
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- gpio-controller
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Boolean.
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Marks the device node as a GPIO controller/provider.
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- #gpio-cells
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Single-cell integer.
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Must be <2>.
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Indicates how many cells are used in a consumer's GPIO specifier.
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In the specifier:
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- The first cell is the pin number.
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See <dt-bindings/gpio/tegra186-gpio.h>.
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- The second cell contains flags:
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- Bit 0 specifies polarity
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- 0: Active-high (normal).
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- 1: Active-low (inverted).
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- interrupt-controller
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Boolean.
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Marks the device node as an interrupt controller/provider.
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- #interrupt-cells
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Single-cell integer.
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Must be <2>.
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Indicates how many cells are used in a consumer's interrupt specifier.
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In the specifier:
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- The first cell is the GPIO number.
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See <dt-bindings/gpio/tegra186-gpio.h>.
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- The second cell is contains flags:
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- Bits [3:0] indicate trigger type and level:
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- 1: Low-to-high edge triggered.
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- 2: High-to-low edge triggered.
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- 4: Active high level-sensitive.
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- 8: Active low level-sensitive.
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Valid combinations are 1, 2, 3, 4, 8.
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Example:
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#include <dt-bindings/interrupt-controller/irq.h>
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gpio@2200000 {
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compatible = "nvidia,tegra186-gpio";
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reg-names = "security", "gpio";
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reg =
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<0x0 0x2200000 0x0 0x10000>,
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<0x0 0x2210000 0x0 0x10000>;
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interrupts =
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<0 47 IRQ_TYPE_LEVEL_HIGH>,
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<0 50 IRQ_TYPE_LEVEL_HIGH>,
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<0 53 IRQ_TYPE_LEVEL_HIGH>,
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<0 56 IRQ_TYPE_LEVEL_HIGH>,
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<0 59 IRQ_TYPE_LEVEL_HIGH>,
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<0 180 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio@c2f0000 {
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compatible = "nvidia,tegra186-gpio-aon";
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reg-names = "security", "gpio";
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reg =
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<0x0 0xc2f0000 0x0 0x1000>,
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<0x0 0xc2f1000 0x0 0x1000>;
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interrupts =
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<0 60 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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include/dt-bindings/gpio/tegra186-gpio.h
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include/dt-bindings/gpio/tegra186-gpio.h
···
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/*
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* This header provides constants for binding nvidia,tegra186-gpio*.
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*
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* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
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* provide names for this.
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*
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* The second cell contains standard flag values specified in gpio.h.
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*/
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#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
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#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
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#include <dt-bindings/gpio/gpio.h>
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/* GPIOs implemented by main GPIO controller */
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#define TEGRA_MAIN_GPIO_PORT_A 0
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#define TEGRA_MAIN_GPIO_PORT_B 1
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#define TEGRA_MAIN_GPIO_PORT_C 2
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#define TEGRA_MAIN_GPIO_PORT_D 3
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#define TEGRA_MAIN_GPIO_PORT_E 4
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#define TEGRA_MAIN_GPIO_PORT_F 5
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#define TEGRA_MAIN_GPIO_PORT_G 6
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#define TEGRA_MAIN_GPIO_PORT_H 7
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#define TEGRA_MAIN_GPIO_PORT_I 8
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#define TEGRA_MAIN_GPIO_PORT_J 9
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#define TEGRA_MAIN_GPIO_PORT_K 10
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#define TEGRA_MAIN_GPIO_PORT_L 11
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#define TEGRA_MAIN_GPIO_PORT_M 12
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#define TEGRA_MAIN_GPIO_PORT_N 13
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#define TEGRA_MAIN_GPIO_PORT_O 14
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#define TEGRA_MAIN_GPIO_PORT_P 15
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#define TEGRA_MAIN_GPIO_PORT_Q 16
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#define TEGRA_MAIN_GPIO_PORT_R 17
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#define TEGRA_MAIN_GPIO_PORT_T 18
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#define TEGRA_MAIN_GPIO_PORT_X 19
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#define TEGRA_MAIN_GPIO_PORT_Y 20
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#define TEGRA_MAIN_GPIO_PORT_BB 21
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#define TEGRA_MAIN_GPIO_PORT_CC 22
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#define TEGRA_MAIN_GPIO(port, offset) \
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((TEGRA_MAIN_GPIO_PORT_##port * 8) + offset)
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/* GPIOs implemented by AON GPIO controller */
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#define TEGRA_AON_GPIO_PORT_S 0
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#define TEGRA_AON_GPIO_PORT_U 1
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#define TEGRA_AON_GPIO_PORT_V 2
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#define TEGRA_AON_GPIO_PORT_W 3
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#define TEGRA_AON_GPIO_PORT_Z 4
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#define TEGRA_AON_GPIO_PORT_AA 5
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#define TEGRA_AON_GPIO_PORT_EE 6
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#define TEGRA_AON_GPIO_PORT_FF 7
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#define TEGRA_AON_GPIO(port, offset) \
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((TEGRA_AON_GPIO_PORT_##port * 8) + offset)
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#endif