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ARM: sunxi: irqchip: Update the documentation

A10 and A13 have a different set of available interrupt sources, reflect
this in the documentation.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Maxime Ripard ec3805e6 af65d459

+146 -85
+2 -85
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
··· 8 8 - #interrupt-cells : Specifies the number of cells needed to encode an 9 9 interrupt source. The value shall be 1. 10 10 11 - The interrupt sources are as follows: 12 - 13 - 0: ENMI 14 - 1: UART0 15 - 2: UART1 16 - 3: UART2 17 - 4: UART3 18 - 5: IR0 19 - 6: IR1 20 - 7: I2C0 21 - 8: I2C1 22 - 9: I2C2 23 - 10: SPI0 24 - 11: SPI1 25 - 12: SPI2 26 - 13: SPDIF 27 - 14: AC97 28 - 15: TS 29 - 16: I2S 30 - 17: UART4 31 - 18: UART5 32 - 19: UART6 33 - 20: UART7 34 - 21: KEYPAD 35 - 22: TIMER0 36 - 23: TIMER1 37 - 24: TIMER2 38 - 25: TIMER3 39 - 26: CAN 40 - 27: DMA 41 - 28: PIO 42 - 29: TOUCH_PANEL 43 - 30: AUDIO_CODEC 44 - 31: LRADC 45 - 32: SDMC0 46 - 33: SDMC1 47 - 34: SDMC2 48 - 35: SDMC3 49 - 36: MEMSTICK 50 - 37: NAND 51 - 38: USB0 52 - 39: USB1 53 - 40: USB2 54 - 41: SCR 55 - 42: CSI0 56 - 43: CSI1 57 - 44: LCDCTRL0 58 - 45: LCDCTRL1 59 - 46: MP 60 - 47: DEFEBE0 61 - 48: DEFEBE1 62 - 49: PMU 63 - 50: SPI3 64 - 51: TZASC 65 - 52: PATA 66 - 53: VE 67 - 54: SS 68 - 55: EMAC 69 - 56: SATA 70 - 57: GPS 71 - 58: HDMI 72 - 59: TVE 73 - 60: ACE 74 - 61: TVD 75 - 62: PS2_0 76 - 63: PS2_1 77 - 64: USB3 78 - 65: USB4 79 - 66: PLE_PFM 80 - 67: TIMER4 81 - 68: TIMER5 82 - 69: GPU_GP 83 - 70: GPU_GPMMU 84 - 71: GPU_PP0 85 - 72: GPU_PPMMU0 86 - 73: GPU_PMU 87 - 74: GPU_RSV0 88 - 75: GPU_RSV1 89 - 76: GPU_RSV2 90 - 77: GPU_RSV3 91 - 78: GPU_RSV4 92 - 79: GPU_RSV5 93 - 80: GPU_RSV6 94 - 82: SYNC_TIMER0 95 - 83: SYNC_TIMER1 11 + For the valid interrupt sources for your SoC, see the documentation in 12 + sunxi/<soc>.txt 96 13 97 14 Example: 98 15
+89
Documentation/devicetree/bindings/interrupt-controller/sunxi/sun4i-a10.txt
··· 1 + Allwinner A10 (sun4i) interrupt sources 2 + --------------------------------------- 3 + 4 + The interrupt sources available for the Allwinner A10 SoC are the 5 + following one: 6 + 7 + 0: ENMI 8 + 1: UART0 9 + 2: UART1 10 + 3: UART2 11 + 4: UART3 12 + 5: IR0 13 + 6: IR1 14 + 7: I2C0 15 + 8: I2C1 16 + 9: I2C2 17 + 10: SPI0 18 + 11: SPI1 19 + 12: SPI2 20 + 13: SPDIF 21 + 14: AC97 22 + 15: TS 23 + 16: I2S 24 + 17: UART4 25 + 18: UART5 26 + 19: UART6 27 + 20: UART7 28 + 21: KEYPAD 29 + 22: TIMER0 30 + 23: TIMER1 31 + 24: TIMER2 32 + 25: TIMER3 33 + 26: CAN 34 + 27: DMA 35 + 28: PIO 36 + 29: TOUCH_PANEL 37 + 30: AUDIO_CODEC 38 + 31: LRADC 39 + 32: MMC0 40 + 33: MMC1 41 + 34: MMC2 42 + 35: MMC3 43 + 36: MEMSTICK 44 + 37: NAND 45 + 38: USB0 46 + 39: USB1 47 + 40: USB2 48 + 41: SCR 49 + 42: CSI0 50 + 43: CSI1 51 + 44: LCDCTRL0 52 + 45: LCDCTRL1 53 + 46: MP 54 + 47: DEFEBE0 55 + 48: DEFEBE1 56 + 49: PMU 57 + 50: SPI3 58 + 51: TZASC 59 + 52: PATA 60 + 53: VE 61 + 54: SS 62 + 55: EMAC 63 + 56: SATA 64 + 57: GPS 65 + 58: HDMI 66 + 59: TVE 67 + 60: ACE 68 + 61: TVD 69 + 62: PS2_0 70 + 63: PS2_1 71 + 64: USB3 72 + 65: USB4 73 + 66: PLE_PFM 74 + 67: TIMER4 75 + 68: TIMER5 76 + 69: GPU_GP 77 + 70: GPU_GPMMU 78 + 71: GPU_PP0 79 + 72: GPU_PPMMU0 80 + 73: GPU_PMU 81 + 74: GPU_RSV0 82 + 75: GPU_RSV1 83 + 76: GPU_RSV2 84 + 77: GPU_RSV3 85 + 78: GPU_RSV4 86 + 79: GPU_RSV5 87 + 80: GPU_RSV6 88 + 82: SYNC_TIMER0 89 + 83: SYNC_TIMER1
+55
Documentation/devicetree/bindings/interrupt-controller/sunxi/sun5i-a13.txt
··· 1 + Allwinner A13 (sun5i) interrupt sources 2 + --------------------------------------- 3 + 4 + The interrupt sources available for the Allwinner A13 SoC are the 5 + following one: 6 + 7 + 0: ENMI 8 + 2: UART1 9 + 4: UART3 10 + 5: IR 11 + 7: I2C0 12 + 8: I2C1 13 + 9: I2C2 14 + 10: SPI0 15 + 11: SPI1 16 + 12: SPI2 17 + 22: TIMER0 18 + 23: TIMER1 19 + 24: TIMER2 20 + 25: TIMER3 21 + 27: DMA 22 + 28: PIO 23 + 29: TOUCH_PANEL 24 + 30: AUDIO_CODEC 25 + 31: LRADC 26 + 32: MMC0 27 + 33: MMC1 28 + 34: MMC2 29 + 37: NAND 30 + 38: USB OTG 31 + 39: USB EHCI 32 + 40: USB OHCI 33 + 42: CSI 34 + 44: LCDCTRL 35 + 47: DEFEBE 36 + 49: PMU 37 + 53: VE 38 + 54: SS 39 + 66: PLE_PFM 40 + 67: TIMER4 41 + 68: TIMER5 42 + 69: GPU_GP 43 + 70: GPU_GPMMU 44 + 71: GPU_PP0 45 + 72: GPU_PPMMU0 46 + 73: GPU_PMU 47 + 74: GPU_RSV0 48 + 75: GPU_RSV1 49 + 76: GPU_RSV2 50 + 77: GPU_RSV3 51 + 78: GPU_RSV4 52 + 79: GPU_RSV5 53 + 80: GPU_RSV6 54 + 82: SYNC_TIMER0 55 + 83: SYNC_TIMER1