tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Disintegrate asm/system.h for Alpha
Disintegrate asm/system.h for Alpha.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: linux-alpha@vger.kernel.org
+388
-402
-1
arch/alpha/boot/bootp.c
-1
arch/alpha/boot/bootp.c
-1
arch/alpha/boot/bootpz.c
-1
arch/alpha/boot/bootpz.c
-1
arch/alpha/boot/head.S
-1
arch/alpha/boot/head.S
-1
arch/alpha/boot/main.c
-1
arch/alpha/boot/main.c
+67
-1
arch/alpha/include/asm/atomic.h
+67
-1
arch/alpha/include/asm/atomic.h
···
3
3
4
4
#include <linux/types.h>
5
5
#include <asm/barrier.h>
6
-
#include <asm/system.h>
7
6
8
7
/*
9
8
* Atomic operations that C can't guarantee us. Useful for
···
167
168
smp_mb();
168
169
return result;
169
170
}
171
+
172
+
/*
173
+
* Atomic exchange routines.
174
+
*/
175
+
176
+
#define __ASM__MB
177
+
#define ____xchg(type, args...) __xchg ## type ## _local(args)
178
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#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
179
+
#include <asm/xchg.h>
180
+
181
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#define xchg_local(ptr,x) \
182
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
184
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(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
185
+
sizeof(*(ptr))); \
186
+
})
187
+
188
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#define cmpxchg_local(ptr, o, n) \
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+
({ \
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__typeof__(*(ptr)) _o_ = (o); \
191
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__typeof__(*(ptr)) _n_ = (n); \
192
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(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
193
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(unsigned long)_n_, \
194
+
sizeof(*(ptr))); \
195
+
})
196
+
197
+
#define cmpxchg64_local(ptr, o, n) \
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+
({ \
199
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
200
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cmpxchg_local((ptr), (o), (n)); \
201
+
})
202
+
203
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#ifdef CONFIG_SMP
204
+
#undef __ASM__MB
205
+
#define __ASM__MB "\tmb\n"
206
+
#endif
207
+
#undef ____xchg
208
+
#undef ____cmpxchg
209
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#define ____xchg(type, args...) __xchg ##type(args)
210
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#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
211
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#include <asm/xchg.h>
212
+
213
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#define xchg(ptr,x) \
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({ \
215
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__typeof__(*(ptr)) _x_ = (x); \
216
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(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
217
+
sizeof(*(ptr))); \
218
+
})
219
+
220
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#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
223
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__typeof__(*(ptr)) _n_ = (n); \
224
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
225
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(unsigned long)_n_, sizeof(*(ptr)));\
226
+
})
227
+
228
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#define cmpxchg64(ptr, o, n) \
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({ \
230
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BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
231
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cmpxchg((ptr), (o), (n)); \
232
+
})
233
+
234
+
#undef __ASM__MB
235
+
#undef ____cmpxchg
236
+
237
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#define __HAVE_ARCH_CMPXCHG 1
170
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#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
172
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+2
arch/alpha/include/asm/auxvec.h
+2
arch/alpha/include/asm/auxvec.h
+1
-1
arch/alpha/include/asm/core_lca.h
+1
-1
arch/alpha/include/asm/core_lca.h
+1
arch/alpha/include/asm/core_mcpcia.h
+1
arch/alpha/include/asm/core_mcpcia.h
-1
arch/alpha/include/asm/core_t2.h
-1
arch/alpha/include/asm/core_t2.h
+1
arch/alpha/include/asm/elf.h
+1
arch/alpha/include/asm/elf.h
+6
arch/alpha/include/asm/exec.h
+6
arch/alpha/include/asm/exec.h
+2
arch/alpha/include/asm/fpu.h
+2
arch/alpha/include/asm/fpu.h
-1
arch/alpha/include/asm/io.h
-1
arch/alpha/include/asm/io.h
+1
-1
arch/alpha/include/asm/irqflags.h
+1
-1
arch/alpha/include/asm/irqflags.h
+83
arch/alpha/include/asm/mce.h
+83
arch/alpha/include/asm/mce.h
···
1
+
#ifndef __ALPHA_MCE_H
2
+
#define __ALPHA_MCE_H
3
+
4
+
/*
5
+
* This is the logout header that should be common to all platforms
6
+
* (assuming they are running OSF/1 PALcode, I guess).
7
+
*/
8
+
struct el_common {
9
+
unsigned int size; /* size in bytes of logout area */
10
+
unsigned int sbz1 : 30; /* should be zero */
11
+
unsigned int err2 : 1; /* second error */
12
+
unsigned int retry : 1; /* retry flag */
13
+
unsigned int proc_offset; /* processor-specific offset */
14
+
unsigned int sys_offset; /* system-specific offset */
15
+
unsigned int code; /* machine check code */
16
+
unsigned int frame_rev; /* frame revision */
17
+
};
18
+
19
+
/* Machine Check Frame for uncorrectable errors (Large format)
20
+
* --- This is used to log uncorrectable errors such as
21
+
* double bit ECC errors.
22
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* --- These errors are detected by both processor and systems.
23
+
*/
24
+
struct el_common_EV5_uncorrectable_mcheck {
25
+
unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
26
+
unsigned long paltemp[24]; /* PAL TEMP REGS. */
27
+
unsigned long exc_addr; /* Address of excepting instruction*/
28
+
unsigned long exc_sum; /* Summary of arithmetic traps. */
29
+
unsigned long exc_mask; /* Exception mask (from exc_sum). */
30
+
unsigned long pal_base; /* Base address for PALcode. */
31
+
unsigned long isr; /* Interrupt Status Reg. */
32
+
unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */
33
+
unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
34
+
<12> set TAG parity*/
35
+
unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
36
+
<2> Data error in bank 0
37
+
<3> Data error in bank 1
38
+
<4> Tag error in bank 0
39
+
<5> Tag error in bank 1 */
40
+
unsigned long va; /* Effective VA of fault or miss. */
41
+
unsigned long mm_stat; /* Holds the reason for D-stream
42
+
fault or D-cache parity errors */
43
+
unsigned long sc_addr; /* Address that was being accessed
44
+
when EV5 detected Secondary cache
45
+
failure. */
46
+
unsigned long sc_stat; /* Helps determine if the error was
47
+
TAG/Data parity(Secondary Cache)*/
48
+
unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
49
+
unsigned long ei_addr; /* Physical address of any transfer
50
+
that is logged in EV5 EI_STAT */
51
+
unsigned long fill_syndrome; /* For correcting ECC errors. */
52
+
unsigned long ei_stat; /* Helps identify reason of any
53
+
processor uncorrectable error
54
+
at its external interface. */
55
+
unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/
56
+
};
57
+
58
+
struct el_common_EV6_mcheck {
59
+
unsigned int FrameSize; /* Bytes, including this field */
60
+
unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */
61
+
unsigned int CpuOffset; /* Offset to CPU-specific info */
62
+
unsigned int SystemOffset; /* Offset to system-specific info */
63
+
unsigned int MCHK_Code;
64
+
unsigned int MCHK_Frame_Rev;
65
+
unsigned long I_STAT; /* EV6 Internal Processor Registers */
66
+
unsigned long DC_STAT; /* (See the 21264 Spec) */
67
+
unsigned long C_ADDR;
68
+
unsigned long DC1_SYNDROME;
69
+
unsigned long DC0_SYNDROME;
70
+
unsigned long C_STAT;
71
+
unsigned long C_STS;
72
+
unsigned long MM_STAT;
73
+
unsigned long EXC_ADDR;
74
+
unsigned long IER_CM;
75
+
unsigned long ISUM;
76
+
unsigned long RESERVED0;
77
+
unsigned long PAL_BASE;
78
+
unsigned long I_CTL;
79
+
unsigned long PCTX;
80
+
};
81
+
82
+
83
+
#endif /* __ALPHA_MCE_H */
-1
arch/alpha/include/asm/mmu_context.h
-1
arch/alpha/include/asm/mmu_context.h
+112
arch/alpha/include/asm/pal.h
+112
arch/alpha/include/asm/pal.h
···
48
48
#define PAL_retsys 61
49
49
#define PAL_rti 63
50
50
51
+
#ifdef __KERNEL__
52
+
#ifndef __ASSEMBLY__
53
+
54
+
extern void halt(void) __attribute__((noreturn));
55
+
#define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
56
+
57
+
#define imb() \
58
+
__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
59
+
60
+
#define draina() \
61
+
__asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
62
+
63
+
#define __CALL_PAL_R0(NAME, TYPE) \
64
+
extern inline TYPE NAME(void) \
65
+
{ \
66
+
register TYPE __r0 __asm__("$0"); \
67
+
__asm__ __volatile__( \
68
+
"call_pal %1 # " #NAME \
69
+
:"=r" (__r0) \
70
+
:"i" (PAL_ ## NAME) \
71
+
:"$1", "$16", "$22", "$23", "$24", "$25"); \
72
+
return __r0; \
73
+
}
74
+
75
+
#define __CALL_PAL_W1(NAME, TYPE0) \
76
+
extern inline void NAME(TYPE0 arg0) \
77
+
{ \
78
+
register TYPE0 __r16 __asm__("$16") = arg0; \
79
+
__asm__ __volatile__( \
80
+
"call_pal %1 # "#NAME \
81
+
: "=r"(__r16) \
82
+
: "i"(PAL_ ## NAME), "0"(__r16) \
83
+
: "$1", "$22", "$23", "$24", "$25"); \
84
+
}
85
+
86
+
#define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
87
+
extern inline void NAME(TYPE0 arg0, TYPE1 arg1) \
88
+
{ \
89
+
register TYPE0 __r16 __asm__("$16") = arg0; \
90
+
register TYPE1 __r17 __asm__("$17") = arg1; \
91
+
__asm__ __volatile__( \
92
+
"call_pal %2 # "#NAME \
93
+
: "=r"(__r16), "=r"(__r17) \
94
+
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
95
+
: "$1", "$22", "$23", "$24", "$25"); \
96
+
}
97
+
98
+
#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
99
+
extern inline RTYPE NAME(TYPE0 arg0) \
100
+
{ \
101
+
register RTYPE __r0 __asm__("$0"); \
102
+
register TYPE0 __r16 __asm__("$16") = arg0; \
103
+
__asm__ __volatile__( \
104
+
"call_pal %2 # "#NAME \
105
+
: "=r"(__r16), "=r"(__r0) \
106
+
: "i"(PAL_ ## NAME), "0"(__r16) \
107
+
: "$1", "$22", "$23", "$24", "$25"); \
108
+
return __r0; \
109
+
}
110
+
111
+
#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
112
+
extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
113
+
{ \
114
+
register RTYPE __r0 __asm__("$0"); \
115
+
register TYPE0 __r16 __asm__("$16") = arg0; \
116
+
register TYPE1 __r17 __asm__("$17") = arg1; \
117
+
__asm__ __volatile__( \
118
+
"call_pal %3 # "#NAME \
119
+
: "=r"(__r16), "=r"(__r17), "=r"(__r0) \
120
+
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
121
+
: "$1", "$22", "$23", "$24", "$25"); \
122
+
return __r0; \
123
+
}
124
+
125
+
__CALL_PAL_W1(cflush, unsigned long);
126
+
__CALL_PAL_R0(rdmces, unsigned long);
127
+
__CALL_PAL_R0(rdps, unsigned long);
128
+
__CALL_PAL_R0(rdusp, unsigned long);
129
+
__CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
130
+
__CALL_PAL_R0(whami, unsigned long);
131
+
__CALL_PAL_W2(wrent, void*, unsigned long);
132
+
__CALL_PAL_W1(wripir, unsigned long);
133
+
__CALL_PAL_W1(wrkgp, unsigned long);
134
+
__CALL_PAL_W1(wrmces, unsigned long);
135
+
__CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
136
+
__CALL_PAL_W1(wrusp, unsigned long);
137
+
__CALL_PAL_W1(wrvptptr, unsigned long);
138
+
139
+
/*
140
+
* TB routines..
141
+
*/
142
+
#define __tbi(nr,arg,arg1...) \
143
+
({ \
144
+
register unsigned long __r16 __asm__("$16") = (nr); \
145
+
register unsigned long __r17 __asm__("$17"); arg; \
146
+
__asm__ __volatile__( \
147
+
"call_pal %3 #__tbi" \
148
+
:"=r" (__r16),"=r" (__r17) \
149
+
:"0" (__r16),"i" (PAL_tbi) ,##arg1 \
150
+
:"$0", "$1", "$22", "$23", "$24", "$25"); \
151
+
})
152
+
153
+
#define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17))
154
+
#define tbisi(x) __tbi(1,__r17=(x),"1" (__r17))
155
+
#define tbisd(x) __tbi(2,__r17=(x),"1" (__r17))
156
+
#define tbis(x) __tbi(3,__r17=(x),"1" (__r17))
157
+
#define tbiap() __tbi(-1, /* no second argument */)
158
+
#define tbia() __tbi(-2, /* no second argument */)
159
+
160
+
#endif /* !__ASSEMBLY__ */
161
+
#endif /* __KERNEL__ */
162
+
51
163
#endif /* __ALPHA_PAL_H */
+1
arch/alpha/include/asm/pgtable.h
+1
arch/alpha/include/asm/pgtable.h
+36
arch/alpha/include/asm/setup.h
+36
arch/alpha/include/asm/setup.h
···
3
3
4
4
#define COMMAND_LINE_SIZE 256
5
5
6
+
/*
7
+
* We leave one page for the initial stack page, and one page for
8
+
* the initial process structure. Also, the console eats 3 MB for
9
+
* the initial bootloader (one of which we can reclaim later).
10
+
*/
11
+
#define BOOT_PCB 0x20000000
12
+
#define BOOT_ADDR 0x20000000
13
+
/* Remove when official MILO sources have ELF support: */
14
+
#define BOOT_SIZE (16*1024)
15
+
16
+
#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
17
+
#define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
18
+
#else
19
+
#define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
20
+
#endif
21
+
22
+
#define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
23
+
#define SWAPPER_PGD KERNEL_START
24
+
#define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
25
+
#define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
26
+
#define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
27
+
#define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
28
+
29
+
#define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
30
+
31
+
/*
32
+
* This is setup by the secondary bootstrap loader. Because
33
+
* the zero page is zeroed out as soon as the vm system is
34
+
* initialized, we need to copy things out into a more permanent
35
+
* place.
36
+
*/
37
+
#define PARAM ZERO_PGE
38
+
#define COMMAND_LINE ((char*)(PARAM + 0x0000))
39
+
#define INITRD_START (*(unsigned long *) (PARAM+0x100))
40
+
#define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
41
+
6
42
#endif
+41
arch/alpha/include/asm/special_insns.h
+41
arch/alpha/include/asm/special_insns.h
···
1
+
#ifndef __ALPHA_SPECIAL_INSNS_H
2
+
#define __ALPHA_SPECIAL_INSNS_H
3
+
4
+
enum implver_enum {
5
+
IMPLVER_EV4,
6
+
IMPLVER_EV5,
7
+
IMPLVER_EV6
8
+
};
9
+
10
+
#ifdef CONFIG_ALPHA_GENERIC
11
+
#define implver() \
12
+
({ unsigned long __implver; \
13
+
__asm__ ("implver %0" : "=r"(__implver)); \
14
+
(enum implver_enum) __implver; })
15
+
#else
16
+
/* Try to eliminate some dead code. */
17
+
#ifdef CONFIG_ALPHA_EV4
18
+
#define implver() IMPLVER_EV4
19
+
#endif
20
+
#ifdef CONFIG_ALPHA_EV5
21
+
#define implver() IMPLVER_EV5
22
+
#endif
23
+
#if defined(CONFIG_ALPHA_EV6)
24
+
#define implver() IMPLVER_EV6
25
+
#endif
26
+
#endif
27
+
28
+
enum amask_enum {
29
+
AMASK_BWX = (1UL << 0),
30
+
AMASK_FIX = (1UL << 1),
31
+
AMASK_CIX = (1UL << 2),
32
+
AMASK_MAX = (1UL << 8),
33
+
AMASK_PRECISE_TRAP = (1UL << 9),
34
+
};
35
+
36
+
#define amask(mask) \
37
+
({ unsigned long __amask, __input = (mask); \
38
+
__asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input)); \
39
+
__amask; })
40
+
41
+
#endif /* __ALPHA_SPECIAL_INSNS_H */
-1
arch/alpha/include/asm/spinlock.h
-1
arch/alpha/include/asm/spinlock.h
+14
arch/alpha/include/asm/switch_to.h
+14
arch/alpha/include/asm/switch_to.h
···
1
+
#ifndef __ALPHA_SWITCH_TO_H
2
+
#define __ALPHA_SWITCH_TO_H
3
+
4
+
5
+
struct task_struct;
6
+
extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct *);
7
+
8
+
#define switch_to(P,N,L) \
9
+
do { \
10
+
(L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
11
+
check_mmu_context(); \
12
+
} while (0)
13
+
14
+
#endif /* __ALPHA_SWITCH_TO_H */
+4
-353
arch/alpha/include/asm/system.h
+4
-353
arch/alpha/include/asm/system.h
···
1
-
#ifndef __ALPHA_SYSTEM_H
2
-
#define __ALPHA_SYSTEM_H
3
-
4
-
#include <asm/pal.h>
5
-
#include <asm/page.h>
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
6
2
#include <asm/barrier.h>
7
-
8
-
/*
9
-
* System defines.. Note that this is included both from .c and .S
10
-
* files, so it does only defines, not any C code.
11
-
*/
12
-
13
-
/*
14
-
* We leave one page for the initial stack page, and one page for
15
-
* the initial process structure. Also, the console eats 3 MB for
16
-
* the initial bootloader (one of which we can reclaim later).
17
-
*/
18
-
#define BOOT_PCB 0x20000000
19
-
#define BOOT_ADDR 0x20000000
20
-
/* Remove when official MILO sources have ELF support: */
21
-
#define BOOT_SIZE (16*1024)
22
-
23
-
#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
24
-
#define KERNEL_START_PHYS 0x300000 /* Old bootloaders hardcoded this. */
25
-
#else
26
-
#define KERNEL_START_PHYS 0x1000000 /* required: Wildfire/Titan/Marvel */
27
-
#endif
28
-
29
-
#define KERNEL_START (PAGE_OFFSET+KERNEL_START_PHYS)
30
-
#define SWAPPER_PGD KERNEL_START
31
-
#define INIT_STACK (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
32
-
#define EMPTY_PGT (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
33
-
#define EMPTY_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
34
-
#define ZERO_PGE (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
35
-
36
-
#define START_ADDR (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
37
-
38
-
/*
39
-
* This is setup by the secondary bootstrap loader. Because
40
-
* the zero page is zeroed out as soon as the vm system is
41
-
* initialized, we need to copy things out into a more permanent
42
-
* place.
43
-
*/
44
-
#define PARAM ZERO_PGE
45
-
#define COMMAND_LINE ((char*)(PARAM + 0x0000))
46
-
#define INITRD_START (*(unsigned long *) (PARAM+0x100))
47
-
#define INITRD_SIZE (*(unsigned long *) (PARAM+0x108))
48
-
49
-
#ifndef __ASSEMBLY__
50
-
#include <linux/kernel.h>
51
-
#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */
52
-
53
-
/*
54
-
* This is the logout header that should be common to all platforms
55
-
* (assuming they are running OSF/1 PALcode, I guess).
56
-
*/
57
-
struct el_common {
58
-
unsigned int size; /* size in bytes of logout area */
59
-
unsigned int sbz1 : 30; /* should be zero */
60
-
unsigned int err2 : 1; /* second error */
61
-
unsigned int retry : 1; /* retry flag */
62
-
unsigned int proc_offset; /* processor-specific offset */
63
-
unsigned int sys_offset; /* system-specific offset */
64
-
unsigned int code; /* machine check code */
65
-
unsigned int frame_rev; /* frame revision */
66
-
};
67
-
68
-
/* Machine Check Frame for uncorrectable errors (Large format)
69
-
* --- This is used to log uncorrectable errors such as
70
-
* double bit ECC errors.
71
-
* --- These errors are detected by both processor and systems.
72
-
*/
73
-
struct el_common_EV5_uncorrectable_mcheck {
74
-
unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
75
-
unsigned long paltemp[24]; /* PAL TEMP REGS. */
76
-
unsigned long exc_addr; /* Address of excepting instruction*/
77
-
unsigned long exc_sum; /* Summary of arithmetic traps. */
78
-
unsigned long exc_mask; /* Exception mask (from exc_sum). */
79
-
unsigned long pal_base; /* Base address for PALcode. */
80
-
unsigned long isr; /* Interrupt Status Reg. */
81
-
unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */
82
-
unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
83
-
<12> set TAG parity*/
84
-
unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
85
-
<2> Data error in bank 0
86
-
<3> Data error in bank 1
87
-
<4> Tag error in bank 0
88
-
<5> Tag error in bank 1 */
89
-
unsigned long va; /* Effective VA of fault or miss. */
90
-
unsigned long mm_stat; /* Holds the reason for D-stream
91
-
fault or D-cache parity errors */
92
-
unsigned long sc_addr; /* Address that was being accessed
93
-
when EV5 detected Secondary cache
94
-
failure. */
95
-
unsigned long sc_stat; /* Helps determine if the error was
96
-
TAG/Data parity(Secondary Cache)*/
97
-
unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
98
-
unsigned long ei_addr; /* Physical address of any transfer
99
-
that is logged in EV5 EI_STAT */
100
-
unsigned long fill_syndrome; /* For correcting ECC errors. */
101
-
unsigned long ei_stat; /* Helps identify reason of any
102
-
processor uncorrectable error
103
-
at its external interface. */
104
-
unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/
105
-
};
106
-
107
-
struct el_common_EV6_mcheck {
108
-
unsigned int FrameSize; /* Bytes, including this field */
109
-
unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */
110
-
unsigned int CpuOffset; /* Offset to CPU-specific info */
111
-
unsigned int SystemOffset; /* Offset to system-specific info */
112
-
unsigned int MCHK_Code;
113
-
unsigned int MCHK_Frame_Rev;
114
-
unsigned long I_STAT; /* EV6 Internal Processor Registers */
115
-
unsigned long DC_STAT; /* (See the 21264 Spec) */
116
-
unsigned long C_ADDR;
117
-
unsigned long DC1_SYNDROME;
118
-
unsigned long DC0_SYNDROME;
119
-
unsigned long C_STAT;
120
-
unsigned long C_STS;
121
-
unsigned long MM_STAT;
122
-
unsigned long EXC_ADDR;
123
-
unsigned long IER_CM;
124
-
unsigned long ISUM;
125
-
unsigned long RESERVED0;
126
-
unsigned long PAL_BASE;
127
-
unsigned long I_CTL;
128
-
unsigned long PCTX;
129
-
};
130
-
131
-
extern void halt(void) __attribute__((noreturn));
132
-
#define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
133
-
134
-
#define switch_to(P,N,L) \
135
-
do { \
136
-
(L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
137
-
check_mmu_context(); \
138
-
} while (0)
139
-
140
-
struct task_struct;
141
-
extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
142
-
143
-
#define imb() \
144
-
__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
145
-
146
-
#define draina() \
147
-
__asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
148
-
149
-
enum implver_enum {
150
-
IMPLVER_EV4,
151
-
IMPLVER_EV5,
152
-
IMPLVER_EV6
153
-
};
154
-
155
-
#ifdef CONFIG_ALPHA_GENERIC
156
-
#define implver() \
157
-
({ unsigned long __implver; \
158
-
__asm__ ("implver %0" : "=r"(__implver)); \
159
-
(enum implver_enum) __implver; })
160
-
#else
161
-
/* Try to eliminate some dead code. */
162
-
#ifdef CONFIG_ALPHA_EV4
163
-
#define implver() IMPLVER_EV4
164
-
#endif
165
-
#ifdef CONFIG_ALPHA_EV5
166
-
#define implver() IMPLVER_EV5
167
-
#endif
168
-
#if defined(CONFIG_ALPHA_EV6)
169
-
#define implver() IMPLVER_EV6
170
-
#endif
171
-
#endif
172
-
173
-
enum amask_enum {
174
-
AMASK_BWX = (1UL << 0),
175
-
AMASK_FIX = (1UL << 1),
176
-
AMASK_CIX = (1UL << 2),
177
-
AMASK_MAX = (1UL << 8),
178
-
AMASK_PRECISE_TRAP = (1UL << 9),
179
-
};
180
-
181
-
#define amask(mask) \
182
-
({ unsigned long __amask, __input = (mask); \
183
-
__asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input)); \
184
-
__amask; })
185
-
186
-
#define __CALL_PAL_R0(NAME, TYPE) \
187
-
extern inline TYPE NAME(void) \
188
-
{ \
189
-
register TYPE __r0 __asm__("$0"); \
190
-
__asm__ __volatile__( \
191
-
"call_pal %1 # " #NAME \
192
-
:"=r" (__r0) \
193
-
:"i" (PAL_ ## NAME) \
194
-
:"$1", "$16", "$22", "$23", "$24", "$25"); \
195
-
return __r0; \
196
-
}
197
-
198
-
#define __CALL_PAL_W1(NAME, TYPE0) \
199
-
extern inline void NAME(TYPE0 arg0) \
200
-
{ \
201
-
register TYPE0 __r16 __asm__("$16") = arg0; \
202
-
__asm__ __volatile__( \
203
-
"call_pal %1 # "#NAME \
204
-
: "=r"(__r16) \
205
-
: "i"(PAL_ ## NAME), "0"(__r16) \
206
-
: "$1", "$22", "$23", "$24", "$25"); \
207
-
}
208
-
209
-
#define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
210
-
extern inline void NAME(TYPE0 arg0, TYPE1 arg1) \
211
-
{ \
212
-
register TYPE0 __r16 __asm__("$16") = arg0; \
213
-
register TYPE1 __r17 __asm__("$17") = arg1; \
214
-
__asm__ __volatile__( \
215
-
"call_pal %2 # "#NAME \
216
-
: "=r"(__r16), "=r"(__r17) \
217
-
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
218
-
: "$1", "$22", "$23", "$24", "$25"); \
219
-
}
220
-
221
-
#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
222
-
extern inline RTYPE NAME(TYPE0 arg0) \
223
-
{ \
224
-
register RTYPE __r0 __asm__("$0"); \
225
-
register TYPE0 __r16 __asm__("$16") = arg0; \
226
-
__asm__ __volatile__( \
227
-
"call_pal %2 # "#NAME \
228
-
: "=r"(__r16), "=r"(__r0) \
229
-
: "i"(PAL_ ## NAME), "0"(__r16) \
230
-
: "$1", "$22", "$23", "$24", "$25"); \
231
-
return __r0; \
232
-
}
233
-
234
-
#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
235
-
extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
236
-
{ \
237
-
register RTYPE __r0 __asm__("$0"); \
238
-
register TYPE0 __r16 __asm__("$16") = arg0; \
239
-
register TYPE1 __r17 __asm__("$17") = arg1; \
240
-
__asm__ __volatile__( \
241
-
"call_pal %3 # "#NAME \
242
-
: "=r"(__r16), "=r"(__r17), "=r"(__r0) \
243
-
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
244
-
: "$1", "$22", "$23", "$24", "$25"); \
245
-
return __r0; \
246
-
}
247
-
248
-
__CALL_PAL_W1(cflush, unsigned long);
249
-
__CALL_PAL_R0(rdmces, unsigned long);
250
-
__CALL_PAL_R0(rdps, unsigned long);
251
-
__CALL_PAL_R0(rdusp, unsigned long);
252
-
__CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
253
-
__CALL_PAL_R0(whami, unsigned long);
254
-
__CALL_PAL_W2(wrent, void*, unsigned long);
255
-
__CALL_PAL_W1(wripir, unsigned long);
256
-
__CALL_PAL_W1(wrkgp, unsigned long);
257
-
__CALL_PAL_W1(wrmces, unsigned long);
258
-
__CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
259
-
__CALL_PAL_W1(wrusp, unsigned long);
260
-
__CALL_PAL_W1(wrvptptr, unsigned long);
261
-
262
-
/*
263
-
* TB routines..
264
-
*/
265
-
#define __tbi(nr,arg,arg1...) \
266
-
({ \
267
-
register unsigned long __r16 __asm__("$16") = (nr); \
268
-
register unsigned long __r17 __asm__("$17"); arg; \
269
-
__asm__ __volatile__( \
270
-
"call_pal %3 #__tbi" \
271
-
:"=r" (__r16),"=r" (__r17) \
272
-
:"0" (__r16),"i" (PAL_tbi) ,##arg1 \
273
-
:"$0", "$1", "$22", "$23", "$24", "$25"); \
274
-
})
275
-
276
-
#define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17))
277
-
#define tbisi(x) __tbi(1,__r17=(x),"1" (__r17))
278
-
#define tbisd(x) __tbi(2,__r17=(x),"1" (__r17))
279
-
#define tbis(x) __tbi(3,__r17=(x),"1" (__r17))
280
-
#define tbiap() __tbi(-1, /* no second argument */)
281
-
#define tbia() __tbi(-2, /* no second argument */)
282
-
283
-
/*
284
-
* Atomic exchange routines.
285
-
*/
286
-
287
-
#define __ASM__MB
288
-
#define ____xchg(type, args...) __xchg ## type ## _local(args)
289
-
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
290
-
#include <asm/xchg.h>
291
-
292
-
#define xchg_local(ptr,x) \
293
-
({ \
294
-
__typeof__(*(ptr)) _x_ = (x); \
295
-
(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
296
-
sizeof(*(ptr))); \
297
-
})
298
-
299
-
#define cmpxchg_local(ptr, o, n) \
300
-
({ \
301
-
__typeof__(*(ptr)) _o_ = (o); \
302
-
__typeof__(*(ptr)) _n_ = (n); \
303
-
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
304
-
(unsigned long)_n_, \
305
-
sizeof(*(ptr))); \
306
-
})
307
-
308
-
#define cmpxchg64_local(ptr, o, n) \
309
-
({ \
310
-
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
311
-
cmpxchg_local((ptr), (o), (n)); \
312
-
})
313
-
314
-
#ifdef CONFIG_SMP
315
-
#undef __ASM__MB
316
-
#define __ASM__MB "\tmb\n"
317
-
#endif
318
-
#undef ____xchg
319
-
#undef ____cmpxchg
320
-
#define ____xchg(type, args...) __xchg ##type(args)
321
-
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
322
-
#include <asm/xchg.h>
323
-
324
-
#define xchg(ptr,x) \
325
-
({ \
326
-
__typeof__(*(ptr)) _x_ = (x); \
327
-
(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
328
-
sizeof(*(ptr))); \
329
-
})
330
-
331
-
#define cmpxchg(ptr, o, n) \
332
-
({ \
333
-
__typeof__(*(ptr)) _o_ = (o); \
334
-
__typeof__(*(ptr)) _n_ = (n); \
335
-
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
336
-
(unsigned long)_n_, sizeof(*(ptr)));\
337
-
})
338
-
339
-
#define cmpxchg64(ptr, o, n) \
340
-
({ \
341
-
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
342
-
cmpxchg((ptr), (o), (n)); \
343
-
})
344
-
345
-
#undef __ASM__MB
346
-
#undef ____cmpxchg
347
-
348
-
#define __HAVE_ARCH_CMPXCHG 1
349
-
350
-
#endif /* __ASSEMBLY__ */
351
-
352
-
#define arch_align_stack(x) (x)
353
-
354
-
#endif
3
+
#include <asm/exec.h>
4
+
#include <asm/special_insns.h>
5
+
#include <asm/switch_to.h>
+1
-1
arch/alpha/include/asm/xchg.h
+1
-1
arch/alpha/include/asm/xchg.h
+1
arch/alpha/kernel/core_apecs.c
+1
arch/alpha/kernel/core_apecs.c
+1
arch/alpha/kernel/core_cia.c
+1
arch/alpha/kernel/core_cia.c
+1
arch/alpha/kernel/core_t2.c
+1
arch/alpha/kernel/core_t2.c
+2
arch/alpha/kernel/err_impl.h
+2
arch/alpha/kernel/err_impl.h
+2
-4
arch/alpha/kernel/head.S
+2
-4
arch/alpha/kernel/head.S
···
8
8
*/
9
9
10
10
#include <linux/init.h>
11
-
#include <asm/system.h>
12
11
#include <asm/asm-offsets.h>
12
+
#include <asm/pal.h>
13
+
#include <asm/setup.h>
13
14
14
15
__HEAD
15
-
.globl swapper_pg_dir
16
16
.globl _stext
17
-
swapper_pg_dir=SWAPPER_PGD
18
-
19
17
.set noreorder
20
18
.globl __start
21
19
.ent __start
-1
arch/alpha/kernel/irq.c
-1
arch/alpha/kernel/irq.c
+1
arch/alpha/kernel/irq_alpha.c
+1
arch/alpha/kernel/irq_alpha.c
-1
arch/alpha/kernel/osf_sys.c
-1
arch/alpha/kernel/osf_sys.c
-1
arch/alpha/kernel/process.c
-1
arch/alpha/kernel/process.c
-1
arch/alpha/kernel/ptrace.c
-1
arch/alpha/kernel/ptrace.c
-1
arch/alpha/kernel/setup.c
-1
arch/alpha/kernel/setup.c
-1
arch/alpha/kernel/sys_alcor.c
-1
arch/alpha/kernel/sys_alcor.c
-1
arch/alpha/kernel/sys_cabriolet.c
-1
arch/alpha/kernel/sys_cabriolet.c
-1
arch/alpha/kernel/sys_dp264.c
-1
arch/alpha/kernel/sys_dp264.c
-1
arch/alpha/kernel/sys_eb64p.c
-1
arch/alpha/kernel/sys_eb64p.c
-1
arch/alpha/kernel/sys_eiger.c
-1
arch/alpha/kernel/sys_eiger.c
-1
arch/alpha/kernel/sys_jensen.c
-1
arch/alpha/kernel/sys_jensen.c
-1
arch/alpha/kernel/sys_marvel.c
-1
arch/alpha/kernel/sys_marvel.c
-1
arch/alpha/kernel/sys_miata.c
-1
arch/alpha/kernel/sys_miata.c
+1
-1
arch/alpha/kernel/sys_mikasa.c
+1
-1
arch/alpha/kernel/sys_mikasa.c
-1
arch/alpha/kernel/sys_nautilus.c
-1
arch/alpha/kernel/sys_nautilus.c
+1
-1
arch/alpha/kernel/sys_noritake.c
+1
-1
arch/alpha/kernel/sys_noritake.c
-1
arch/alpha/kernel/sys_rawhide.c
-1
arch/alpha/kernel/sys_rawhide.c
-1
arch/alpha/kernel/sys_ruffian.c
-1
arch/alpha/kernel/sys_ruffian.c
-1
arch/alpha/kernel/sys_rx164.c
-1
arch/alpha/kernel/sys_rx164.c
-1
arch/alpha/kernel/sys_sable.c
-1
arch/alpha/kernel/sys_sable.c
-1
arch/alpha/kernel/sys_sio.c
-1
arch/alpha/kernel/sys_sio.c
+1
-1
arch/alpha/kernel/sys_sx164.c
+1
-1
arch/alpha/kernel/sys_sx164.c
···
17
17
#include <linux/bitops.h>
18
18
19
19
#include <asm/ptrace.h>
20
-
#include <asm/system.h>
21
20
#include <asm/dma.h>
22
21
#include <asm/irq.h>
23
22
#include <asm/mmu_context.h>
···
25
26
#include <asm/core_cia.h>
26
27
#include <asm/hwrpb.h>
27
28
#include <asm/tlbflush.h>
29
+
#include <asm/special_insns.h>
28
30
29
31
#include "proto.h"
30
32
#include "irq_impl.h"
-1
arch/alpha/kernel/sys_takara.c
-1
arch/alpha/kernel/sys_takara.c
-1
arch/alpha/kernel/sys_titan.c
-1
arch/alpha/kernel/sys_titan.c
-1
arch/alpha/kernel/sys_wildfire.c
-1
arch/alpha/kernel/sys_wildfire.c
+1
arch/alpha/kernel/traps.c
+1
arch/alpha/kernel/traps.c
+2
arch/alpha/kernel/vmlinux.lds.S
+2
arch/alpha/kernel/vmlinux.lds.S
···
2
2
#include <asm/thread_info.h>
3
3
#include <asm/cache.h>
4
4
#include <asm/page.h>
5
+
#include <asm/setup.h>
5
6
6
7
OUTPUT_FORMAT("elf64-alpha")
7
8
OUTPUT_ARCH(alpha)
···
26
25
*(.fixup)
27
26
*(.gnu.warning)
28
27
} :kernel
28
+
swapper_pg_dir = SWAPPER_PGD;
29
29
_etext = .; /* End of text section */
30
30
31
31
NOTES :kernel :note
-1
arch/alpha/lib/stacktrace.c
-1
arch/alpha/lib/stacktrace.c
-1
arch/alpha/mm/fault.c
-1
arch/alpha/mm/fault.c
+1
-1
arch/alpha/mm/init.c
+1
-1
arch/alpha/mm/init.c
···
22
22
#include <linux/vmalloc.h>
23
23
#include <linux/gfp.h>
24
24
25
-
#include <asm/system.h>
26
25
#include <asm/uaccess.h>
27
26
#include <asm/pgtable.h>
28
27
#include <asm/pgalloc.h>
···
30
31
#include <asm/mmu_context.h>
31
32
#include <asm/console.h>
32
33
#include <asm/tlb.h>
34
+
#include <asm/setup.h>
33
35
34
36
extern void die_if_kernel(char *,struct pt_regs *,long);
35
37
-1
arch/alpha/oprofile/common.c
-1
arch/alpha/oprofile/common.c
-1
arch/alpha/oprofile/op_model_ev4.c
-1
arch/alpha/oprofile/op_model_ev4.c
-1
arch/alpha/oprofile/op_model_ev5.c
-1
arch/alpha/oprofile/op_model_ev5.c
-1
arch/alpha/oprofile/op_model_ev6.c
-1
arch/alpha/oprofile/op_model_ev6.c