Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

net: fec: don't dump RX FIFO register when not available

Commit db65f35f50e0 ("net: fec: add support of ethtool get_regs") introduce
ethool "--register-dump" interface to dump all FEC registers.

But not all silicon implementations of the Freescale FEC hardware module
have the FRBR (FIFO Receive Bound Register) and FRSR (FIFO Receive Start
Register) register, so we should not be trying to dump them on those that
don't.

To fix it we create a quirk flag, FEC_QUIRK_HAS_RFREG, and check it before
dump those RX FIFO registers.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

authored by

Fugang Duan and committed by
David S. Miller
ec20a63a fbe1222c

+16 -4
+4
drivers/net/ethernet/freescale/fec.h
··· 452 452 * initialisation. 453 453 */ 454 454 #define FEC_QUIRK_MIB_CLEAR (1 << 15) 455 + /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers, 456 + * those FIFO receive registers are resolved in other platforms. 457 + */ 458 + #define FEC_QUIRK_HAS_FRREG (1 << 16) 455 459 456 460 struct bufdesc_prop { 457 461 int qid;
+12 -4
drivers/net/ethernet/freescale/fec_main.c
··· 91 91 .driver_data = 0, 92 92 }, { 93 93 .name = "imx25-fec", 94 - .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR, 94 + .driver_data = FEC_QUIRK_USE_GASKET | FEC_QUIRK_MIB_CLEAR | 95 + FEC_QUIRK_HAS_FRREG, 95 96 }, { 96 97 .name = "imx27-fec", 97 - .driver_data = FEC_QUIRK_MIB_CLEAR, 98 + .driver_data = FEC_QUIRK_MIB_CLEAR | FEC_QUIRK_HAS_FRREG, 98 99 }, { 99 100 .name = "imx28-fec", 100 101 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_SWAP_FRAME | 101 - FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC, 102 + FEC_QUIRK_SINGLE_MDIO | FEC_QUIRK_HAS_RACC | 103 + FEC_QUIRK_HAS_FRREG, 102 104 }, { 103 105 .name = "imx6q-fec", 104 106 .driver_data = FEC_QUIRK_ENET_MAC | FEC_QUIRK_HAS_GBIT | ··· 2166 2164 memset(buf, 0, regs->len); 2167 2165 2168 2166 for (i = 0; i < ARRAY_SIZE(fec_enet_register_offset); i++) { 2169 - off = fec_enet_register_offset[i] / 4; 2167 + off = fec_enet_register_offset[i]; 2168 + 2169 + if ((off == FEC_R_BOUND || off == FEC_R_FSTART) && 2170 + !(fep->quirks & FEC_QUIRK_HAS_FRREG)) 2171 + continue; 2172 + 2173 + off >>= 2; 2170 2174 buf[off] = readl(&theregs[off]); 2171 2175 } 2172 2176 }