tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/vmwgfx: Update device headers
Historically our device headers have been forked versions of the
internal device headers, this has made maintaining them a bit
of a burden. To fix the situation, going forward, the device headers
will be verbatim copies of the internal headers.
To do that the driver code has to be adapted to use pristine
device headers. This will make future update to the device
headers trivial and automatic.
Signed-off-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Martin Krastev <krastevm@vmware.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210615182336.995192-2-zackr@vmware.com
+7066
-10005
-3
drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
-3
drivers/gpu/drm/vmwgfx/device_include/includeCheck.h
-111
drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
-111
drivers/gpu/drm/vmwgfx/device_include/svga3d_caps.h
···
1
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
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/**********************************************************
3
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* Copyright 2007-2015 VMware, Inc.
4
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*
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* Permission is hereby granted, free of charge, to any person
6
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* obtaining a copy of this software and associated documentation
7
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* files (the "Software"), to deal in the Software without
8
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* restriction, including without limitation the rights to use, copy,
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* modify, merge, publish, distribute, sublicense, and/or sell copies
10
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* of the Software, and to permit persons to whom the Software is
11
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* furnished to do so, subject to the following conditions:
12
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
21
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23
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* SOFTWARE.
24
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*
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**********************************************************/
26
-
27
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/*
28
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* svga3d_caps.h --
29
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*
30
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* Definitions for SVGA3D hardware capabilities. Capabilities
31
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* are used to query for optional rendering features during
32
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* driver initialization. The capability data is stored as very
33
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* basic key/value dictionary within the "FIFO register" memory
34
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* area at the beginning of BAR2.
35
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*
36
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* Note that these definitions are only for 3D capabilities.
37
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* The SVGA device also has "device capabilities" and "FIFO
38
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* capabilities", which are non-3D-specific and are stored as
39
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* bitfields rather than key/value pairs.
40
-
*/
41
-
42
-
#ifndef _SVGA3D_CAPS_H_
43
-
#define _SVGA3D_CAPS_H_
44
-
45
-
#define INCLUDE_ALLOW_MODULE
46
-
#define INCLUDE_ALLOW_USERLEVEL
47
-
48
-
#include "includeCheck.h"
49
-
50
-
#include "svga_reg.h"
51
-
52
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#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - \
53
-
SVGA_FIFO_3D_CAPS + 1)
54
-
55
-
56
-
/*
57
-
* SVGA3dCapsRecordType
58
-
*
59
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* Record types that can be found in the caps block.
60
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* Related record types are grouped together numerically so that
61
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* SVGA3dCaps_FindRecord() can be applied on a range of record
62
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* types.
63
-
*/
64
-
65
-
typedef enum {
66
-
SVGA3DCAPS_RECORD_UNKNOWN = 0,
67
-
SVGA3DCAPS_RECORD_DEVCAPS_MIN = 0x100,
68
-
SVGA3DCAPS_RECORD_DEVCAPS = 0x100,
69
-
SVGA3DCAPS_RECORD_DEVCAPS_MAX = 0x1ff,
70
-
} SVGA3dCapsRecordType;
71
-
72
-
73
-
/*
74
-
* SVGA3dCapsRecordHeader
75
-
*
76
-
* Header field leading each caps block record. Contains the offset (in
77
-
* register words, NOT bytes) to the next caps block record (or the end
78
-
* of caps block records which will be a zero word) and the record type
79
-
* as defined above.
80
-
*/
81
-
82
-
typedef
83
-
#include "vmware_pack_begin.h"
84
-
struct SVGA3dCapsRecordHeader {
85
-
uint32 length;
86
-
SVGA3dCapsRecordType type;
87
-
}
88
-
#include "vmware_pack_end.h"
89
-
SVGA3dCapsRecordHeader;
90
-
91
-
92
-
/*
93
-
* SVGA3dCapsRecord
94
-
*
95
-
* Caps block record; "data" is a placeholder for the actual data structure
96
-
* contained within the record;
97
-
*/
98
-
99
-
typedef
100
-
#include "vmware_pack_begin.h"
101
-
struct SVGA3dCapsRecord {
102
-
SVGA3dCapsRecordHeader header;
103
-
uint32 data[1];
104
-
}
105
-
#include "vmware_pack_end.h"
106
-
SVGA3dCapsRecord;
107
-
108
-
109
-
typedef uint32 SVGA3dCapPair[2];
110
-
111
-
#endif
+1255
-2017
drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
+1255
-2017
drivers/gpu/drm/vmwgfx/device_include/svga3d_cmd.h
···
1
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 1998-2020 VMware, Inc.
2
+
* Copyright 2012-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_cmd.h --
29
29
*
30
-
* SVGA 3d hardware cmd definitions
30
+
* SVGA 3d hardware cmd definitions
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_CMD_H_
34
36
#define _SVGA3D_CMD_H_
35
37
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
39
-
40
-
#include "includeCheck.h"
41
38
#include "svga3d_types.h"
39
+
#include "svga3d_limits.h"
40
+
#include "svga_reg.h"
42
41
43
-
/*
44
-
* Identifiers for commands in the command FIFO.
45
-
*
46
-
* IDs between 1000 and 1039 (inclusive) were used by obsolete versions of
47
-
* the SVGA3D protocol and remain reserved; they should not be used in the
48
-
* future.
49
-
*
50
-
* IDs between 1040 and 2999 (inclusive) are available for use by the
51
-
* current SVGA3D protocol.
52
-
*
53
-
* FIFO clients other than SVGA3D should stay below 1000, or at 3000
54
-
* and up.
55
-
*/
42
+
typedef enum SVGAFifo3dCmdId {
43
+
SVGA_3D_CMD_LEGACY_BASE = 1000,
44
+
SVGA_3D_CMD_BASE = 1040,
56
45
57
-
typedef enum {
58
-
SVGA_3D_CMD_LEGACY_BASE = 1000,
59
-
SVGA_3D_CMD_BASE = 1040,
46
+
SVGA_3D_CMD_SURFACE_DEFINE = 1040,
47
+
SVGA_3D_CMD_SURFACE_DESTROY = 1041,
48
+
SVGA_3D_CMD_SURFACE_COPY = 1042,
49
+
SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
50
+
SVGA_3D_CMD_SURFACE_DMA = 1044,
51
+
SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
52
+
SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
53
+
SVGA_3D_CMD_SETTRANSFORM = 1047,
54
+
SVGA_3D_CMD_SETZRANGE = 1048,
55
+
SVGA_3D_CMD_SETRENDERSTATE = 1049,
56
+
SVGA_3D_CMD_SETRENDERTARGET = 1050,
57
+
SVGA_3D_CMD_SETTEXTURESTATE = 1051,
58
+
SVGA_3D_CMD_SETMATERIAL = 1052,
59
+
SVGA_3D_CMD_SETLIGHTDATA = 1053,
60
+
SVGA_3D_CMD_SETLIGHTENABLED = 1054,
61
+
SVGA_3D_CMD_SETVIEWPORT = 1055,
62
+
SVGA_3D_CMD_SETCLIPPLANE = 1056,
63
+
SVGA_3D_CMD_CLEAR = 1057,
64
+
SVGA_3D_CMD_PRESENT = 1058,
65
+
SVGA_3D_CMD_SHADER_DEFINE = 1059,
66
+
SVGA_3D_CMD_SHADER_DESTROY = 1060,
67
+
SVGA_3D_CMD_SET_SHADER = 1061,
68
+
SVGA_3D_CMD_SET_SHADER_CONST = 1062,
69
+
SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
70
+
SVGA_3D_CMD_SETSCISSORRECT = 1064,
71
+
SVGA_3D_CMD_BEGIN_QUERY = 1065,
72
+
SVGA_3D_CMD_END_QUERY = 1066,
73
+
SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
74
+
SVGA_3D_CMD_PRESENT_READBACK = 1068,
75
+
SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
76
+
SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
77
+
SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
78
+
SVGA_3D_CMD_DEAD4 = 1072,
79
+
SVGA_3D_CMD_DEAD5 = 1073,
80
+
SVGA_3D_CMD_DEAD6 = 1074,
81
+
SVGA_3D_CMD_DEAD7 = 1075,
82
+
SVGA_3D_CMD_DEAD8 = 1076,
83
+
SVGA_3D_CMD_DEAD9 = 1077,
84
+
SVGA_3D_CMD_DEAD10 = 1078,
85
+
SVGA_3D_CMD_DEAD11 = 1079,
86
+
SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
87
+
SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
88
+
SVGA_3D_CMD_SCREEN_DMA = 1082,
89
+
SVGA_3D_CMD_DEAD1 = 1083,
90
+
SVGA_3D_CMD_DEAD2 = 1084,
60
91
61
-
SVGA_3D_CMD_SURFACE_DEFINE = 1040,
62
-
SVGA_3D_CMD_SURFACE_DESTROY = 1041,
63
-
SVGA_3D_CMD_SURFACE_COPY = 1042,
64
-
SVGA_3D_CMD_SURFACE_STRETCHBLT = 1043,
65
-
SVGA_3D_CMD_SURFACE_DMA = 1044,
66
-
SVGA_3D_CMD_CONTEXT_DEFINE = 1045,
67
-
SVGA_3D_CMD_CONTEXT_DESTROY = 1046,
68
-
SVGA_3D_CMD_SETTRANSFORM = 1047,
69
-
SVGA_3D_CMD_SETZRANGE = 1048,
70
-
SVGA_3D_CMD_SETRENDERSTATE = 1049,
71
-
SVGA_3D_CMD_SETRENDERTARGET = 1050,
72
-
SVGA_3D_CMD_SETTEXTURESTATE = 1051,
73
-
SVGA_3D_CMD_SETMATERIAL = 1052,
74
-
SVGA_3D_CMD_SETLIGHTDATA = 1053,
75
-
SVGA_3D_CMD_SETLIGHTENABLED = 1054,
76
-
SVGA_3D_CMD_SETVIEWPORT = 1055,
77
-
SVGA_3D_CMD_SETCLIPPLANE = 1056,
78
-
SVGA_3D_CMD_CLEAR = 1057,
79
-
SVGA_3D_CMD_PRESENT = 1058,
80
-
SVGA_3D_CMD_SHADER_DEFINE = 1059,
81
-
SVGA_3D_CMD_SHADER_DESTROY = 1060,
82
-
SVGA_3D_CMD_SET_SHADER = 1061,
83
-
SVGA_3D_CMD_SET_SHADER_CONST = 1062,
84
-
SVGA_3D_CMD_DRAW_PRIMITIVES = 1063,
85
-
SVGA_3D_CMD_SETSCISSORRECT = 1064,
86
-
SVGA_3D_CMD_BEGIN_QUERY = 1065,
87
-
SVGA_3D_CMD_END_QUERY = 1066,
88
-
SVGA_3D_CMD_WAIT_FOR_QUERY = 1067,
89
-
SVGA_3D_CMD_PRESENT_READBACK = 1068,
90
-
SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN = 1069,
91
-
SVGA_3D_CMD_SURFACE_DEFINE_V2 = 1070,
92
-
SVGA_3D_CMD_GENERATE_MIPMAPS = 1071,
93
-
SVGA_3D_CMD_DEAD4 = 1072,
94
-
SVGA_3D_CMD_DEAD5 = 1073,
95
-
SVGA_3D_CMD_DEAD6 = 1074,
96
-
SVGA_3D_CMD_DEAD7 = 1075,
97
-
SVGA_3D_CMD_DEAD8 = 1076,
98
-
SVGA_3D_CMD_DEAD9 = 1077,
99
-
SVGA_3D_CMD_DEAD10 = 1078,
100
-
SVGA_3D_CMD_DEAD11 = 1079,
101
-
SVGA_3D_CMD_ACTIVATE_SURFACE = 1080,
102
-
SVGA_3D_CMD_DEACTIVATE_SURFACE = 1081,
103
-
SVGA_3D_CMD_SCREEN_DMA = 1082,
104
-
SVGA_3D_CMD_DEAD1 = 1083,
105
-
SVGA_3D_CMD_DEAD2 = 1084,
92
+
SVGA_3D_CMD_DEAD12 = 1085,
93
+
SVGA_3D_CMD_DEAD13 = 1086,
94
+
SVGA_3D_CMD_DEAD14 = 1087,
95
+
SVGA_3D_CMD_DEAD15 = 1088,
96
+
SVGA_3D_CMD_DEAD16 = 1089,
97
+
SVGA_3D_CMD_DEAD17 = 1090,
106
98
107
-
SVGA_3D_CMD_DEAD12 = 1085,
108
-
SVGA_3D_CMD_DEAD13 = 1086,
109
-
SVGA_3D_CMD_DEAD14 = 1087,
110
-
SVGA_3D_CMD_DEAD15 = 1088,
111
-
SVGA_3D_CMD_DEAD16 = 1089,
112
-
SVGA_3D_CMD_DEAD17 = 1090,
99
+
SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
100
+
SVGA_3D_CMD_READBACK_OTABLE = 1092,
113
101
114
-
SVGA_3D_CMD_SET_OTABLE_BASE = 1091,
115
-
SVGA_3D_CMD_READBACK_OTABLE = 1092,
102
+
SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
103
+
SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
104
+
SVGA_3D_CMD_DEAD3 = 1095,
105
+
SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
116
106
117
-
SVGA_3D_CMD_DEFINE_GB_MOB = 1093,
118
-
SVGA_3D_CMD_DESTROY_GB_MOB = 1094,
119
-
SVGA_3D_CMD_DEAD3 = 1095,
120
-
SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING = 1096,
107
+
SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
108
+
SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
109
+
SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
110
+
SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
111
+
SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
112
+
SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
113
+
SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
114
+
SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
115
+
SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
116
+
SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
121
117
122
-
SVGA_3D_CMD_DEFINE_GB_SURFACE = 1097,
123
-
SVGA_3D_CMD_DESTROY_GB_SURFACE = 1098,
124
-
SVGA_3D_CMD_BIND_GB_SURFACE = 1099,
125
-
SVGA_3D_CMD_COND_BIND_GB_SURFACE = 1100,
126
-
SVGA_3D_CMD_UPDATE_GB_IMAGE = 1101,
127
-
SVGA_3D_CMD_UPDATE_GB_SURFACE = 1102,
128
-
SVGA_3D_CMD_READBACK_GB_IMAGE = 1103,
129
-
SVGA_3D_CMD_READBACK_GB_SURFACE = 1104,
130
-
SVGA_3D_CMD_INVALIDATE_GB_IMAGE = 1105,
131
-
SVGA_3D_CMD_INVALIDATE_GB_SURFACE = 1106,
118
+
SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
119
+
SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
120
+
SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
121
+
SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
122
+
SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
132
123
133
-
SVGA_3D_CMD_DEFINE_GB_CONTEXT = 1107,
134
-
SVGA_3D_CMD_DESTROY_GB_CONTEXT = 1108,
135
-
SVGA_3D_CMD_BIND_GB_CONTEXT = 1109,
136
-
SVGA_3D_CMD_READBACK_GB_CONTEXT = 1110,
137
-
SVGA_3D_CMD_INVALIDATE_GB_CONTEXT = 1111,
124
+
SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
125
+
SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
126
+
SVGA_3D_CMD_BIND_GB_SHADER = 1114,
138
127
139
-
SVGA_3D_CMD_DEFINE_GB_SHADER = 1112,
140
-
SVGA_3D_CMD_DESTROY_GB_SHADER = 1113,
141
-
SVGA_3D_CMD_BIND_GB_SHADER = 1114,
128
+
SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
142
129
143
-
SVGA_3D_CMD_SET_OTABLE_BASE64 = 1115,
130
+
SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
131
+
SVGA_3D_CMD_END_GB_QUERY = 1117,
132
+
SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
144
133
145
-
SVGA_3D_CMD_BEGIN_GB_QUERY = 1116,
146
-
SVGA_3D_CMD_END_GB_QUERY = 1117,
147
-
SVGA_3D_CMD_WAIT_FOR_GB_QUERY = 1118,
134
+
SVGA_3D_CMD_NOP = 1119,
148
135
149
-
SVGA_3D_CMD_NOP = 1119,
136
+
SVGA_3D_CMD_ENABLE_GART = 1120,
137
+
SVGA_3D_CMD_DISABLE_GART = 1121,
138
+
SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
139
+
SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
150
140
151
-
SVGA_3D_CMD_ENABLE_GART = 1120,
152
-
SVGA_3D_CMD_DISABLE_GART = 1121,
153
-
SVGA_3D_CMD_MAP_MOB_INTO_GART = 1122,
154
-
SVGA_3D_CMD_UNMAP_GART_RANGE = 1123,
141
+
SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
142
+
SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
143
+
SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
144
+
SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
155
145
156
-
SVGA_3D_CMD_DEFINE_GB_SCREENTARGET = 1124,
157
-
SVGA_3D_CMD_DESTROY_GB_SCREENTARGET = 1125,
158
-
SVGA_3D_CMD_BIND_GB_SCREENTARGET = 1126,
159
-
SVGA_3D_CMD_UPDATE_GB_SCREENTARGET = 1127,
146
+
SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
147
+
SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
160
148
161
-
SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL = 1128,
162
-
SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL = 1129,
149
+
SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
163
150
164
-
SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE = 1130,
151
+
SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
152
+
SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
153
+
SVGA_3D_CMD_GB_MOB_FENCE = 1133,
154
+
SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
155
+
SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
156
+
SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
157
+
SVGA_3D_CMD_NOP_ERROR = 1137,
165
158
166
-
SVGA_3D_CMD_GB_SCREEN_DMA = 1131,
167
-
SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH = 1132,
168
-
SVGA_3D_CMD_GB_MOB_FENCE = 1133,
169
-
SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 = 1134,
170
-
SVGA_3D_CMD_DEFINE_GB_MOB64 = 1135,
171
-
SVGA_3D_CMD_REDEFINE_GB_MOB64 = 1136,
172
-
SVGA_3D_CMD_NOP_ERROR = 1137,
159
+
SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
160
+
SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
161
+
SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
162
+
SVGA_3D_CMD_DRAW = 1141,
163
+
SVGA_3D_CMD_DRAW_INDEXED = 1142,
173
164
174
-
SVGA_3D_CMD_SET_VERTEX_STREAMS = 1138,
175
-
SVGA_3D_CMD_SET_VERTEX_DECLS = 1139,
176
-
SVGA_3D_CMD_SET_VERTEX_DIVISORS = 1140,
177
-
SVGA_3D_CMD_DRAW = 1141,
178
-
SVGA_3D_CMD_DRAW_INDEXED = 1142,
165
+
SVGA_3D_CMD_DX_MIN = 1143,
166
+
SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
167
+
SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
168
+
SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
169
+
SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
170
+
SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
171
+
SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
172
+
SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
173
+
SVGA_3D_CMD_DX_SET_SHADER = 1150,
174
+
SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
175
+
SVGA_3D_CMD_DX_DRAW = 1152,
176
+
SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
177
+
SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
178
+
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
179
+
SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
180
+
SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
181
+
SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
182
+
SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
183
+
SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
184
+
SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
185
+
SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
186
+
SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
187
+
SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
188
+
SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
189
+
SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
190
+
SVGA_3D_CMD_DX_BIND_QUERY = 1167,
191
+
SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
192
+
SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
193
+
SVGA_3D_CMD_DX_END_QUERY = 1170,
194
+
SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
195
+
SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
196
+
SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
197
+
SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
198
+
SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
199
+
SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
200
+
SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
201
+
SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
202
+
SVGA_3D_CMD_DX_PRED_COPY = 1179,
203
+
SVGA_3D_CMD_DX_PRESENTBLT = 1180,
204
+
SVGA_3D_CMD_DX_GENMIPS = 1181,
205
+
SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
206
+
SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
207
+
SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
208
+
SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
209
+
SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
210
+
SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
211
+
SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
212
+
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
213
+
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
214
+
SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
215
+
SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
216
+
SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
217
+
SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
218
+
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
219
+
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
220
+
SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
221
+
SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
222
+
SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
223
+
SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
224
+
SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
225
+
SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
226
+
SVGA_3D_CMD_DX_BIND_SHADER = 1203,
227
+
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
228
+
SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
229
+
SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
230
+
SVGA_3D_CMD_DX_SET_COTABLE = 1207,
231
+
SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
232
+
SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
233
+
SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
234
+
SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
235
+
SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
236
+
SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
237
+
SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
238
+
SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
239
+
SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
240
+
SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
241
+
SVGA_3D_CMD_DX_HINT = 1218,
242
+
SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
243
+
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
244
+
SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
245
+
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
246
+
SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
247
+
SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
248
+
SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,
179
249
180
-
/*
181
-
* DX10 Commands
182
-
*/
183
-
SVGA_3D_CMD_DX_MIN = 1143,
184
-
SVGA_3D_CMD_DX_DEFINE_CONTEXT = 1143,
185
-
SVGA_3D_CMD_DX_DESTROY_CONTEXT = 1144,
186
-
SVGA_3D_CMD_DX_BIND_CONTEXT = 1145,
187
-
SVGA_3D_CMD_DX_READBACK_CONTEXT = 1146,
188
-
SVGA_3D_CMD_DX_INVALIDATE_CONTEXT = 1147,
189
-
SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER = 1148,
190
-
SVGA_3D_CMD_DX_SET_SHADER_RESOURCES = 1149,
191
-
SVGA_3D_CMD_DX_SET_SHADER = 1150,
192
-
SVGA_3D_CMD_DX_SET_SAMPLERS = 1151,
193
-
SVGA_3D_CMD_DX_DRAW = 1152,
194
-
SVGA_3D_CMD_DX_DRAW_INDEXED = 1153,
195
-
SVGA_3D_CMD_DX_DRAW_INSTANCED = 1154,
196
-
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED = 1155,
197
-
SVGA_3D_CMD_DX_DRAW_AUTO = 1156,
198
-
SVGA_3D_CMD_DX_SET_INPUT_LAYOUT = 1157,
199
-
SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS = 1158,
200
-
SVGA_3D_CMD_DX_SET_INDEX_BUFFER = 1159,
201
-
SVGA_3D_CMD_DX_SET_TOPOLOGY = 1160,
202
-
SVGA_3D_CMD_DX_SET_RENDERTARGETS = 1161,
203
-
SVGA_3D_CMD_DX_SET_BLEND_STATE = 1162,
204
-
SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE = 1163,
205
-
SVGA_3D_CMD_DX_SET_RASTERIZER_STATE = 1164,
206
-
SVGA_3D_CMD_DX_DEFINE_QUERY = 1165,
207
-
SVGA_3D_CMD_DX_DESTROY_QUERY = 1166,
208
-
SVGA_3D_CMD_DX_BIND_QUERY = 1167,
209
-
SVGA_3D_CMD_DX_SET_QUERY_OFFSET = 1168,
210
-
SVGA_3D_CMD_DX_BEGIN_QUERY = 1169,
211
-
SVGA_3D_CMD_DX_END_QUERY = 1170,
212
-
SVGA_3D_CMD_DX_READBACK_QUERY = 1171,
213
-
SVGA_3D_CMD_DX_SET_PREDICATION = 1172,
214
-
SVGA_3D_CMD_DX_SET_SOTARGETS = 1173,
215
-
SVGA_3D_CMD_DX_SET_VIEWPORTS = 1174,
216
-
SVGA_3D_CMD_DX_SET_SCISSORRECTS = 1175,
217
-
SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW = 1176,
218
-
SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW = 1177,
219
-
SVGA_3D_CMD_DX_PRED_COPY_REGION = 1178,
220
-
SVGA_3D_CMD_DX_PRED_COPY = 1179,
221
-
SVGA_3D_CMD_DX_PRESENTBLT = 1180,
222
-
SVGA_3D_CMD_DX_GENMIPS = 1181,
223
-
SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE = 1182,
224
-
SVGA_3D_CMD_DX_READBACK_SUBRESOURCE = 1183,
225
-
SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE = 1184,
226
-
SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW = 1185,
227
-
SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW = 1186,
228
-
SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW = 1187,
229
-
SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW = 1188,
230
-
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW = 1189,
231
-
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW = 1190,
232
-
SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT = 1191,
233
-
SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT = 1192,
234
-
SVGA_3D_CMD_DX_DEFINE_BLEND_STATE = 1193,
235
-
SVGA_3D_CMD_DX_DESTROY_BLEND_STATE = 1194,
236
-
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE = 1195,
237
-
SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE = 1196,
238
-
SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE = 1197,
239
-
SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE = 1198,
240
-
SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE = 1199,
241
-
SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE = 1200,
242
-
SVGA_3D_CMD_DX_DEFINE_SHADER = 1201,
243
-
SVGA_3D_CMD_DX_DESTROY_SHADER = 1202,
244
-
SVGA_3D_CMD_DX_BIND_SHADER = 1203,
245
-
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT = 1204,
246
-
SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT = 1205,
247
-
SVGA_3D_CMD_DX_SET_STREAMOUTPUT = 1206,
248
-
SVGA_3D_CMD_DX_SET_COTABLE = 1207,
249
-
SVGA_3D_CMD_DX_READBACK_COTABLE = 1208,
250
-
SVGA_3D_CMD_DX_BUFFER_COPY = 1209,
251
-
SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER = 1210,
252
-
SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK = 1211,
253
-
SVGA_3D_CMD_DX_MOVE_QUERY = 1212,
254
-
SVGA_3D_CMD_DX_BIND_ALL_QUERY = 1213,
255
-
SVGA_3D_CMD_DX_READBACK_ALL_QUERY = 1214,
256
-
SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER = 1215,
257
-
SVGA_3D_CMD_DX_MOB_FENCE_64 = 1216,
258
-
SVGA_3D_CMD_DX_BIND_ALL_SHADER = 1217,
259
-
SVGA_3D_CMD_DX_HINT = 1218,
260
-
SVGA_3D_CMD_DX_BUFFER_UPDATE = 1219,
261
-
SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET = 1220,
262
-
SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET = 1221,
263
-
SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET = 1222,
264
-
SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET = 1223,
265
-
SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET = 1224,
266
-
SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET = 1225,
250
+
SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
251
+
SVGA_3D_CMD_DX_MAX = 1227,
267
252
268
-
SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER = 1226,
269
-
SVGA_3D_CMD_DX_MAX = 1227,
253
+
SVGA_3D_CMD_SCREEN_COPY = 1227,
270
254
271
-
SVGA_3D_CMD_SCREEN_COPY = 1227,
255
+
SVGA_3D_CMD_RESERVED1 = 1228,
256
+
SVGA_3D_CMD_RESERVED2 = 1229,
257
+
SVGA_3D_CMD_RESERVED3 = 1230,
258
+
SVGA_3D_CMD_RESERVED4 = 1231,
259
+
SVGA_3D_CMD_RESERVED5 = 1232,
260
+
SVGA_3D_CMD_RESERVED6 = 1233,
261
+
SVGA_3D_CMD_RESERVED7 = 1234,
262
+
SVGA_3D_CMD_RESERVED8 = 1235,
272
263
273
-
SVGA_3D_CMD_RESERVED1 = 1228,
274
-
SVGA_3D_CMD_RESERVED2 = 1229,
275
-
SVGA_3D_CMD_RESERVED3 = 1230,
276
-
SVGA_3D_CMD_RESERVED4 = 1231,
277
-
SVGA_3D_CMD_RESERVED5 = 1232,
278
-
SVGA_3D_CMD_RESERVED6 = 1233,
279
-
SVGA_3D_CMD_RESERVED7 = 1234,
280
-
SVGA_3D_CMD_RESERVED8 = 1235,
264
+
SVGA_3D_CMD_GROW_OTABLE = 1236,
265
+
SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
266
+
SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
281
267
282
-
SVGA_3D_CMD_GROW_OTABLE = 1236,
283
-
SVGA_3D_CMD_DX_GROW_COTABLE = 1237,
284
-
SVGA_3D_CMD_INTRA_SURFACE_COPY = 1238,
268
+
SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
285
269
286
-
SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 = 1239,
270
+
SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
271
+
SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
272
+
SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
273
+
SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
274
+
SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
287
275
288
-
SVGA_3D_CMD_DX_RESOLVE_COPY = 1240,
289
-
SVGA_3D_CMD_DX_PRED_RESOLVE_COPY = 1241,
290
-
SVGA_3D_CMD_DX_PRED_CONVERT_REGION = 1242,
291
-
SVGA_3D_CMD_DX_PRED_CONVERT = 1243,
292
-
SVGA_3D_CMD_WHOLE_SURFACE_COPY = 1244,
276
+
SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
277
+
SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
278
+
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
279
+
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
280
+
SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
281
+
SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,
293
282
294
-
SVGA_3D_CMD_DX_DEFINE_UA_VIEW = 1245,
295
-
SVGA_3D_CMD_DX_DESTROY_UA_VIEW = 1246,
296
-
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT = 1247,
297
-
SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT = 1248,
298
-
SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT = 1249,
299
-
SVGA_3D_CMD_DX_SET_UA_VIEWS = 1250,
283
+
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
284
+
SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
285
+
SVGA_3D_CMD_DX_DISPATCH = 1253,
286
+
SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,
300
287
301
-
SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT = 1251,
302
-
SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT = 1252,
303
-
SVGA_3D_CMD_DX_DISPATCH = 1253,
304
-
SVGA_3D_CMD_DX_DISPATCH_INDIRECT = 1254,
288
+
SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
289
+
SVGA_3D_CMD_UPDATE_ZERO_SURFACE = 1256,
290
+
SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
291
+
SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,
305
292
306
-
SVGA_3D_CMD_WRITE_ZERO_SURFACE = 1255,
307
-
SVGA_3D_CMD_HINT_ZERO_SURFACE = 1256,
308
-
SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER = 1257,
309
-
SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT = 1258,
293
+
SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
294
+
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
295
+
SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
296
+
SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
297
+
SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
298
+
SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,
310
299
311
-
SVGA_3D_CMD_LOGICOPS_BITBLT = 1259,
312
-
SVGA_3D_CMD_LOGICOPS_TRANSBLT = 1260,
313
-
SVGA_3D_CMD_LOGICOPS_STRETCHBLT = 1261,
314
-
SVGA_3D_CMD_LOGICOPS_COLORFILL = 1262,
315
-
SVGA_3D_CMD_LOGICOPS_ALPHABLEND = 1263,
316
-
SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND = 1264,
300
+
SVGA_3D_CMD_DX_COPY_COTABLE_INTO_MOB = 1265,
317
301
318
-
SVGA_3D_CMD_RESERVED2_1 = 1265,
302
+
SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_V2 = 1266,
319
303
320
-
SVGA_3D_CMD_RESERVED2_2 = 1266,
321
-
SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
322
-
SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
323
-
SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
324
-
SVGA_3D_CMD_RESERVED2_3 = 1270,
325
-
SVGA_3D_CMD_RESERVED2_4 = 1271,
326
-
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
327
-
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
328
-
SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
329
-
SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
330
-
SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
331
-
SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,
304
+
SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 = 1267,
305
+
SVGA_3D_CMD_DX_SET_CS_UA_VIEWS = 1268,
306
+
SVGA_3D_CMD_DX_SET_MIN_LOD = 1269,
332
307
333
-
SVGA_3D_CMD_MAX = 1278,
334
-
SVGA_3D_CMD_FUTURE_MAX = 3000
308
+
SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 = 1272,
309
+
SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB = 1273,
310
+
SVGA_3D_CMD_DX_SET_SHADER_IFACE = 1274,
311
+
SVGA_3D_CMD_DX_BIND_STREAMOUTPUT = 1275,
312
+
SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS = 1276,
313
+
SVGA_3D_CMD_DX_BIND_SHADER_IFACE = 1277,
314
+
315
+
SVGA_3D_CMD_UPDATE_GB_SCREENTARGET_MOVE = 1278,
316
+
317
+
SVGA_3D_CMD_DX_PRED_STAGING_COPY = 1281,
318
+
SVGA_3D_CMD_DX_STAGING_COPY = 1282,
319
+
SVGA_3D_CMD_DX_PRED_STAGING_COPY_REGION = 1283,
320
+
SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_V2 = 1284,
321
+
SVGA_3D_CMD_DX_SET_INDEX_BUFFER_V2 = 1285,
322
+
SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS_OFFSET_AND_SIZE = 1286,
323
+
SVGA_3D_CMD_DX_SET_INDEX_BUFFER_OFFSET_AND_SIZE = 1287,
324
+
SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE_V2 = 1288,
325
+
SVGA_3D_CMD_DX_PRED_STAGING_CONVERT_REGION = 1289,
326
+
SVGA_3D_CMD_DX_PRED_STAGING_CONVERT = 1290,
327
+
SVGA_3D_CMD_DX_STAGING_BUFFER_COPY = 1291,
328
+
329
+
SVGA_3D_CMD_MAX = 1303,
330
+
SVGA_3D_CMD_FUTURE_MAX = 3000
335
331
} SVGAFifo3dCmdId;
336
332
337
333
#define SVGA_NUM_3D_CMD (SVGA_3D_CMD_MAX - SVGA_3D_CMD_BASE)
338
334
339
-
/*
340
-
* FIFO command format definitions:
341
-
*/
335
+
#pragma pack(push, 1)
336
+
typedef struct {
337
+
uint32 id;
338
+
uint32 size;
339
+
} SVGA3dCmdHeader;
340
+
#pragma pack(pop)
342
341
343
-
/*
344
-
* The data size header following cmdNum for every 3d command
345
-
*/
346
-
typedef
347
-
#include "vmware_pack_begin.h"
348
-
struct {
349
-
uint32 id;
350
-
uint32 size;
351
-
}
352
-
#include "vmware_pack_end.h"
353
-
SVGA3dCmdHeader;
342
+
#pragma pack(push, 1)
343
+
typedef struct {
344
+
uint32 numMipLevels;
345
+
} SVGA3dSurfaceFace;
346
+
#pragma pack(pop)
354
347
355
-
typedef
356
-
#include "vmware_pack_begin.h"
357
-
struct {
358
-
uint32 numMipLevels;
359
-
}
360
-
#include "vmware_pack_end.h"
361
-
SVGA3dSurfaceFace;
348
+
#pragma pack(push, 1)
349
+
typedef struct {
350
+
uint32 sid;
351
+
SVGA3dSurface1Flags surfaceFlags;
352
+
SVGA3dSurfaceFormat format;
362
353
363
-
typedef
364
-
#include "vmware_pack_begin.h"
365
-
struct {
366
-
uint32 sid;
367
-
SVGA3dSurface1Flags surfaceFlags;
368
-
SVGA3dSurfaceFormat format;
354
+
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
369
355
370
-
/*
371
-
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
372
-
* structures must have the same value of numMipLevels field.
373
-
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
374
-
* numMipLevels set to 0.
375
-
*/
376
-
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
356
+
} SVGA3dCmdDefineSurface;
357
+
#pragma pack(pop)
377
358
378
-
/*
379
-
* Followed by an SVGA3dSize structure for each mip level in each face.
380
-
*
381
-
* A note on surface sizes: Sizes are always specified in pixels,
382
-
* even if the true surface size is not a multiple of the minimum
383
-
* block size of the surface's format. For example, a 3x3x1 DXT1
384
-
* compressed texture would actually be stored as a 4x4x1 image in
385
-
* memory.
386
-
*/
387
-
}
388
-
#include "vmware_pack_end.h"
389
-
SVGA3dCmdDefineSurface; /* SVGA_3D_CMD_SURFACE_DEFINE */
359
+
#pragma pack(push, 1)
360
+
typedef struct {
361
+
uint32 sid;
362
+
SVGA3dSurface1Flags surfaceFlags;
363
+
SVGA3dSurfaceFormat format;
390
364
391
-
typedef
392
-
#include "vmware_pack_begin.h"
393
-
struct {
394
-
uint32 sid;
395
-
SVGA3dSurface1Flags surfaceFlags;
396
-
SVGA3dSurfaceFormat format;
365
+
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
366
+
uint32 multisampleCount;
367
+
SVGA3dTextureFilter autogenFilter;
397
368
398
-
/*
399
-
* If surfaceFlags has SVGA3D_SURFACE_CUBEMAP bit set, all SVGA3dSurfaceFace
400
-
* structures must have the same value of numMipLevels field.
401
-
* Otherwise, all but the first SVGA3dSurfaceFace structures must have the
402
-
* numMipLevels set to 0.
403
-
*/
404
-
SVGA3dSurfaceFace face[SVGA3D_MAX_SURFACE_FACES];
405
-
uint32 multisampleCount;
406
-
SVGA3dTextureFilter autogenFilter;
369
+
} SVGA3dCmdDefineSurface_v2;
370
+
#pragma pack(pop)
407
371
408
-
/*
409
-
* Followed by an SVGA3dSize structure for each mip level in each face.
410
-
*
411
-
* A note on surface sizes: Sizes are always specified in pixels,
412
-
* even if the true surface size is not a multiple of the minimum
413
-
* block size of the surface's format. For example, a 3x3x1 DXT1
414
-
* compressed texture would actually be stored as a 4x4x1 image in
415
-
* memory.
416
-
*/
417
-
}
418
-
#include "vmware_pack_end.h"
419
-
SVGA3dCmdDefineSurface_v2; /* SVGA_3D_CMD_SURFACE_DEFINE_V2 */
372
+
#pragma pack(push, 1)
373
+
typedef struct {
374
+
uint32 sid;
375
+
} SVGA3dCmdDestroySurface;
376
+
#pragma pack(pop)
420
377
421
-
typedef
422
-
#include "vmware_pack_begin.h"
423
-
struct {
424
-
uint32 sid;
425
-
}
426
-
#include "vmware_pack_end.h"
427
-
SVGA3dCmdDestroySurface; /* SVGA_3D_CMD_SURFACE_DESTROY */
378
+
#pragma pack(push, 1)
379
+
typedef struct {
380
+
uint32 cid;
381
+
} SVGA3dCmdDefineContext;
382
+
#pragma pack(pop)
428
383
429
-
typedef
430
-
#include "vmware_pack_begin.h"
431
-
struct {
432
-
uint32 cid;
433
-
}
434
-
#include "vmware_pack_end.h"
435
-
SVGA3dCmdDefineContext; /* SVGA_3D_CMD_CONTEXT_DEFINE */
384
+
#pragma pack(push, 1)
385
+
typedef struct {
386
+
uint32 cid;
387
+
} SVGA3dCmdDestroyContext;
388
+
#pragma pack(pop)
436
389
437
-
typedef
438
-
#include "vmware_pack_begin.h"
439
-
struct {
440
-
uint32 cid;
441
-
}
442
-
#include "vmware_pack_end.h"
443
-
SVGA3dCmdDestroyContext; /* SVGA_3D_CMD_CONTEXT_DESTROY */
390
+
#pragma pack(push, 1)
391
+
typedef struct {
392
+
uint32 cid;
393
+
SVGA3dClearFlag clearFlag;
394
+
uint32 color;
395
+
float depth;
396
+
uint32 stencil;
444
397
445
-
typedef
446
-
#include "vmware_pack_begin.h"
447
-
struct {
448
-
uint32 cid;
449
-
SVGA3dClearFlag clearFlag;
450
-
uint32 color;
451
-
float depth;
452
-
uint32 stencil;
453
-
/* Followed by variable number of SVGA3dRect structures */
454
-
}
455
-
#include "vmware_pack_end.h"
456
-
SVGA3dCmdClear; /* SVGA_3D_CMD_CLEAR */
398
+
} SVGA3dCmdClear;
399
+
#pragma pack(pop)
457
400
458
-
typedef
459
-
#include "vmware_pack_begin.h"
460
-
struct {
461
-
SVGA3dLightType type;
462
-
SVGA3dBool inWorldSpace;
463
-
float diffuse[4];
464
-
float specular[4];
465
-
float ambient[4];
466
-
float position[4];
467
-
float direction[4];
468
-
float range;
469
-
float falloff;
470
-
float attenuation0;
471
-
float attenuation1;
472
-
float attenuation2;
473
-
float theta;
474
-
float phi;
475
-
}
476
-
#include "vmware_pack_end.h"
477
-
SVGA3dLightData;
401
+
#pragma pack(push, 1)
402
+
typedef struct {
403
+
SVGA3dLightType type;
404
+
SVGA3dBool inWorldSpace;
405
+
float diffuse[4];
406
+
float specular[4];
407
+
float ambient[4];
408
+
float position[4];
409
+
float direction[4];
410
+
float range;
411
+
float falloff;
412
+
float attenuation0;
413
+
float attenuation1;
414
+
float attenuation2;
415
+
float theta;
416
+
float phi;
417
+
} SVGA3dLightData;
418
+
#pragma pack(pop)
478
419
479
-
typedef
480
-
#include "vmware_pack_begin.h"
481
-
struct {
482
-
uint32 sid;
483
-
/* Followed by variable number of SVGA3dCopyRect structures */
484
-
}
485
-
#include "vmware_pack_end.h"
486
-
SVGA3dCmdPresent; /* SVGA_3D_CMD_PRESENT */
420
+
#pragma pack(push, 1)
421
+
typedef struct {
422
+
uint32 sid;
487
423
488
-
typedef
489
-
#include "vmware_pack_begin.h"
490
-
struct {
491
-
SVGA3dRenderStateName state;
492
-
union {
493
-
uint32 uintValue;
494
-
float floatValue;
495
-
};
496
-
}
497
-
#include "vmware_pack_end.h"
498
-
SVGA3dRenderState;
424
+
} SVGA3dCmdPresent;
425
+
#pragma pack(pop)
499
426
500
-
typedef
501
-
#include "vmware_pack_begin.h"
502
-
struct {
503
-
uint32 cid;
504
-
/* Followed by variable number of SVGA3dRenderState structures */
505
-
}
506
-
#include "vmware_pack_end.h"
507
-
SVGA3dCmdSetRenderState; /* SVGA_3D_CMD_SETRENDERSTATE */
427
+
#pragma pack(push, 1)
428
+
typedef struct {
429
+
SVGA3dRenderStateName state;
430
+
union {
431
+
uint32 uintValue;
432
+
float floatValue;
433
+
};
434
+
} SVGA3dRenderState;
435
+
#pragma pack(pop)
508
436
509
-
typedef
510
-
#include "vmware_pack_begin.h"
511
-
struct {
512
-
uint32 cid;
513
-
SVGA3dRenderTargetType type;
514
-
SVGA3dSurfaceImageId target;
515
-
}
516
-
#include "vmware_pack_end.h"
517
-
SVGA3dCmdSetRenderTarget; /* SVGA_3D_CMD_SETRENDERTARGET */
437
+
#pragma pack(push, 1)
438
+
typedef struct {
439
+
uint32 cid;
518
440
519
-
typedef
520
-
#include "vmware_pack_begin.h"
521
-
struct {
522
-
SVGA3dSurfaceImageId src;
523
-
SVGA3dSurfaceImageId dest;
524
-
/* Followed by variable number of SVGA3dCopyBox structures */
525
-
}
526
-
#include "vmware_pack_end.h"
527
-
SVGA3dCmdSurfaceCopy; /* SVGA_3D_CMD_SURFACE_COPY */
441
+
} SVGA3dCmdSetRenderState;
442
+
#pragma pack(pop)
528
443
529
-
/*
530
-
* Perform a surface copy within the same image.
531
-
* The src/dest boxes are allowed to overlap.
532
-
*/
533
-
typedef
534
-
#include "vmware_pack_begin.h"
535
-
struct {
536
-
SVGA3dSurfaceImageId surface;
537
-
SVGA3dCopyBox box;
538
-
}
539
-
#include "vmware_pack_end.h"
540
-
SVGA3dCmdIntraSurfaceCopy; /* SVGA_3D_CMD_INTRA_SURFACE_COPY */
444
+
#pragma pack(push, 1)
445
+
typedef struct {
446
+
uint32 cid;
447
+
SVGA3dRenderTargetType type;
448
+
SVGA3dSurfaceImageId target;
449
+
} SVGA3dCmdSetRenderTarget;
450
+
#pragma pack(pop)
541
451
542
-
typedef
543
-
#include "vmware_pack_begin.h"
544
-
struct {
545
-
uint32 srcSid;
546
-
uint32 destSid;
547
-
}
548
-
#include "vmware_pack_end.h"
549
-
SVGA3dCmdWholeSurfaceCopy; /* SVGA_3D_CMD_WHOLE_SURFACE_COPY */
452
+
#pragma pack(push, 1)
453
+
typedef struct {
454
+
SVGA3dSurfaceImageId src;
455
+
SVGA3dSurfaceImageId dest;
550
456
551
-
typedef
552
-
#include "vmware_pack_begin.h"
553
-
struct {
554
-
SVGA3dSurfaceImageId src;
555
-
SVGA3dSurfaceImageId dest;
556
-
SVGA3dBox boxSrc;
557
-
SVGA3dBox boxDest;
558
-
}
559
-
#include "vmware_pack_end.h"
560
-
SVGA3dCmdSurfaceStretchBltNonMSToMS;
561
-
/* SVGA_3D_CMD_SURFACE_STRETCHBLT_NON_MS_TO_MS */
457
+
} SVGA3dCmdSurfaceCopy;
458
+
#pragma pack(pop)
562
459
563
-
typedef
564
-
#include "vmware_pack_begin.h"
565
-
struct {
566
-
SVGA3dSurfaceImageId src;
567
-
SVGA3dSurfaceImageId dest;
568
-
SVGA3dBox boxSrc;
569
-
SVGA3dBox boxDest;
570
-
SVGA3dStretchBltMode mode;
571
-
}
572
-
#include "vmware_pack_end.h"
573
-
SVGA3dCmdSurfaceStretchBlt; /* SVGA_3D_CMD_SURFACE_STRETCHBLT */
460
+
#pragma pack(push, 1)
461
+
typedef struct {
462
+
SVGA3dSurfaceImageId surface;
463
+
SVGA3dCopyBox box;
464
+
} SVGA3dCmdIntraSurfaceCopy;
465
+
#pragma pack(pop)
574
466
575
-
typedef
576
-
#include "vmware_pack_begin.h"
577
-
struct {
578
-
/*
579
-
* If the discard flag is present in a surface DMA operation, the host may
580
-
* discard the contents of the current mipmap level and face of the target
581
-
* surface before applying the surface DMA contents.
582
-
*/
583
-
uint32 discard : 1;
467
+
#pragma pack(push, 1)
468
+
typedef struct {
469
+
uint32 srcSid;
470
+
uint32 destSid;
471
+
} SVGA3dCmdWholeSurfaceCopy;
472
+
#pragma pack(pop)
584
473
585
-
/*
586
-
* If the unsynchronized flag is present, the host may perform this upload
587
-
* without syncing to pending reads on this surface.
588
-
*/
589
-
uint32 unsynchronized : 1;
474
+
#pragma pack(push, 1)
475
+
typedef struct {
476
+
SVGA3dSurfaceImageId src;
477
+
SVGA3dSurfaceImageId dest;
478
+
SVGA3dBox boxSrc;
479
+
SVGA3dBox boxDest;
480
+
} SVGA3dCmdSurfaceStretchBltNonMSToMS;
481
+
#pragma pack(pop)
590
482
591
-
/*
592
-
* Guests *MUST* set the reserved bits to 0 before submitting the command
593
-
* suffix as future flags may occupy these bits.
594
-
*/
595
-
uint32 reserved : 30;
596
-
}
597
-
#include "vmware_pack_end.h"
598
-
SVGA3dSurfaceDMAFlags;
483
+
#pragma pack(push, 1)
484
+
typedef struct {
485
+
SVGA3dSurfaceImageId src;
486
+
SVGA3dSurfaceImageId dest;
487
+
SVGA3dBox boxSrc;
488
+
SVGA3dBox boxDest;
489
+
SVGA3dStretchBltMode mode;
490
+
} SVGA3dCmdSurfaceStretchBlt;
491
+
#pragma pack(pop)
599
492
600
-
typedef
601
-
#include "vmware_pack_begin.h"
602
-
struct {
603
-
SVGAGuestImage guest;
604
-
SVGA3dSurfaceImageId host;
605
-
SVGA3dTransferType transfer;
493
+
#pragma pack(push, 1)
494
+
typedef struct {
495
+
uint32 discard : 1;
606
496
607
-
/*
608
-
* Followed by variable number of SVGA3dCopyBox structures. For consistency
609
-
* in all clipping logic and coordinate translation, we define the
610
-
* "source" in each copyBox as the guest image and the
611
-
* "destination" as the host image, regardless of transfer
612
-
* direction.
613
-
*
614
-
* For efficiency, the SVGA3D device is free to copy more data than
615
-
* specified. For example, it may round copy boxes outwards such
616
-
* that they lie on particular alignment boundaries.
617
-
*/
618
-
}
619
-
#include "vmware_pack_end.h"
620
-
SVGA3dCmdSurfaceDMA; /* SVGA_3D_CMD_SURFACE_DMA */
497
+
uint32 unsynchronized : 1;
621
498
622
-
/*
623
-
* SVGA3dCmdSurfaceDMASuffix --
624
-
*
625
-
* This is a command suffix that will appear after a SurfaceDMA command in
626
-
* the FIFO. It contains some extra information that hosts may use to
627
-
* optimize performance or protect the guest. This suffix exists to preserve
628
-
* backwards compatibility while also allowing for new functionality to be
629
-
* implemented.
630
-
*/
499
+
uint32 reserved : 30;
500
+
} SVGA3dSurfaceDMAFlags;
501
+
#pragma pack(pop)
631
502
632
-
typedef
633
-
#include "vmware_pack_begin.h"
634
-
struct {
635
-
uint32 suffixSize;
503
+
#pragma pack(push, 1)
504
+
typedef struct {
505
+
SVGAGuestImage guest;
506
+
SVGA3dSurfaceImageId host;
507
+
SVGA3dTransferType transfer;
636
508
637
-
/*
638
-
* The maximum offset is used to determine the maximum offset from the
639
-
* guestPtr base address that will be accessed or written to during this
640
-
* surfaceDMA. If the suffix is supported, the host will respect this
641
-
* boundary while performing surface DMAs.
642
-
*
643
-
* Defaults to MAX_UINT32
644
-
*/
645
-
uint32 maximumOffset;
509
+
} SVGA3dCmdSurfaceDMA;
510
+
#pragma pack(pop)
646
511
647
-
/*
648
-
* A set of flags that describes optimizations that the host may perform
649
-
* while performing this surface DMA operation. The guest should never rely
650
-
* on behaviour that is different when these flags are set for correctness.
651
-
*
652
-
* Defaults to 0
653
-
*/
654
-
SVGA3dSurfaceDMAFlags flags;
655
-
}
656
-
#include "vmware_pack_end.h"
657
-
SVGA3dCmdSurfaceDMASuffix;
512
+
#pragma pack(push, 1)
513
+
typedef struct {
514
+
uint32 suffixSize;
658
515
659
-
/*
660
-
* SVGA_3D_CMD_DRAW_PRIMITIVES --
661
-
*
662
-
* This command is the SVGA3D device's generic drawing entry point.
663
-
* It can draw multiple ranges of primitives, optionally using an
664
-
* index buffer, using an arbitrary collection of vertex buffers.
665
-
*
666
-
* Each SVGA3dVertexDecl defines a distinct vertex array to bind
667
-
* during this draw call. The declarations specify which surface
668
-
* the vertex data lives in, what that vertex data is used for,
669
-
* and how to interpret it.
670
-
*
671
-
* Each SVGA3dPrimitiveRange defines a collection of primitives
672
-
* to render using the same vertex arrays. An index buffer is
673
-
* optional.
674
-
*/
516
+
uint32 maximumOffset;
675
517
676
-
typedef
677
-
#include "vmware_pack_begin.h"
678
-
struct {
679
-
/*
680
-
* A range hint is an optional specification for the range of indices
681
-
* in an SVGA3dArray that will be used. If 'last' is zero, it is assumed
682
-
* that the entire array will be used.
683
-
*
684
-
* These are only hints. The SVGA3D device may use them for
685
-
* performance optimization if possible, but it's also allowed to
686
-
* ignore these values.
687
-
*/
688
-
uint32 first;
689
-
uint32 last;
690
-
}
691
-
#include "vmware_pack_end.h"
692
-
SVGA3dArrayRangeHint;
518
+
SVGA3dSurfaceDMAFlags flags;
519
+
} SVGA3dCmdSurfaceDMASuffix;
520
+
#pragma pack(pop)
693
521
694
-
typedef
695
-
#include "vmware_pack_begin.h"
696
-
struct {
697
-
/*
698
-
* Define the origin and shape of a vertex or index array. Both
699
-
* 'offset' and 'stride' are in bytes. The provided surface will be
700
-
* reinterpreted as a flat array of bytes in the same format used
701
-
* by surface DMA operations. To avoid unnecessary conversions, the
702
-
* surface should be created with the SVGA3D_BUFFER format.
703
-
*
704
-
* Index 0 in the array starts 'offset' bytes into the surface.
705
-
* Index 1 begins at byte 'offset + stride', etc. Array indices may
706
-
* not be negative.
707
-
*/
708
-
uint32 surfaceId;
709
-
uint32 offset;
710
-
uint32 stride;
711
-
}
712
-
#include "vmware_pack_end.h"
713
-
SVGA3dArray;
522
+
#pragma pack(push, 1)
523
+
typedef struct {
524
+
uint32 first;
525
+
uint32 last;
526
+
} SVGA3dArrayRangeHint;
527
+
#pragma pack(pop)
714
528
715
-
typedef
716
-
#include "vmware_pack_begin.h"
717
-
struct {
718
-
/*
719
-
* Describe a vertex array's data type, and define how it is to be
720
-
* used by the fixed function pipeline or the vertex shader. It
721
-
* isn't useful to have two VertexDecls with the same
722
-
* VertexArrayIdentity in one draw call.
723
-
*/
724
-
SVGA3dDeclType type;
725
-
SVGA3dDeclMethod method;
726
-
SVGA3dDeclUsage usage;
727
-
uint32 usageIndex;
728
-
}
729
-
#include "vmware_pack_end.h"
730
-
SVGA3dVertexArrayIdentity;
529
+
#pragma pack(push, 1)
530
+
typedef struct {
531
+
uint32 surfaceId;
532
+
uint32 offset;
533
+
uint32 stride;
534
+
} SVGA3dArray;
535
+
#pragma pack(pop)
731
536
732
-
typedef
733
-
#include "vmware_pack_begin.h"
734
-
struct SVGA3dVertexDecl {
735
-
SVGA3dVertexArrayIdentity identity;
736
-
SVGA3dArray array;
737
-
SVGA3dArrayRangeHint rangeHint;
738
-
}
739
-
#include "vmware_pack_end.h"
740
-
SVGA3dVertexDecl;
537
+
#pragma pack(push, 1)
538
+
typedef struct {
539
+
SVGA3dDeclType type;
540
+
SVGA3dDeclMethod method;
541
+
SVGA3dDeclUsage usage;
542
+
uint32 usageIndex;
543
+
} SVGA3dVertexArrayIdentity;
544
+
#pragma pack(pop)
741
545
742
-
typedef
743
-
#include "vmware_pack_begin.h"
744
-
struct SVGA3dPrimitiveRange {
745
-
/*
746
-
* Define a group of primitives to render, from sequential indices.
747
-
*
748
-
* The value of 'primitiveType' and 'primitiveCount' imply the
749
-
* total number of vertices that will be rendered.
750
-
*/
751
-
SVGA3dPrimitiveType primType;
752
-
uint32 primitiveCount;
546
+
#pragma pack(push, 1)
547
+
typedef struct SVGA3dVertexDecl {
548
+
SVGA3dVertexArrayIdentity identity;
549
+
SVGA3dArray array;
550
+
SVGA3dArrayRangeHint rangeHint;
551
+
} SVGA3dVertexDecl;
552
+
#pragma pack(pop)
753
553
754
-
/*
755
-
* Optional index buffer. If indexArray.surfaceId is
756
-
* SVGA3D_INVALID_ID, we render without an index buffer. Rendering
757
-
* without an index buffer is identical to rendering with an index
758
-
* buffer containing the sequence [0, 1, 2, 3, ...].
759
-
*
760
-
* If an index buffer is in use, indexWidth specifies the width in
761
-
* bytes of each index value. It must be less than or equal to
762
-
* indexArray.stride.
763
-
*
764
-
* (Currently, the SVGA3D device requires index buffers to be tightly
765
-
* packed. In other words, indexWidth == indexArray.stride)
766
-
*/
767
-
SVGA3dArray indexArray;
768
-
uint32 indexWidth;
554
+
#pragma pack(push, 1)
555
+
typedef struct SVGA3dPrimitiveRange {
556
+
SVGA3dPrimitiveType primType;
557
+
uint32 primitiveCount;
769
558
770
-
/*
771
-
* Optional index bias. This number is added to all indices from
772
-
* indexArray before they are used as vertex array indices. This
773
-
* can be used in multiple ways:
774
-
*
775
-
* - When not using an indexArray, this bias can be used to
776
-
* specify where in the vertex arrays to begin rendering.
777
-
*
778
-
* - A positive number here is equivalent to increasing the
779
-
* offset in each vertex array.
780
-
*
781
-
* - A negative number can be used to render using a small
782
-
* vertex array and an index buffer that contains large
783
-
* values. This may be used by some applications that
784
-
* crop a vertex buffer without modifying their index
785
-
* buffer.
786
-
*
787
-
* Note that rendering with a negative bias value may be slower and
788
-
* use more memory than rendering with a positive or zero bias.
789
-
*/
790
-
int32 indexBias;
791
-
}
792
-
#include "vmware_pack_end.h"
793
-
SVGA3dPrimitiveRange;
559
+
SVGA3dArray indexArray;
560
+
uint32 indexWidth;
794
561
795
-
typedef
796
-
#include "vmware_pack_begin.h"
797
-
struct {
798
-
uint32 cid;
799
-
uint32 numVertexDecls;
800
-
uint32 numRanges;
562
+
int32 indexBias;
563
+
} SVGA3dPrimitiveRange;
564
+
#pragma pack(pop)
801
565
802
-
/*
803
-
* There are two variable size arrays after the
804
-
* SVGA3dCmdDrawPrimitives structure. In order,
805
-
* they are:
806
-
*
807
-
* 1. SVGA3dVertexDecl, quantity 'numVertexDecls', but no more than
808
-
* SVGA3D_MAX_VERTEX_ARRAYS;
809
-
* 2. SVGA3dPrimitiveRange, quantity 'numRanges', but no more than
810
-
* SVGA3D_MAX_DRAW_PRIMITIVE_RANGES;
811
-
* 3. Optionally, SVGA3dVertexDivisor, quantity 'numVertexDecls' (contains
812
-
* the frequency divisor for the corresponding vertex decl).
813
-
*/
814
-
}
815
-
#include "vmware_pack_end.h"
816
-
SVGA3dCmdDrawPrimitives; /* SVGA_3D_CMD_DRAWPRIMITIVES */
566
+
#pragma pack(push, 1)
567
+
typedef struct {
568
+
uint32 cid;
569
+
uint32 numVertexDecls;
570
+
uint32 numRanges;
817
571
818
-
typedef
819
-
#include "vmware_pack_begin.h"
820
-
struct {
821
-
uint32 cid;
572
+
} SVGA3dCmdDrawPrimitives;
573
+
#pragma pack(pop)
822
574
823
-
uint32 primitiveCount; /* How many primitives to render */
824
-
uint32 startVertexLocation; /* Which vertex do we start rendering at. */
575
+
#pragma pack(push, 1)
576
+
typedef struct {
577
+
uint32 cid;
825
578
826
-
uint8 primitiveType; /* SVGA3dPrimitiveType */
827
-
uint8 padding[3];
828
-
}
829
-
#include "vmware_pack_end.h"
830
-
SVGA3dCmdDraw;
579
+
uint32 primitiveCount;
580
+
uint32 startVertexLocation;
831
581
832
-
typedef
833
-
#include "vmware_pack_begin.h"
834
-
struct {
835
-
uint32 cid;
582
+
uint8 primitiveType;
583
+
uint8 padding[3];
584
+
} SVGA3dCmdDraw;
585
+
#pragma pack(pop)
836
586
837
-
uint8 primitiveType; /* SVGA3dPrimitiveType */
587
+
#pragma pack(push, 1)
588
+
typedef struct {
589
+
uint32 cid;
838
590
839
-
uint32 indexBufferSid; /* Valid index buffer sid. */
840
-
uint32 indexBufferOffset; /* Byte offset into the vertex buffer, almost */
841
-
/* always 0 for pre SM guests, non-zero for OpenGL */
842
-
/* guests. We can't represent non-multiple of */
843
-
/* stride offsets in D3D9Renderer... */
844
-
uint8 indexBufferStride; /* Allowable values = 1, 2, or 4 */
591
+
uint8 primitiveType;
845
592
846
-
int32 baseVertexLocation; /* Bias applied to the index when selecting a */
847
-
/* vertex from the streams, may be negative */
593
+
uint32 indexBufferSid;
594
+
uint32 indexBufferOffset;
848
595
849
-
uint32 primitiveCount; /* How many primitives to render */
850
-
uint32 pad0;
851
-
uint16 pad1;
852
-
}
853
-
#include "vmware_pack_end.h"
854
-
SVGA3dCmdDrawIndexed;
596
+
uint8 indexBufferStride;
855
597
856
-
typedef
857
-
#include "vmware_pack_begin.h"
858
-
struct {
859
-
/*
860
-
* Describe a vertex array's data type, and define how it is to be
861
-
* used by the fixed function pipeline or the vertex shader. It
862
-
* isn't useful to have two VertexDecls with the same
863
-
* VertexArrayIdentity in one draw call.
864
-
*/
865
-
uint16 streamOffset;
866
-
uint8 stream;
867
-
uint8 type; /* SVGA3dDeclType */
868
-
uint8 method; /* SVGA3dDeclMethod */
869
-
uint8 usage; /* SVGA3dDeclUsage */
870
-
uint8 usageIndex;
871
-
uint8 padding;
598
+
int32 baseVertexLocation;
872
599
873
-
}
874
-
#include "vmware_pack_end.h"
875
-
SVGA3dVertexElement;
600
+
uint32 primitiveCount;
601
+
uint32 pad0;
602
+
uint16 pad1;
603
+
} SVGA3dCmdDrawIndexed;
604
+
#pragma pack(pop)
876
605
877
-
/*
878
-
* Should the vertex element respect the stream value? The high bit of the
879
-
* stream should be set to indicate that the stream should be respected. If
880
-
* the high bit is not set, the stream will be ignored and replaced by the index
881
-
* of the position of the currently considered vertex element.
882
-
*
883
-
* All guests should set this bit and correctly specify the stream going
884
-
* forward.
885
-
*/
606
+
#pragma pack(push, 1)
607
+
typedef struct {
608
+
uint16 streamOffset;
609
+
uint8 stream;
610
+
uint8 type;
611
+
uint8 method;
612
+
uint8 usage;
613
+
uint8 usageIndex;
614
+
uint8 padding;
615
+
616
+
} SVGA3dVertexElement;
617
+
#pragma pack(pop)
618
+
886
619
#define SVGA3D_VERTEX_ELEMENT_RESPECT_STREAM (1 << 7)
887
620
888
-
typedef
889
-
#include "vmware_pack_begin.h"
890
-
struct {
891
-
uint32 cid;
621
+
#pragma pack(push, 1)
622
+
typedef struct {
623
+
uint32 cid;
892
624
893
-
uint32 numElements;
625
+
uint32 numElements;
894
626
895
-
/*
896
-
* Followed by numElements SVGA3dVertexElement structures.
897
-
*
898
-
* If numElements < SVGA3D_MAX_VERTEX_ARRAYS, the remaining elements
899
-
* are cleared and will not be used by following draws.
900
-
*/
901
-
}
902
-
#include "vmware_pack_end.h"
903
-
SVGA3dCmdSetVertexDecls;
627
+
} SVGA3dCmdSetVertexDecls;
628
+
#pragma pack(pop)
904
629
905
-
typedef
906
-
#include "vmware_pack_begin.h"
907
-
struct {
908
-
uint32 sid;
909
-
uint32 stride;
910
-
uint32 offset;
911
-
}
912
-
#include "vmware_pack_end.h"
913
-
SVGA3dVertexStream;
630
+
#pragma pack(push, 1)
631
+
typedef struct {
632
+
uint32 sid;
633
+
uint32 stride;
634
+
uint32 offset;
635
+
} SVGA3dVertexStream;
636
+
#pragma pack(pop)
914
637
915
-
typedef
916
-
#include "vmware_pack_begin.h"
917
-
struct {
918
-
uint32 cid;
638
+
#pragma pack(push, 1)
639
+
typedef struct {
640
+
uint32 cid;
919
641
920
-
uint32 numStreams;
921
-
/*
922
-
* Followed by numStream SVGA3dVertexStream structures.
923
-
*
924
-
* If numStreams < SVGA3D_MAX_VERTEX_ARRAYS, the remaining streams
925
-
* are cleared and will not be used by following draws.
926
-
*/
927
-
}
928
-
#include "vmware_pack_end.h"
929
-
SVGA3dCmdSetVertexStreams;
642
+
uint32 numStreams;
930
643
931
-
typedef
932
-
#include "vmware_pack_begin.h"
933
-
struct {
934
-
uint32 cid;
935
-
uint32 numDivisors;
936
-
}
937
-
#include "vmware_pack_end.h"
938
-
SVGA3dCmdSetVertexDivisors;
644
+
} SVGA3dCmdSetVertexStreams;
645
+
#pragma pack(pop)
939
646
940
-
typedef
941
-
#include "vmware_pack_begin.h"
942
-
struct {
943
-
uint32 stage;
944
-
SVGA3dTextureStateName name;
945
-
union {
946
-
uint32 value;
947
-
float floatValue;
948
-
};
949
-
}
950
-
#include "vmware_pack_end.h"
951
-
SVGA3dTextureState;
647
+
#pragma pack(push, 1)
648
+
typedef struct {
649
+
uint32 cid;
650
+
uint32 numDivisors;
651
+
} SVGA3dCmdSetVertexDivisors;
652
+
#pragma pack(pop)
952
653
953
-
typedef
954
-
#include "vmware_pack_begin.h"
955
-
struct {
956
-
uint32 cid;
957
-
/* Followed by variable number of SVGA3dTextureState structures */
958
-
}
959
-
#include "vmware_pack_end.h"
960
-
SVGA3dCmdSetTextureState; /* SVGA_3D_CMD_SETTEXTURESTATE */
654
+
#pragma pack(push, 1)
655
+
typedef struct {
656
+
uint32 stage;
657
+
SVGA3dTextureStateName name;
658
+
union {
659
+
uint32 value;
660
+
float floatValue;
661
+
};
662
+
} SVGA3dTextureState;
663
+
#pragma pack(pop)
961
664
962
-
typedef
963
-
#include "vmware_pack_begin.h"
964
-
struct {
965
-
uint32 cid;
966
-
SVGA3dTransformType type;
967
-
float matrix[16];
968
-
}
969
-
#include "vmware_pack_end.h"
970
-
SVGA3dCmdSetTransform; /* SVGA_3D_CMD_SETTRANSFORM */
665
+
#pragma pack(push, 1)
666
+
typedef struct {
667
+
uint32 cid;
971
668
972
-
typedef
973
-
#include "vmware_pack_begin.h"
974
-
struct {
975
-
float min;
976
-
float max;
977
-
}
978
-
#include "vmware_pack_end.h"
979
-
SVGA3dZRange;
669
+
} SVGA3dCmdSetTextureState;
670
+
#pragma pack(pop)
980
671
981
-
typedef
982
-
#include "vmware_pack_begin.h"
983
-
struct {
984
-
uint32 cid;
985
-
SVGA3dZRange zRange;
986
-
}
987
-
#include "vmware_pack_end.h"
988
-
SVGA3dCmdSetZRange; /* SVGA_3D_CMD_SETZRANGE */
672
+
#pragma pack(push, 1)
673
+
typedef struct {
674
+
uint32 cid;
675
+
SVGA3dTransformType type;
676
+
float matrix[16];
677
+
} SVGA3dCmdSetTransform;
678
+
#pragma pack(pop)
989
679
990
-
typedef
991
-
#include "vmware_pack_begin.h"
992
-
struct {
993
-
float diffuse[4];
994
-
float ambient[4];
995
-
float specular[4];
996
-
float emissive[4];
997
-
float shininess;
998
-
}
999
-
#include "vmware_pack_end.h"
1000
-
SVGA3dMaterial;
680
+
#pragma pack(push, 1)
681
+
typedef struct {
682
+
float min;
683
+
float max;
684
+
} SVGA3dZRange;
685
+
#pragma pack(pop)
1001
686
1002
-
typedef
1003
-
#include "vmware_pack_begin.h"
1004
-
struct {
1005
-
uint32 cid;
1006
-
SVGA3dFace face;
1007
-
SVGA3dMaterial material;
1008
-
}
1009
-
#include "vmware_pack_end.h"
1010
-
SVGA3dCmdSetMaterial; /* SVGA_3D_CMD_SETMATERIAL */
687
+
#pragma pack(push, 1)
688
+
typedef struct {
689
+
uint32 cid;
690
+
SVGA3dZRange zRange;
691
+
} SVGA3dCmdSetZRange;
692
+
#pragma pack(pop)
1011
693
1012
-
typedef
1013
-
#include "vmware_pack_begin.h"
1014
-
struct {
1015
-
uint32 cid;
1016
-
uint32 index;
1017
-
SVGA3dLightData data;
1018
-
}
1019
-
#include "vmware_pack_end.h"
1020
-
SVGA3dCmdSetLightData; /* SVGA_3D_CMD_SETLIGHTDATA */
694
+
#pragma pack(push, 1)
695
+
typedef struct {
696
+
float diffuse[4];
697
+
float ambient[4];
698
+
float specular[4];
699
+
float emissive[4];
700
+
float shininess;
701
+
} SVGA3dMaterial;
702
+
#pragma pack(pop)
1021
703
1022
-
typedef
1023
-
#include "vmware_pack_begin.h"
1024
-
struct {
1025
-
uint32 cid;
1026
-
uint32 index;
1027
-
uint32 enabled;
1028
-
}
1029
-
#include "vmware_pack_end.h"
1030
-
SVGA3dCmdSetLightEnabled; /* SVGA_3D_CMD_SETLIGHTENABLED */
704
+
#pragma pack(push, 1)
705
+
typedef struct {
706
+
uint32 cid;
707
+
SVGA3dFace face;
708
+
SVGA3dMaterial material;
709
+
} SVGA3dCmdSetMaterial;
710
+
#pragma pack(pop)
1031
711
1032
-
typedef
1033
-
#include "vmware_pack_begin.h"
1034
-
struct {
1035
-
uint32 cid;
1036
-
SVGA3dRect rect;
1037
-
}
1038
-
#include "vmware_pack_end.h"
1039
-
SVGA3dCmdSetViewport; /* SVGA_3D_CMD_SETVIEWPORT */
712
+
#pragma pack(push, 1)
713
+
typedef struct {
714
+
uint32 cid;
715
+
uint32 index;
716
+
SVGA3dLightData data;
717
+
} SVGA3dCmdSetLightData;
718
+
#pragma pack(pop)
1040
719
1041
-
typedef
1042
-
#include "vmware_pack_begin.h"
1043
-
struct {
1044
-
uint32 cid;
1045
-
SVGA3dRect rect;
1046
-
}
1047
-
#include "vmware_pack_end.h"
1048
-
SVGA3dCmdSetScissorRect; /* SVGA_3D_CMD_SETSCISSORRECT */
720
+
#pragma pack(push, 1)
721
+
typedef struct {
722
+
uint32 cid;
723
+
uint32 index;
724
+
uint32 enabled;
725
+
} SVGA3dCmdSetLightEnabled;
726
+
#pragma pack(pop)
1049
727
1050
-
typedef
1051
-
#include "vmware_pack_begin.h"
1052
-
struct {
1053
-
uint32 cid;
1054
-
uint32 index;
1055
-
float plane[4];
1056
-
}
1057
-
#include "vmware_pack_end.h"
1058
-
SVGA3dCmdSetClipPlane; /* SVGA_3D_CMD_SETCLIPPLANE */
728
+
#pragma pack(push, 1)
729
+
typedef struct {
730
+
uint32 cid;
731
+
SVGA3dRect rect;
732
+
} SVGA3dCmdSetViewport;
733
+
#pragma pack(pop)
1059
734
1060
-
typedef
1061
-
#include "vmware_pack_begin.h"
1062
-
struct {
1063
-
uint32 cid;
1064
-
uint32 shid;
1065
-
SVGA3dShaderType type;
1066
-
/* Followed by variable number of DWORDs for shader bycode */
1067
-
}
1068
-
#include "vmware_pack_end.h"
1069
-
SVGA3dCmdDefineShader; /* SVGA_3D_CMD_SHADER_DEFINE */
735
+
#pragma pack(push, 1)
736
+
typedef struct {
737
+
uint32 cid;
738
+
SVGA3dRect rect;
739
+
} SVGA3dCmdSetScissorRect;
740
+
#pragma pack(pop)
1070
741
1071
-
typedef
1072
-
#include "vmware_pack_begin.h"
1073
-
struct {
1074
-
uint32 cid;
1075
-
uint32 shid;
1076
-
SVGA3dShaderType type;
1077
-
}
1078
-
#include "vmware_pack_end.h"
1079
-
SVGA3dCmdDestroyShader; /* SVGA_3D_CMD_SHADER_DESTROY */
742
+
#pragma pack(push, 1)
743
+
typedef struct {
744
+
uint32 cid;
745
+
uint32 index;
746
+
float plane[4];
747
+
} SVGA3dCmdSetClipPlane;
748
+
#pragma pack(pop)
1080
749
1081
-
typedef
1082
-
#include "vmware_pack_begin.h"
1083
-
struct {
1084
-
uint32 cid;
1085
-
uint32 reg; /* register number */
1086
-
SVGA3dShaderType type;
1087
-
SVGA3dShaderConstType ctype;
1088
-
uint32 values[4];
750
+
#pragma pack(push, 1)
751
+
typedef struct {
752
+
uint32 cid;
753
+
uint32 shid;
754
+
SVGA3dShaderType type;
1089
755
1090
-
/*
1091
-
* Followed by a variable number of additional values.
1092
-
*/
1093
-
}
1094
-
#include "vmware_pack_end.h"
1095
-
SVGA3dCmdSetShaderConst; /* SVGA_3D_CMD_SET_SHADER_CONST */
756
+
} SVGA3dCmdDefineShader;
757
+
#pragma pack(pop)
1096
758
1097
-
typedef
1098
-
#include "vmware_pack_begin.h"
1099
-
struct {
1100
-
uint32 cid;
1101
-
SVGA3dShaderType type;
1102
-
uint32 shid;
1103
-
}
1104
-
#include "vmware_pack_end.h"
1105
-
SVGA3dCmdSetShader; /* SVGA_3D_CMD_SET_SHADER */
759
+
#pragma pack(push, 1)
760
+
typedef struct {
761
+
uint32 cid;
762
+
uint32 shid;
763
+
SVGA3dShaderType type;
764
+
} SVGA3dCmdDestroyShader;
765
+
#pragma pack(pop)
1106
766
1107
-
typedef
1108
-
#include "vmware_pack_begin.h"
1109
-
struct {
1110
-
uint32 cid;
1111
-
SVGA3dQueryType type;
1112
-
}
1113
-
#include "vmware_pack_end.h"
1114
-
SVGA3dCmdBeginQuery; /* SVGA_3D_CMD_BEGIN_QUERY */
767
+
#pragma pack(push, 1)
768
+
typedef struct {
769
+
uint32 cid;
770
+
uint32 reg;
771
+
SVGA3dShaderType type;
772
+
SVGA3dShaderConstType ctype;
773
+
uint32 values[4];
1115
774
1116
-
typedef
1117
-
#include "vmware_pack_begin.h"
1118
-
struct {
1119
-
uint32 cid;
1120
-
SVGA3dQueryType type;
1121
-
SVGAGuestPtr guestResult; /* Points to an SVGA3dQueryResult structure */
1122
-
}
1123
-
#include "vmware_pack_end.h"
1124
-
SVGA3dCmdEndQuery; /* SVGA_3D_CMD_END_QUERY */
775
+
} SVGA3dCmdSetShaderConst;
776
+
#pragma pack(pop)
1125
777
778
+
#pragma pack(push, 1)
779
+
typedef struct {
780
+
uint32 cid;
781
+
SVGA3dShaderType type;
782
+
uint32 shid;
783
+
} SVGA3dCmdSetShader;
784
+
#pragma pack(pop)
1126
785
1127
-
/*
1128
-
* SVGA3D_CMD_WAIT_FOR_QUERY --
1129
-
*
1130
-
* Will read the SVGA3dQueryResult structure pointed to by guestResult,
1131
-
* and if the state member is set to anything else than
1132
-
* SVGA3D_QUERYSTATE_PENDING, this command will always be a no-op.
1133
-
*
1134
-
* Otherwise, in addition to the query explicitly waited for,
1135
-
* All queries with the same type and issued with the same cid, for which
1136
-
* an SVGA_3D_CMD_END_QUERY command has previously been sent, will
1137
-
* be finished after execution of this command.
1138
-
*
1139
-
* A query will be identified by the gmrId and offset of the guestResult
1140
-
* member. If the device can't find an SVGA_3D_CMD_END_QUERY that has
1141
-
* been sent previously with an indentical gmrId and offset, it will
1142
-
* effectively end all queries with an identical type issued with the
1143
-
* same cid, and the SVGA3dQueryResult structure pointed to by
1144
-
* guestResult will not be written to. This property can be used to
1145
-
* implement a query barrier for a given cid and query type.
1146
-
*/
786
+
#pragma pack(push, 1)
787
+
typedef struct {
788
+
uint32 cid;
789
+
SVGA3dQueryType type;
790
+
} SVGA3dCmdBeginQuery;
791
+
#pragma pack(pop)
1147
792
1148
-
typedef
1149
-
#include "vmware_pack_begin.h"
1150
-
struct {
1151
-
uint32 cid; /* Same parameters passed to END_QUERY */
1152
-
SVGA3dQueryType type;
1153
-
SVGAGuestPtr guestResult;
1154
-
}
1155
-
#include "vmware_pack_end.h"
1156
-
SVGA3dCmdWaitForQuery; /* SVGA_3D_CMD_WAIT_FOR_QUERY */
793
+
#pragma pack(push, 1)
794
+
typedef struct {
795
+
uint32 cid;
796
+
SVGA3dQueryType type;
797
+
SVGAGuestPtr guestResult;
798
+
} SVGA3dCmdEndQuery;
799
+
#pragma pack(pop)
1157
800
1158
-
typedef
1159
-
#include "vmware_pack_begin.h"
1160
-
struct {
1161
-
uint32 totalSize; /* Set by guest before query is ended. */
1162
-
SVGA3dQueryState state; /* Set by host or guest. See SVGA3dQueryState. */
1163
-
union { /* Set by host on exit from PENDING state */
1164
-
uint32 result32;
1165
-
uint32 queryCookie; /* May be used to identify which QueryGetData this
1166
-
result corresponds to. */
1167
-
};
1168
-
}
1169
-
#include "vmware_pack_end.h"
1170
-
SVGA3dQueryResult;
801
+
#pragma pack(push, 1)
802
+
typedef struct {
803
+
uint32 cid;
804
+
SVGA3dQueryType type;
805
+
SVGAGuestPtr guestResult;
806
+
} SVGA3dCmdWaitForQuery;
807
+
#pragma pack(pop)
1171
808
809
+
#pragma pack(push, 1)
810
+
typedef struct {
811
+
uint32 totalSize;
812
+
SVGA3dQueryState state;
813
+
union {
814
+
uint32 result32;
815
+
uint32 queryCookie;
816
+
};
817
+
} SVGA3dQueryResult;
818
+
#pragma pack(pop)
1172
819
1173
-
/*
1174
-
* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN --
1175
-
*
1176
-
* This is a blit from an SVGA3D surface to a Screen Object.
1177
-
* This blit must be directed at a specific screen.
1178
-
*
1179
-
* The blit copies from a rectangular region of an SVGA3D surface
1180
-
* image to a rectangular region of a screen.
1181
-
*
1182
-
* This command takes an optional variable-length list of clipping
1183
-
* rectangles after the body of the command. If no rectangles are
1184
-
* specified, there is no clipping region. The entire destRect is
1185
-
* drawn to. If one or more rectangles are included, they describe
1186
-
* a clipping region. The clip rectangle coordinates are measured
1187
-
* relative to the top-left corner of destRect.
1188
-
*
1189
-
* The srcImage must be from mip=0 face=0.
1190
-
*
1191
-
* This supports scaling if the src and dest are of different sizes.
1192
-
*
1193
-
* Availability:
1194
-
* SVGA_FIFO_CAP_SCREEN_OBJECT
1195
-
*/
820
+
#pragma pack(push, 1)
821
+
typedef struct {
822
+
SVGA3dSurfaceImageId srcImage;
823
+
SVGASignedRect srcRect;
824
+
uint32 destScreenId;
825
+
SVGASignedRect destRect;
1196
826
1197
-
typedef
1198
-
#include "vmware_pack_begin.h"
1199
-
struct {
1200
-
SVGA3dSurfaceImageId srcImage;
1201
-
SVGASignedRect srcRect;
1202
-
uint32 destScreenId; /* Screen Object ID */
1203
-
SVGASignedRect destRect;
1204
-
/* Clipping: zero or more SVGASignedRects follow */
1205
-
}
1206
-
#include "vmware_pack_end.h"
1207
-
SVGA3dCmdBlitSurfaceToScreen; /* SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN */
827
+
} SVGA3dCmdBlitSurfaceToScreen;
828
+
#pragma pack(pop)
1208
829
1209
-
typedef
1210
-
#include "vmware_pack_begin.h"
1211
-
struct {
1212
-
uint32 sid;
1213
-
SVGA3dTextureFilter filter;
1214
-
}
1215
-
#include "vmware_pack_end.h"
1216
-
SVGA3dCmdGenerateMipmaps; /* SVGA_3D_CMD_GENERATE_MIPMAPS */
830
+
#pragma pack(push, 1)
831
+
typedef struct {
832
+
uint32 sid;
833
+
SVGA3dTextureFilter filter;
834
+
} SVGA3dCmdGenerateMipmaps;
835
+
#pragma pack(pop)
1217
836
1218
-
typedef
1219
-
#include "vmware_pack_begin.h"
1220
-
struct {
1221
-
uint32 sid;
1222
-
}
1223
-
#include "vmware_pack_end.h"
1224
-
SVGA3dCmdActivateSurface; /* SVGA_3D_CMD_ACTIVATE_SURFACE */
837
+
#pragma pack(push, 1)
838
+
typedef struct {
839
+
uint32 sid;
840
+
} SVGA3dCmdActivateSurface;
841
+
#pragma pack(pop)
1225
842
1226
-
typedef
1227
-
#include "vmware_pack_begin.h"
1228
-
struct {
1229
-
uint32 sid;
1230
-
}
1231
-
#include "vmware_pack_end.h"
1232
-
SVGA3dCmdDeactivateSurface; /* SVGA_3D_CMD_DEACTIVATE_SURFACE */
843
+
#pragma pack(push, 1)
844
+
typedef struct {
845
+
uint32 sid;
846
+
} SVGA3dCmdDeactivateSurface;
847
+
#pragma pack(pop)
1233
848
1234
-
/*
1235
-
* Screen DMA command
1236
-
*
1237
-
* Available with SVGA_FIFO_CAP_SCREEN_OBJECT_2. The SVGA_CAP_3D device
1238
-
* cap bit is not required.
1239
-
*
1240
-
* - refBuffer and destBuffer are 32bit BGRX; refBuffer and destBuffer could
1241
-
* be different, but it is required that guest makes sure refBuffer has
1242
-
* exactly the same contents that were written to when last time screen DMA
1243
-
* command is received by host.
1244
-
*
1245
-
* - changemap is generated by lib/blit, and it has the changes from last
1246
-
* received screen DMA or more.
1247
-
*/
849
+
#pragma pack(push, 1)
850
+
typedef struct SVGA3dCmdScreenDMA {
851
+
uint32 screenId;
852
+
SVGAGuestImage refBuffer;
853
+
SVGAGuestImage destBuffer;
854
+
SVGAGuestImage changeMap;
855
+
} SVGA3dCmdScreenDMA;
856
+
#pragma pack(pop)
1248
857
1249
-
typedef
1250
-
#include "vmware_pack_begin.h"
1251
-
struct SVGA3dCmdScreenDMA {
1252
-
uint32 screenId;
1253
-
SVGAGuestImage refBuffer;
1254
-
SVGAGuestImage destBuffer;
1255
-
SVGAGuestImage changeMap;
1256
-
}
1257
-
#include "vmware_pack_end.h"
1258
-
SVGA3dCmdScreenDMA; /* SVGA_3D_CMD_SCREEN_DMA */
858
+
#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
859
+
#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
860
+
#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
861
+
#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
1259
862
1260
-
/*
1261
-
* Logic ops
1262
-
*/
863
+
#pragma pack(push, 1)
864
+
typedef struct SVGA3dCmdLogicOpsBitBlt {
865
+
SVGA3dSurfaceImageId src;
866
+
SVGA3dSurfaceImageId dst;
867
+
SVGA3dLogicOp logicOp;
868
+
SVGA3dLogicOpRop3 logicOpRop3;
1263
869
1264
-
#define SVGA3D_LOTRANSBLT_HONORALPHA (0x01)
1265
-
#define SVGA3D_LOSTRETCHBLT_MIRRORX (0x01)
1266
-
#define SVGA3D_LOSTRETCHBLT_MIRRORY (0x02)
1267
-
#define SVGA3D_LOALPHABLEND_SRCHASALPHA (0x01)
870
+
} SVGA3dCmdLogicOpsBitBlt;
871
+
#pragma pack(pop)
1268
872
1269
-
typedef
1270
-
#include "vmware_pack_begin.h"
1271
-
struct SVGA3dCmdLogicOpsBitBlt {
1272
-
/*
1273
-
* All LogicOps surfaces are one-level
1274
-
* surfaces so mipmap & face should always
1275
-
* be zero.
1276
-
*/
1277
-
SVGA3dSurfaceImageId src;
1278
-
SVGA3dSurfaceImageId dst;
1279
-
SVGA3dLogicOp logicOp;
1280
-
SVGA3dLogicOpRop3 logicOpRop3;
1281
-
/* Followed by variable number of SVGA3dCopyBox structures */
1282
-
}
1283
-
#include "vmware_pack_end.h"
1284
-
SVGA3dCmdLogicOpsBitBlt; /* SVGA_3D_CMD_LOGICOPS_BITBLT */
873
+
#pragma pack(push, 1)
874
+
typedef struct SVGA3dCmdLogicOpsTransBlt {
875
+
SVGA3dSurfaceImageId src;
876
+
SVGA3dSurfaceImageId dst;
877
+
uint32 color;
878
+
uint32 flags;
879
+
SVGA3dBox srcBox;
880
+
SVGA3dSignedBox dstBox;
881
+
SVGA3dBox clipBox;
882
+
} SVGA3dCmdLogicOpsTransBlt;
883
+
#pragma pack(pop)
1285
884
885
+
#pragma pack(push, 1)
886
+
typedef struct SVGA3dCmdLogicOpsStretchBlt {
887
+
SVGA3dSurfaceImageId src;
888
+
SVGA3dSurfaceImageId dst;
889
+
uint16 mode;
890
+
uint16 flags;
891
+
SVGA3dBox srcBox;
892
+
SVGA3dSignedBox dstBox;
893
+
SVGA3dBox clipBox;
894
+
} SVGA3dCmdLogicOpsStretchBlt;
895
+
#pragma pack(pop)
1286
896
1287
-
typedef
1288
-
#include "vmware_pack_begin.h"
1289
-
struct SVGA3dCmdLogicOpsTransBlt {
1290
-
/*
1291
-
* All LogicOps surfaces are one-level
1292
-
* surfaces so mipmap & face should always
1293
-
* be zero.
1294
-
*/
1295
-
SVGA3dSurfaceImageId src;
1296
-
SVGA3dSurfaceImageId dst;
1297
-
uint32 color;
1298
-
uint32 flags;
1299
-
SVGA3dBox srcBox;
1300
-
SVGA3dSignedBox dstBox;
1301
-
SVGA3dBox clipBox;
1302
-
}
1303
-
#include "vmware_pack_end.h"
1304
-
SVGA3dCmdLogicOpsTransBlt; /* SVGA_3D_CMD_LOGICOPS_TRANSBLT */
897
+
#pragma pack(push, 1)
898
+
typedef struct SVGA3dCmdLogicOpsColorFill {
899
+
SVGA3dSurfaceImageId dst;
900
+
uint32 color;
901
+
SVGA3dLogicOp logicOp;
902
+
SVGA3dLogicOpRop3 logicOpRop3;
1305
903
904
+
} SVGA3dCmdLogicOpsColorFill;
905
+
#pragma pack(pop)
1306
906
1307
-
typedef
1308
-
#include "vmware_pack_begin.h"
1309
-
struct SVGA3dCmdLogicOpsStretchBlt {
1310
-
/*
1311
-
* All LogicOps surfaces are one-level
1312
-
* surfaces so mipmap & face should always
1313
-
* be zero.
1314
-
*/
1315
-
SVGA3dSurfaceImageId src;
1316
-
SVGA3dSurfaceImageId dst;
1317
-
uint16 mode;
1318
-
uint16 flags;
1319
-
SVGA3dBox srcBox;
1320
-
SVGA3dSignedBox dstBox;
1321
-
SVGA3dBox clipBox;
1322
-
}
1323
-
#include "vmware_pack_end.h"
1324
-
SVGA3dCmdLogicOpsStretchBlt; /* SVGA_3D_CMD_LOGICOPS_STRETCHBLT */
1325
-
1326
-
1327
-
typedef
1328
-
#include "vmware_pack_begin.h"
1329
-
struct SVGA3dCmdLogicOpsColorFill {
1330
-
/*
1331
-
* All LogicOps surfaces are one-level
1332
-
* surfaces so mipmap & face should always
1333
-
* be zero.
1334
-
*/
1335
-
SVGA3dSurfaceImageId dst;
1336
-
uint32 color;
1337
-
SVGA3dLogicOp logicOp;
1338
-
SVGA3dLogicOpRop3 logicOpRop3;
1339
-
/* Followed by variable number of SVGA3dRect structures. */
1340
-
}
1341
-
#include "vmware_pack_end.h"
1342
-
SVGA3dCmdLogicOpsColorFill; /* SVGA_3D_CMD_LOGICOPS_COLORFILL */
1343
-
1344
-
1345
-
typedef
1346
-
#include "vmware_pack_begin.h"
1347
-
struct SVGA3dCmdLogicOpsAlphaBlend {
1348
-
/*
1349
-
* All LogicOps surfaces are one-level
1350
-
* surfaces so mipmap & face should always
1351
-
* be zero.
1352
-
*/
1353
-
SVGA3dSurfaceImageId src;
1354
-
SVGA3dSurfaceImageId dst;
1355
-
uint32 alphaVal;
1356
-
uint32 flags;
1357
-
SVGA3dBox srcBox;
1358
-
SVGA3dSignedBox dstBox;
1359
-
SVGA3dBox clipBox;
1360
-
}
1361
-
#include "vmware_pack_end.h"
1362
-
SVGA3dCmdLogicOpsAlphaBlend; /* SVGA_3D_CMD_LOGICOPS_ALPHABLEND */
907
+
#pragma pack(push, 1)
908
+
typedef struct SVGA3dCmdLogicOpsAlphaBlend {
909
+
SVGA3dSurfaceImageId src;
910
+
SVGA3dSurfaceImageId dst;
911
+
uint32 alphaVal;
912
+
uint32 flags;
913
+
SVGA3dBox srcBox;
914
+
SVGA3dSignedBox dstBox;
915
+
SVGA3dBox clipBox;
916
+
} SVGA3dCmdLogicOpsAlphaBlend;
917
+
#pragma pack(pop)
1363
918
1364
919
#define SVGA3D_CLEARTYPE_INVALID_GAMMA_INDEX 0xFFFFFFFF
1365
920
1366
-
#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
921
+
#define SVGA3D_CLEARTYPE_GAMMA_WIDTH 512
1367
922
#define SVGA3D_CLEARTYPE_GAMMA_HEIGHT 16
1368
923
1369
-
typedef
1370
-
#include "vmware_pack_begin.h"
1371
-
struct SVGA3dCmdLogicOpsClearTypeBlend {
1372
-
/*
1373
-
* All LogicOps surfaces are one-level
1374
-
* surfaces so mipmap & face should always
1375
-
* be zero.
1376
-
*/
1377
-
SVGA3dSurfaceImageId tmp;
1378
-
SVGA3dSurfaceImageId dst;
1379
-
SVGA3dSurfaceImageId gammaSurf;
1380
-
SVGA3dSurfaceImageId alphaSurf;
1381
-
uint32 gamma;
1382
-
uint32 color;
1383
-
uint32 color2;
1384
-
int32 alphaOffsetX;
1385
-
int32 alphaOffsetY;
1386
-
/* Followed by variable number of SVGA3dBox structures */
1387
-
}
1388
-
#include "vmware_pack_end.h"
1389
-
SVGA3dCmdLogicOpsClearTypeBlend; /* SVGA_3D_CMD_LOGICOPS_CLEARTYPEBLEND */
924
+
#pragma pack(push, 1)
925
+
typedef struct SVGA3dCmdLogicOpsClearTypeBlend {
926
+
SVGA3dSurfaceImageId tmp;
927
+
SVGA3dSurfaceImageId dst;
928
+
SVGA3dSurfaceImageId gammaSurf;
929
+
SVGA3dSurfaceImageId alphaSurf;
930
+
uint32 gamma;
931
+
uint32 color;
932
+
uint32 color2;
933
+
int32 alphaOffsetX;
934
+
int32 alphaOffsetY;
1390
935
936
+
} SVGA3dCmdLogicOpsClearTypeBlend;
937
+
#pragma pack(pop)
1391
938
1392
-
/*
1393
-
* Guest-backed objects definitions.
1394
-
*/
939
+
#pragma pack(push, 1)
940
+
typedef struct {
941
+
SVGAMobFormat ptDepth;
942
+
uint32 sizeInBytes;
943
+
PPN64 base;
944
+
} SVGAOTableMobEntry;
945
+
#pragma pack(pop)
1395
946
1396
-
typedef
1397
-
#include "vmware_pack_begin.h"
1398
-
struct {
1399
-
SVGAMobFormat ptDepth;
1400
-
uint32 sizeInBytes;
1401
-
PPN64 base;
1402
-
}
1403
-
#include "vmware_pack_end.h"
1404
-
SVGAOTableMobEntry;
1405
-
#define SVGA3D_OTABLE_MOB_ENTRY_SIZE (sizeof(SVGAOTableMobEntry))
947
+
#pragma pack(push, 1)
948
+
typedef struct {
949
+
SVGA3dSurfaceFormat format;
950
+
SVGA3dSurface1Flags surface1Flags;
951
+
uint32 numMipLevels;
952
+
uint32 multisampleCount;
953
+
SVGA3dTextureFilter autogenFilter;
954
+
SVGA3dSize size;
955
+
SVGAMobId mobid;
956
+
uint32 arraySize;
957
+
uint32 mobPitch;
958
+
SVGA3dSurface2Flags surface2Flags;
959
+
uint8 multisamplePattern;
960
+
uint8 qualityLevel;
961
+
uint16 bufferByteStride;
962
+
float minLOD;
963
+
uint32 pad0[2];
964
+
} SVGAOTableSurfaceEntry;
965
+
#pragma pack(pop)
1406
966
1407
-
typedef
1408
-
#include "vmware_pack_begin.h"
1409
-
struct {
1410
-
SVGA3dSurfaceFormat format;
1411
-
SVGA3dSurface1Flags surface1Flags;
1412
-
uint32 numMipLevels;
1413
-
uint32 multisampleCount;
1414
-
SVGA3dTextureFilter autogenFilter;
1415
-
SVGA3dSize size;
1416
-
SVGAMobId mobid;
1417
-
uint32 arraySize;
1418
-
uint32 mobPitch;
1419
-
SVGA3dSurface2Flags surface2Flags;
1420
-
uint8 multisamplePattern;
1421
-
uint8 qualityLevel;
1422
-
uint16 bufferByteStride;
1423
-
float minLOD;
1424
-
uint32 pad0[2];
1425
-
}
1426
-
#include "vmware_pack_end.h"
1427
-
SVGAOTableSurfaceEntry;
1428
-
#define SVGA3D_OTABLE_SURFACE_ENTRY_SIZE (sizeof(SVGAOTableSurfaceEntry))
967
+
#pragma pack(push, 1)
968
+
typedef struct {
969
+
uint32 cid;
970
+
SVGAMobId mobid;
971
+
} SVGAOTableContextEntry;
972
+
#pragma pack(pop)
1429
973
1430
-
typedef
1431
-
#include "vmware_pack_begin.h"
1432
-
struct {
1433
-
uint32 cid;
1434
-
SVGAMobId mobid;
1435
-
}
1436
-
#include "vmware_pack_end.h"
1437
-
SVGAOTableContextEntry;
1438
-
#define SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE (sizeof(SVGAOTableContextEntry))
974
+
#pragma pack(push, 1)
975
+
typedef struct {
976
+
SVGA3dShaderType type;
977
+
uint32 sizeInBytes;
978
+
uint32 offsetInBytes;
979
+
SVGAMobId mobid;
980
+
} SVGAOTableShaderEntry;
981
+
#pragma pack(pop)
1439
982
1440
-
typedef
1441
-
#include "vmware_pack_begin.h"
1442
-
struct {
1443
-
SVGA3dShaderType type;
1444
-
uint32 sizeInBytes;
1445
-
uint32 offsetInBytes;
1446
-
SVGAMobId mobid;
1447
-
}
1448
-
#include "vmware_pack_end.h"
1449
-
SVGAOTableShaderEntry;
1450
-
#define SVGA3D_OTABLE_SHADER_ENTRY_SIZE (sizeof(SVGAOTableShaderEntry))
1451
-
1452
-
#define SVGA_STFLAG_PRIMARY (1 << 0)
1453
-
#define SVGA_STFLAG_RESERVED (1 << 1) /* Added with cap SVGA_CAP_HP_CMD_QUEUE */
983
+
#define SVGA_STFLAG_PRIMARY (1 << 0)
984
+
#define SVGA_STFLAG_RESERVED (1 << 1)
1454
985
typedef uint32 SVGAScreenTargetFlags;
1455
986
1456
-
typedef
1457
-
#include "vmware_pack_begin.h"
1458
-
struct {
1459
-
SVGA3dSurfaceImageId image;
1460
-
uint32 width;
1461
-
uint32 height;
1462
-
int32 xRoot;
1463
-
int32 yRoot;
1464
-
SVGAScreenTargetFlags flags;
1465
-
uint32 dpi;
1466
-
uint32 pad[7];
1467
-
}
1468
-
#include "vmware_pack_end.h"
1469
-
SVGAOTableScreenTargetEntry;
1470
-
#define SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE \
1471
-
(sizeof(SVGAOTableScreenTargetEntry))
987
+
#pragma pack(push, 1)
988
+
typedef struct {
989
+
SVGA3dSurfaceImageId image;
990
+
uint32 width;
991
+
uint32 height;
992
+
int32 xRoot;
993
+
int32 yRoot;
994
+
SVGAScreenTargetFlags flags;
995
+
uint32 dpi;
996
+
uint32 pad[7];
997
+
} SVGAOTableScreenTargetEntry;
998
+
#pragma pack(pop)
1472
999
1473
-
typedef
1474
-
#include "vmware_pack_begin.h"
1475
-
struct {
1476
-
float value[4];
1477
-
}
1478
-
#include "vmware_pack_end.h"
1479
-
SVGA3dShaderConstFloat;
1000
+
#pragma pack(push, 1)
1001
+
typedef struct {
1002
+
float value[4];
1003
+
} SVGA3dShaderConstFloat;
1004
+
#pragma pack(pop)
1480
1005
1481
-
typedef
1482
-
#include "vmware_pack_begin.h"
1483
-
struct {
1484
-
int32 value[4];
1485
-
}
1486
-
#include "vmware_pack_end.h"
1487
-
SVGA3dShaderConstInt;
1006
+
#pragma pack(push, 1)
1007
+
typedef struct {
1008
+
int32 value[4];
1009
+
} SVGA3dShaderConstInt;
1010
+
#pragma pack(pop)
1488
1011
1489
-
typedef
1490
-
#include "vmware_pack_begin.h"
1491
-
struct {
1492
-
uint32 value;
1493
-
}
1494
-
#include "vmware_pack_end.h"
1495
-
SVGA3dShaderConstBool;
1012
+
#pragma pack(push, 1)
1013
+
typedef struct {
1014
+
uint32 value;
1015
+
} SVGA3dShaderConstBool;
1016
+
#pragma pack(pop)
1496
1017
1497
-
typedef
1498
-
#include "vmware_pack_begin.h"
1499
-
struct {
1500
-
uint16 streamOffset;
1501
-
uint8 stream;
1502
-
uint8 type;
1503
-
uint8 methodUsage;
1504
-
uint8 usageIndex;
1505
-
}
1506
-
#include "vmware_pack_end.h"
1507
-
SVGAGBVertexElement;
1018
+
#pragma pack(push, 1)
1019
+
typedef struct {
1020
+
uint16 streamOffset;
1021
+
uint8 stream;
1022
+
uint8 type;
1023
+
uint8 methodUsage;
1024
+
uint8 usageIndex;
1025
+
} SVGAGBVertexElement;
1026
+
#pragma pack(pop)
1508
1027
1509
-
typedef
1510
-
#include "vmware_pack_begin.h"
1511
-
struct {
1512
-
uint32 sid;
1513
-
uint16 stride;
1514
-
uint32 offset;
1515
-
}
1516
-
#include "vmware_pack_end.h"
1517
-
SVGAGBVertexStream;
1518
-
typedef
1519
-
#include "vmware_pack_begin.h"
1520
-
struct {
1521
-
SVGA3dRect viewport;
1522
-
SVGA3dRect scissorRect;
1523
-
SVGA3dZRange zRange;
1028
+
#pragma pack(push, 1)
1029
+
typedef struct {
1030
+
uint32 sid;
1031
+
uint16 stride;
1032
+
uint32 offset;
1033
+
} SVGAGBVertexStream;
1034
+
#pragma pack(pop)
1035
+
#pragma pack(push, 1)
1036
+
typedef struct {
1037
+
SVGA3dRect viewport;
1038
+
SVGA3dRect scissorRect;
1039
+
SVGA3dZRange zRange;
1524
1040
1525
-
SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
1526
-
SVGAGBVertexElement decl1[4];
1041
+
SVGA3dSurfaceImageId renderTargets[SVGA3D_RT_MAX];
1042
+
SVGAGBVertexElement decl1[4];
1527
1043
1528
-
uint32 renderStates[SVGA3D_RS_MAX];
1529
-
SVGAGBVertexElement decl2[18];
1530
-
uint32 pad0[2];
1044
+
uint32 renderStates[SVGA3D_RS_MAX];
1045
+
SVGAGBVertexElement decl2[18];
1046
+
uint32 pad0[2];
1531
1047
1532
-
struct {
1533
-
SVGA3dFace face;
1534
-
SVGA3dMaterial material;
1535
-
} material;
1048
+
struct {
1049
+
SVGA3dFace face;
1050
+
SVGA3dMaterial material;
1051
+
} material;
1536
1052
1537
-
float clipPlanes[SVGA3D_NUM_CLIPPLANES][4];
1538
-
float matrices[SVGA3D_TRANSFORM_MAX][16];
1053
+
float clipPlanes[SVGA3D_MAX_CLIP_PLANES][4];
1054
+
float matrices[SVGA3D_TRANSFORM_MAX][16];
1539
1055
1540
-
SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
1541
-
SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
1056
+
SVGA3dBool lightEnabled[SVGA3D_NUM_LIGHTS];
1057
+
SVGA3dLightData lightData[SVGA3D_NUM_LIGHTS];
1542
1058
1543
-
/*
1544
-
* Shaders currently bound
1545
-
*/
1546
-
uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
1547
-
SVGAGBVertexElement decl3[10];
1548
-
uint32 pad1[3];
1059
+
uint32 shaders[SVGA3D_NUM_SHADERTYPE_PREDX];
1060
+
SVGAGBVertexElement decl3[10];
1061
+
uint32 pad1[3];
1549
1062
1550
-
uint32 occQueryActive;
1551
-
uint32 occQueryValue;
1063
+
uint32 occQueryActive;
1064
+
uint32 occQueryValue;
1552
1065
1553
-
/*
1554
-
* Int/Bool Shader constants
1555
-
*/
1556
-
SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
1557
-
SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
1558
-
uint16 pShaderBValues;
1559
-
uint16 vShaderBValues;
1066
+
SVGA3dShaderConstInt pShaderIValues[SVGA3D_CONSTINTREG_MAX];
1067
+
SVGA3dShaderConstInt vShaderIValues[SVGA3D_CONSTINTREG_MAX];
1068
+
uint16 pShaderBValues;
1069
+
uint16 vShaderBValues;
1560
1070
1071
+
SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
1072
+
SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
1073
+
uint32 numVertexDecls;
1074
+
uint32 numVertexStreams;
1075
+
uint32 numVertexDivisors;
1076
+
uint32 pad2[30];
1561
1077
1562
-
SVGAGBVertexStream streams[SVGA3D_MAX_VERTEX_ARRAYS];
1563
-
SVGA3dVertexDivisor divisors[SVGA3D_MAX_VERTEX_ARRAYS];
1564
-
uint32 numVertexDecls;
1565
-
uint32 numVertexStreams;
1566
-
uint32 numVertexDivisors;
1567
-
uint32 pad2[30];
1078
+
uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
1079
+
uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
1080
+
uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
1568
1081
1569
-
/*
1570
-
* Texture Stages
1571
-
*
1572
-
* SVGA3D_TS_INVALID through SVGA3D_TS_CONSTANT are in the
1573
-
* textureStages array.
1574
-
* SVGA3D_TS_COLOR_KEY is in tsColorKey.
1575
-
*/
1576
-
uint32 tsColorKey[SVGA3D_NUM_TEXTURE_UNITS];
1577
-
uint32 textureStages[SVGA3D_NUM_TEXTURE_UNITS][SVGA3D_TS_CONSTANT + 1];
1578
-
uint32 tsColorKeyEnable[SVGA3D_NUM_TEXTURE_UNITS];
1082
+
SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
1083
+
SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
1084
+
} SVGAGBContextData;
1085
+
#pragma pack(pop)
1579
1086
1580
-
/*
1581
-
* Float Shader constants.
1582
-
*/
1583
-
SVGA3dShaderConstFloat pShaderFValues[SVGA3D_CONSTREG_MAX];
1584
-
SVGA3dShaderConstFloat vShaderFValues[SVGA3D_CONSTREG_MAX];
1585
-
}
1586
-
#include "vmware_pack_end.h"
1587
-
SVGAGBContextData;
1588
-
#define SVGA3D_CONTEXT_DATA_SIZE (sizeof(SVGAGBContextData))
1087
+
#pragma pack(push, 1)
1088
+
typedef struct {
1089
+
SVGAOTableType type;
1090
+
PPN32 baseAddress;
1091
+
uint32 sizeInBytes;
1092
+
uint32 validSizeInBytes;
1093
+
SVGAMobFormat ptDepth;
1094
+
} SVGA3dCmdSetOTableBase;
1095
+
#pragma pack(pop)
1589
1096
1590
-
/*
1591
-
* SVGA3dCmdSetOTableBase --
1592
-
*
1593
-
* This command allows the guest to specify the base PPN of the
1594
-
* specified object table.
1595
-
*/
1097
+
#pragma pack(push, 1)
1098
+
typedef struct {
1099
+
SVGAOTableType type;
1100
+
PPN64 baseAddress;
1101
+
uint32 sizeInBytes;
1102
+
uint32 validSizeInBytes;
1103
+
SVGAMobFormat ptDepth;
1104
+
} SVGA3dCmdSetOTableBase64;
1105
+
#pragma pack(pop)
1596
1106
1597
-
typedef
1598
-
#include "vmware_pack_begin.h"
1599
-
struct {
1600
-
SVGAOTableType type;
1601
-
PPN32 baseAddress;
1602
-
uint32 sizeInBytes;
1603
-
uint32 validSizeInBytes;
1604
-
SVGAMobFormat ptDepth;
1605
-
}
1606
-
#include "vmware_pack_end.h"
1607
-
SVGA3dCmdSetOTableBase; /* SVGA_3D_CMD_SET_OTABLE_BASE */
1107
+
#pragma pack(push, 1)
1108
+
typedef struct {
1109
+
SVGAOTableType type;
1110
+
PPN64 baseAddress;
1111
+
uint32 sizeInBytes;
1112
+
uint32 validSizeInBytes;
1113
+
SVGAMobFormat ptDepth;
1114
+
} SVGA3dCmdGrowOTable;
1115
+
#pragma pack(pop)
1608
1116
1609
-
typedef
1610
-
#include "vmware_pack_begin.h"
1611
-
struct {
1612
-
SVGAOTableType type;
1613
-
PPN64 baseAddress;
1614
-
uint32 sizeInBytes;
1615
-
uint32 validSizeInBytes;
1616
-
SVGAMobFormat ptDepth;
1617
-
}
1618
-
#include "vmware_pack_end.h"
1619
-
SVGA3dCmdSetOTableBase64; /* SVGA_3D_CMD_SET_OTABLE_BASE64 */
1117
+
#pragma pack(push, 1)
1118
+
typedef struct {
1119
+
SVGAOTableType type;
1120
+
} SVGA3dCmdReadbackOTable;
1121
+
#pragma pack(pop)
1620
1122
1621
-
/*
1622
-
* Guests using SVGA_3D_CMD_GROW_OTABLE are promising that
1623
-
* the new OTable contains the same contents as the old one, except possibly
1624
-
* for some new invalid entries at the end.
1625
-
*
1626
-
* (Otherwise, guests should use one of the SetOTableBase commands.)
1627
-
*/
1628
-
typedef
1629
-
#include "vmware_pack_begin.h"
1630
-
struct {
1631
-
SVGAOTableType type;
1632
-
PPN64 baseAddress;
1633
-
uint32 sizeInBytes;
1634
-
uint32 validSizeInBytes;
1635
-
SVGAMobFormat ptDepth;
1636
-
}
1637
-
#include "vmware_pack_end.h"
1638
-
SVGA3dCmdGrowOTable; /* SVGA_3D_CMD_GROW_OTABLE */
1123
+
#pragma pack(push, 1)
1124
+
typedef struct SVGA3dCmdDefineGBMob {
1125
+
SVGAMobId mobid;
1126
+
SVGAMobFormat ptDepth;
1127
+
PPN32 base;
1128
+
uint32 sizeInBytes;
1129
+
} SVGA3dCmdDefineGBMob;
1130
+
#pragma pack(pop)
1639
1131
1640
-
typedef
1641
-
#include "vmware_pack_begin.h"
1642
-
struct {
1643
-
SVGAOTableType type;
1644
-
}
1645
-
#include "vmware_pack_end.h"
1646
-
SVGA3dCmdReadbackOTable; /* SVGA_3D_CMD_READBACK_OTABLE */
1132
+
#pragma pack(push, 1)
1133
+
typedef struct SVGA3dCmdDestroyGBMob {
1134
+
SVGAMobId mobid;
1135
+
} SVGA3dCmdDestroyGBMob;
1136
+
#pragma pack(pop)
1647
1137
1648
-
/*
1649
-
* Define a memory object (Mob) in the OTable.
1650
-
*/
1138
+
#pragma pack(push, 1)
1139
+
typedef struct SVGA3dCmdDefineGBMob64 {
1140
+
SVGAMobId mobid;
1141
+
SVGAMobFormat ptDepth;
1142
+
PPN64 base;
1143
+
uint32 sizeInBytes;
1144
+
} SVGA3dCmdDefineGBMob64;
1145
+
#pragma pack(pop)
1651
1146
1652
-
typedef
1653
-
#include "vmware_pack_begin.h"
1654
-
struct SVGA3dCmdDefineGBMob {
1655
-
SVGAMobId mobid;
1656
-
SVGAMobFormat ptDepth;
1657
-
PPN32 base;
1658
-
uint32 sizeInBytes;
1659
-
}
1660
-
#include "vmware_pack_end.h"
1661
-
SVGA3dCmdDefineGBMob; /* SVGA_3D_CMD_DEFINE_GB_MOB */
1147
+
#pragma pack(push, 1)
1148
+
typedef struct SVGA3dCmdRedefineGBMob64 {
1149
+
SVGAMobId mobid;
1150
+
SVGAMobFormat ptDepth;
1151
+
PPN64 base;
1152
+
uint32 sizeInBytes;
1153
+
} SVGA3dCmdRedefineGBMob64;
1154
+
#pragma pack(pop)
1662
1155
1156
+
#pragma pack(push, 1)
1157
+
typedef struct SVGA3dCmdUpdateGBMobMapping {
1158
+
SVGAMobId mobid;
1159
+
} SVGA3dCmdUpdateGBMobMapping;
1160
+
#pragma pack(pop)
1663
1161
1664
-
/*
1665
-
* Destroys an object in the OTable.
1666
-
*/
1162
+
#pragma pack(push, 1)
1163
+
typedef struct SVGA3dCmdDefineGBSurface {
1164
+
uint32 sid;
1165
+
SVGA3dSurface1Flags surfaceFlags;
1166
+
SVGA3dSurfaceFormat format;
1167
+
uint32 numMipLevels;
1168
+
uint32 multisampleCount;
1169
+
SVGA3dTextureFilter autogenFilter;
1170
+
SVGA3dSize size;
1171
+
} SVGA3dCmdDefineGBSurface;
1172
+
#pragma pack(pop)
1667
1173
1668
-
typedef
1669
-
#include "vmware_pack_begin.h"
1670
-
struct SVGA3dCmdDestroyGBMob {
1671
-
SVGAMobId mobid;
1672
-
}
1673
-
#include "vmware_pack_end.h"
1674
-
SVGA3dCmdDestroyGBMob; /* SVGA_3D_CMD_DESTROY_GB_MOB */
1174
+
#pragma pack(push, 1)
1175
+
typedef struct SVGA3dCmdDefineGBSurface_v2 {
1176
+
uint32 sid;
1177
+
SVGA3dSurface1Flags surfaceFlags;
1178
+
SVGA3dSurfaceFormat format;
1179
+
uint32 numMipLevels;
1180
+
uint32 multisampleCount;
1181
+
SVGA3dTextureFilter autogenFilter;
1182
+
SVGA3dSize size;
1183
+
uint32 arraySize;
1184
+
uint32 pad;
1185
+
} SVGA3dCmdDefineGBSurface_v2;
1186
+
#pragma pack(pop)
1675
1187
1676
-
/*
1677
-
* Define a memory object (Mob) in the OTable with a PPN64 base.
1678
-
*/
1188
+
#pragma pack(push, 1)
1189
+
typedef struct SVGA3dCmdDefineGBSurface_v3 {
1190
+
uint32 sid;
1191
+
SVGA3dSurfaceAllFlags surfaceFlags;
1192
+
SVGA3dSurfaceFormat format;
1193
+
uint32 numMipLevels;
1194
+
uint32 multisampleCount;
1195
+
SVGA3dMSPattern multisamplePattern;
1196
+
SVGA3dMSQualityLevel qualityLevel;
1197
+
SVGA3dTextureFilter autogenFilter;
1198
+
SVGA3dSize size;
1199
+
uint32 arraySize;
1200
+
} SVGA3dCmdDefineGBSurface_v3;
1201
+
#pragma pack(pop)
1679
1202
1680
-
typedef
1681
-
#include "vmware_pack_begin.h"
1682
-
struct SVGA3dCmdDefineGBMob64 {
1683
-
SVGAMobId mobid;
1684
-
SVGAMobFormat ptDepth;
1685
-
PPN64 base;
1686
-
uint32 sizeInBytes;
1687
-
}
1688
-
#include "vmware_pack_end.h"
1689
-
SVGA3dCmdDefineGBMob64; /* SVGA_3D_CMD_DEFINE_GB_MOB64 */
1203
+
#pragma pack(push, 1)
1204
+
typedef struct SVGA3dCmdDefineGBSurface_v4 {
1205
+
uint32 sid;
1206
+
SVGA3dSurfaceAllFlags surfaceFlags;
1207
+
SVGA3dSurfaceFormat format;
1208
+
uint32 numMipLevels;
1209
+
uint32 multisampleCount;
1210
+
SVGA3dMSPattern multisamplePattern;
1211
+
SVGA3dMSQualityLevel qualityLevel;
1212
+
SVGA3dTextureFilter autogenFilter;
1213
+
SVGA3dSize size;
1214
+
uint32 arraySize;
1215
+
uint32 bufferByteStride;
1216
+
} SVGA3dCmdDefineGBSurface_v4;
1217
+
#pragma pack(pop)
1690
1218
1691
-
/*
1692
-
* Redefine an object in the OTable with PPN64 base.
1693
-
*/
1219
+
#pragma pack(push, 1)
1220
+
typedef struct SVGA3dCmdDestroyGBSurface {
1221
+
uint32 sid;
1222
+
} SVGA3dCmdDestroyGBSurface;
1223
+
#pragma pack(pop)
1694
1224
1695
-
typedef
1696
-
#include "vmware_pack_begin.h"
1697
-
struct SVGA3dCmdRedefineGBMob64 {
1698
-
SVGAMobId mobid;
1699
-
SVGAMobFormat ptDepth;
1700
-
PPN64 base;
1701
-
uint32 sizeInBytes;
1702
-
}
1703
-
#include "vmware_pack_end.h"
1704
-
SVGA3dCmdRedefineGBMob64; /* SVGA_3D_CMD_REDEFINE_GB_MOB64 */
1225
+
#pragma pack(push, 1)
1226
+
typedef struct SVGA3dCmdBindGBSurface {
1227
+
uint32 sid;
1228
+
SVGAMobId mobid;
1229
+
} SVGA3dCmdBindGBSurface;
1230
+
#pragma pack(pop)
1705
1231
1706
-
/*
1707
-
* Notification that the page tables have been modified.
1708
-
*/
1709
-
1710
-
typedef
1711
-
#include "vmware_pack_begin.h"
1712
-
struct SVGA3dCmdUpdateGBMobMapping {
1713
-
SVGAMobId mobid;
1714
-
}
1715
-
#include "vmware_pack_end.h"
1716
-
SVGA3dCmdUpdateGBMobMapping; /* SVGA_3D_CMD_UPDATE_GB_MOB_MAPPING */
1717
-
1718
-
/*
1719
-
* Define a guest-backed surface.
1720
-
*/
1721
-
1722
-
typedef
1723
-
#include "vmware_pack_begin.h"
1724
-
struct SVGA3dCmdDefineGBSurface {
1725
-
uint32 sid;
1726
-
SVGA3dSurface1Flags surfaceFlags;
1727
-
SVGA3dSurfaceFormat format;
1728
-
uint32 numMipLevels;
1729
-
uint32 multisampleCount;
1730
-
SVGA3dTextureFilter autogenFilter;
1731
-
SVGA3dSize size;
1732
-
}
1733
-
#include "vmware_pack_end.h"
1734
-
SVGA3dCmdDefineGBSurface; /* SVGA_3D_CMD_DEFINE_GB_SURFACE */
1735
-
1736
-
/*
1737
-
* Defines a guest-backed surface, adding the arraySize field.
1738
-
*/
1739
-
typedef
1740
-
#include "vmware_pack_begin.h"
1741
-
struct SVGA3dCmdDefineGBSurface_v2 {
1742
-
uint32 sid;
1743
-
SVGA3dSurface1Flags surfaceFlags;
1744
-
SVGA3dSurfaceFormat format;
1745
-
uint32 numMipLevels;
1746
-
uint32 multisampleCount;
1747
-
SVGA3dTextureFilter autogenFilter;
1748
-
SVGA3dSize size;
1749
-
uint32 arraySize;
1750
-
uint32 pad;
1751
-
}
1752
-
#include "vmware_pack_end.h"
1753
-
SVGA3dCmdDefineGBSurface_v2; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V2 */
1754
-
1755
-
/*
1756
-
* Defines a guest-backed surface, adding the larger flags.
1757
-
*/
1758
-
typedef
1759
-
#include "vmware_pack_begin.h"
1760
-
struct SVGA3dCmdDefineGBSurface_v3 {
1761
-
uint32 sid;
1762
-
SVGA3dSurfaceAllFlags surfaceFlags;
1763
-
SVGA3dSurfaceFormat format;
1764
-
uint32 numMipLevels;
1765
-
uint32 multisampleCount;
1766
-
SVGA3dMSPattern multisamplePattern;
1767
-
SVGA3dMSQualityLevel qualityLevel;
1768
-
SVGA3dTextureFilter autogenFilter;
1769
-
SVGA3dSize size;
1770
-
uint32 arraySize;
1771
-
}
1772
-
#include "vmware_pack_end.h"
1773
-
SVGA3dCmdDefineGBSurface_v3; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V3 */
1774
-
1775
-
/*
1776
-
* Defines a guest-backed surface, adding buffer byte stride.
1777
-
*/
1778
-
typedef
1779
-
#include "vmware_pack_begin.h"
1780
-
struct SVGA3dCmdDefineGBSurface_v4 {
1781
-
uint32 sid;
1782
-
SVGA3dSurfaceAllFlags surfaceFlags;
1783
-
SVGA3dSurfaceFormat format;
1784
-
uint32 numMipLevels;
1785
-
uint32 multisampleCount;
1786
-
SVGA3dMSPattern multisamplePattern;
1787
-
SVGA3dMSQualityLevel qualityLevel;
1788
-
SVGA3dTextureFilter autogenFilter;
1789
-
SVGA3dSize size;
1790
-
uint32 arraySize;
1791
-
uint32 bufferByteStride;
1792
-
}
1793
-
#include "vmware_pack_end.h"
1794
-
SVGA3dCmdDefineGBSurface_v4; /* SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 */
1795
-
1796
-
/*
1797
-
* Destroy a guest-backed surface.
1798
-
*/
1799
-
1800
-
typedef
1801
-
#include "vmware_pack_begin.h"
1802
-
struct SVGA3dCmdDestroyGBSurface {
1803
-
uint32 sid;
1804
-
}
1805
-
#include "vmware_pack_end.h"
1806
-
SVGA3dCmdDestroyGBSurface; /* SVGA_3D_CMD_DESTROY_GB_SURFACE */
1807
-
1808
-
/*
1809
-
* Bind a guest-backed surface to a mob.
1810
-
*/
1811
-
1812
-
typedef
1813
-
#include "vmware_pack_begin.h"
1814
-
struct SVGA3dCmdBindGBSurface {
1815
-
uint32 sid;
1816
-
SVGAMobId mobid;
1817
-
}
1818
-
#include "vmware_pack_end.h"
1819
-
SVGA3dCmdBindGBSurface; /* SVGA_3D_CMD_BIND_GB_SURFACE */
1820
-
1821
-
typedef
1822
-
#include "vmware_pack_begin.h"
1823
-
struct SVGA3dCmdBindGBSurfaceWithPitch {
1824
-
uint32 sid;
1825
-
SVGAMobId mobid;
1826
-
uint32 baseLevelPitch;
1827
-
}
1828
-
#include "vmware_pack_end.h"
1829
-
SVGA3dCmdBindGBSurfaceWithPitch; /* SVGA_3D_CMD_BIND_GB_SURFACE_WITH_PITCH */
1830
-
1831
-
/*
1832
-
* Conditionally bind a mob to a guest-backed surface if testMobid
1833
-
* matches the currently bound mob. Optionally issue a
1834
-
* readback/update on the surface while it is still bound to the old
1835
-
* mobid if the mobid is changed by this command.
1836
-
*/
1232
+
#pragma pack(push, 1)
1233
+
typedef struct SVGA3dCmdBindGBSurfaceWithPitch {
1234
+
uint32 sid;
1235
+
SVGAMobId mobid;
1236
+
uint32 baseLevelPitch;
1237
+
} SVGA3dCmdBindGBSurfaceWithPitch;
1238
+
#pragma pack(pop)
1837
1239
1838
1240
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_READBACK (1 << 0)
1839
-
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
1241
+
#define SVGA3D_COND_BIND_GB_SURFACE_FLAG_UPDATE (1 << 1)
1840
1242
1841
-
typedef
1842
-
#include "vmware_pack_begin.h"
1843
-
struct SVGA3dCmdCondBindGBSurface {
1844
-
uint32 sid;
1845
-
SVGAMobId testMobid;
1846
-
SVGAMobId mobid;
1847
-
uint32 flags;
1848
-
}
1849
-
#include "vmware_pack_end.h"
1850
-
SVGA3dCmdCondBindGBSurface; /* SVGA_3D_CMD_COND_BIND_GB_SURFACE */
1243
+
#pragma pack(push, 1)
1244
+
typedef struct SVGA3dCmdCondBindGBSurface {
1245
+
uint32 sid;
1246
+
SVGAMobId testMobid;
1247
+
SVGAMobId mobid;
1248
+
uint32 flags;
1249
+
} SVGA3dCmdCondBindGBSurface;
1250
+
#pragma pack(pop)
1851
1251
1852
-
/*
1853
-
* Update an image in a guest-backed surface.
1854
-
* (Inform the device that the guest-contents have been updated.)
1855
-
*/
1252
+
#pragma pack(push, 1)
1253
+
typedef struct SVGA3dCmdUpdateGBImage {
1254
+
SVGA3dSurfaceImageId image;
1255
+
SVGA3dBox box;
1256
+
} SVGA3dCmdUpdateGBImage;
1257
+
#pragma pack(pop)
1856
1258
1857
-
typedef
1858
-
#include "vmware_pack_begin.h"
1859
-
struct SVGA3dCmdUpdateGBImage {
1860
-
SVGA3dSurfaceImageId image;
1861
-
SVGA3dBox box;
1862
-
}
1863
-
#include "vmware_pack_end.h"
1864
-
SVGA3dCmdUpdateGBImage; /* SVGA_3D_CMD_UPDATE_GB_IMAGE */
1259
+
#pragma pack(push, 1)
1260
+
typedef struct SVGA3dCmdUpdateGBSurface {
1261
+
uint32 sid;
1262
+
} SVGA3dCmdUpdateGBSurface;
1263
+
#pragma pack(pop)
1865
1264
1866
-
/*
1867
-
* Update an entire guest-backed surface.
1868
-
* (Inform the device that the guest-contents have been updated.)
1869
-
*/
1265
+
#pragma pack(push, 1)
1266
+
typedef struct SVGA3dCmdReadbackGBImage {
1267
+
SVGA3dSurfaceImageId image;
1268
+
} SVGA3dCmdReadbackGBImage;
1269
+
#pragma pack(pop)
1870
1270
1871
-
typedef
1872
-
#include "vmware_pack_begin.h"
1873
-
struct SVGA3dCmdUpdateGBSurface {
1874
-
uint32 sid;
1875
-
}
1876
-
#include "vmware_pack_end.h"
1877
-
SVGA3dCmdUpdateGBSurface; /* SVGA_3D_CMD_UPDATE_GB_SURFACE */
1271
+
#pragma pack(push, 1)
1272
+
typedef struct SVGA3dCmdReadbackGBSurface {
1273
+
uint32 sid;
1274
+
} SVGA3dCmdReadbackGBSurface;
1275
+
#pragma pack(pop)
1878
1276
1879
-
/*
1880
-
* Readback an image in a guest-backed surface.
1881
-
* (Request the device to flush the dirty contents into the guest.)
1882
-
*/
1277
+
#pragma pack(push, 1)
1278
+
typedef struct SVGA3dCmdReadbackGBImagePartial {
1279
+
SVGA3dSurfaceImageId image;
1280
+
SVGA3dBox box;
1281
+
uint32 invertBox;
1282
+
} SVGA3dCmdReadbackGBImagePartial;
1283
+
#pragma pack(pop)
1883
1284
1884
-
typedef
1885
-
#include "vmware_pack_begin.h"
1886
-
struct SVGA3dCmdReadbackGBImage {
1887
-
SVGA3dSurfaceImageId image;
1888
-
}
1889
-
#include "vmware_pack_end.h"
1890
-
SVGA3dCmdReadbackGBImage; /* SVGA_3D_CMD_READBACK_GB_IMAGE */
1285
+
#pragma pack(push, 1)
1286
+
typedef struct SVGA3dCmdInvalidateGBImage {
1287
+
SVGA3dSurfaceImageId image;
1288
+
} SVGA3dCmdInvalidateGBImage;
1289
+
#pragma pack(pop)
1891
1290
1892
-
/*
1893
-
* Readback an entire guest-backed surface.
1894
-
* (Request the device to flush the dirty contents into the guest.)
1895
-
*/
1291
+
#pragma pack(push, 1)
1292
+
typedef struct SVGA3dCmdInvalidateGBSurface {
1293
+
uint32 sid;
1294
+
} SVGA3dCmdInvalidateGBSurface;
1295
+
#pragma pack(pop)
1896
1296
1897
-
typedef
1898
-
#include "vmware_pack_begin.h"
1899
-
struct SVGA3dCmdReadbackGBSurface {
1900
-
uint32 sid;
1901
-
}
1902
-
#include "vmware_pack_end.h"
1903
-
SVGA3dCmdReadbackGBSurface; /* SVGA_3D_CMD_READBACK_GB_SURFACE */
1297
+
#pragma pack(push, 1)
1298
+
typedef struct SVGA3dCmdInvalidateGBImagePartial {
1299
+
SVGA3dSurfaceImageId image;
1300
+
SVGA3dBox box;
1301
+
uint32 invertBox;
1302
+
} SVGA3dCmdInvalidateGBImagePartial;
1303
+
#pragma pack(pop)
1904
1304
1905
-
/*
1906
-
* Readback a sub rect of an image in a guest-backed surface. After
1907
-
* issuing this command the driver is required to issue an update call
1908
-
* of the same region before issuing any other commands that reference
1909
-
* this surface or rendering is not guaranteed.
1910
-
*/
1305
+
#pragma pack(push, 1)
1306
+
typedef struct SVGA3dCmdDefineGBContext {
1307
+
uint32 cid;
1308
+
} SVGA3dCmdDefineGBContext;
1309
+
#pragma pack(pop)
1911
1310
1912
-
typedef
1913
-
#include "vmware_pack_begin.h"
1914
-
struct SVGA3dCmdReadbackGBImagePartial {
1915
-
SVGA3dSurfaceImageId image;
1916
-
SVGA3dBox box;
1917
-
uint32 invertBox;
1918
-
}
1919
-
#include "vmware_pack_end.h"
1920
-
SVGA3dCmdReadbackGBImagePartial; /* SVGA_3D_CMD_READBACK_GB_IMAGE_PARTIAL */
1311
+
#pragma pack(push, 1)
1312
+
typedef struct SVGA3dCmdDestroyGBContext {
1313
+
uint32 cid;
1314
+
} SVGA3dCmdDestroyGBContext;
1315
+
#pragma pack(pop)
1921
1316
1317
+
#pragma pack(push, 1)
1318
+
typedef struct SVGA3dCmdBindGBContext {
1319
+
uint32 cid;
1320
+
SVGAMobId mobid;
1321
+
uint32 validContents;
1322
+
} SVGA3dCmdBindGBContext;
1323
+
#pragma pack(pop)
1922
1324
1923
-
/*
1924
-
* Invalidate an image in a guest-backed surface.
1925
-
* (Notify the device that the contents can be lost.)
1926
-
*/
1325
+
#pragma pack(push, 1)
1326
+
typedef struct SVGA3dCmdReadbackGBContext {
1327
+
uint32 cid;
1328
+
} SVGA3dCmdReadbackGBContext;
1329
+
#pragma pack(pop)
1927
1330
1928
-
typedef
1929
-
#include "vmware_pack_begin.h"
1930
-
struct SVGA3dCmdInvalidateGBImage {
1931
-
SVGA3dSurfaceImageId image;
1932
-
}
1933
-
#include "vmware_pack_end.h"
1934
-
SVGA3dCmdInvalidateGBImage; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE */
1331
+
#pragma pack(push, 1)
1332
+
typedef struct SVGA3dCmdInvalidateGBContext {
1333
+
uint32 cid;
1334
+
} SVGA3dCmdInvalidateGBContext;
1335
+
#pragma pack(pop)
1935
1336
1936
-
/*
1937
-
* Invalidate an entire guest-backed surface.
1938
-
* (Notify the device that the contents if all images can be lost.)
1939
-
*/
1337
+
#pragma pack(push, 1)
1338
+
typedef struct SVGA3dCmdDefineGBShader {
1339
+
uint32 shid;
1340
+
SVGA3dShaderType type;
1341
+
uint32 sizeInBytes;
1342
+
} SVGA3dCmdDefineGBShader;
1343
+
#pragma pack(pop)
1940
1344
1941
-
typedef
1942
-
#include "vmware_pack_begin.h"
1943
-
struct SVGA3dCmdInvalidateGBSurface {
1944
-
uint32 sid;
1945
-
}
1946
-
#include "vmware_pack_end.h"
1947
-
SVGA3dCmdInvalidateGBSurface; /* SVGA_3D_CMD_INVALIDATE_GB_SURFACE */
1345
+
#pragma pack(push, 1)
1346
+
typedef struct SVGA3dCmdBindGBShader {
1347
+
uint32 shid;
1348
+
SVGAMobId mobid;
1349
+
uint32 offsetInBytes;
1350
+
} SVGA3dCmdBindGBShader;
1351
+
#pragma pack(pop)
1948
1352
1949
-
/*
1950
-
* Invalidate a sub rect of an image in a guest-backed surface. After
1951
-
* issuing this command the driver is required to issue an update call
1952
-
* of the same region before issuing any other commands that reference
1953
-
* this surface or rendering is not guaranteed.
1954
-
*/
1353
+
#pragma pack(push, 1)
1354
+
typedef struct SVGA3dCmdDestroyGBShader {
1355
+
uint32 shid;
1356
+
} SVGA3dCmdDestroyGBShader;
1357
+
#pragma pack(pop)
1955
1358
1956
-
typedef
1957
-
#include "vmware_pack_begin.h"
1958
-
struct SVGA3dCmdInvalidateGBImagePartial {
1959
-
SVGA3dSurfaceImageId image;
1960
-
SVGA3dBox box;
1961
-
uint32 invertBox;
1962
-
}
1963
-
#include "vmware_pack_end.h"
1964
-
SVGA3dCmdInvalidateGBImagePartial; /* SVGA_3D_CMD_INVALIDATE_GB_IMAGE_PARTIAL */
1359
+
#pragma pack(push, 1)
1360
+
typedef struct {
1361
+
uint32 cid;
1362
+
uint32 regStart;
1363
+
SVGA3dShaderType shaderType;
1364
+
SVGA3dShaderConstType constType;
1965
1365
1366
+
} SVGA3dCmdSetGBShaderConstInline;
1367
+
#pragma pack(pop)
1966
1368
1967
-
/*
1968
-
* Define a guest-backed context.
1969
-
*/
1369
+
#pragma pack(push, 1)
1370
+
typedef struct {
1371
+
uint32 cid;
1372
+
SVGA3dQueryType type;
1373
+
} SVGA3dCmdBeginGBQuery;
1374
+
#pragma pack(pop)
1970
1375
1971
-
typedef
1972
-
#include "vmware_pack_begin.h"
1973
-
struct SVGA3dCmdDefineGBContext {
1974
-
uint32 cid;
1975
-
}
1976
-
#include "vmware_pack_end.h"
1977
-
SVGA3dCmdDefineGBContext; /* SVGA_3D_CMD_DEFINE_GB_CONTEXT */
1376
+
#pragma pack(push, 1)
1377
+
typedef struct {
1378
+
uint32 cid;
1379
+
SVGA3dQueryType type;
1380
+
SVGAMobId mobid;
1381
+
uint32 offset;
1382
+
} SVGA3dCmdEndGBQuery;
1383
+
#pragma pack(pop)
1978
1384
1979
-
/*
1980
-
* Destroy a guest-backed context.
1981
-
*/
1385
+
#pragma pack(push, 1)
1386
+
typedef struct {
1387
+
uint32 cid;
1388
+
SVGA3dQueryType type;
1389
+
SVGAMobId mobid;
1390
+
uint32 offset;
1391
+
} SVGA3dCmdWaitForGBQuery;
1392
+
#pragma pack(pop)
1982
1393
1983
-
typedef
1984
-
#include "vmware_pack_begin.h"
1985
-
struct SVGA3dCmdDestroyGBContext {
1986
-
uint32 cid;
1987
-
}
1988
-
#include "vmware_pack_end.h"
1989
-
SVGA3dCmdDestroyGBContext; /* SVGA_3D_CMD_DESTROY_GB_CONTEXT */
1394
+
#pragma pack(push, 1)
1395
+
typedef struct {
1396
+
SVGAMobId mobid;
1397
+
uint32 mustBeZero;
1398
+
uint32 initialized;
1399
+
} SVGA3dCmdEnableGart;
1400
+
#pragma pack(pop)
1990
1401
1991
-
/*
1992
-
* Bind a guest-backed context.
1993
-
*
1994
-
* validContents should be set to 0 for new contexts,
1995
-
* and 1 if this is an old context which is getting paged
1996
-
* back on to the device.
1997
-
*
1998
-
* For new contexts, it is recommended that the driver
1999
-
* issue commands to initialize all interesting state
2000
-
* prior to rendering.
2001
-
*/
1402
+
#pragma pack(push, 1)
1403
+
typedef struct {
1404
+
SVGAMobId mobid;
1405
+
uint32 gartOffset;
1406
+
} SVGA3dCmdMapMobIntoGart;
1407
+
#pragma pack(pop)
2002
1408
2003
-
typedef
2004
-
#include "vmware_pack_begin.h"
2005
-
struct SVGA3dCmdBindGBContext {
2006
-
uint32 cid;
2007
-
SVGAMobId mobid;
2008
-
uint32 validContents;
2009
-
}
2010
-
#include "vmware_pack_end.h"
2011
-
SVGA3dCmdBindGBContext; /* SVGA_3D_CMD_BIND_GB_CONTEXT */
1409
+
#pragma pack(push, 1)
1410
+
typedef struct {
1411
+
uint32 gartOffset;
1412
+
uint32 numPages;
1413
+
} SVGA3dCmdUnmapGartRange;
1414
+
#pragma pack(pop)
2012
1415
2013
-
/*
2014
-
* Readback a guest-backed context.
2015
-
* (Request that the device flush the contents back into guest memory.)
2016
-
*/
1416
+
#pragma pack(push, 1)
1417
+
typedef struct {
1418
+
uint32 stid;
1419
+
uint32 width;
1420
+
uint32 height;
1421
+
int32 xRoot;
1422
+
int32 yRoot;
1423
+
SVGAScreenTargetFlags flags;
2017
1424
2018
-
typedef
2019
-
#include "vmware_pack_begin.h"
2020
-
struct SVGA3dCmdReadbackGBContext {
2021
-
uint32 cid;
2022
-
}
2023
-
#include "vmware_pack_end.h"
2024
-
SVGA3dCmdReadbackGBContext; /* SVGA_3D_CMD_READBACK_GB_CONTEXT */
1425
+
uint32 dpi;
1426
+
} SVGA3dCmdDefineGBScreenTarget;
1427
+
#pragma pack(pop)
2025
1428
2026
-
/*
2027
-
* Invalidate a guest-backed context.
2028
-
*/
2029
-
typedef
2030
-
#include "vmware_pack_begin.h"
2031
-
struct SVGA3dCmdInvalidateGBContext {
2032
-
uint32 cid;
2033
-
}
2034
-
#include "vmware_pack_end.h"
2035
-
SVGA3dCmdInvalidateGBContext; /* SVGA_3D_CMD_INVALIDATE_GB_CONTEXT */
1429
+
#pragma pack(push, 1)
1430
+
typedef struct {
1431
+
uint32 stid;
1432
+
} SVGA3dCmdDestroyGBScreenTarget;
1433
+
#pragma pack(pop)
2036
1434
2037
-
/*
2038
-
* Define a guest-backed shader.
2039
-
*/
1435
+
#pragma pack(push, 1)
1436
+
typedef struct {
1437
+
uint32 stid;
1438
+
SVGA3dSurfaceImageId image;
1439
+
} SVGA3dCmdBindGBScreenTarget;
1440
+
#pragma pack(pop)
2040
1441
2041
-
typedef
2042
-
#include "vmware_pack_begin.h"
2043
-
struct SVGA3dCmdDefineGBShader {
2044
-
uint32 shid;
2045
-
SVGA3dShaderType type;
2046
-
uint32 sizeInBytes;
2047
-
}
2048
-
#include "vmware_pack_end.h"
2049
-
SVGA3dCmdDefineGBShader; /* SVGA_3D_CMD_DEFINE_GB_SHADER */
1442
+
#pragma pack(push, 1)
1443
+
typedef struct {
1444
+
uint32 stid;
1445
+
SVGA3dRect rect;
1446
+
} SVGA3dCmdUpdateGBScreenTarget;
1447
+
#pragma pack(pop)
2050
1448
2051
-
/*
2052
-
* Bind a guest-backed shader.
2053
-
*/
1449
+
#pragma pack(push, 1)
1450
+
typedef struct {
1451
+
uint32 stid;
1452
+
SVGA3dRect rect;
1453
+
SVGA3dFrameUpdateType type;
1454
+
} SVGA3dCmdUpdateGBScreenTarget_v2;
1455
+
#pragma pack(pop)
2054
1456
2055
-
typedef
2056
-
#include "vmware_pack_begin.h"
2057
-
struct SVGA3dCmdBindGBShader {
2058
-
uint32 shid;
2059
-
SVGAMobId mobid;
2060
-
uint32 offsetInBytes;
2061
-
}
2062
-
#include "vmware_pack_end.h"
2063
-
SVGA3dCmdBindGBShader; /* SVGA_3D_CMD_BIND_GB_SHADER */
1457
+
#pragma pack(push, 1)
1458
+
typedef struct {
1459
+
uint32 stid;
1460
+
SVGA3dRect rect;
1461
+
SVGA3dFrameUpdateType type;
1462
+
SVGAUnsignedPoint srcPoint;
1463
+
} SVGA3dCmdUpdateGBScreenTargetMove;
1464
+
#pragma pack(pop)
2064
1465
2065
-
/*
2066
-
* Destroy a guest-backed shader.
2067
-
*/
1466
+
#pragma pack(push, 1)
1467
+
typedef struct SVGA3dCmdGBScreenDMA {
1468
+
uint32 screenId;
1469
+
uint32 dead;
1470
+
SVGAMobId destMobID;
1471
+
uint32 destPitch;
1472
+
SVGAMobId changeMapMobID;
1473
+
} SVGA3dCmdGBScreenDMA;
1474
+
#pragma pack(pop)
2068
1475
2069
-
typedef
2070
-
#include "vmware_pack_begin.h"
2071
-
struct SVGA3dCmdDestroyGBShader {
2072
-
uint32 shid;
2073
-
}
2074
-
#include "vmware_pack_end.h"
2075
-
SVGA3dCmdDestroyGBShader; /* SVGA_3D_CMD_DESTROY_GB_SHADER */
1476
+
#pragma pack(push, 1)
1477
+
typedef struct {
1478
+
uint32 value;
1479
+
uint32 mobId;
1480
+
uint32 mobOffset;
1481
+
} SVGA3dCmdGBMobFence;
1482
+
#pragma pack(pop)
2076
1483
2077
-
typedef
2078
-
#include "vmware_pack_begin.h"
2079
-
struct {
2080
-
uint32 cid;
2081
-
uint32 regStart;
2082
-
SVGA3dShaderType shaderType;
2083
-
SVGA3dShaderConstType constType;
1484
+
#pragma pack(push, 1)
1485
+
typedef struct {
1486
+
uint32 stid;
1487
+
SVGA3dSurfaceImageId dest;
2084
1488
2085
-
/*
2086
-
* Followed by a variable number of shader constants.
2087
-
*
2088
-
* Note that FLOAT and INT constants are 4-dwords in length, while
2089
-
* BOOL constants are 1-dword in length.
2090
-
*/
2091
-
}
2092
-
#include "vmware_pack_end.h"
2093
-
SVGA3dCmdSetGBShaderConstInline; /* SVGA_3D_CMD_SET_GB_SHADERCONSTS_INLINE */
1489
+
uint32 statusMobId;
1490
+
uint32 statusMobOffset;
2094
1491
2095
-
2096
-
typedef
2097
-
#include "vmware_pack_begin.h"
2098
-
struct {
2099
-
uint32 cid;
2100
-
SVGA3dQueryType type;
2101
-
}
2102
-
#include "vmware_pack_end.h"
2103
-
SVGA3dCmdBeginGBQuery; /* SVGA_3D_CMD_BEGIN_GB_QUERY */
2104
-
2105
-
typedef
2106
-
#include "vmware_pack_begin.h"
2107
-
struct {
2108
-
uint32 cid;
2109
-
SVGA3dQueryType type;
2110
-
SVGAMobId mobid;
2111
-
uint32 offset;
2112
-
}
2113
-
#include "vmware_pack_end.h"
2114
-
SVGA3dCmdEndGBQuery; /* SVGA_3D_CMD_END_GB_QUERY */
2115
-
2116
-
2117
-
/*
2118
-
* SVGA_3D_CMD_WAIT_FOR_GB_QUERY --
2119
-
*
2120
-
* The semantics of this command are identical to the
2121
-
* SVGA_3D_CMD_WAIT_FOR_QUERY except that the results are written
2122
-
* to a Mob instead of a GMR.
2123
-
*/
2124
-
2125
-
typedef
2126
-
#include "vmware_pack_begin.h"
2127
-
struct {
2128
-
uint32 cid;
2129
-
SVGA3dQueryType type;
2130
-
SVGAMobId mobid;
2131
-
uint32 offset;
2132
-
}
2133
-
#include "vmware_pack_end.h"
2134
-
SVGA3dCmdWaitForGBQuery; /* SVGA_3D_CMD_WAIT_FOR_GB_QUERY */
2135
-
2136
-
2137
-
typedef
2138
-
#include "vmware_pack_begin.h"
2139
-
struct {
2140
-
SVGAMobId mobid;
2141
-
uint32 mustBeZero;
2142
-
uint32 initialized;
2143
-
}
2144
-
#include "vmware_pack_end.h"
2145
-
SVGA3dCmdEnableGart; /* SVGA_3D_CMD_ENABLE_GART */
2146
-
2147
-
typedef
2148
-
#include "vmware_pack_begin.h"
2149
-
struct {
2150
-
SVGAMobId mobid;
2151
-
uint32 gartOffset;
2152
-
}
2153
-
#include "vmware_pack_end.h"
2154
-
SVGA3dCmdMapMobIntoGart; /* SVGA_3D_CMD_MAP_MOB_INTO_GART */
2155
-
2156
-
2157
-
typedef
2158
-
#include "vmware_pack_begin.h"
2159
-
struct {
2160
-
uint32 gartOffset;
2161
-
uint32 numPages;
2162
-
}
2163
-
#include "vmware_pack_end.h"
2164
-
SVGA3dCmdUnmapGartRange; /* SVGA_3D_CMD_UNMAP_GART_RANGE */
2165
-
2166
-
2167
-
/*
2168
-
* Screen Targets
2169
-
*/
2170
-
2171
-
typedef
2172
-
#include "vmware_pack_begin.h"
2173
-
struct {
2174
-
uint32 stid;
2175
-
uint32 width;
2176
-
uint32 height;
2177
-
int32 xRoot;
2178
-
int32 yRoot;
2179
-
SVGAScreenTargetFlags flags;
2180
-
2181
-
/*
2182
-
* The physical DPI that the guest expects this screen displayed at.
2183
-
*
2184
-
* Guests which are not DPI-aware should set this to zero.
2185
-
*/
2186
-
uint32 dpi;
2187
-
}
2188
-
#include "vmware_pack_end.h"
2189
-
SVGA3dCmdDefineGBScreenTarget; /* SVGA_3D_CMD_DEFINE_GB_SCREENTARGET */
2190
-
2191
-
typedef
2192
-
#include "vmware_pack_begin.h"
2193
-
struct {
2194
-
uint32 stid;
2195
-
}
2196
-
#include "vmware_pack_end.h"
2197
-
SVGA3dCmdDestroyGBScreenTarget; /* SVGA_3D_CMD_DESTROY_GB_SCREENTARGET */
2198
-
2199
-
typedef
2200
-
#include "vmware_pack_begin.h"
2201
-
struct {
2202
-
uint32 stid;
2203
-
SVGA3dSurfaceImageId image;
2204
-
}
2205
-
#include "vmware_pack_end.h"
2206
-
SVGA3dCmdBindGBScreenTarget; /* SVGA_3D_CMD_BIND_GB_SCREENTARGET */
2207
-
2208
-
typedef
2209
-
#include "vmware_pack_begin.h"
2210
-
struct {
2211
-
uint32 stid;
2212
-
SVGA3dRect rect;
2213
-
}
2214
-
#include "vmware_pack_end.h"
2215
-
SVGA3dCmdUpdateGBScreenTarget; /* SVGA_3D_CMD_UPDATE_GB_SCREENTARGET */
2216
-
2217
-
typedef
2218
-
#include "vmware_pack_begin.h"
2219
-
struct SVGA3dCmdGBScreenDMA {
2220
-
uint32 screenId;
2221
-
uint32 dead;
2222
-
SVGAMobId destMobID;
2223
-
uint32 destPitch;
2224
-
SVGAMobId changeMapMobID;
2225
-
}
2226
-
#include "vmware_pack_end.h"
2227
-
SVGA3dCmdGBScreenDMA; /* SVGA_3D_CMD_GB_SCREEN_DMA */
2228
-
2229
-
typedef
2230
-
#include "vmware_pack_begin.h"
2231
-
struct {
2232
-
uint32 value;
2233
-
uint32 mobId;
2234
-
uint32 mobOffset;
2235
-
}
2236
-
#include "vmware_pack_end.h"
2237
-
SVGA3dCmdGBMobFence; /* SVGA_3D_CMD_GB_MOB_FENCE */
2238
-
2239
-
typedef
2240
-
#include "vmware_pack_begin.h"
2241
-
struct {
2242
-
uint32 stid;
2243
-
SVGA3dSurfaceImageId dest;
2244
-
2245
-
uint32 statusMobId;
2246
-
uint32 statusMobOffset;
2247
-
2248
-
/* Reserved fields */
2249
-
uint32 mustBeInvalidId;
2250
-
uint32 mustBeZero;
2251
-
}
2252
-
#include "vmware_pack_end.h"
2253
-
SVGA3dCmdScreenCopy; /* SVGA_3D_CMD_SCREEN_COPY */
1492
+
uint32 mustBeInvalidId;
1493
+
uint32 mustBeZero;
1494
+
} SVGA3dCmdScreenCopy;
1495
+
#pragma pack(pop)
2254
1496
2255
1497
#define SVGA_SCREEN_COPY_STATUS_FAILURE 0x00
2256
1498
#define SVGA_SCREEN_COPY_STATUS_SUCCESS 0x01
2257
1499
#define SVGA_SCREEN_COPY_STATUS_INVALID 0xFFFFFFFF
2258
1500
2259
-
typedef
2260
-
#include "vmware_pack_begin.h"
2261
-
struct {
2262
-
uint32 sid;
2263
-
}
2264
-
#include "vmware_pack_end.h"
2265
-
SVGA3dCmdWriteZeroSurface; /* SVGA_3D_CMD_WRITE_ZERO_SURFACE */
1501
+
#pragma pack(push, 1)
1502
+
typedef struct {
1503
+
uint32 sid;
1504
+
} SVGA3dCmdWriteZeroSurface;
1505
+
#pragma pack(pop)
2266
1506
2267
-
typedef
2268
-
#include "vmware_pack_begin.h"
2269
-
struct {
2270
-
uint32 sid;
2271
-
}
2272
-
#include "vmware_pack_end.h"
2273
-
SVGA3dCmdHintZeroSurface; /* SVGA_3D_CMD_HINT_ZERO_SURFACE */
1507
+
#pragma pack(push, 1)
1508
+
typedef struct {
1509
+
uint32 sid;
1510
+
} SVGA3dCmdUpdateZeroSurface;
1511
+
#pragma pack(pop)
2274
1512
2275
-
#endif /* _SVGA3D_CMD_H_ */
1513
+
#endif
+296
-435
drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
+296
-435
drivers/gpu/drm/vmwgfx/device_include/svga3d_devcaps.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 1998-2019 VMware, Inc.
2
+
* Copyright 1998-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_devcaps.h --
29
29
*
30
-
* SVGA 3d caps definitions
30
+
* SVGA 3d caps definitions
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_DEVCAPS_H_
34
36
#define _SVGA3D_DEVCAPS_H_
35
37
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
39
-
40
-
#include "includeCheck.h"
41
-
42
38
#include "svga3d_types.h"
43
39
44
-
/*
45
-
* 3D Hardware Version
46
-
*
47
-
* The hardware version is stored in the SVGA_FIFO_3D_HWVERSION fifo
48
-
* register. Is set by the host and read by the guest. This lets
49
-
* us make new guest drivers which are backwards-compatible with old
50
-
* SVGA hardware revisions. It does not let us support old guest
51
-
* drivers. Good enough for now.
52
-
*
53
-
*/
54
-
55
-
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
56
-
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
57
-
#define SVGA3D_MINOR_HWVERSION(version) ((version) & 0xFF)
40
+
#define SVGA3D_MAKE_HWVERSION(major, minor) (((major) << 16) | ((minor)&0xFF))
41
+
#define SVGA3D_MAJOR_HWVERSION(version) ((version) >> 16)
42
+
#define SVGA3D_MINOR_HWVERSION(version) ((version)&0xFF)
58
43
59
44
typedef enum {
60
-
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
61
-
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
62
-
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
63
-
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
64
-
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
65
-
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
66
-
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
67
-
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
45
+
SVGA3D_HWVERSION_WS5_RC1 = SVGA3D_MAKE_HWVERSION(0, 1),
46
+
SVGA3D_HWVERSION_WS5_RC2 = SVGA3D_MAKE_HWVERSION(0, 2),
47
+
SVGA3D_HWVERSION_WS51_RC1 = SVGA3D_MAKE_HWVERSION(0, 3),
48
+
SVGA3D_HWVERSION_WS6_B1 = SVGA3D_MAKE_HWVERSION(1, 1),
49
+
SVGA3D_HWVERSION_FUSION_11 = SVGA3D_MAKE_HWVERSION(1, 4),
50
+
SVGA3D_HWVERSION_WS65_B1 = SVGA3D_MAKE_HWVERSION(2, 0),
51
+
SVGA3D_HWVERSION_WS8_B1 = SVGA3D_MAKE_HWVERSION(2, 1),
52
+
SVGA3D_HWVERSION_CURRENT = SVGA3D_HWVERSION_WS8_B1,
68
53
} SVGA3dHardwareVersion;
69
-
70
-
/*
71
-
* DevCap indexes.
72
-
*/
73
54
74
55
typedef uint32 SVGA3dDevCapIndex;
75
56
76
-
#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
77
-
#define SVGA3D_DEVCAP_3D 0
78
-
#define SVGA3D_DEVCAP_MAX_LIGHTS 1
57
+
#define SVGA3D_DEVCAP_INVALID ((uint32)-1)
58
+
#define SVGA3D_DEVCAP_3D 0
59
+
#define SVGA3D_DEVCAP_MAX_LIGHTS 1
79
60
80
-
/*
81
-
* SVGA3D_DEVCAP_MAX_TEXTURES reflects the maximum number of
82
-
* fixed-function texture units available. Each of these units
83
-
* work in both FFP and Shader modes, and they support texture
84
-
* transforms and texture coordinates. The host may have additional
85
-
* texture image units that are only usable with shaders.
86
-
*/
87
-
#define SVGA3D_DEVCAP_MAX_TEXTURES 2
88
-
#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
89
-
#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
90
-
#define SVGA3D_DEVCAP_VERTEX_SHADER 5
91
-
#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
92
-
#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
93
-
#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
94
-
#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
95
-
#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
96
-
#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
97
-
#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
98
-
#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
99
-
#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
100
-
#define SVGA3D_DEVCAP_QUERY_TYPES 15
101
-
#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
102
-
#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
103
-
#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
104
-
#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
105
-
#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
106
-
#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
107
-
#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
108
-
#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
109
-
#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
110
-
#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
111
-
#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
112
-
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
113
-
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
114
-
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
115
-
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
116
-
#define SVGA3D_DEVCAP_TEXTURE_OPS 31
117
-
#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
118
-
#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
119
-
#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
120
-
#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
121
-
#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
122
-
#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
123
-
#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
124
-
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
125
-
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
126
-
#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
127
-
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
128
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
129
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
130
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
131
-
#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
132
-
#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
133
-
#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
134
-
#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
135
-
#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
136
-
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
137
-
#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
138
-
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
139
-
#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
140
-
#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
141
-
#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
142
-
#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
143
-
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
144
-
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
145
-
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
146
-
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
61
+
#define SVGA3D_DEVCAP_MAX_TEXTURES 2
62
+
#define SVGA3D_DEVCAP_MAX_CLIP_PLANES 3
63
+
#define SVGA3D_DEVCAP_VERTEX_SHADER_VERSION 4
64
+
#define SVGA3D_DEVCAP_VERTEX_SHADER 5
65
+
#define SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION 6
66
+
#define SVGA3D_DEVCAP_FRAGMENT_SHADER 7
67
+
#define SVGA3D_DEVCAP_MAX_RENDER_TARGETS 8
68
+
#define SVGA3D_DEVCAP_S23E8_TEXTURES 9
69
+
#define SVGA3D_DEVCAP_S10E5_TEXTURES 10
70
+
#define SVGA3D_DEVCAP_MAX_FIXED_VERTEXBLEND 11
71
+
#define SVGA3D_DEVCAP_D16_BUFFER_FORMAT 12
72
+
#define SVGA3D_DEVCAP_D24S8_BUFFER_FORMAT 13
73
+
#define SVGA3D_DEVCAP_D24X8_BUFFER_FORMAT 14
74
+
#define SVGA3D_DEVCAP_QUERY_TYPES 15
75
+
#define SVGA3D_DEVCAP_TEXTURE_GRADIENT_SAMPLING 16
76
+
#define SVGA3D_DEVCAP_MAX_POINT_SIZE 17
77
+
#define SVGA3D_DEVCAP_MAX_SHADER_TEXTURES 18
78
+
#define SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH 19
79
+
#define SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT 20
80
+
#define SVGA3D_DEVCAP_MAX_VOLUME_EXTENT 21
81
+
#define SVGA3D_DEVCAP_MAX_TEXTURE_REPEAT 22
82
+
#define SVGA3D_DEVCAP_MAX_TEXTURE_ASPECT_RATIO 23
83
+
#define SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY 24
84
+
#define SVGA3D_DEVCAP_MAX_PRIMITIVE_COUNT 25
85
+
#define SVGA3D_DEVCAP_MAX_VERTEX_INDEX 26
86
+
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS 27
87
+
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS 28
88
+
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS 29
89
+
#define SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS 30
90
+
#define SVGA3D_DEVCAP_TEXTURE_OPS 31
91
+
#define SVGA3D_DEVCAP_SURFACEFMT_X8R8G8B8 32
92
+
#define SVGA3D_DEVCAP_SURFACEFMT_A8R8G8B8 33
93
+
#define SVGA3D_DEVCAP_SURFACEFMT_A2R10G10B10 34
94
+
#define SVGA3D_DEVCAP_SURFACEFMT_X1R5G5B5 35
95
+
#define SVGA3D_DEVCAP_SURFACEFMT_A1R5G5B5 36
96
+
#define SVGA3D_DEVCAP_SURFACEFMT_A4R4G4B4 37
97
+
#define SVGA3D_DEVCAP_SURFACEFMT_R5G6B5 38
98
+
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE16 39
99
+
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8_ALPHA8 40
100
+
#define SVGA3D_DEVCAP_SURFACEFMT_ALPHA8 41
101
+
#define SVGA3D_DEVCAP_SURFACEFMT_LUMINANCE8 42
102
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D16 43
103
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8 44
104
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24X8 45
105
+
#define SVGA3D_DEVCAP_SURFACEFMT_DXT1 46
106
+
#define SVGA3D_DEVCAP_SURFACEFMT_DXT2 47
107
+
#define SVGA3D_DEVCAP_SURFACEFMT_DXT3 48
108
+
#define SVGA3D_DEVCAP_SURFACEFMT_DXT4 49
109
+
#define SVGA3D_DEVCAP_SURFACEFMT_DXT5 50
110
+
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPX8L8V8U8 51
111
+
#define SVGA3D_DEVCAP_SURFACEFMT_A2W10V10U10 52
112
+
#define SVGA3D_DEVCAP_SURFACEFMT_BUMPU8V8 53
113
+
#define SVGA3D_DEVCAP_SURFACEFMT_Q8W8V8U8 54
114
+
#define SVGA3D_DEVCAP_SURFACEFMT_CxV8U8 55
115
+
#define SVGA3D_DEVCAP_SURFACEFMT_R_S10E5 56
116
+
#define SVGA3D_DEVCAP_SURFACEFMT_R_S23E8 57
117
+
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S10E5 58
118
+
#define SVGA3D_DEVCAP_SURFACEFMT_RG_S23E8 59
119
+
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S10E5 60
120
+
#define SVGA3D_DEVCAP_SURFACEFMT_ARGB_S23E8 61
147
121
148
-
/*
149
-
* There is a hole in our devcap definitions for
150
-
* historical reasons.
151
-
*
152
-
* Define a constant just for completeness.
153
-
*/
154
-
#define SVGA3D_DEVCAP_MISSING62 62
122
+
#define SVGA3D_DEVCAP_MISSING62 62
155
123
156
-
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
124
+
#define SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEXTURES 63
157
125
158
-
/*
159
-
* Note that MAX_SIMULTANEOUS_RENDER_TARGETS is a maximum count of color
160
-
* render targets. This does not include the depth or stencil targets.
161
-
*/
162
-
#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
126
+
#define SVGA3D_DEVCAP_MAX_SIMULTANEOUS_RENDER_TARGETS 64
163
127
164
-
#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
165
-
#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
166
-
#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
167
-
#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
168
-
#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
128
+
#define SVGA3D_DEVCAP_SURFACEFMT_V16U16 65
129
+
#define SVGA3D_DEVCAP_SURFACEFMT_G16R16 66
130
+
#define SVGA3D_DEVCAP_SURFACEFMT_A16B16G16R16 67
131
+
#define SVGA3D_DEVCAP_SURFACEFMT_UYVY 68
132
+
#define SVGA3D_DEVCAP_SURFACEFMT_YUY2 69
169
133
170
-
/*
171
-
* Deprecated.
172
-
*/
173
-
#define SVGA3D_DEVCAP_DEAD4 70
174
-
#define SVGA3D_DEVCAP_DEAD5 71
175
-
#define SVGA3D_DEVCAP_DEAD7 72
176
-
#define SVGA3D_DEVCAP_DEAD6 73
134
+
#define SVGA3D_DEVCAP_DEAD4 70
135
+
#define SVGA3D_DEVCAP_DEAD5 71
136
+
#define SVGA3D_DEVCAP_DEAD7 72
137
+
#define SVGA3D_DEVCAP_DEAD6 73
177
138
178
-
#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
179
-
#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
180
-
#define SVGA3D_DEVCAP_DEAD10 76
139
+
#define SVGA3D_DEVCAP_AUTOGENMIPMAPS 74
140
+
#define SVGA3D_DEVCAP_SURFACEFMT_NV12 75
141
+
#define SVGA3D_DEVCAP_DEAD10 76
181
142
182
-
/*
183
-
* This is the maximum number of SVGA context IDs that the guest
184
-
* can define using SVGA_3D_CMD_CONTEXT_DEFINE.
185
-
*/
186
-
#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
143
+
#define SVGA3D_DEVCAP_MAX_CONTEXT_IDS 77
187
144
188
-
/*
189
-
* This is the maximum number of SVGA surface IDs that the guest
190
-
* can define using SVGA_3D_CMD_SURFACE_DEFINE*.
191
-
*/
192
-
#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
145
+
#define SVGA3D_DEVCAP_MAX_SURFACE_IDS 78
193
146
194
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
195
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
196
-
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
147
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF16 79
148
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_DF24 80
149
+
#define SVGA3D_DEVCAP_SURFACEFMT_Z_D24S8_INT 81
197
150
198
-
#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
199
-
#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
151
+
#define SVGA3D_DEVCAP_SURFACEFMT_ATI1 82
152
+
#define SVGA3D_DEVCAP_SURFACEFMT_ATI2 83
200
153
201
-
/*
202
-
* Deprecated.
203
-
*/
204
-
#define SVGA3D_DEVCAP_DEAD1 84
205
-
#define SVGA3D_DEVCAP_DEAD8 85
206
-
#define SVGA3D_DEVCAP_DEAD9 86
154
+
#define SVGA3D_DEVCAP_DEAD1 84
155
+
#define SVGA3D_DEVCAP_DEAD8 85
156
+
#define SVGA3D_DEVCAP_DEAD9 86
207
157
208
-
#define SVGA3D_DEVCAP_LINE_AA 87 /* boolean */
209
-
#define SVGA3D_DEVCAP_LINE_STIPPLE 88 /* boolean */
210
-
#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89 /* float */
211
-
#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90 /* float */
158
+
#define SVGA3D_DEVCAP_LINE_AA 87
159
+
#define SVGA3D_DEVCAP_LINE_STIPPLE 88
160
+
#define SVGA3D_DEVCAP_MAX_LINE_WIDTH 89
161
+
#define SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH 90
212
162
213
-
#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
163
+
#define SVGA3D_DEVCAP_SURFACEFMT_YV12 91
214
164
215
-
/*
216
-
* Deprecated.
217
-
*/
218
-
#define SVGA3D_DEVCAP_DEAD3 92
165
+
#define SVGA3D_DEVCAP_DEAD3 92
219
166
220
-
/*
221
-
* Are TS_CONSTANT, TS_COLOR_KEY, and TS_COLOR_KEY_ENABLE supported?
222
-
*/
223
-
#define SVGA3D_DEVCAP_TS_COLOR_KEY 93 /* boolean */
167
+
#define SVGA3D_DEVCAP_TS_COLOR_KEY 93
224
168
225
-
/*
226
-
* Deprecated.
227
-
*/
228
-
#define SVGA3D_DEVCAP_DEAD2 94
169
+
#define SVGA3D_DEVCAP_DEAD2 94
229
170
230
-
/*
231
-
* Does the device support DXContexts?
232
-
*/
233
-
#define SVGA3D_DEVCAP_DXCONTEXT 95
171
+
#define SVGA3D_DEVCAP_DXCONTEXT 95
234
172
235
-
/*
236
-
* Deprecated.
237
-
*/
238
-
#define SVGA3D_DEVCAP_DEAD11 96
173
+
#define SVGA3D_DEVCAP_DEAD11 96
239
174
240
-
/*
241
-
* What is the maximum number of vertex buffers or vertex input registers
242
-
* that can be expected to work correctly with a DXContext?
243
-
*
244
-
* The guest is allowed to set up to SVGA3D_DX_MAX_VERTEXBUFFERS, but
245
-
* anything in excess of this cap is not guaranteed to render correctly.
246
-
*
247
-
* Similarly, the guest can set up to SVGA3D_DX_MAX_VERTEXINPUTREGISTERS
248
-
* input registers without the SVGA3D_DEVCAP_SM4_1 cap, or
249
-
* SVGA3D_DX_SM41_MAX_VERTEXINPUTREGISTERS with the SVGA3D_DEVCAP_SM4_1,
250
-
* but only the registers up to this cap value are guaranteed to render
251
-
* correctly.
252
-
*
253
-
* If guest-drivers are able to expose a lower-limit, it's recommended
254
-
* that they clamp to this value. Otherwise, the host will make a
255
-
* best-effort on case-by-case basis if guests exceed this.
256
-
*/
257
-
#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
175
+
#define SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS 97
258
176
259
-
/*
260
-
* What is the maximum number of constant buffers that can be expected to
261
-
* work correctly with a DX context?
262
-
*
263
-
* The guest is allowed to set up to SVGA3D_DX_MAX_CONSTBUFFERS, but
264
-
* anything in excess of this cap is not guaranteed to render correctly.
265
-
*
266
-
* If guest-drivers are able to expose a lower-limit, it's recommended
267
-
* that they clamp to this value. Otherwise, the host will make a
268
-
* best-effort on case-by-case basis if guests exceed this.
269
-
*/
270
-
#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
177
+
#define SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS 98
271
178
272
-
/*
273
-
* Does the device support provoking vertex control?
274
-
*
275
-
* If this cap is present, the provokingVertexLast field in the
276
-
* rasterizer state is enabled. (Guests can then set it to FALSE,
277
-
* meaning that the first vertex is the provoking vertex, or TRUE,
278
-
* meaning that the last verteix is the provoking vertex.)
279
-
*
280
-
* If this cap is FALSE, then guests should set the provokingVertexLast
281
-
* to FALSE, otherwise rendering behavior is undefined.
282
-
*/
283
-
#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
179
+
#define SVGA3D_DEVCAP_DX_PROVOKING_VERTEX 99
284
180
285
-
#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
286
-
#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
287
-
#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
288
-
#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
289
-
#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
290
-
#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
291
-
#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
292
-
#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
293
-
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
294
-
#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
295
-
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
296
-
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
297
-
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
298
-
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
299
-
#define SVGA3D_DEVCAP_DXFMT_DXT1 114
300
-
#define SVGA3D_DEVCAP_DXFMT_DXT2 115
301
-
#define SVGA3D_DEVCAP_DXFMT_DXT3 116
302
-
#define SVGA3D_DEVCAP_DXFMT_DXT4 117
303
-
#define SVGA3D_DEVCAP_DXFMT_DXT5 118
304
-
#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
305
-
#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
306
-
#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
307
-
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
308
-
#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
309
-
#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
310
-
#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
311
-
#define SVGA3D_DEVCAP_DXFMT_V8U8 126
312
-
#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
313
-
#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
314
-
#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
315
-
#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
316
-
#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
317
-
#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
318
-
#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
319
-
#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
320
-
#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
321
-
#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
322
-
#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
323
-
#define SVGA3D_DEVCAP_DXFMT_V16U16 138
324
-
#define SVGA3D_DEVCAP_DXFMT_G16R16 139
325
-
#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
326
-
#define SVGA3D_DEVCAP_DXFMT_UYVY 141
327
-
#define SVGA3D_DEVCAP_DXFMT_YUY2 142
328
-
#define SVGA3D_DEVCAP_DXFMT_NV12 143
329
-
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
330
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
331
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
332
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
333
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
334
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
335
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
336
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
337
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
338
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
339
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
340
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
341
-
#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
342
-
#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
343
-
#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
344
-
#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
345
-
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
346
-
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
347
-
#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
348
-
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
349
-
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
350
-
#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
351
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
352
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
353
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
354
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
355
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
356
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
357
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
358
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
359
-
#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
360
-
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
361
-
#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
362
-
#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
363
-
#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
364
-
#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
365
-
#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
366
-
#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
367
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
368
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
369
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
370
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
371
-
#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
372
-
#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
373
-
#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
374
-
#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
375
-
#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
376
-
#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
377
-
#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
378
-
#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
379
-
#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
380
-
#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
381
-
#define SVGA3D_DEVCAP_DXFMT_P8 196
382
-
#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
383
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
384
-
#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
385
-
#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
386
-
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
387
-
#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
388
-
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
389
-
#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
390
-
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
391
-
#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
392
-
#define SVGA3D_DEVCAP_DXFMT_ATI1 207
393
-
#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
394
-
#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
395
-
#define SVGA3D_DEVCAP_DXFMT_ATI2 210
396
-
#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
397
-
#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
398
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
399
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
400
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
401
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
402
-
#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
403
-
#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
404
-
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
405
-
#define SVGA3D_DEVCAP_DXFMT_YV12 220
406
-
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
407
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
408
-
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
409
-
#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
410
-
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
411
-
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
412
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
413
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
414
-
#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
415
-
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
416
-
#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
417
-
#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
418
-
#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
419
-
#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
420
-
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
421
-
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
422
-
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
423
-
#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
424
-
#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
425
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
426
-
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
427
-
#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
428
-
#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
181
+
#define SVGA3D_DEVCAP_DXFMT_X8R8G8B8 100
182
+
#define SVGA3D_DEVCAP_DXFMT_A8R8G8B8 101
183
+
#define SVGA3D_DEVCAP_DXFMT_R5G6B5 102
184
+
#define SVGA3D_DEVCAP_DXFMT_X1R5G5B5 103
185
+
#define SVGA3D_DEVCAP_DXFMT_A1R5G5B5 104
186
+
#define SVGA3D_DEVCAP_DXFMT_A4R4G4B4 105
187
+
#define SVGA3D_DEVCAP_DXFMT_Z_D32 106
188
+
#define SVGA3D_DEVCAP_DXFMT_Z_D16 107
189
+
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8 108
190
+
#define SVGA3D_DEVCAP_DXFMT_Z_D15S1 109
191
+
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8 110
192
+
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE4_ALPHA4 111
193
+
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE16 112
194
+
#define SVGA3D_DEVCAP_DXFMT_LUMINANCE8_ALPHA8 113
195
+
#define SVGA3D_DEVCAP_DXFMT_DXT1 114
196
+
#define SVGA3D_DEVCAP_DXFMT_DXT2 115
197
+
#define SVGA3D_DEVCAP_DXFMT_DXT3 116
198
+
#define SVGA3D_DEVCAP_DXFMT_DXT4 117
199
+
#define SVGA3D_DEVCAP_DXFMT_DXT5 118
200
+
#define SVGA3D_DEVCAP_DXFMT_BUMPU8V8 119
201
+
#define SVGA3D_DEVCAP_DXFMT_BUMPL6V5U5 120
202
+
#define SVGA3D_DEVCAP_DXFMT_BUMPX8L8V8U8 121
203
+
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD1 122
204
+
#define SVGA3D_DEVCAP_DXFMT_ARGB_S10E5 123
205
+
#define SVGA3D_DEVCAP_DXFMT_ARGB_S23E8 124
206
+
#define SVGA3D_DEVCAP_DXFMT_A2R10G10B10 125
207
+
#define SVGA3D_DEVCAP_DXFMT_V8U8 126
208
+
#define SVGA3D_DEVCAP_DXFMT_Q8W8V8U8 127
209
+
#define SVGA3D_DEVCAP_DXFMT_CxV8U8 128
210
+
#define SVGA3D_DEVCAP_DXFMT_X8L8V8U8 129
211
+
#define SVGA3D_DEVCAP_DXFMT_A2W10V10U10 130
212
+
#define SVGA3D_DEVCAP_DXFMT_ALPHA8 131
213
+
#define SVGA3D_DEVCAP_DXFMT_R_S10E5 132
214
+
#define SVGA3D_DEVCAP_DXFMT_R_S23E8 133
215
+
#define SVGA3D_DEVCAP_DXFMT_RG_S10E5 134
216
+
#define SVGA3D_DEVCAP_DXFMT_RG_S23E8 135
217
+
#define SVGA3D_DEVCAP_DXFMT_BUFFER 136
218
+
#define SVGA3D_DEVCAP_DXFMT_Z_D24X8 137
219
+
#define SVGA3D_DEVCAP_DXFMT_V16U16 138
220
+
#define SVGA3D_DEVCAP_DXFMT_G16R16 139
221
+
#define SVGA3D_DEVCAP_DXFMT_A16B16G16R16 140
222
+
#define SVGA3D_DEVCAP_DXFMT_UYVY 141
223
+
#define SVGA3D_DEVCAP_DXFMT_YUY2 142
224
+
#define SVGA3D_DEVCAP_DXFMT_NV12 143
225
+
#define SVGA3D_DEVCAP_DXFMT_FORMAT_DEAD2 144
226
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_TYPELESS 145
227
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_UINT 146
228
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_SINT 147
229
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_TYPELESS 148
230
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_FLOAT 149
231
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_UINT 150
232
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32_SINT 151
233
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_TYPELESS 152
234
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UINT 153
235
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SNORM 154
236
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_SINT 155
237
+
#define SVGA3D_DEVCAP_DXFMT_R32G32_TYPELESS 156
238
+
#define SVGA3D_DEVCAP_DXFMT_R32G32_UINT 157
239
+
#define SVGA3D_DEVCAP_DXFMT_R32G32_SINT 158
240
+
#define SVGA3D_DEVCAP_DXFMT_R32G8X24_TYPELESS 159
241
+
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT_S8X24_UINT 160
242
+
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT_X8X24 161
243
+
#define SVGA3D_DEVCAP_DXFMT_X32_G8X24_UINT 162
244
+
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_TYPELESS 163
245
+
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UINT 164
246
+
#define SVGA3D_DEVCAP_DXFMT_R11G11B10_FLOAT 165
247
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_TYPELESS 166
248
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM 167
249
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UNORM_SRGB 168
250
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_UINT 169
251
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SINT 170
252
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_TYPELESS 171
253
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_UINT 172
254
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_SINT 173
255
+
#define SVGA3D_DEVCAP_DXFMT_R32_TYPELESS 174
256
+
#define SVGA3D_DEVCAP_DXFMT_D32_FLOAT 175
257
+
#define SVGA3D_DEVCAP_DXFMT_R32_UINT 176
258
+
#define SVGA3D_DEVCAP_DXFMT_R32_SINT 177
259
+
#define SVGA3D_DEVCAP_DXFMT_R24G8_TYPELESS 178
260
+
#define SVGA3D_DEVCAP_DXFMT_D24_UNORM_S8_UINT 179
261
+
#define SVGA3D_DEVCAP_DXFMT_R24_UNORM_X8 180
262
+
#define SVGA3D_DEVCAP_DXFMT_X24_G8_UINT 181
263
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_TYPELESS 182
264
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_UNORM 183
265
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_UINT 184
266
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_SINT 185
267
+
#define SVGA3D_DEVCAP_DXFMT_R16_TYPELESS 186
268
+
#define SVGA3D_DEVCAP_DXFMT_R16_UNORM 187
269
+
#define SVGA3D_DEVCAP_DXFMT_R16_UINT 188
270
+
#define SVGA3D_DEVCAP_DXFMT_R16_SNORM 189
271
+
#define SVGA3D_DEVCAP_DXFMT_R16_SINT 190
272
+
#define SVGA3D_DEVCAP_DXFMT_R8_TYPELESS 191
273
+
#define SVGA3D_DEVCAP_DXFMT_R8_UNORM 192
274
+
#define SVGA3D_DEVCAP_DXFMT_R8_UINT 193
275
+
#define SVGA3D_DEVCAP_DXFMT_R8_SNORM 194
276
+
#define SVGA3D_DEVCAP_DXFMT_R8_SINT 195
277
+
#define SVGA3D_DEVCAP_DXFMT_P8 196
278
+
#define SVGA3D_DEVCAP_DXFMT_R9G9B9E5_SHAREDEXP 197
279
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_B8G8_UNORM 198
280
+
#define SVGA3D_DEVCAP_DXFMT_G8R8_G8B8_UNORM 199
281
+
#define SVGA3D_DEVCAP_DXFMT_BC1_TYPELESS 200
282
+
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM_SRGB 201
283
+
#define SVGA3D_DEVCAP_DXFMT_BC2_TYPELESS 202
284
+
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM_SRGB 203
285
+
#define SVGA3D_DEVCAP_DXFMT_BC3_TYPELESS 204
286
+
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM_SRGB 205
287
+
#define SVGA3D_DEVCAP_DXFMT_BC4_TYPELESS 206
288
+
#define SVGA3D_DEVCAP_DXFMT_ATI1 207
289
+
#define SVGA3D_DEVCAP_DXFMT_BC4_SNORM 208
290
+
#define SVGA3D_DEVCAP_DXFMT_BC5_TYPELESS 209
291
+
#define SVGA3D_DEVCAP_DXFMT_ATI2 210
292
+
#define SVGA3D_DEVCAP_DXFMT_BC5_SNORM 211
293
+
#define SVGA3D_DEVCAP_DXFMT_R10G10B10_XR_BIAS_A2_UNORM 212
294
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_TYPELESS 213
295
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM_SRGB 214
296
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_TYPELESS 215
297
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM_SRGB 216
298
+
#define SVGA3D_DEVCAP_DXFMT_Z_DF16 217
299
+
#define SVGA3D_DEVCAP_DXFMT_Z_DF24 218
300
+
#define SVGA3D_DEVCAP_DXFMT_Z_D24S8_INT 219
301
+
#define SVGA3D_DEVCAP_DXFMT_YV12 220
302
+
#define SVGA3D_DEVCAP_DXFMT_R32G32B32A32_FLOAT 221
303
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_FLOAT 222
304
+
#define SVGA3D_DEVCAP_DXFMT_R16G16B16A16_UNORM 223
305
+
#define SVGA3D_DEVCAP_DXFMT_R32G32_FLOAT 224
306
+
#define SVGA3D_DEVCAP_DXFMT_R10G10B10A2_UNORM 225
307
+
#define SVGA3D_DEVCAP_DXFMT_R8G8B8A8_SNORM 226
308
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_FLOAT 227
309
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_UNORM 228
310
+
#define SVGA3D_DEVCAP_DXFMT_R16G16_SNORM 229
311
+
#define SVGA3D_DEVCAP_DXFMT_R32_FLOAT 230
312
+
#define SVGA3D_DEVCAP_DXFMT_R8G8_SNORM 231
313
+
#define SVGA3D_DEVCAP_DXFMT_R16_FLOAT 232
314
+
#define SVGA3D_DEVCAP_DXFMT_D16_UNORM 233
315
+
#define SVGA3D_DEVCAP_DXFMT_A8_UNORM 234
316
+
#define SVGA3D_DEVCAP_DXFMT_BC1_UNORM 235
317
+
#define SVGA3D_DEVCAP_DXFMT_BC2_UNORM 236
318
+
#define SVGA3D_DEVCAP_DXFMT_BC3_UNORM 237
319
+
#define SVGA3D_DEVCAP_DXFMT_B5G6R5_UNORM 238
320
+
#define SVGA3D_DEVCAP_DXFMT_B5G5R5A1_UNORM 239
321
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8A8_UNORM 240
322
+
#define SVGA3D_DEVCAP_DXFMT_B8G8R8X8_UNORM 241
323
+
#define SVGA3D_DEVCAP_DXFMT_BC4_UNORM 242
324
+
#define SVGA3D_DEVCAP_DXFMT_BC5_UNORM 243
429
325
430
-
/*
431
-
* Advertises shaderModel 4.1 support, independent blend-states,
432
-
* cube-map arrays, and a higher vertex input registers limit.
433
-
*
434
-
* (See documentation on SVGA3D_DEVCAP_DX_MAX_VERTEXBUFFERS.)
435
-
*/
436
-
#define SVGA3D_DEVCAP_SM41 244
437
-
#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
438
-
#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
326
+
#define SVGA3D_DEVCAP_SM41 244
327
+
#define SVGA3D_DEVCAP_MULTISAMPLE_2X 245
328
+
#define SVGA3D_DEVCAP_MULTISAMPLE_4X 246
439
329
440
-
/*
441
-
* Indicates that the device has rendering support for
442
-
* the full multisample quality. If this cap is not present,
443
-
* the host may or may not support full quality rendering.
444
-
*
445
-
* See also SVGA_REG_MS_HINT_RESOLVED.
446
-
*/
447
-
#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
330
+
#define SVGA3D_DEVCAP_MS_FULL_QUALITY 247
448
331
449
-
/*
450
-
* Advertises support for the SVGA3D LogicOps commands.
451
-
*/
452
-
#define SVGA3D_DEVCAP_LOGICOPS 248
332
+
#define SVGA3D_DEVCAP_LOGICOPS 248
453
333
454
-
/*
455
-
* Advertises support for using logicOps in the DXBlendStates.
456
-
*/
457
-
#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
334
+
#define SVGA3D_DEVCAP_LOGIC_BLENDOPS 249
458
335
459
-
/*
460
-
* Note DXFMT range is now non-contiguous.
461
-
*/
462
-
#define SVGA3D_DEVCAP_RESERVED_1 250
463
-
#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
464
-
#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
465
-
#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
466
-
#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
467
-
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
468
-
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
469
-
#define SVGA3D_DEVCAP_RESERVED_2 257
336
+
#define SVGA3D_DEVCAP_DEAD12 250
470
337
471
-
#define SVGA3D_DEVCAP_SM5 258
472
-
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
338
+
#define SVGA3D_DEVCAP_DXFMT_BC6H_TYPELESS 251
339
+
#define SVGA3D_DEVCAP_DXFMT_BC6H_UF16 252
340
+
#define SVGA3D_DEVCAP_DXFMT_BC6H_SF16 253
341
+
#define SVGA3D_DEVCAP_DXFMT_BC7_TYPELESS 254
342
+
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM 255
343
+
#define SVGA3D_DEVCAP_DXFMT_BC7_UNORM_SRGB 256
473
344
474
-
/* This must be the last index. */
475
-
#define SVGA3D_DEVCAP_MAX 260
345
+
#define SVGA3D_DEVCAP_DEAD13 257
476
346
477
-
/*
478
-
* Bit definitions for DXFMT devcaps
479
-
*
480
-
*
481
-
* SUPPORTED: Can the format be defined?
482
-
* SHADER_SAMPLE: Can the format be sampled from a shader?
483
-
* COLOR_RENDERTARGET: Can the format be a color render target?
484
-
* DEPTH_RENDERTARGET: Can the format be a depth render target?
485
-
* BLENDABLE: Is the format blendable?
486
-
* MIPS: Does the format support mip levels?
487
-
* ARRAY: Does the format support texture arrays?
488
-
* VOLUME: Does the format support having volume?
489
-
* MULTISAMPLE: Does the format support multisample?
490
-
*/
491
-
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
492
-
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
493
-
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
494
-
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
495
-
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
496
-
#define SVGA3D_DXFMT_MIPS (1 << 5)
497
-
#define SVGA3D_DXFMT_ARRAY (1 << 6)
498
-
#define SVGA3D_DXFMT_VOLUME (1 << 7)
499
-
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
500
-
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
501
-
#define SVGA3D_DXFMT_MAX (1 << 10)
347
+
#define SVGA3D_DEVCAP_SM5 258
348
+
#define SVGA3D_DEVCAP_MULTISAMPLE_8X 259
349
+
350
+
#define SVGA3D_DEVCAP_MAX 262
351
+
352
+
#define SVGA3D_DXFMT_SUPPORTED (1 << 0)
353
+
#define SVGA3D_DXFMT_SHADER_SAMPLE (1 << 1)
354
+
#define SVGA3D_DXFMT_COLOR_RENDERTARGET (1 << 2)
355
+
#define SVGA3D_DXFMT_DEPTH_RENDERTARGET (1 << 3)
356
+
#define SVGA3D_DXFMT_BLENDABLE (1 << 4)
357
+
#define SVGA3D_DXFMT_MIPS (1 << 5)
358
+
#define SVGA3D_DXFMT_ARRAY (1 << 6)
359
+
#define SVGA3D_DXFMT_VOLUME (1 << 7)
360
+
#define SVGA3D_DXFMT_DX_VERTEX_BUFFER (1 << 8)
361
+
#define SVGA3D_DXFMT_MULTISAMPLE (1 << 9)
362
+
#define SVGA3D_DXFMT_MAX (1 << 10)
502
363
503
364
typedef union {
504
-
SVGA3dBool b;
505
-
uint32 u;
506
-
int32 i;
507
-
float f;
365
+
SVGA3dBool b;
366
+
uint32 u;
367
+
int32 i;
368
+
float f;
508
369
} SVGA3dDevCapResult;
509
370
510
-
#endif /* _SVGA3D_DEVCAPS_H_ */
371
+
#endif
+1413
-1756
drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
+1413
-1756
drivers/gpu/drm/vmwgfx/device_include/svga3d_dx.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 2012-2019 VMware, Inc.
2
+
* Copyright 2012-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_dx.h --
29
29
*
30
-
* SVGA 3d hardware definitions for DX10 support.
30
+
* SVGA 3d hardware definitions for DX10 support.
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_DX_H_
34
36
#define _SVGA3D_DX_H_
35
37
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
39
-
#include "includeCheck.h"
40
-
38
+
#include "svga_reg.h"
41
39
#include "svga3d_limits.h"
40
+
#include "svga3d_types.h"
42
41
43
-
#define SVGA3D_INPUT_MIN 0
44
-
#define SVGA3D_INPUT_PER_VERTEX_DATA 0
42
+
#define SVGA3D_INPUT_MIN 0
43
+
#define SVGA3D_INPUT_PER_VERTEX_DATA 0
45
44
#define SVGA3D_INPUT_PER_INSTANCE_DATA 1
46
-
#define SVGA3D_INPUT_MAX 2
45
+
#define SVGA3D_INPUT_MAX 2
47
46
typedef uint32 SVGA3dInputClassification;
48
47
49
-
#define SVGA3D_RESOURCE_TYPE_MIN 1
50
-
#define SVGA3D_RESOURCE_BUFFER 1
51
-
#define SVGA3D_RESOURCE_TEXTURE1D 2
52
-
#define SVGA3D_RESOURCE_TEXTURE2D 3
53
-
#define SVGA3D_RESOURCE_TEXTURE3D 4
54
-
#define SVGA3D_RESOURCE_TEXTURECUBE 5
55
-
#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
56
-
#define SVGA3D_RESOURCE_BUFFEREX 6
57
-
#define SVGA3D_RESOURCE_TYPE_MAX 7
58
-
typedef uint32 SVGA3dResourceType;
59
-
60
-
#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
61
-
#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
62
-
#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
63
-
#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
64
-
#define SVGA3D_COLOR_WRITE_ENABLE_ALL (SVGA3D_COLOR_WRITE_ENABLE_RED | \
65
-
SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
66
-
SVGA3D_COLOR_WRITE_ENABLE_BLUE | \
67
-
SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
48
+
#define SVGA3D_COLOR_WRITE_ENABLE_RED (1 << 0)
49
+
#define SVGA3D_COLOR_WRITE_ENABLE_GREEN (1 << 1)
50
+
#define SVGA3D_COLOR_WRITE_ENABLE_BLUE (1 << 2)
51
+
#define SVGA3D_COLOR_WRITE_ENABLE_ALPHA (1 << 3)
52
+
#define SVGA3D_COLOR_WRITE_ENABLE_ALL \
53
+
(SVGA3D_COLOR_WRITE_ENABLE_RED | SVGA3D_COLOR_WRITE_ENABLE_GREEN | \
54
+
SVGA3D_COLOR_WRITE_ENABLE_BLUE | SVGA3D_COLOR_WRITE_ENABLE_ALPHA)
68
55
typedef uint8 SVGA3dColorWriteEnable;
69
56
70
-
#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
71
-
#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
57
+
#define SVGA3D_DEPTH_WRITE_MASK_ZERO 0
58
+
#define SVGA3D_DEPTH_WRITE_MASK_ALL 1
72
59
typedef uint8 SVGA3dDepthWriteMask;
73
60
74
-
#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
75
-
#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
76
-
#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
61
+
#define SVGA3D_FILTER_MIP_LINEAR (1 << 0)
62
+
#define SVGA3D_FILTER_MAG_LINEAR (1 << 2)
63
+
#define SVGA3D_FILTER_MIN_LINEAR (1 << 4)
77
64
#define SVGA3D_FILTER_ANISOTROPIC (1 << 6)
78
-
#define SVGA3D_FILTER_COMPARE (1 << 7)
65
+
#define SVGA3D_FILTER_COMPARE (1 << 7)
79
66
typedef uint32 SVGA3dFilter;
80
67
81
68
#define SVGA3D_CULL_INVALID 0
82
-
#define SVGA3D_CULL_MIN 1
83
-
#define SVGA3D_CULL_NONE 1
84
-
#define SVGA3D_CULL_FRONT 2
85
-
#define SVGA3D_CULL_BACK 3
86
-
#define SVGA3D_CULL_MAX 4
69
+
#define SVGA3D_CULL_MIN 1
70
+
#define SVGA3D_CULL_NONE 1
71
+
#define SVGA3D_CULL_FRONT 2
72
+
#define SVGA3D_CULL_BACK 3
73
+
#define SVGA3D_CULL_MAX 4
87
74
typedef uint8 SVGA3dCullMode;
88
75
89
-
#define SVGA3D_COMPARISON_INVALID 0
90
-
#define SVGA3D_COMPARISON_MIN 1
91
-
#define SVGA3D_COMPARISON_NEVER 1
92
-
#define SVGA3D_COMPARISON_LESS 2
93
-
#define SVGA3D_COMPARISON_EQUAL 3
94
-
#define SVGA3D_COMPARISON_LESS_EQUAL 4
95
-
#define SVGA3D_COMPARISON_GREATER 5
96
-
#define SVGA3D_COMPARISON_NOT_EQUAL 6
97
-
#define SVGA3D_COMPARISON_GREATER_EQUAL 7
98
-
#define SVGA3D_COMPARISON_ALWAYS 8
99
-
#define SVGA3D_COMPARISON_MAX 9
76
+
#define SVGA3D_COMPARISON_INVALID 0
77
+
#define SVGA3D_COMPARISON_MIN 1
78
+
#define SVGA3D_COMPARISON_NEVER 1
79
+
#define SVGA3D_COMPARISON_LESS 2
80
+
#define SVGA3D_COMPARISON_EQUAL 3
81
+
#define SVGA3D_COMPARISON_LESS_EQUAL 4
82
+
#define SVGA3D_COMPARISON_GREATER 5
83
+
#define SVGA3D_COMPARISON_NOT_EQUAL 6
84
+
#define SVGA3D_COMPARISON_GREATER_EQUAL 7
85
+
#define SVGA3D_COMPARISON_ALWAYS 8
86
+
#define SVGA3D_COMPARISON_MAX 9
100
87
typedef uint8 SVGA3dComparisonFunc;
101
88
102
-
/*
103
-
* SVGA3D_MULTISAMPLE_RAST_DISABLE disables MSAA for all primitives.
104
-
* SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE, which is supported in SM41,
105
-
* disables MSAA for lines only.
106
-
*/
107
-
#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
108
-
#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
109
-
#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
110
-
#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
111
-
#define SVGA3D_MULTISAMPLE_RAST_MAX 2
89
+
#define SVGA3D_MULTISAMPLE_RAST_DISABLE 0
90
+
#define SVGA3D_MULTISAMPLE_RAST_ENABLE 1
91
+
#define SVGA3D_MULTISAMPLE_RAST_DX_MAX 1
92
+
#define SVGA3D_MULTISAMPLE_RAST_DISABLE_LINE 2
93
+
#define SVGA3D_MULTISAMPLE_RAST_MAX 2
112
94
typedef uint8 SVGA3dMultisampleRastEnable;
113
95
114
96
#define SVGA3D_DX_MAX_VERTEXBUFFERS 32
···
119
137
typedef uint32 SVGA3dStreamOutputId;
120
138
121
139
typedef union {
122
-
struct {
123
-
float r;
124
-
float g;
125
-
float b;
126
-
float a;
127
-
};
140
+
struct {
141
+
uint32 r;
142
+
uint32 g;
143
+
uint32 b;
144
+
uint32 a;
145
+
};
128
146
129
-
float value[4];
130
-
} SVGA3dRGBAFloat;
131
-
132
-
typedef union {
133
-
struct {
134
-
uint32 r;
135
-
uint32 g;
136
-
uint32 b;
137
-
uint32 a;
138
-
};
139
-
140
-
uint32 value[4];
147
+
uint32 value[4];
141
148
} SVGA3dRGBAUint32;
142
149
143
-
typedef
144
-
#include "vmware_pack_begin.h"
145
-
struct {
146
-
uint32 cid;
147
-
SVGAMobId mobid;
148
-
}
149
-
#include "vmware_pack_end.h"
150
-
SVGAOTableDXContextEntry;
150
+
#pragma pack(push, 1)
151
+
typedef struct {
152
+
uint32 cid;
153
+
SVGAMobId mobid;
154
+
} SVGAOTableDXContextEntry;
155
+
#pragma pack(pop)
151
156
152
-
typedef
153
-
#include "vmware_pack_begin.h"
154
-
struct SVGA3dCmdDXDefineContext {
155
-
uint32 cid;
156
-
}
157
-
#include "vmware_pack_end.h"
158
-
SVGA3dCmdDXDefineContext; /* SVGA_3D_CMD_DX_DEFINE_CONTEXT */
157
+
#pragma pack(push, 1)
158
+
typedef struct SVGA3dCmdDXDefineContext {
159
+
uint32 cid;
160
+
} SVGA3dCmdDXDefineContext;
161
+
#pragma pack(pop)
159
162
160
-
typedef
161
-
#include "vmware_pack_begin.h"
162
-
struct SVGA3dCmdDXDestroyContext {
163
-
uint32 cid;
164
-
}
165
-
#include "vmware_pack_end.h"
166
-
SVGA3dCmdDXDestroyContext; /* SVGA_3D_CMD_DX_DESTROY_CONTEXT */
163
+
#pragma pack(push, 1)
164
+
typedef struct SVGA3dCmdDXDestroyContext {
165
+
uint32 cid;
166
+
} SVGA3dCmdDXDestroyContext;
167
+
#pragma pack(pop)
167
168
168
-
/*
169
-
* Bind a DX context.
170
-
*
171
-
* validContents should be set to 0 for new contexts,
172
-
* and 1 if this is an old context which is getting paged
173
-
* back on to the device.
174
-
*
175
-
* For new contexts, it is recommended that the driver
176
-
* issue commands to initialize all interesting state
177
-
* prior to rendering.
178
-
*/
179
-
typedef
180
-
#include "vmware_pack_begin.h"
181
-
struct SVGA3dCmdDXBindContext {
182
-
uint32 cid;
183
-
SVGAMobId mobid;
184
-
uint32 validContents;
185
-
}
186
-
#include "vmware_pack_end.h"
187
-
SVGA3dCmdDXBindContext; /* SVGA_3D_CMD_DX_BIND_CONTEXT */
169
+
#pragma pack(push, 1)
170
+
typedef struct SVGA3dCmdDXBindContext {
171
+
uint32 cid;
172
+
SVGAMobId mobid;
173
+
uint32 validContents;
174
+
} SVGA3dCmdDXBindContext;
175
+
#pragma pack(pop)
188
176
189
-
/*
190
-
* Readback a DX context.
191
-
* (Request that the device flush the contents back into guest memory.)
192
-
*/
193
-
typedef
194
-
#include "vmware_pack_begin.h"
195
-
struct SVGA3dCmdDXReadbackContext {
196
-
uint32 cid;
197
-
}
198
-
#include "vmware_pack_end.h"
199
-
SVGA3dCmdDXReadbackContext; /* SVGA_3D_CMD_DX_READBACK_CONTEXT */
177
+
#pragma pack(push, 1)
178
+
typedef struct SVGA3dCmdDXReadbackContext {
179
+
uint32 cid;
180
+
} SVGA3dCmdDXReadbackContext;
181
+
#pragma pack(pop)
200
182
201
-
/*
202
-
* Invalidate a guest-backed context.
203
-
*/
204
-
typedef
205
-
#include "vmware_pack_begin.h"
206
-
struct SVGA3dCmdDXInvalidateContext {
207
-
uint32 cid;
208
-
}
209
-
#include "vmware_pack_end.h"
210
-
SVGA3dCmdDXInvalidateContext; /* SVGA_3D_CMD_DX_INVALIDATE_CONTEXT */
183
+
#pragma pack(push, 1)
184
+
typedef struct SVGA3dCmdDXInvalidateContext {
185
+
uint32 cid;
186
+
} SVGA3dCmdDXInvalidateContext;
187
+
#pragma pack(pop)
211
188
212
-
typedef
213
-
#include "vmware_pack_begin.h"
214
-
struct SVGA3dCmdDXSetSingleConstantBuffer {
215
-
uint32 slot;
216
-
SVGA3dShaderType type;
217
-
SVGA3dSurfaceId sid;
218
-
uint32 offsetInBytes;
219
-
uint32 sizeInBytes;
220
-
}
221
-
#include "vmware_pack_end.h"
222
-
SVGA3dCmdDXSetSingleConstantBuffer;
223
-
/* SVGA_3D_CMD_DX_SET_SINGLE_CONSTANT_BUFFER */
189
+
#pragma pack(push, 1)
190
+
typedef struct SVGA3dCmdDXSetSingleConstantBuffer {
191
+
uint32 slot;
192
+
SVGA3dShaderType type;
193
+
SVGA3dSurfaceId sid;
194
+
uint32 offsetInBytes;
195
+
uint32 sizeInBytes;
196
+
} SVGA3dCmdDXSetSingleConstantBuffer;
197
+
#pragma pack(pop)
224
198
225
-
typedef
226
-
#include "vmware_pack_begin.h"
227
-
struct SVGA3dCmdDXSetShaderResources {
228
-
uint32 startView;
229
-
SVGA3dShaderType type;
199
+
#pragma pack(push, 1)
200
+
typedef struct SVGA3dCmdDXSetShaderResources {
201
+
uint32 startView;
202
+
SVGA3dShaderType type;
230
203
231
-
/*
232
-
* Followed by a variable number of SVGA3dShaderResourceViewId's.
233
-
*/
234
-
}
235
-
#include "vmware_pack_end.h"
236
-
SVGA3dCmdDXSetShaderResources; /* SVGA_3D_CMD_DX_SET_SHADER_RESOURCES */
204
+
} SVGA3dCmdDXSetShaderResources;
205
+
#pragma pack(pop)
237
206
238
-
typedef
239
-
#include "vmware_pack_begin.h"
240
-
struct SVGA3dCmdDXSetShader {
241
-
SVGA3dShaderId shaderId;
242
-
SVGA3dShaderType type;
243
-
}
244
-
#include "vmware_pack_end.h"
245
-
SVGA3dCmdDXSetShader; /* SVGA_3D_CMD_DX_SET_SHADER */
207
+
#pragma pack(push, 1)
208
+
typedef struct SVGA3dCmdDXSetShader {
209
+
SVGA3dShaderId shaderId;
210
+
SVGA3dShaderType type;
211
+
} SVGA3dCmdDXSetShader;
212
+
#pragma pack(pop)
246
213
247
214
typedef union {
248
-
struct {
249
-
uint32 cbOffset : 12;
250
-
uint32 cbId : 4;
251
-
uint32 baseSamp : 4;
252
-
uint32 baseTex : 7;
253
-
uint32 reserved : 5;
254
-
};
255
-
uint32 value;
215
+
struct {
216
+
uint32 cbOffset : 12;
217
+
uint32 cbId : 4;
218
+
uint32 baseSamp : 4;
219
+
uint32 baseTex : 7;
220
+
uint32 reserved : 5;
221
+
};
222
+
uint32 value;
256
223
} SVGA3dIfaceData;
257
224
258
-
typedef
259
-
#include "vmware_pack_begin.h"
260
-
struct SVGA3dCmdDXSetShaderIface {
261
-
SVGA3dShaderType type;
262
-
uint32 numClassInstances;
263
-
uint32 index;
264
-
uint32 iface;
265
-
SVGA3dIfaceData data;
266
-
}
267
-
#include "vmware_pack_end.h"
268
-
SVGA3dCmdDXSetShaderIface; /* SVGA_3D_CMD_DX_SET_SHADER_IFACE */
225
+
#pragma pack(push, 1)
226
+
typedef struct SVGA3dCmdDXSetShaderIface {
227
+
SVGA3dShaderType type;
228
+
uint32 numClassInstances;
229
+
uint32 index;
230
+
uint32 iface;
231
+
SVGA3dIfaceData data;
232
+
} SVGA3dCmdDXSetShaderIface;
233
+
#pragma pack(pop)
269
234
270
-
typedef
271
-
#include "vmware_pack_begin.h"
272
-
struct SVGA3dCmdDXBindShaderIface {
273
-
uint32 cid;
274
-
SVGAMobId mobid;
275
-
uint32 offsetInBytes;
276
-
}
277
-
#include "vmware_pack_end.h"
278
-
SVGA3dCmdDXBindShaderIface; /* SVGA_3D_CMD_DX_BIND_SHADER_IFACE */
235
+
#pragma pack(push, 1)
236
+
typedef struct SVGA3dCmdDXBindShaderIface {
237
+
uint32 cid;
238
+
SVGAMobId mobid;
239
+
uint32 offsetInBytes;
240
+
} SVGA3dCmdDXBindShaderIface;
241
+
#pragma pack(pop)
279
242
280
-
typedef
281
-
#include "vmware_pack_begin.h"
282
-
struct SVGA3dCmdDXSetSamplers {
283
-
uint32 startSampler;
284
-
SVGA3dShaderType type;
243
+
#pragma pack(push, 1)
244
+
typedef struct SVGA3dCmdDXSetSamplers {
245
+
uint32 startSampler;
246
+
SVGA3dShaderType type;
285
247
286
-
/*
287
-
* Followed by a variable number of SVGA3dSamplerId's.
288
-
*/
289
-
}
290
-
#include "vmware_pack_end.h"
291
-
SVGA3dCmdDXSetSamplers; /* SVGA_3D_CMD_DX_SET_SAMPLERS */
248
+
} SVGA3dCmdDXSetSamplers;
249
+
#pragma pack(pop)
292
250
293
-
typedef
294
-
#include "vmware_pack_begin.h"
295
-
struct SVGA3dCmdDXDraw {
296
-
uint32 vertexCount;
297
-
uint32 startVertexLocation;
298
-
}
299
-
#include "vmware_pack_end.h"
300
-
SVGA3dCmdDXDraw; /* SVGA_3D_CMD_DX_DRAW */
251
+
#pragma pack(push, 1)
252
+
typedef struct SVGA3dCmdDXDraw {
253
+
uint32 vertexCount;
254
+
uint32 startVertexLocation;
255
+
} SVGA3dCmdDXDraw;
256
+
#pragma pack(pop)
301
257
302
-
typedef
303
-
#include "vmware_pack_begin.h"
304
-
struct SVGA3dCmdDXDrawIndexed {
305
-
uint32 indexCount;
306
-
uint32 startIndexLocation;
307
-
int32 baseVertexLocation;
308
-
}
309
-
#include "vmware_pack_end.h"
310
-
SVGA3dCmdDXDrawIndexed; /* SVGA_3D_CMD_DX_DRAW_INDEXED */
258
+
#pragma pack(push, 1)
259
+
typedef struct SVGA3dCmdDXDrawIndexed {
260
+
uint32 indexCount;
261
+
uint32 startIndexLocation;
262
+
int32 baseVertexLocation;
263
+
} SVGA3dCmdDXDrawIndexed;
264
+
#pragma pack(pop)
311
265
312
-
typedef
313
-
#include "vmware_pack_begin.h"
314
-
struct SVGA3dCmdDXDrawInstanced {
315
-
uint32 vertexCountPerInstance;
316
-
uint32 instanceCount;
317
-
uint32 startVertexLocation;
318
-
uint32 startInstanceLocation;
319
-
}
320
-
#include "vmware_pack_end.h"
321
-
SVGA3dCmdDXDrawInstanced; /* SVGA_3D_CMD_DX_DRAW_INSTANCED */
266
+
#pragma pack(push, 1)
267
+
typedef struct SVGA3dCmdDXDrawInstanced {
268
+
uint32 vertexCountPerInstance;
269
+
uint32 instanceCount;
270
+
uint32 startVertexLocation;
271
+
uint32 startInstanceLocation;
272
+
} SVGA3dCmdDXDrawInstanced;
273
+
#pragma pack(pop)
322
274
323
-
typedef
324
-
#include "vmware_pack_begin.h"
325
-
struct SVGA3dCmdDXDrawIndexedInstanced {
326
-
uint32 indexCountPerInstance;
327
-
uint32 instanceCount;
328
-
uint32 startIndexLocation;
329
-
int32 baseVertexLocation;
330
-
uint32 startInstanceLocation;
331
-
}
332
-
#include "vmware_pack_end.h"
333
-
SVGA3dCmdDXDrawIndexedInstanced; /* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED */
275
+
#pragma pack(push, 1)
276
+
typedef struct SVGA3dCmdDXDrawIndexedInstanced {
277
+
uint32 indexCountPerInstance;
278
+
uint32 instanceCount;
279
+
uint32 startIndexLocation;
280
+
int32 baseVertexLocation;
281
+
uint32 startInstanceLocation;
282
+
} SVGA3dCmdDXDrawIndexedInstanced;
283
+
#pragma pack(pop)
334
284
335
-
typedef
336
-
#include "vmware_pack_begin.h"
337
-
struct SVGA3dCmdDXDrawIndexedInstancedIndirect {
338
-
SVGA3dSurfaceId argsBufferSid;
339
-
uint32 byteOffsetForArgs;
340
-
}
341
-
#include "vmware_pack_end.h"
342
-
SVGA3dCmdDXDrawIndexedInstancedIndirect;
343
-
/* SVGA_3D_CMD_DX_DRAW_INDEXED_INSTANCED_INDIRECT */
285
+
#pragma pack(push, 1)
286
+
typedef struct SVGA3dCmdDXDrawIndexedInstancedIndirect {
287
+
SVGA3dSurfaceId argsBufferSid;
288
+
uint32 byteOffsetForArgs;
289
+
} SVGA3dCmdDXDrawIndexedInstancedIndirect;
290
+
#pragma pack(pop)
344
291
345
-
typedef
346
-
#include "vmware_pack_begin.h"
347
-
struct SVGA3dCmdDXDrawInstancedIndirect {
348
-
SVGA3dSurfaceId argsBufferSid;
349
-
uint32 byteOffsetForArgs;
350
-
}
351
-
#include "vmware_pack_end.h"
352
-
SVGA3dCmdDXDrawInstancedIndirect;
353
-
/* SVGA_3D_CMD_DX_DRAW_INSTANCED_INDIRECT */
292
+
#pragma pack(push, 1)
293
+
typedef struct SVGA3dCmdDXDrawInstancedIndirect {
294
+
SVGA3dSurfaceId argsBufferSid;
295
+
uint32 byteOffsetForArgs;
296
+
} SVGA3dCmdDXDrawInstancedIndirect;
297
+
#pragma pack(pop)
354
298
355
-
typedef
356
-
#include "vmware_pack_begin.h"
357
-
struct SVGA3dCmdDXDrawAuto {
358
-
uint32 pad0;
359
-
}
360
-
#include "vmware_pack_end.h"
361
-
SVGA3dCmdDXDrawAuto; /* SVGA_3D_CMD_DX_DRAW_AUTO */
299
+
#pragma pack(push, 1)
300
+
typedef struct SVGA3dCmdDXDrawAuto {
301
+
uint32 pad0;
302
+
} SVGA3dCmdDXDrawAuto;
303
+
#pragma pack(pop)
362
304
363
-
typedef
364
-
#include "vmware_pack_begin.h"
365
-
struct SVGA3dCmdDXDispatch {
366
-
uint32 threadGroupCountX;
367
-
uint32 threadGroupCountY;
368
-
uint32 threadGroupCountZ;
369
-
}
370
-
#include "vmware_pack_end.h"
371
-
SVGA3dCmdDXDispatch;
372
-
/* SVGA_3D_CMD_DX_DISPATCH */
305
+
#pragma pack(push, 1)
306
+
typedef struct SVGA3dCmdDXDispatch {
307
+
uint32 threadGroupCountX;
308
+
uint32 threadGroupCountY;
309
+
uint32 threadGroupCountZ;
310
+
} SVGA3dCmdDXDispatch;
311
+
#pragma pack(pop)
373
312
374
-
typedef
375
-
#include "vmware_pack_begin.h"
376
-
struct SVGA3dCmdDXDispatchIndirect {
377
-
SVGA3dSurfaceId argsBufferSid;
378
-
uint32 byteOffsetForArgs;
379
-
}
380
-
#include "vmware_pack_end.h"
381
-
SVGA3dCmdDXDispatchIndirect;
382
-
/* SVGA_3D_CMD_DX_DISPATCH_INDIRECT */
313
+
#pragma pack(push, 1)
314
+
typedef struct SVGA3dCmdDXDispatchIndirect {
315
+
SVGA3dSurfaceId argsBufferSid;
316
+
uint32 byteOffsetForArgs;
317
+
} SVGA3dCmdDXDispatchIndirect;
318
+
#pragma pack(pop)
383
319
384
-
typedef
385
-
#include "vmware_pack_begin.h"
386
-
struct SVGA3dCmdDXSetInputLayout {
387
-
SVGA3dElementLayoutId elementLayoutId;
388
-
}
389
-
#include "vmware_pack_end.h"
390
-
SVGA3dCmdDXSetInputLayout; /* SVGA_3D_CMD_DX_SET_INPUT_LAYOUT */
320
+
#pragma pack(push, 1)
321
+
typedef struct SVGA3dCmdDXSetInputLayout {
322
+
SVGA3dElementLayoutId elementLayoutId;
323
+
} SVGA3dCmdDXSetInputLayout;
324
+
#pragma pack(pop)
391
325
392
-
typedef
393
-
#include "vmware_pack_begin.h"
394
-
struct SVGA3dVertexBuffer {
395
-
SVGA3dSurfaceId sid;
396
-
uint32 stride;
397
-
uint32 offset;
398
-
}
399
-
#include "vmware_pack_end.h"
400
-
SVGA3dVertexBuffer;
326
+
#pragma pack(push, 1)
327
+
typedef struct SVGA3dVertexBuffer {
328
+
SVGA3dSurfaceId sid;
329
+
uint32 stride;
330
+
uint32 offset;
331
+
} SVGA3dVertexBuffer;
332
+
#pragma pack(pop)
401
333
402
-
typedef
403
-
#include "vmware_pack_begin.h"
404
-
struct SVGA3dCmdDXSetVertexBuffers {
405
-
uint32 startBuffer;
406
-
/* Followed by a variable number of SVGA3dVertexBuffer's. */
407
-
}
408
-
#include "vmware_pack_end.h"
409
-
SVGA3dCmdDXSetVertexBuffers; /* SVGA_3D_CMD_DX_SET_VERTEX_BUFFERS */
334
+
#pragma pack(push, 1)
335
+
typedef struct SVGA3dCmdDXSetVertexBuffers {
336
+
uint32 startBuffer;
410
337
411
-
typedef
412
-
#include "vmware_pack_begin.h"
413
-
struct SVGA3dCmdDXSetIndexBuffer {
414
-
SVGA3dSurfaceId sid;
415
-
SVGA3dSurfaceFormat format;
416
-
uint32 offset;
417
-
}
418
-
#include "vmware_pack_end.h"
419
-
SVGA3dCmdDXSetIndexBuffer; /* SVGA_3D_CMD_DX_SET_INDEX_BUFFER */
338
+
} SVGA3dCmdDXSetVertexBuffers;
339
+
#pragma pack(pop)
420
340
421
-
typedef
422
-
#include "vmware_pack_begin.h"
423
-
struct SVGA3dCmdDXSetTopology {
424
-
SVGA3dPrimitiveType topology;
425
-
}
426
-
#include "vmware_pack_end.h"
427
-
SVGA3dCmdDXSetTopology; /* SVGA_3D_CMD_DX_SET_TOPOLOGY */
341
+
#pragma pack(push, 1)
342
+
typedef struct SVGA3dVertexBuffer_v2 {
343
+
SVGA3dSurfaceId sid;
344
+
uint32 stride;
345
+
uint32 offset;
346
+
uint32 sizeInBytes;
347
+
} SVGA3dVertexBuffer_v2;
348
+
#pragma pack(pop)
428
349
429
-
typedef
430
-
#include "vmware_pack_begin.h"
431
-
struct SVGA3dCmdDXSetRenderTargets {
432
-
SVGA3dDepthStencilViewId depthStencilViewId;
433
-
/* Followed by a variable number of SVGA3dRenderTargetViewId's. */
434
-
}
435
-
#include "vmware_pack_end.h"
436
-
SVGA3dCmdDXSetRenderTargets; /* SVGA_3D_CMD_DX_SET_RENDERTARGETS */
350
+
#pragma pack(push, 1)
351
+
typedef struct SVGA3dCmdDXSetVertexBuffers_v2 {
352
+
uint32 startBuffer;
437
353
438
-
typedef
439
-
#include "vmware_pack_begin.h"
440
-
struct SVGA3dCmdDXSetBlendState {
441
-
SVGA3dBlendStateId blendId;
442
-
float blendFactor[4];
443
-
uint32 sampleMask;
444
-
}
445
-
#include "vmware_pack_end.h"
446
-
SVGA3dCmdDXSetBlendState; /* SVGA_3D_CMD_DX_SET_BLEND_STATE */
354
+
} SVGA3dCmdDXSetVertexBuffers_v2;
355
+
#pragma pack(pop)
447
356
448
-
typedef
449
-
#include "vmware_pack_begin.h"
450
-
struct SVGA3dCmdDXSetDepthStencilState {
451
-
SVGA3dDepthStencilStateId depthStencilId;
452
-
uint32 stencilRef;
453
-
}
454
-
#include "vmware_pack_end.h"
455
-
SVGA3dCmdDXSetDepthStencilState; /* SVGA_3D_CMD_DX_SET_DEPTHSTENCIL_STATE */
357
+
#pragma pack(push, 1)
358
+
typedef struct SVGA3dVertexBufferOffsetAndSize {
359
+
uint32 stride;
360
+
uint32 offset;
361
+
uint32 sizeInBytes;
362
+
} SVGA3dVertexBufferOffsetAndSize;
363
+
#pragma pack(pop)
456
364
457
-
typedef
458
-
#include "vmware_pack_begin.h"
459
-
struct SVGA3dCmdDXSetRasterizerState {
460
-
SVGA3dRasterizerStateId rasterizerId;
461
-
}
462
-
#include "vmware_pack_end.h"
463
-
SVGA3dCmdDXSetRasterizerState; /* SVGA_3D_CMD_DX_SET_RASTERIZER_STATE */
365
+
#pragma pack(push, 1)
366
+
typedef struct SVGA3dCmdDXSetVertexBuffersOffsetAndSize {
367
+
uint32 startBuffer;
368
+
369
+
} SVGA3dCmdDXSetVertexBuffersOffsetAndSize;
370
+
#pragma pack(pop)
371
+
372
+
#pragma pack(push, 1)
373
+
typedef struct SVGA3dCmdDXSetIndexBuffer {
374
+
SVGA3dSurfaceId sid;
375
+
SVGA3dSurfaceFormat format;
376
+
uint32 offset;
377
+
} SVGA3dCmdDXSetIndexBuffer;
378
+
#pragma pack(pop)
379
+
380
+
#pragma pack(push, 1)
381
+
typedef struct SVGA3dCmdDXSetIndexBuffer_v2 {
382
+
SVGA3dSurfaceId sid;
383
+
SVGA3dSurfaceFormat format;
384
+
uint32 offset;
385
+
uint32 sizeInBytes;
386
+
} SVGA3dCmdDXSetIndexBuffer_v2;
387
+
#pragma pack(pop)
388
+
389
+
#pragma pack(push, 1)
390
+
typedef struct SVGA3dCmdDXSetIndexBufferOffsetAndSize {
391
+
SVGA3dSurfaceFormat format;
392
+
uint32 offset;
393
+
uint32 sizeInBytes;
394
+
} SVGA3dCmdDXSetIndexBufferOffsetAndSize;
395
+
#pragma pack(pop)
396
+
397
+
#pragma pack(push, 1)
398
+
typedef struct SVGA3dCmdDXSetTopology {
399
+
SVGA3dPrimitiveType topology;
400
+
} SVGA3dCmdDXSetTopology;
401
+
#pragma pack(pop)
402
+
403
+
#pragma pack(push, 1)
404
+
typedef struct SVGA3dCmdDXSetRenderTargets {
405
+
SVGA3dDepthStencilViewId depthStencilViewId;
406
+
407
+
} SVGA3dCmdDXSetRenderTargets;
408
+
#pragma pack(pop)
409
+
410
+
#pragma pack(push, 1)
411
+
typedef struct SVGA3dCmdDXSetBlendState {
412
+
SVGA3dBlendStateId blendId;
413
+
float blendFactor[4];
414
+
uint32 sampleMask;
415
+
} SVGA3dCmdDXSetBlendState;
416
+
#pragma pack(pop)
417
+
418
+
#pragma pack(push, 1)
419
+
typedef struct SVGA3dCmdDXSetDepthStencilState {
420
+
SVGA3dDepthStencilStateId depthStencilId;
421
+
uint32 stencilRef;
422
+
} SVGA3dCmdDXSetDepthStencilState;
423
+
#pragma pack(pop)
424
+
425
+
#pragma pack(push, 1)
426
+
typedef struct SVGA3dCmdDXSetRasterizerState {
427
+
SVGA3dRasterizerStateId rasterizerId;
428
+
} SVGA3dCmdDXSetRasterizerState;
429
+
#pragma pack(pop)
464
430
465
431
#define SVGA3D_DXQUERY_FLAG_PREDICATEHINT (1 << 0)
466
432
typedef uint32 SVGA3dDXQueryFlags;
467
433
468
-
/*
469
-
* The SVGADXQueryDeviceState and SVGADXQueryDeviceBits are used by the device
470
-
* to track query state transitions, but are not intended to be used by the
471
-
* driver.
472
-
*/
473
-
#define SVGADX_QDSTATE_INVALID ((uint8)-1) /* Query has no state */
474
-
#define SVGADX_QDSTATE_MIN 0
475
-
#define SVGADX_QDSTATE_IDLE 0 /* Query hasn't started yet */
476
-
#define SVGADX_QDSTATE_ACTIVE 1 /* Query is actively gathering data */
477
-
#define SVGADX_QDSTATE_PENDING 2 /* Query is waiting for results */
478
-
#define SVGADX_QDSTATE_FINISHED 3 /* Query has completed */
479
-
#define SVGADX_QDSTATE_MAX 4
434
+
#define SVGADX_QDSTATE_INVALID ((uint8)-1)
435
+
#define SVGADX_QDSTATE_MIN 0
436
+
#define SVGADX_QDSTATE_IDLE 0
437
+
#define SVGADX_QDSTATE_ACTIVE 1
438
+
#define SVGADX_QDSTATE_PENDING 2
439
+
#define SVGADX_QDSTATE_FINISHED 3
440
+
#define SVGADX_QDSTATE_MAX 4
480
441
typedef uint8 SVGADXQueryDeviceState;
481
442
482
-
typedef
483
-
#include "vmware_pack_begin.h"
484
-
struct {
485
-
SVGA3dQueryTypeUint8 type;
486
-
uint16 pad0;
487
-
SVGADXQueryDeviceState state;
488
-
SVGA3dDXQueryFlags flags;
489
-
SVGAMobId mobid;
490
-
uint32 offset;
491
-
}
492
-
#include "vmware_pack_end.h"
493
-
SVGACOTableDXQueryEntry;
443
+
#pragma pack(push, 1)
444
+
typedef struct {
445
+
SVGA3dQueryTypeUint8 type;
446
+
uint16 pad0;
447
+
SVGADXQueryDeviceState state;
448
+
SVGA3dDXQueryFlags flags;
449
+
SVGAMobId mobid;
450
+
uint32 offset;
451
+
} SVGACOTableDXQueryEntry;
452
+
#pragma pack(pop)
494
453
495
-
typedef
496
-
#include "vmware_pack_begin.h"
497
-
struct SVGA3dCmdDXDefineQuery {
498
-
SVGA3dQueryId queryId;
499
-
SVGA3dQueryType type;
500
-
SVGA3dDXQueryFlags flags;
501
-
}
502
-
#include "vmware_pack_end.h"
503
-
SVGA3dCmdDXDefineQuery; /* SVGA_3D_CMD_DX_DEFINE_QUERY */
454
+
#pragma pack(push, 1)
455
+
typedef struct SVGA3dCmdDXDefineQuery {
456
+
SVGA3dQueryId queryId;
457
+
SVGA3dQueryType type;
458
+
SVGA3dDXQueryFlags flags;
459
+
} SVGA3dCmdDXDefineQuery;
460
+
#pragma pack(pop)
504
461
505
-
typedef
506
-
#include "vmware_pack_begin.h"
507
-
struct SVGA3dCmdDXDestroyQuery {
508
-
SVGA3dQueryId queryId;
509
-
}
510
-
#include "vmware_pack_end.h"
511
-
SVGA3dCmdDXDestroyQuery; /* SVGA_3D_CMD_DX_DESTROY_QUERY */
462
+
#pragma pack(push, 1)
463
+
typedef struct SVGA3dCmdDXDestroyQuery {
464
+
SVGA3dQueryId queryId;
465
+
} SVGA3dCmdDXDestroyQuery;
466
+
#pragma pack(pop)
512
467
513
-
typedef
514
-
#include "vmware_pack_begin.h"
515
-
struct SVGA3dCmdDXBindQuery {
516
-
SVGA3dQueryId queryId;
517
-
SVGAMobId mobid;
518
-
}
519
-
#include "vmware_pack_end.h"
520
-
SVGA3dCmdDXBindQuery; /* SVGA_3D_CMD_DX_BIND_QUERY */
468
+
#pragma pack(push, 1)
469
+
typedef struct SVGA3dCmdDXBindQuery {
470
+
SVGA3dQueryId queryId;
471
+
SVGAMobId mobid;
472
+
} SVGA3dCmdDXBindQuery;
473
+
#pragma pack(pop)
521
474
522
-
typedef
523
-
#include "vmware_pack_begin.h"
524
-
struct SVGA3dCmdDXSetQueryOffset {
525
-
SVGA3dQueryId queryId;
526
-
uint32 mobOffset;
527
-
}
528
-
#include "vmware_pack_end.h"
529
-
SVGA3dCmdDXSetQueryOffset; /* SVGA_3D_CMD_DX_SET_QUERY_OFFSET */
475
+
#pragma pack(push, 1)
476
+
typedef struct SVGA3dCmdDXSetQueryOffset {
477
+
SVGA3dQueryId queryId;
478
+
uint32 mobOffset;
479
+
} SVGA3dCmdDXSetQueryOffset;
480
+
#pragma pack(pop)
530
481
531
-
typedef
532
-
#include "vmware_pack_begin.h"
533
-
struct SVGA3dCmdDXBeginQuery {
534
-
SVGA3dQueryId queryId;
535
-
}
536
-
#include "vmware_pack_end.h"
537
-
SVGA3dCmdDXBeginQuery; /* SVGA_3D_CMD_DX_QUERY_BEGIN */
482
+
#pragma pack(push, 1)
483
+
typedef struct SVGA3dCmdDXBeginQuery {
484
+
SVGA3dQueryId queryId;
485
+
} SVGA3dCmdDXBeginQuery;
486
+
#pragma pack(pop)
538
487
539
-
typedef
540
-
#include "vmware_pack_begin.h"
541
-
struct SVGA3dCmdDXEndQuery {
542
-
SVGA3dQueryId queryId;
543
-
}
544
-
#include "vmware_pack_end.h"
545
-
SVGA3dCmdDXEndQuery; /* SVGA_3D_CMD_DX_QUERY_END */
488
+
#pragma pack(push, 1)
489
+
typedef struct SVGA3dCmdDXEndQuery {
490
+
SVGA3dQueryId queryId;
491
+
} SVGA3dCmdDXEndQuery;
492
+
#pragma pack(pop)
546
493
547
-
typedef
548
-
#include "vmware_pack_begin.h"
549
-
struct SVGA3dCmdDXReadbackQuery {
550
-
SVGA3dQueryId queryId;
551
-
}
552
-
#include "vmware_pack_end.h"
553
-
SVGA3dCmdDXReadbackQuery; /* SVGA_3D_CMD_DX_READBACK_QUERY */
494
+
#pragma pack(push, 1)
495
+
typedef struct SVGA3dCmdDXReadbackQuery {
496
+
SVGA3dQueryId queryId;
497
+
} SVGA3dCmdDXReadbackQuery;
498
+
#pragma pack(pop)
554
499
555
-
typedef
556
-
#include "vmware_pack_begin.h"
557
-
struct SVGA3dCmdDXMoveQuery {
558
-
SVGA3dQueryId queryId;
559
-
SVGAMobId mobid;
560
-
uint32 mobOffset;
561
-
}
562
-
#include "vmware_pack_end.h"
563
-
SVGA3dCmdDXMoveQuery; /* SVGA_3D_CMD_DX_MOVE_QUERY */
500
+
#pragma pack(push, 1)
501
+
typedef struct SVGA3dCmdDXMoveQuery {
502
+
SVGA3dQueryId queryId;
503
+
SVGAMobId mobid;
504
+
uint32 mobOffset;
505
+
} SVGA3dCmdDXMoveQuery;
506
+
#pragma pack(pop)
564
507
565
-
typedef
566
-
#include "vmware_pack_begin.h"
567
-
struct SVGA3dCmdDXBindAllQuery {
568
-
uint32 cid;
569
-
SVGAMobId mobid;
570
-
}
571
-
#include "vmware_pack_end.h"
572
-
SVGA3dCmdDXBindAllQuery; /* SVGA_3D_CMD_DX_BIND_ALL_QUERY */
508
+
#pragma pack(push, 1)
509
+
typedef struct SVGA3dCmdDXBindAllQuery {
510
+
uint32 cid;
511
+
SVGAMobId mobid;
512
+
} SVGA3dCmdDXBindAllQuery;
513
+
#pragma pack(pop)
573
514
574
-
typedef
575
-
#include "vmware_pack_begin.h"
576
-
struct SVGA3dCmdDXReadbackAllQuery {
577
-
uint32 cid;
578
-
}
579
-
#include "vmware_pack_end.h"
580
-
SVGA3dCmdDXReadbackAllQuery; /* SVGA_3D_CMD_DX_READBACK_ALL_QUERY */
515
+
#pragma pack(push, 1)
516
+
typedef struct SVGA3dCmdDXReadbackAllQuery {
517
+
uint32 cid;
518
+
} SVGA3dCmdDXReadbackAllQuery;
519
+
#pragma pack(pop)
581
520
582
-
typedef
583
-
#include "vmware_pack_begin.h"
584
-
struct SVGA3dCmdDXSetPredication {
585
-
SVGA3dQueryId queryId;
586
-
uint32 predicateValue;
587
-
}
588
-
#include "vmware_pack_end.h"
589
-
SVGA3dCmdDXSetPredication; /* SVGA_3D_CMD_DX_SET_PREDICATION */
521
+
#pragma pack(push, 1)
522
+
typedef struct SVGA3dCmdDXSetPredication {
523
+
SVGA3dQueryId queryId;
524
+
uint32 predicateValue;
525
+
} SVGA3dCmdDXSetPredication;
526
+
#pragma pack(pop)
590
527
591
-
typedef
592
-
#include "vmware_pack_begin.h"
593
-
struct MKS3dDXSOState {
594
-
uint32 offset; /* Starting offset */
595
-
uint32 intOffset; /* Internal offset */
596
-
uint32 vertexCount; /* vertices written */
597
-
uint32 dead;
598
-
}
599
-
#include "vmware_pack_end.h"
600
-
SVGA3dDXSOState;
528
+
#pragma pack(push, 1)
529
+
typedef struct MKS3dDXSOState {
530
+
uint32 offset;
531
+
uint32 intOffset;
532
+
uint32 vertexCount;
533
+
uint32 dead;
534
+
} SVGA3dDXSOState;
535
+
#pragma pack(pop)
601
536
602
-
/* Set the offset field to this value to append SO values to the buffer */
603
-
#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32) ~0u)
537
+
#define SVGA3D_DX_SO_OFFSET_APPEND ((uint32)~0u)
604
538
605
-
typedef
606
-
#include "vmware_pack_begin.h"
607
-
struct SVGA3dSoTarget {
608
-
SVGA3dSurfaceId sid;
609
-
uint32 offset;
610
-
uint32 sizeInBytes;
611
-
}
612
-
#include "vmware_pack_end.h"
613
-
SVGA3dSoTarget;
539
+
#pragma pack(push, 1)
540
+
typedef struct SVGA3dSoTarget {
541
+
SVGA3dSurfaceId sid;
542
+
uint32 offset;
543
+
uint32 sizeInBytes;
544
+
} SVGA3dSoTarget;
545
+
#pragma pack(pop)
614
546
615
-
typedef
616
-
#include "vmware_pack_begin.h"
617
-
struct SVGA3dCmdDXSetSOTargets {
618
-
uint32 pad0;
619
-
/* Followed by a variable number of SVGA3dSOTarget's. */
620
-
}
621
-
#include "vmware_pack_end.h"
622
-
SVGA3dCmdDXSetSOTargets; /* SVGA_3D_CMD_DX_SET_SOTARGETS */
547
+
#pragma pack(push, 1)
548
+
typedef struct SVGA3dCmdDXSetSOTargets {
549
+
uint32 pad0;
623
550
624
-
typedef
625
-
#include "vmware_pack_begin.h"
626
-
struct SVGA3dViewport
627
-
{
628
-
float x;
629
-
float y;
630
-
float width;
631
-
float height;
632
-
float minDepth;
633
-
float maxDepth;
634
-
}
635
-
#include "vmware_pack_end.h"
636
-
SVGA3dViewport;
551
+
} SVGA3dCmdDXSetSOTargets;
552
+
#pragma pack(pop)
637
553
638
-
typedef
639
-
#include "vmware_pack_begin.h"
640
-
struct SVGA3dCmdDXSetViewports {
641
-
uint32 pad0;
642
-
/* Followed by a variable number of SVGA3dViewport's. */
643
-
}
644
-
#include "vmware_pack_end.h"
645
-
SVGA3dCmdDXSetViewports; /* SVGA_3D_CMD_DX_SET_VIEWPORTS */
554
+
#pragma pack(push, 1)
555
+
typedef struct SVGA3dViewport {
556
+
float x;
557
+
float y;
558
+
float width;
559
+
float height;
560
+
float minDepth;
561
+
float maxDepth;
562
+
} SVGA3dViewport;
563
+
#pragma pack(pop)
646
564
647
-
#define SVGA3D_DX_MAX_VIEWPORTS 16
565
+
#pragma pack(push, 1)
566
+
typedef struct SVGA3dCmdDXSetViewports {
567
+
uint32 pad0;
648
568
649
-
typedef
650
-
#include "vmware_pack_begin.h"
651
-
struct SVGA3dCmdDXSetScissorRects {
652
-
uint32 pad0;
653
-
/* Followed by a variable number of SVGASignedRect's. */
654
-
}
655
-
#include "vmware_pack_end.h"
656
-
SVGA3dCmdDXSetScissorRects; /* SVGA_3D_CMD_DX_SET_SCISSORRECTS */
569
+
} SVGA3dCmdDXSetViewports;
570
+
#pragma pack(pop)
657
571
658
-
#define SVGA3D_DX_MAX_SCISSORRECTS 16
572
+
#define SVGA3D_DX_MAX_VIEWPORTS 16
659
573
660
-
typedef
661
-
#include "vmware_pack_begin.h"
662
-
struct SVGA3dCmdDXClearRenderTargetView {
663
-
SVGA3dRenderTargetViewId renderTargetViewId;
664
-
SVGA3dRGBAFloat rgba;
665
-
}
666
-
#include "vmware_pack_end.h"
667
-
SVGA3dCmdDXClearRenderTargetView; /* SVGA_3D_CMD_DX_CLEAR_RENDERTARGET_VIEW */
574
+
#pragma pack(push, 1)
575
+
typedef struct SVGA3dCmdDXSetScissorRects {
576
+
uint32 pad0;
668
577
669
-
typedef
670
-
#include "vmware_pack_begin.h"
671
-
struct SVGA3dCmdDXClearDepthStencilView {
672
-
uint16 flags;
673
-
uint16 stencil;
674
-
SVGA3dDepthStencilViewId depthStencilViewId;
675
-
float depth;
676
-
}
677
-
#include "vmware_pack_end.h"
678
-
SVGA3dCmdDXClearDepthStencilView; /* SVGA_3D_CMD_DX_CLEAR_DEPTHSTENCIL_VIEW */
578
+
} SVGA3dCmdDXSetScissorRects;
579
+
#pragma pack(pop)
679
580
680
-
typedef
681
-
#include "vmware_pack_begin.h"
682
-
struct SVGA3dCmdDXPredCopyRegion {
683
-
SVGA3dSurfaceId dstSid;
684
-
uint32 dstSubResource;
685
-
SVGA3dSurfaceId srcSid;
686
-
uint32 srcSubResource;
687
-
SVGA3dCopyBox box;
688
-
}
689
-
#include "vmware_pack_end.h"
690
-
SVGA3dCmdDXPredCopyRegion;
691
-
/* SVGA_3D_CMD_DX_PRED_COPY_REGION */
581
+
#define SVGA3D_DX_MAX_SCISSORRECTS 16
692
582
693
-
typedef
694
-
#include "vmware_pack_begin.h"
695
-
struct SVGA3dCmdDXPredCopy {
696
-
SVGA3dSurfaceId dstSid;
697
-
SVGA3dSurfaceId srcSid;
698
-
}
699
-
#include "vmware_pack_end.h"
700
-
SVGA3dCmdDXPredCopy; /* SVGA_3D_CMD_DX_PRED_COPY */
583
+
#pragma pack(push, 1)
584
+
typedef struct SVGA3dCmdDXClearRenderTargetView {
585
+
SVGA3dRenderTargetViewId renderTargetViewId;
586
+
SVGA3dRGBAFloat rgba;
587
+
} SVGA3dCmdDXClearRenderTargetView;
588
+
#pragma pack(pop)
701
589
702
-
typedef
703
-
#include "vmware_pack_begin.h"
704
-
struct SVGA3dCmdDXPredConvertRegion {
705
-
SVGA3dSurfaceId dstSid;
706
-
uint32 dstSubResource;
707
-
SVGA3dBox destBox;
708
-
SVGA3dSurfaceId srcSid;
709
-
uint32 srcSubResource;
710
-
SVGA3dBox srcBox;
711
-
}
712
-
#include "vmware_pack_end.h"
713
-
SVGA3dCmdDXPredConvertRegion; /* SVGA_3D_CMD_DX_PRED_CONVERT_REGION */
590
+
#pragma pack(push, 1)
591
+
typedef struct SVGA3dCmdDXClearDepthStencilView {
592
+
uint16 flags;
593
+
uint16 stencil;
594
+
SVGA3dDepthStencilViewId depthStencilViewId;
595
+
float depth;
596
+
} SVGA3dCmdDXClearDepthStencilView;
597
+
#pragma pack(pop)
714
598
715
-
typedef
716
-
#include "vmware_pack_begin.h"
717
-
struct SVGA3dCmdDXPredConvert {
718
-
SVGA3dSurfaceId dstSid;
719
-
SVGA3dSurfaceId srcSid;
720
-
}
721
-
#include "vmware_pack_end.h"
722
-
SVGA3dCmdDXPredConvert; /* SVGA_3D_CMD_DX_PRED_CONVERT */
599
+
#pragma pack(push, 1)
600
+
typedef struct SVGA3dCmdDXPredCopyRegion {
601
+
SVGA3dSurfaceId dstSid;
602
+
uint32 dstSubResource;
603
+
SVGA3dSurfaceId srcSid;
604
+
uint32 srcSubResource;
605
+
SVGA3dCopyBox box;
606
+
} SVGA3dCmdDXPredCopyRegion;
607
+
#pragma pack(pop)
723
608
724
-
typedef
725
-
#include "vmware_pack_begin.h"
726
-
struct SVGA3dCmdDXBufferCopy {
727
-
SVGA3dSurfaceId dest;
728
-
SVGA3dSurfaceId src;
729
-
uint32 destX;
730
-
uint32 srcX;
731
-
uint32 width;
732
-
}
733
-
#include "vmware_pack_end.h"
734
-
SVGA3dCmdDXBufferCopy;
735
-
/* SVGA_3D_CMD_DX_BUFFER_COPY */
609
+
#pragma pack(push, 1)
610
+
typedef struct SVGA3dCmdDXPredStagingCopyRegion {
611
+
SVGA3dSurfaceId dstSid;
612
+
uint32 dstSubResource;
613
+
SVGA3dSurfaceId srcSid;
614
+
uint32 srcSubResource;
615
+
SVGA3dCopyBox box;
616
+
uint8 readback;
617
+
uint8 unsynchronized;
618
+
uint8 mustBeZero[2];
619
+
} SVGA3dCmdDXPredStagingCopyRegion;
620
+
#pragma pack(pop)
736
621
737
-
/*
738
-
* Perform a surface copy between a multisample, and a non-multisampled
739
-
* surface.
740
-
*/
741
-
typedef
742
-
#include "vmware_pack_begin.h"
743
-
struct {
744
-
SVGA3dSurfaceId dstSid;
745
-
uint32 dstSubResource;
746
-
SVGA3dSurfaceId srcSid;
747
-
uint32 srcSubResource;
748
-
SVGA3dSurfaceFormat copyFormat;
749
-
}
750
-
#include "vmware_pack_end.h"
751
-
SVGA3dCmdDXResolveCopy; /* SVGA_3D_CMD_DX_RESOLVE_COPY */
622
+
#pragma pack(push, 1)
623
+
typedef struct SVGA3dCmdDXPredCopy {
624
+
SVGA3dSurfaceId dstSid;
625
+
SVGA3dSurfaceId srcSid;
626
+
} SVGA3dCmdDXPredCopy;
627
+
#pragma pack(pop)
752
628
753
-
/*
754
-
* Perform a predicated surface copy between a multisample, and a
755
-
* non-multisampled surface.
756
-
*/
757
-
typedef
758
-
#include "vmware_pack_begin.h"
759
-
struct {
760
-
SVGA3dSurfaceId dstSid;
761
-
uint32 dstSubResource;
762
-
SVGA3dSurfaceId srcSid;
763
-
uint32 srcSubResource;
764
-
SVGA3dSurfaceFormat copyFormat;
765
-
}
766
-
#include "vmware_pack_end.h"
767
-
SVGA3dCmdDXPredResolveCopy; /* SVGA_3D_CMD_DX_PRED_RESOLVE_COPY */
629
+
#pragma pack(push, 1)
630
+
typedef struct SVGA3dCmdDXPredConvertRegion {
631
+
SVGA3dSurfaceId dstSid;
632
+
uint32 dstSubResource;
633
+
SVGA3dBox destBox;
634
+
SVGA3dSurfaceId srcSid;
635
+
uint32 srcSubResource;
636
+
SVGA3dBox srcBox;
637
+
} SVGA3dCmdDXPredConvertRegion;
638
+
#pragma pack(pop)
639
+
640
+
#pragma pack(push, 1)
641
+
typedef struct SVGA3dCmdDXPredStagingConvertRegion {
642
+
SVGA3dSurfaceId dstSid;
643
+
uint32 dstSubResource;
644
+
SVGA3dBox destBox;
645
+
SVGA3dSurfaceId srcSid;
646
+
uint32 srcSubResource;
647
+
SVGA3dBox srcBox;
648
+
uint8 readback;
649
+
uint8 unsynchronized;
650
+
uint8 mustBeZero[2];
651
+
} SVGA3dCmdDXPredStagingConvertRegion;
652
+
#pragma pack(pop)
653
+
654
+
#pragma pack(push, 1)
655
+
typedef struct SVGA3dCmdDXPredConvert {
656
+
SVGA3dSurfaceId dstSid;
657
+
SVGA3dSurfaceId srcSid;
658
+
} SVGA3dCmdDXPredConvert;
659
+
#pragma pack(pop)
660
+
661
+
#pragma pack(push, 1)
662
+
typedef struct SVGA3dCmdDXPredStagingConvert {
663
+
SVGA3dSurfaceId dstSid;
664
+
SVGA3dSurfaceId srcSid;
665
+
uint8 readback;
666
+
uint8 unsynchronized;
667
+
uint8 mustBeZero[2];
668
+
} SVGA3dCmdDXPredStagingConvert;
669
+
#pragma pack(pop)
670
+
671
+
#pragma pack(push, 1)
672
+
typedef struct SVGA3dCmdDXBufferCopy {
673
+
SVGA3dSurfaceId dest;
674
+
SVGA3dSurfaceId src;
675
+
uint32 destX;
676
+
uint32 srcX;
677
+
uint32 width;
678
+
} SVGA3dCmdDXBufferCopy;
679
+
#pragma pack(pop)
680
+
681
+
#pragma pack(push, 1)
682
+
typedef struct SVGA3dCmdDXStagingBufferCopy {
683
+
SVGA3dSurfaceId dest;
684
+
SVGA3dSurfaceId src;
685
+
uint32 destX;
686
+
uint32 srcX;
687
+
uint32 width;
688
+
uint8 readback;
689
+
uint8 unsynchronized;
690
+
uint8 mustBeZero[2];
691
+
} SVGA3dCmdDXStagingBufferCopy;
692
+
#pragma pack(pop)
693
+
694
+
#pragma pack(push, 1)
695
+
typedef struct {
696
+
SVGA3dSurfaceId dstSid;
697
+
uint32 dstSubResource;
698
+
SVGA3dSurfaceId srcSid;
699
+
uint32 srcSubResource;
700
+
SVGA3dSurfaceFormat copyFormat;
701
+
} SVGA3dCmdDXResolveCopy;
702
+
#pragma pack(pop)
703
+
704
+
#pragma pack(push, 1)
705
+
typedef struct {
706
+
SVGA3dSurfaceId dstSid;
707
+
uint32 dstSubResource;
708
+
SVGA3dSurfaceId srcSid;
709
+
uint32 srcSubResource;
710
+
SVGA3dSurfaceFormat copyFormat;
711
+
} SVGA3dCmdDXPredResolveCopy;
712
+
#pragma pack(pop)
768
713
769
714
typedef uint32 SVGA3dDXPresentBltMode;
770
-
#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
771
-
#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
715
+
#define SVGADX_PRESENTBLT_LINEAR (1 << 0)
716
+
#define SVGADX_PRESENTBLT_FORCE_SRC_SRGB (1 << 1)
772
717
#define SVGADX_PRESENTBLT_FORCE_SRC_XRBIAS (1 << 2)
773
-
#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
718
+
#define SVGADX_PRESENTBLT_MODE_MAX (1 << 3)
774
719
775
-
typedef
776
-
#include "vmware_pack_begin.h"
777
-
struct SVGA3dCmdDXPresentBlt {
778
-
SVGA3dSurfaceId srcSid;
779
-
uint32 srcSubResource;
780
-
SVGA3dSurfaceId dstSid;
781
-
uint32 destSubResource;
782
-
SVGA3dBox boxSrc;
783
-
SVGA3dBox boxDest;
784
-
SVGA3dDXPresentBltMode mode;
785
-
}
786
-
#include "vmware_pack_end.h"
787
-
SVGA3dCmdDXPresentBlt; /* SVGA_3D_CMD_DX_PRESENTBLT*/
720
+
#pragma pack(push, 1)
721
+
typedef struct SVGA3dCmdDXPresentBlt {
722
+
SVGA3dSurfaceId srcSid;
723
+
uint32 srcSubResource;
724
+
SVGA3dSurfaceId dstSid;
725
+
uint32 destSubResource;
726
+
SVGA3dBox boxSrc;
727
+
SVGA3dBox boxDest;
728
+
SVGA3dDXPresentBltMode mode;
729
+
} SVGA3dCmdDXPresentBlt;
730
+
#pragma pack(pop)
788
731
789
-
typedef
790
-
#include "vmware_pack_begin.h"
791
-
struct SVGA3dCmdDXGenMips {
792
-
SVGA3dShaderResourceViewId shaderResourceViewId;
793
-
}
794
-
#include "vmware_pack_end.h"
795
-
SVGA3dCmdDXGenMips; /* SVGA_3D_CMD_DX_GENMIPS */
732
+
#pragma pack(push, 1)
733
+
typedef struct SVGA3dCmdDXGenMips {
734
+
SVGA3dShaderResourceViewId shaderResourceViewId;
735
+
} SVGA3dCmdDXGenMips;
736
+
#pragma pack(pop)
796
737
797
-
/*
798
-
* Update a sub-resource in a guest-backed resource.
799
-
* (Inform the device that the guest-contents have been updated.)
800
-
*/
801
-
typedef
802
-
#include "vmware_pack_begin.h"
803
-
struct SVGA3dCmdDXUpdateSubResource {
804
-
SVGA3dSurfaceId sid;
805
-
uint32 subResource;
806
-
SVGA3dBox box;
807
-
}
808
-
#include "vmware_pack_end.h"
809
-
SVGA3dCmdDXUpdateSubResource; /* SVGA_3D_CMD_DX_UPDATE_SUBRESOURCE */
738
+
#pragma pack(push, 1)
739
+
typedef struct SVGA3dCmdDXUpdateSubResource {
740
+
SVGA3dSurfaceId sid;
741
+
uint32 subResource;
742
+
SVGA3dBox box;
743
+
} SVGA3dCmdDXUpdateSubResource;
744
+
#pragma pack(pop)
810
745
811
-
/*
812
-
* Readback a subresource in a guest-backed resource.
813
-
* (Request the device to flush the dirty contents into the guest.)
814
-
*/
815
-
typedef
816
-
#include "vmware_pack_begin.h"
817
-
struct SVGA3dCmdDXReadbackSubResource {
818
-
SVGA3dSurfaceId sid;
819
-
uint32 subResource;
820
-
}
821
-
#include "vmware_pack_end.h"
822
-
SVGA3dCmdDXReadbackSubResource; /* SVGA_3D_CMD_DX_READBACK_SUBRESOURCE */
746
+
#pragma pack(push, 1)
747
+
typedef struct SVGA3dCmdDXReadbackSubResource {
748
+
SVGA3dSurfaceId sid;
749
+
uint32 subResource;
750
+
} SVGA3dCmdDXReadbackSubResource;
751
+
#pragma pack(pop)
823
752
824
-
/*
825
-
* Invalidate an image in a guest-backed surface.
826
-
* (Notify the device that the contents can be lost.)
827
-
*/
828
-
typedef
829
-
#include "vmware_pack_begin.h"
830
-
struct SVGA3dCmdDXInvalidateSubResource {
831
-
SVGA3dSurfaceId sid;
832
-
uint32 subResource;
833
-
}
834
-
#include "vmware_pack_end.h"
835
-
SVGA3dCmdDXInvalidateSubResource; /* SVGA_3D_CMD_DX_INVALIDATE_SUBRESOURCE */
753
+
#pragma pack(push, 1)
754
+
typedef struct SVGA3dCmdDXInvalidateSubResource {
755
+
SVGA3dSurfaceId sid;
756
+
uint32 subResource;
757
+
} SVGA3dCmdDXInvalidateSubResource;
758
+
#pragma pack(pop)
836
759
760
+
#pragma pack(push, 1)
761
+
typedef struct SVGA3dCmdDXTransferFromBuffer {
762
+
SVGA3dSurfaceId srcSid;
763
+
uint32 srcOffset;
764
+
uint32 srcPitch;
765
+
uint32 srcSlicePitch;
766
+
SVGA3dSurfaceId destSid;
767
+
uint32 destSubResource;
768
+
SVGA3dBox destBox;
769
+
} SVGA3dCmdDXTransferFromBuffer;
770
+
#pragma pack(pop)
837
771
838
-
/*
839
-
* Raw byte wise transfer from a buffer surface into another surface
840
-
* of the requested box. Supported if 3d is enabled and SVGA_CAP_DX
841
-
* is set. This command does not take a context.
842
-
*/
843
-
typedef
844
-
#include "vmware_pack_begin.h"
845
-
struct SVGA3dCmdDXTransferFromBuffer {
846
-
SVGA3dSurfaceId srcSid;
847
-
uint32 srcOffset;
848
-
uint32 srcPitch;
849
-
uint32 srcSlicePitch;
850
-
SVGA3dSurfaceId destSid;
851
-
uint32 destSubResource;
852
-
SVGA3dBox destBox;
853
-
}
854
-
#include "vmware_pack_end.h"
855
-
SVGA3dCmdDXTransferFromBuffer; /* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER */
856
-
857
-
858
-
#define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0)
772
+
#define SVGA3D_TRANSFER_TO_BUFFER_READBACK (1 << 0)
859
773
#define SVGA3D_TRANSFER_TO_BUFFER_FLAGS_MASK (1 << 0)
860
774
typedef uint32 SVGA3dTransferToBufferFlags;
861
775
862
-
/*
863
-
* Raw byte wise transfer to a buffer surface from another surface
864
-
* of the requested box. Supported if SVGA_CAP_DX2 is set. This
865
-
* command does not take a context.
866
-
*/
867
-
typedef
868
-
#include "vmware_pack_begin.h"
869
-
struct SVGA3dCmdDXTransferToBuffer {
870
-
SVGA3dSurfaceId srcSid;
871
-
uint32 srcSubResource;
872
-
SVGA3dBox srcBox;
873
-
SVGA3dSurfaceId destSid;
874
-
uint32 destOffset;
875
-
uint32 destPitch;
876
-
uint32 destSlicePitch;
877
-
SVGA3dTransferToBufferFlags flags;
878
-
}
879
-
#include "vmware_pack_end.h"
880
-
SVGA3dCmdDXTransferToBuffer; /* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER */
776
+
#pragma pack(push, 1)
777
+
typedef struct SVGA3dCmdDXTransferToBuffer {
778
+
SVGA3dSurfaceId srcSid;
779
+
uint32 srcSubResource;
780
+
SVGA3dBox srcBox;
781
+
SVGA3dSurfaceId destSid;
782
+
uint32 destOffset;
783
+
uint32 destPitch;
784
+
uint32 destSlicePitch;
785
+
SVGA3dTransferToBufferFlags flags;
786
+
} SVGA3dCmdDXTransferToBuffer;
787
+
#pragma pack(pop)
881
788
789
+
#pragma pack(push, 1)
790
+
typedef struct SVGA3dCmdDXPredTransferFromBuffer {
791
+
SVGA3dSurfaceId srcSid;
792
+
uint32 srcOffset;
793
+
uint32 srcPitch;
794
+
uint32 srcSlicePitch;
795
+
SVGA3dSurfaceId destSid;
796
+
uint32 destSubResource;
797
+
SVGA3dBox destBox;
798
+
} SVGA3dCmdDXPredTransferFromBuffer;
799
+
#pragma pack(pop)
882
800
883
-
/*
884
-
* Raw byte wise transfer from a buffer surface into another surface
885
-
* of the requested box. Supported if SVGA3D_DEVCAP_DXCONTEXT is set.
886
-
* The context is implied from the command buffer header.
887
-
*/
888
-
typedef
889
-
#include "vmware_pack_begin.h"
890
-
struct SVGA3dCmdDXPredTransferFromBuffer {
891
-
SVGA3dSurfaceId srcSid;
892
-
uint32 srcOffset;
893
-
uint32 srcPitch;
894
-
uint32 srcSlicePitch;
895
-
SVGA3dSurfaceId destSid;
896
-
uint32 destSubResource;
897
-
SVGA3dBox destBox;
898
-
}
899
-
#include "vmware_pack_end.h"
900
-
SVGA3dCmdDXPredTransferFromBuffer;
901
-
/* SVGA_3D_CMD_DX_PRED_TRANSFER_FROM_BUFFER */
801
+
#pragma pack(push, 1)
802
+
typedef struct SVGA3dCmdDXSurfaceCopyAndReadback {
803
+
SVGA3dSurfaceId srcSid;
804
+
SVGA3dSurfaceId destSid;
805
+
SVGA3dCopyBox box;
806
+
} SVGA3dCmdDXSurfaceCopyAndReadback;
807
+
#pragma pack(pop)
902
808
903
-
904
-
typedef
905
-
#include "vmware_pack_begin.h"
906
-
struct SVGA3dCmdDXSurfaceCopyAndReadback {
907
-
SVGA3dSurfaceId srcSid;
908
-
SVGA3dSurfaceId destSid;
909
-
SVGA3dCopyBox box;
910
-
}
911
-
#include "vmware_pack_end.h"
912
-
SVGA3dCmdDXSurfaceCopyAndReadback;
913
-
/* SVGA_3D_CMD_DX_SURFACE_COPY_AND_READBACK */
914
-
915
-
/*
916
-
* SVGA_DX_HINT_NONE: Does nothing.
917
-
*
918
-
* SVGA_DX_HINT_PREFETCH_OBJECT:
919
-
* SVGA_DX_HINT_PREEVICT_OBJECT:
920
-
* Consumes a SVGAObjectRef, and hints that the host should consider
921
-
* fetching/evicting the specified object.
922
-
*
923
-
* An id of SVGA3D_INVALID_ID can be used if the guest isn't sure
924
-
* what object was affected. (For instance, if the guest knows that
925
-
* it is about to evict a DXShader, but doesn't know precisely which one,
926
-
* the device can still use this to help limit it's search, or track
927
-
* how many page-outs have happened.)
928
-
*
929
-
* SVGA_DX_HINT_PREFETCH_COBJECT:
930
-
* SVGA_DX_HINT_PREEVICT_COBJECT:
931
-
* Same as the above, except they consume an SVGACObjectRef.
932
-
*/
933
809
typedef uint32 SVGADXHintId;
934
-
#define SVGA_DX_HINT_NONE 0
935
-
#define SVGA_DX_HINT_PREFETCH_OBJECT 1
936
-
#define SVGA_DX_HINT_PREEVICT_OBJECT 2
937
-
#define SVGA_DX_HINT_PREFETCH_COBJECT 3
938
-
#define SVGA_DX_HINT_PREEVICT_COBJECT 4
939
-
#define SVGA_DX_HINT_MAX 5
810
+
#define SVGA_DX_HINT_NONE 0
811
+
#define SVGA_DX_HINT_PREFETCH_OBJECT 1
812
+
#define SVGA_DX_HINT_PREEVICT_OBJECT 2
813
+
#define SVGA_DX_HINT_PREFETCH_COBJECT 3
814
+
#define SVGA_DX_HINT_PREEVICT_COBJECT 4
815
+
#define SVGA_DX_HINT_MAX 5
940
816
941
-
typedef
942
-
#include "vmware_pack_begin.h"
943
-
struct SVGAObjectRef {
944
-
SVGAOTableType type;
945
-
uint32 id;
946
-
}
947
-
#include "vmware_pack_end.h"
948
-
SVGAObjectRef;
817
+
#pragma pack(push, 1)
818
+
typedef struct SVGAObjectRef {
819
+
SVGAOTableType type;
820
+
uint32 id;
821
+
} SVGAObjectRef;
822
+
#pragma pack(pop)
949
823
950
-
typedef
951
-
#include "vmware_pack_begin.h"
952
-
struct SVGACObjectRef {
953
-
SVGACOTableType type;
954
-
uint32 cid;
955
-
uint32 id;
956
-
}
957
-
#include "vmware_pack_end.h"
958
-
SVGACObjectRef;
824
+
#pragma pack(push, 1)
825
+
typedef struct SVGACObjectRef {
826
+
SVGACOTableType type;
827
+
uint32 cid;
828
+
uint32 id;
829
+
} SVGACObjectRef;
830
+
#pragma pack(pop)
959
831
960
-
typedef
961
-
#include "vmware_pack_begin.h"
962
-
struct SVGA3dCmdDXHint {
963
-
SVGADXHintId hintId;
832
+
#pragma pack(push, 1)
833
+
typedef struct SVGA3dCmdDXHint {
834
+
SVGADXHintId hintId;
964
835
965
-
/*
966
-
* Followed by variable sized data depending on the hintId.
967
-
*/
968
-
}
969
-
#include "vmware_pack_end.h"
970
-
SVGA3dCmdDXHint;
971
-
/* SVGA_3D_CMD_DX_HINT */
836
+
} SVGA3dCmdDXHint;
837
+
#pragma pack(pop)
972
838
973
-
typedef
974
-
#include "vmware_pack_begin.h"
975
-
struct SVGA3dCmdDXBufferUpdate {
976
-
SVGA3dSurfaceId sid;
977
-
uint32 x;
978
-
uint32 width;
979
-
}
980
-
#include "vmware_pack_end.h"
981
-
SVGA3dCmdDXBufferUpdate;
982
-
/* SVGA_3D_CMD_DX_BUFFER_UPDATE */
839
+
#pragma pack(push, 1)
840
+
typedef struct SVGA3dCmdDXBufferUpdate {
841
+
SVGA3dSurfaceId sid;
842
+
uint32 x;
843
+
uint32 width;
844
+
} SVGA3dCmdDXBufferUpdate;
845
+
#pragma pack(pop)
983
846
984
-
typedef
985
-
#include "vmware_pack_begin.h"
986
-
struct SVGA3dCmdDXSetConstantBufferOffset {
987
-
uint32 slot;
988
-
uint32 offsetInBytes;
989
-
}
990
-
#include "vmware_pack_end.h"
991
-
SVGA3dCmdDXSetConstantBufferOffset;
847
+
#pragma pack(push, 1)
848
+
typedef struct SVGA3dCmdDXSetConstantBufferOffset {
849
+
uint32 slot;
850
+
uint32 offsetInBytes;
851
+
} SVGA3dCmdDXSetConstantBufferOffset;
852
+
#pragma pack(pop)
992
853
993
854
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetVSConstantBufferOffset;
994
-
/* SVGA_3D_CMD_DX_SET_VS_CONSTANT_BUFFER_OFFSET */
995
855
996
856
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetPSConstantBufferOffset;
997
-
/* SVGA_3D_CMD_DX_SET_PS_CONSTANT_BUFFER_OFFSET */
998
857
999
858
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetGSConstantBufferOffset;
1000
-
/* SVGA_3D_CMD_DX_SET_GS_CONSTANT_BUFFER_OFFSET */
1001
859
1002
860
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetHSConstantBufferOffset;
1003
-
/* SVGA_3D_CMD_DX_SET_HS_CONSTANT_BUFFER_OFFSET */
1004
861
1005
862
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetDSConstantBufferOffset;
1006
-
/* SVGA_3D_CMD_DX_SET_DS_CONSTANT_BUFFER_OFFSET */
1007
863
1008
864
typedef SVGA3dCmdDXSetConstantBufferOffset SVGA3dCmdDXSetCSConstantBufferOffset;
1009
-
/* SVGA_3D_CMD_DX_SET_CS_CONSTANT_BUFFER_OFFSET */
1010
865
1011
-
1012
-
#define SVGA3D_BUFFEREX_SRV_RAW (1 << 0)
1013
-
#define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1)
866
+
#define SVGA3D_BUFFEREX_SRV_RAW (1 << 0)
867
+
#define SVGA3D_BUFFEREX_SRV_FLAGS_MAX (1 << 1)
1014
868
#define SVGA3D_BUFFEREX_SRV_FLAGS_MASK (SVGA3D_BUFFEREX_SRV_FLAGS_MAX - 1)
1015
869
typedef uint32 SVGA3dBufferExFlags;
1016
870
1017
-
typedef
1018
-
#include "vmware_pack_begin.h"
1019
-
struct {
1020
-
union {
1021
-
struct {
1022
-
uint32 firstElement;
1023
-
uint32 numElements;
1024
-
uint32 pad0;
1025
-
uint32 pad1;
1026
-
} buffer;
1027
-
struct {
1028
-
uint32 mostDetailedMip;
1029
-
uint32 firstArraySlice;
1030
-
uint32 mipLevels;
1031
-
uint32 arraySize;
1032
-
} tex; /* 1d, 2d, 3d, cube */
1033
-
struct {
1034
-
uint32 firstElement;
1035
-
uint32 numElements;
1036
-
SVGA3dBufferExFlags flags;
1037
-
uint32 pad0;
1038
-
} bufferex;
1039
-
};
1040
-
}
1041
-
#include "vmware_pack_end.h"
1042
-
SVGA3dShaderResourceViewDesc;
871
+
#pragma pack(push, 1)
872
+
typedef struct {
873
+
union {
874
+
struct {
875
+
uint32 firstElement;
876
+
uint32 numElements;
877
+
uint32 pad0;
878
+
uint32 pad1;
879
+
} buffer;
880
+
struct {
881
+
uint32 mostDetailedMip;
882
+
uint32 firstArraySlice;
883
+
uint32 mipLevels;
884
+
uint32 arraySize;
885
+
} tex;
886
+
struct {
887
+
uint32 firstElement;
888
+
uint32 numElements;
889
+
SVGA3dBufferExFlags flags;
890
+
uint32 pad0;
891
+
} bufferex;
892
+
};
893
+
} SVGA3dShaderResourceViewDesc;
894
+
#pragma pack(pop)
1043
895
1044
-
typedef
1045
-
#include "vmware_pack_begin.h"
1046
-
struct {
1047
-
SVGA3dSurfaceId sid;
1048
-
SVGA3dSurfaceFormat format;
1049
-
SVGA3dResourceType resourceDimension;
1050
-
SVGA3dShaderResourceViewDesc desc;
1051
-
uint32 pad;
1052
-
}
1053
-
#include "vmware_pack_end.h"
1054
-
SVGACOTableDXSRViewEntry;
896
+
#pragma pack(push, 1)
897
+
typedef struct {
898
+
SVGA3dSurfaceId sid;
899
+
SVGA3dSurfaceFormat format;
900
+
SVGA3dResourceType resourceDimension;
901
+
SVGA3dShaderResourceViewDesc desc;
902
+
uint32 pad;
903
+
} SVGACOTableDXSRViewEntry;
904
+
#pragma pack(pop)
1055
905
1056
-
typedef
1057
-
#include "vmware_pack_begin.h"
1058
-
struct SVGA3dCmdDXDefineShaderResourceView {
1059
-
SVGA3dShaderResourceViewId shaderResourceViewId;
906
+
#pragma pack(push, 1)
907
+
typedef struct SVGA3dCmdDXDefineShaderResourceView {
908
+
SVGA3dShaderResourceViewId shaderResourceViewId;
1060
909
1061
-
SVGA3dSurfaceId sid;
1062
-
SVGA3dSurfaceFormat format;
1063
-
SVGA3dResourceType resourceDimension;
910
+
SVGA3dSurfaceId sid;
911
+
SVGA3dSurfaceFormat format;
912
+
SVGA3dResourceType resourceDimension;
1064
913
1065
-
SVGA3dShaderResourceViewDesc desc;
1066
-
}
1067
-
#include "vmware_pack_end.h"
1068
-
SVGA3dCmdDXDefineShaderResourceView;
1069
-
/* SVGA_3D_CMD_DX_DEFINE_SHADERRESOURCE_VIEW */
914
+
SVGA3dShaderResourceViewDesc desc;
915
+
} SVGA3dCmdDXDefineShaderResourceView;
916
+
#pragma pack(pop)
1070
917
1071
-
typedef
1072
-
#include "vmware_pack_begin.h"
1073
-
struct SVGA3dCmdDXDestroyShaderResourceView {
1074
-
SVGA3dShaderResourceViewId shaderResourceViewId;
1075
-
}
1076
-
#include "vmware_pack_end.h"
1077
-
SVGA3dCmdDXDestroyShaderResourceView;
1078
-
/* SVGA_3D_CMD_DX_DESTROY_SHADERRESOURCE_VIEW */
918
+
#pragma pack(push, 1)
919
+
typedef struct SVGA3dCmdDXDestroyShaderResourceView {
920
+
SVGA3dShaderResourceViewId shaderResourceViewId;
921
+
} SVGA3dCmdDXDestroyShaderResourceView;
922
+
#pragma pack(pop)
1079
923
1080
-
typedef
1081
-
#include "vmware_pack_begin.h"
1082
-
struct SVGA3dRenderTargetViewDesc {
1083
-
union {
1084
-
struct {
1085
-
uint32 firstElement;
1086
-
uint32 numElements;
1087
-
uint32 padding0;
1088
-
} buffer;
1089
-
struct {
1090
-
uint32 mipSlice;
1091
-
uint32 firstArraySlice;
1092
-
uint32 arraySize;
1093
-
} tex; /* 1d, 2d, cube */
1094
-
struct {
1095
-
uint32 mipSlice;
1096
-
uint32 firstW;
1097
-
uint32 wSize;
1098
-
} tex3D;
1099
-
};
1100
-
}
1101
-
#include "vmware_pack_end.h"
1102
-
SVGA3dRenderTargetViewDesc;
924
+
#pragma pack(push, 1)
925
+
typedef struct SVGA3dRenderTargetViewDesc {
926
+
union {
927
+
struct {
928
+
uint32 firstElement;
929
+
uint32 numElements;
930
+
uint32 padding0;
931
+
} buffer;
932
+
struct {
933
+
uint32 mipSlice;
934
+
uint32 firstArraySlice;
935
+
uint32 arraySize;
936
+
} tex;
937
+
struct {
938
+
uint32 mipSlice;
939
+
uint32 firstW;
940
+
uint32 wSize;
941
+
} tex3D;
942
+
};
943
+
} SVGA3dRenderTargetViewDesc;
944
+
#pragma pack(pop)
1103
945
1104
-
typedef
1105
-
#include "vmware_pack_begin.h"
1106
-
struct {
1107
-
SVGA3dSurfaceId sid;
1108
-
SVGA3dSurfaceFormat format;
1109
-
SVGA3dResourceType resourceDimension;
1110
-
SVGA3dRenderTargetViewDesc desc;
1111
-
uint32 pad[2];
1112
-
}
1113
-
#include "vmware_pack_end.h"
1114
-
SVGACOTableDXRTViewEntry;
946
+
#pragma pack(push, 1)
947
+
typedef struct {
948
+
SVGA3dSurfaceId sid;
949
+
SVGA3dSurfaceFormat format;
950
+
SVGA3dResourceType resourceDimension;
951
+
SVGA3dRenderTargetViewDesc desc;
952
+
uint32 pad[2];
953
+
} SVGACOTableDXRTViewEntry;
954
+
#pragma pack(pop)
1115
955
1116
-
typedef
1117
-
#include "vmware_pack_begin.h"
1118
-
struct SVGA3dCmdDXDefineRenderTargetView {
1119
-
SVGA3dRenderTargetViewId renderTargetViewId;
956
+
#pragma pack(push, 1)
957
+
typedef struct SVGA3dCmdDXDefineRenderTargetView {
958
+
SVGA3dRenderTargetViewId renderTargetViewId;
1120
959
1121
-
SVGA3dSurfaceId sid;
1122
-
SVGA3dSurfaceFormat format;
1123
-
SVGA3dResourceType resourceDimension;
960
+
SVGA3dSurfaceId sid;
961
+
SVGA3dSurfaceFormat format;
962
+
SVGA3dResourceType resourceDimension;
1124
963
1125
-
SVGA3dRenderTargetViewDesc desc;
1126
-
}
1127
-
#include "vmware_pack_end.h"
1128
-
SVGA3dCmdDXDefineRenderTargetView;
1129
-
/* SVGA_3D_CMD_DX_DEFINE_RENDERTARGET_VIEW */
964
+
SVGA3dRenderTargetViewDesc desc;
965
+
} SVGA3dCmdDXDefineRenderTargetView;
966
+
#pragma pack(pop)
1130
967
1131
-
typedef
1132
-
#include "vmware_pack_begin.h"
1133
-
struct SVGA3dCmdDXDestroyRenderTargetView {
1134
-
SVGA3dRenderTargetViewId renderTargetViewId;
1135
-
}
1136
-
#include "vmware_pack_end.h"
1137
-
SVGA3dCmdDXDestroyRenderTargetView;
1138
-
/* SVGA_3D_CMD_DX_DESTROY_RENDERTARGET_VIEW */
968
+
#pragma pack(push, 1)
969
+
typedef struct SVGA3dCmdDXDestroyRenderTargetView {
970
+
SVGA3dRenderTargetViewId renderTargetViewId;
971
+
} SVGA3dCmdDXDestroyRenderTargetView;
972
+
#pragma pack(pop)
1139
973
1140
-
/*
1141
-
*/
1142
-
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
974
+
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_DEPTH 0x01
1143
975
#define SVGA3D_DXDSVIEW_CREATE_READ_ONLY_STENCIL 0x02
1144
-
#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
976
+
#define SVGA3D_DXDSVIEW_CREATE_FLAG_MASK 0x03
1145
977
typedef uint8 SVGA3DCreateDSViewFlags;
1146
978
1147
-
typedef
1148
-
#include "vmware_pack_begin.h"
1149
-
struct {
1150
-
SVGA3dSurfaceId sid;
1151
-
SVGA3dSurfaceFormat format;
1152
-
SVGA3dResourceType resourceDimension;
1153
-
uint32 mipSlice;
1154
-
uint32 firstArraySlice;
1155
-
uint32 arraySize;
1156
-
SVGA3DCreateDSViewFlags flags;
1157
-
uint8 pad0;
1158
-
uint16 pad1;
1159
-
uint32 pad2;
1160
-
}
1161
-
#include "vmware_pack_end.h"
1162
-
SVGACOTableDXDSViewEntry;
979
+
#pragma pack(push, 1)
980
+
typedef struct {
981
+
SVGA3dSurfaceId sid;
982
+
SVGA3dSurfaceFormat format;
983
+
SVGA3dResourceType resourceDimension;
984
+
uint32 mipSlice;
985
+
uint32 firstArraySlice;
986
+
uint32 arraySize;
987
+
SVGA3DCreateDSViewFlags flags;
988
+
uint8 pad0;
989
+
uint16 pad1;
990
+
uint32 pad2;
991
+
} SVGACOTableDXDSViewEntry;
992
+
#pragma pack(pop)
1163
993
1164
-
typedef
1165
-
#include "vmware_pack_begin.h"
1166
-
struct SVGA3dCmdDXDefineDepthStencilView {
1167
-
SVGA3dDepthStencilViewId depthStencilViewId;
994
+
#pragma pack(push, 1)
995
+
typedef struct SVGA3dCmdDXDefineDepthStencilView {
996
+
SVGA3dDepthStencilViewId depthStencilViewId;
1168
997
1169
-
SVGA3dSurfaceId sid;
1170
-
SVGA3dSurfaceFormat format;
1171
-
SVGA3dResourceType resourceDimension;
1172
-
uint32 mipSlice;
1173
-
uint32 firstArraySlice;
1174
-
uint32 arraySize;
1175
-
SVGA3DCreateDSViewFlags flags;
1176
-
uint8 pad0;
1177
-
uint16 pad1;
1178
-
}
1179
-
#include "vmware_pack_end.h"
1180
-
SVGA3dCmdDXDefineDepthStencilView;
1181
-
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW */
998
+
SVGA3dSurfaceId sid;
999
+
SVGA3dSurfaceFormat format;
1000
+
SVGA3dResourceType resourceDimension;
1001
+
uint32 mipSlice;
1002
+
uint32 firstArraySlice;
1003
+
uint32 arraySize;
1004
+
SVGA3DCreateDSViewFlags flags;
1005
+
uint8 pad0;
1006
+
uint16 pad1;
1007
+
} SVGA3dCmdDXDefineDepthStencilView;
1008
+
#pragma pack(pop)
1182
1009
1183
-
/*
1184
-
* Version 2 needed in order to start validating and using the flags
1185
-
* field. Unfortunately the device wasn't validating or using the
1186
-
* flags field and the driver wasn't initializing it in shipped code,
1187
-
* so a new version of the command is needed to allow that code to
1188
-
* continue to work.
1189
-
*/
1190
-
typedef
1191
-
#include "vmware_pack_begin.h"
1192
-
struct SVGA3dCmdDXDefineDepthStencilView_v2 {
1193
-
SVGA3dDepthStencilViewId depthStencilViewId;
1010
+
#pragma pack(push, 1)
1011
+
typedef struct SVGA3dCmdDXDefineDepthStencilView_v2 {
1012
+
SVGA3dDepthStencilViewId depthStencilViewId;
1194
1013
1195
-
SVGA3dSurfaceId sid;
1196
-
SVGA3dSurfaceFormat format;
1197
-
SVGA3dResourceType resourceDimension;
1198
-
uint32 mipSlice;
1199
-
uint32 firstArraySlice;
1200
-
uint32 arraySize;
1201
-
SVGA3DCreateDSViewFlags flags;
1202
-
uint8 pad0;
1203
-
uint16 pad1;
1204
-
}
1205
-
#include "vmware_pack_end.h"
1206
-
SVGA3dCmdDXDefineDepthStencilView_v2;
1207
-
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_VIEW_V2 */
1014
+
SVGA3dSurfaceId sid;
1015
+
SVGA3dSurfaceFormat format;
1016
+
SVGA3dResourceType resourceDimension;
1017
+
uint32 mipSlice;
1018
+
uint32 firstArraySlice;
1019
+
uint32 arraySize;
1020
+
SVGA3DCreateDSViewFlags flags;
1021
+
uint8 pad0;
1022
+
uint16 pad1;
1023
+
} SVGA3dCmdDXDefineDepthStencilView_v2;
1024
+
#pragma pack(pop)
1208
1025
1209
-
typedef
1210
-
#include "vmware_pack_begin.h"
1211
-
struct SVGA3dCmdDXDestroyDepthStencilView {
1212
-
SVGA3dDepthStencilViewId depthStencilViewId;
1213
-
}
1214
-
#include "vmware_pack_end.h"
1215
-
SVGA3dCmdDXDestroyDepthStencilView;
1216
-
/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_VIEW */
1026
+
#pragma pack(push, 1)
1027
+
typedef struct SVGA3dCmdDXDestroyDepthStencilView {
1028
+
SVGA3dDepthStencilViewId depthStencilViewId;
1029
+
} SVGA3dCmdDXDestroyDepthStencilView;
1030
+
#pragma pack(pop)
1217
1031
1218
-
1219
-
#define SVGA3D_UABUFFER_RAW (1 << 0)
1220
-
#define SVGA3D_UABUFFER_APPEND (1 << 1)
1032
+
#define SVGA3D_UABUFFER_RAW (1 << 0)
1033
+
#define SVGA3D_UABUFFER_APPEND (1 << 1)
1221
1034
#define SVGA3D_UABUFFER_COUNTER (1 << 2)
1222
1035
typedef uint32 SVGA3dUABufferFlags;
1223
1036
1224
-
typedef
1225
-
#include "vmware_pack_begin.h"
1226
-
struct {
1227
-
union {
1228
-
struct {
1229
-
uint32 firstElement;
1230
-
uint32 numElements;
1231
-
SVGA3dUABufferFlags flags;
1232
-
uint32 padding0;
1233
-
uint32 padding1;
1234
-
} buffer;
1235
-
struct {
1236
-
uint32 mipSlice;
1237
-
uint32 firstArraySlice;
1238
-
uint32 arraySize;
1239
-
uint32 padding0;
1240
-
uint32 padding1;
1241
-
} tex; /* 1d, 2d */
1242
-
struct {
1243
-
uint32 mipSlice;
1244
-
uint32 firstW;
1245
-
uint32 wSize;
1246
-
uint32 padding0;
1247
-
uint32 padding1;
1248
-
} tex3D;
1249
-
};
1250
-
}
1251
-
#include "vmware_pack_end.h"
1252
-
SVGA3dUAViewDesc;
1037
+
#pragma pack(push, 1)
1038
+
typedef struct {
1039
+
union {
1040
+
struct {
1041
+
uint32 firstElement;
1042
+
uint32 numElements;
1043
+
SVGA3dUABufferFlags flags;
1044
+
uint32 padding0;
1045
+
uint32 padding1;
1046
+
} buffer;
1047
+
struct {
1048
+
uint32 mipSlice;
1049
+
uint32 firstArraySlice;
1050
+
uint32 arraySize;
1051
+
uint32 padding0;
1052
+
uint32 padding1;
1053
+
} tex;
1054
+
struct {
1055
+
uint32 mipSlice;
1056
+
uint32 firstW;
1057
+
uint32 wSize;
1058
+
uint32 padding0;
1059
+
uint32 padding1;
1060
+
} tex3D;
1061
+
};
1062
+
} SVGA3dUAViewDesc;
1063
+
#pragma pack(pop)
1253
1064
1254
-
typedef
1255
-
#include "vmware_pack_begin.h"
1256
-
struct {
1257
-
SVGA3dSurfaceId sid;
1258
-
SVGA3dSurfaceFormat format;
1259
-
SVGA3dResourceType resourceDimension;
1260
-
SVGA3dUAViewDesc desc;
1261
-
uint32 structureCount;
1262
-
uint32 pad[7];
1263
-
}
1264
-
#include "vmware_pack_end.h"
1265
-
SVGACOTableDXUAViewEntry;
1065
+
#pragma pack(push, 1)
1066
+
typedef struct {
1067
+
SVGA3dSurfaceId sid;
1068
+
SVGA3dSurfaceFormat format;
1069
+
SVGA3dResourceType resourceDimension;
1070
+
SVGA3dUAViewDesc desc;
1071
+
uint32 structureCount;
1072
+
uint32 pad[7];
1073
+
} SVGACOTableDXUAViewEntry;
1074
+
#pragma pack(pop)
1266
1075
1267
-
typedef
1268
-
#include "vmware_pack_begin.h"
1269
-
struct SVGA3dCmdDXDefineUAView {
1270
-
SVGA3dUAViewId uaViewId;
1076
+
#pragma pack(push, 1)
1077
+
typedef struct SVGA3dCmdDXDefineUAView {
1078
+
SVGA3dUAViewId uaViewId;
1271
1079
1272
-
SVGA3dSurfaceId sid;
1273
-
SVGA3dSurfaceFormat format;
1274
-
SVGA3dResourceType resourceDimension;
1080
+
SVGA3dSurfaceId sid;
1081
+
SVGA3dSurfaceFormat format;
1082
+
SVGA3dResourceType resourceDimension;
1275
1083
1276
-
SVGA3dUAViewDesc desc;
1277
-
}
1278
-
#include "vmware_pack_end.h"
1279
-
SVGA3dCmdDXDefineUAView;
1280
-
/* SVGA_3D_CMD_DX_DEFINE_UA_VIEW */
1084
+
SVGA3dUAViewDesc desc;
1085
+
} SVGA3dCmdDXDefineUAView;
1086
+
#pragma pack(pop)
1281
1087
1282
-
typedef
1283
-
#include "vmware_pack_begin.h"
1284
-
struct SVGA3dCmdDXDestroyUAView {
1285
-
SVGA3dUAViewId uaViewId;
1286
-
}
1287
-
#include "vmware_pack_end.h"
1288
-
SVGA3dCmdDXDestroyUAView;
1289
-
/* SVGA_3D_CMD_DX_DESTROY_UA_VIEW */
1088
+
#pragma pack(push, 1)
1089
+
typedef struct SVGA3dCmdDXDestroyUAView {
1090
+
SVGA3dUAViewId uaViewId;
1091
+
} SVGA3dCmdDXDestroyUAView;
1092
+
#pragma pack(pop)
1290
1093
1291
-
typedef
1292
-
#include "vmware_pack_begin.h"
1293
-
struct SVGA3dCmdDXClearUAViewUint {
1294
-
SVGA3dUAViewId uaViewId;
1295
-
SVGA3dRGBAUint32 value;
1296
-
}
1297
-
#include "vmware_pack_end.h"
1298
-
SVGA3dCmdDXClearUAViewUint;
1299
-
/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_UINT */
1094
+
#pragma pack(push, 1)
1095
+
typedef struct SVGA3dCmdDXClearUAViewUint {
1096
+
SVGA3dUAViewId uaViewId;
1097
+
SVGA3dRGBAUint32 value;
1098
+
} SVGA3dCmdDXClearUAViewUint;
1099
+
#pragma pack(pop)
1300
1100
1301
-
typedef
1302
-
#include "vmware_pack_begin.h"
1303
-
struct SVGA3dCmdDXClearUAViewFloat {
1304
-
SVGA3dUAViewId uaViewId;
1305
-
SVGA3dRGBAFloat value;
1306
-
}
1307
-
#include "vmware_pack_end.h"
1308
-
SVGA3dCmdDXClearUAViewFloat;
1309
-
/* SVGA_3D_CMD_DX_CLEAR_UA_VIEW_FLOAT */
1101
+
#pragma pack(push, 1)
1102
+
typedef struct SVGA3dCmdDXClearUAViewFloat {
1103
+
SVGA3dUAViewId uaViewId;
1104
+
SVGA3dRGBAFloat value;
1105
+
} SVGA3dCmdDXClearUAViewFloat;
1106
+
#pragma pack(pop)
1310
1107
1311
-
typedef
1312
-
#include "vmware_pack_begin.h"
1313
-
struct SVGA3dCmdDXCopyStructureCount {
1314
-
SVGA3dUAViewId srcUAViewId;
1315
-
SVGA3dSurfaceId destSid;
1316
-
uint32 destByteOffset;
1317
-
}
1318
-
#include "vmware_pack_end.h"
1319
-
SVGA3dCmdDXCopyStructureCount;
1320
-
/* SVGA_3D_CMD_DX_COPY_STRUCTURE_COUNT */
1108
+
#pragma pack(push, 1)
1109
+
typedef struct SVGA3dCmdDXCopyStructureCount {
1110
+
SVGA3dUAViewId srcUAViewId;
1111
+
SVGA3dSurfaceId destSid;
1112
+
uint32 destByteOffset;
1113
+
} SVGA3dCmdDXCopyStructureCount;
1114
+
#pragma pack(pop)
1321
1115
1322
-
typedef
1323
-
#include "vmware_pack_begin.h"
1324
-
struct SVGA3dCmdDXSetStructureCount {
1325
-
SVGA3dUAViewId uaViewId;
1326
-
uint32 structureCount;
1327
-
}
1328
-
#include "vmware_pack_end.h"
1329
-
SVGA3dCmdDXSetStructureCount;
1330
-
/* SVGA_3D_CMD_DX_SET_STRUCTURE_COUNT */
1116
+
#pragma pack(push, 1)
1117
+
typedef struct SVGA3dCmdDXSetStructureCount {
1118
+
SVGA3dUAViewId uaViewId;
1119
+
uint32 structureCount;
1120
+
} SVGA3dCmdDXSetStructureCount;
1121
+
#pragma pack(pop)
1331
1122
1332
-
typedef
1333
-
#include "vmware_pack_begin.h"
1334
-
struct SVGA3dCmdDXSetUAViews {
1335
-
uint32 uavSpliceIndex;
1336
-
/* Followed by a variable number of SVGA3dUAViewId's. */
1337
-
}
1338
-
#include "vmware_pack_end.h"
1339
-
SVGA3dCmdDXSetUAViews; /* SVGA_3D_CMD_DX_SET_UA_VIEWS */
1123
+
#pragma pack(push, 1)
1124
+
typedef struct SVGA3dCmdDXSetUAViews {
1125
+
uint32 uavSpliceIndex;
1340
1126
1341
-
typedef
1342
-
#include "vmware_pack_begin.h"
1343
-
struct SVGA3dCmdDXSetCSUAViews {
1344
-
uint32 startIndex;
1345
-
/* Followed by a variable number of SVGA3dUAViewId's. */
1346
-
}
1347
-
#include "vmware_pack_end.h"
1348
-
SVGA3dCmdDXSetCSUAViews; /* SVGA_3D_CMD_DX_SET_CS_UA_VIEWS */
1127
+
} SVGA3dCmdDXSetUAViews;
1128
+
#pragma pack(pop)
1349
1129
1350
-
typedef
1351
-
#include "vmware_pack_begin.h"
1352
-
struct SVGA3dInputElementDesc {
1353
-
uint32 inputSlot;
1354
-
uint32 alignedByteOffset;
1355
-
SVGA3dSurfaceFormat format;
1356
-
SVGA3dInputClassification inputSlotClass;
1357
-
uint32 instanceDataStepRate;
1358
-
uint32 inputRegister;
1359
-
}
1360
-
#include "vmware_pack_end.h"
1361
-
SVGA3dInputElementDesc;
1130
+
#pragma pack(push, 1)
1131
+
typedef struct SVGA3dCmdDXSetCSUAViews {
1132
+
uint32 startIndex;
1362
1133
1363
-
typedef
1364
-
#include "vmware_pack_begin.h"
1365
-
struct {
1366
-
uint32 elid;
1367
-
uint32 numDescs;
1368
-
SVGA3dInputElementDesc descs[32];
1369
-
uint32 pad[62];
1370
-
}
1371
-
#include "vmware_pack_end.h"
1372
-
SVGACOTableDXElementLayoutEntry;
1134
+
} SVGA3dCmdDXSetCSUAViews;
1135
+
#pragma pack(pop)
1373
1136
1374
-
typedef
1375
-
#include "vmware_pack_begin.h"
1376
-
struct SVGA3dCmdDXDefineElementLayout {
1377
-
SVGA3dElementLayoutId elementLayoutId;
1378
-
/* Followed by a variable number of SVGA3dInputElementDesc's. */
1379
-
}
1380
-
#include "vmware_pack_end.h"
1381
-
SVGA3dCmdDXDefineElementLayout;
1382
-
/* SVGA_3D_CMD_DX_DEFINE_ELEMENTLAYOUT */
1137
+
#pragma pack(push, 1)
1138
+
typedef struct SVGA3dInputElementDesc {
1139
+
uint32 inputSlot;
1140
+
uint32 alignedByteOffset;
1141
+
SVGA3dSurfaceFormat format;
1142
+
SVGA3dInputClassification inputSlotClass;
1143
+
uint32 instanceDataStepRate;
1144
+
uint32 inputRegister;
1145
+
} SVGA3dInputElementDesc;
1146
+
#pragma pack(pop)
1383
1147
1384
-
typedef
1385
-
#include "vmware_pack_begin.h"
1386
-
struct SVGA3dCmdDXDestroyElementLayout {
1387
-
SVGA3dElementLayoutId elementLayoutId;
1388
-
}
1389
-
#include "vmware_pack_end.h"
1390
-
SVGA3dCmdDXDestroyElementLayout;
1391
-
/* SVGA_3D_CMD_DX_DESTROY_ELEMENTLAYOUT */
1148
+
#pragma pack(push, 1)
1149
+
typedef struct {
1150
+
uint32 elid;
1151
+
uint32 numDescs;
1152
+
SVGA3dInputElementDesc descs[32];
1153
+
uint32 pad[62];
1154
+
} SVGACOTableDXElementLayoutEntry;
1155
+
#pragma pack(pop)
1392
1156
1157
+
#pragma pack(push, 1)
1158
+
typedef struct SVGA3dCmdDXDefineElementLayout {
1159
+
SVGA3dElementLayoutId elementLayoutId;
1160
+
1161
+
} SVGA3dCmdDXDefineElementLayout;
1162
+
#pragma pack(pop)
1163
+
1164
+
#pragma pack(push, 1)
1165
+
typedef struct SVGA3dCmdDXDestroyElementLayout {
1166
+
SVGA3dElementLayoutId elementLayoutId;
1167
+
} SVGA3dCmdDXDestroyElementLayout;
1168
+
#pragma pack(pop)
1393
1169
1394
1170
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
1395
1171
1396
-
typedef
1397
-
#include "vmware_pack_begin.h"
1398
-
struct SVGA3dDXBlendStatePerRT {
1399
-
uint8 blendEnable;
1400
-
uint8 srcBlend;
1401
-
uint8 destBlend;
1402
-
uint8 blendOp;
1403
-
uint8 srcBlendAlpha;
1404
-
uint8 destBlendAlpha;
1405
-
uint8 blendOpAlpha;
1406
-
SVGA3dColorWriteEnable renderTargetWriteMask;
1407
-
uint8 logicOpEnable;
1408
-
uint8 logicOp;
1409
-
uint16 pad0;
1410
-
}
1411
-
#include "vmware_pack_end.h"
1412
-
SVGA3dDXBlendStatePerRT;
1172
+
#pragma pack(push, 1)
1173
+
typedef struct SVGA3dDXBlendStatePerRT {
1174
+
uint8 blendEnable;
1175
+
uint8 srcBlend;
1176
+
uint8 destBlend;
1177
+
uint8 blendOp;
1178
+
uint8 srcBlendAlpha;
1179
+
uint8 destBlendAlpha;
1180
+
uint8 blendOpAlpha;
1181
+
SVGA3dColorWriteEnable renderTargetWriteMask;
1182
+
uint8 logicOpEnable;
1183
+
uint8 logicOp;
1184
+
uint16 pad0;
1185
+
} SVGA3dDXBlendStatePerRT;
1186
+
#pragma pack(pop)
1413
1187
1414
-
typedef
1415
-
#include "vmware_pack_begin.h"
1416
-
struct {
1417
-
uint8 alphaToCoverageEnable;
1418
-
uint8 independentBlendEnable;
1419
-
uint16 pad0;
1420
-
SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
1421
-
uint32 pad1[7];
1422
-
}
1423
-
#include "vmware_pack_end.h"
1424
-
SVGACOTableDXBlendStateEntry;
1188
+
#pragma pack(push, 1)
1189
+
typedef struct {
1190
+
uint8 alphaToCoverageEnable;
1191
+
uint8 independentBlendEnable;
1192
+
uint16 pad0;
1193
+
SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS];
1194
+
uint32 pad1[7];
1195
+
} SVGACOTableDXBlendStateEntry;
1196
+
#pragma pack(pop)
1425
1197
1426
-
/*
1427
-
*/
1428
-
typedef
1429
-
#include "vmware_pack_begin.h"
1430
-
struct SVGA3dCmdDXDefineBlendState {
1431
-
SVGA3dBlendStateId blendId;
1432
-
uint8 alphaToCoverageEnable;
1433
-
uint8 independentBlendEnable;
1434
-
uint16 pad0;
1435
-
SVGA3dDXBlendStatePerRT perRT[SVGA3D_MAX_RENDER_TARGETS];
1436
-
}
1437
-
#include "vmware_pack_end.h"
1438
-
SVGA3dCmdDXDefineBlendState; /* SVGA_3D_CMD_DX_DEFINE_BLEND_STATE */
1198
+
#pragma pack(push, 1)
1199
+
typedef struct SVGA3dCmdDXDefineBlendState {
1200
+
SVGA3dBlendStateId blendId;
1201
+
uint8 alphaToCoverageEnable;
1202
+
uint8 independentBlendEnable;
1203
+
uint16 pad0;
1204
+
SVGA3dDXBlendStatePerRT perRT[SVGA3D_DX_MAX_RENDER_TARGETS];
1205
+
} SVGA3dCmdDXDefineBlendState;
1206
+
#pragma pack(pop)
1439
1207
1440
-
typedef
1441
-
#include "vmware_pack_begin.h"
1442
-
struct SVGA3dCmdDXDestroyBlendState {
1443
-
SVGA3dBlendStateId blendId;
1444
-
}
1445
-
#include "vmware_pack_end.h"
1446
-
SVGA3dCmdDXDestroyBlendState; /* SVGA_3D_CMD_DX_DESTROY_BLEND_STATE */
1208
+
#pragma pack(push, 1)
1209
+
typedef struct SVGA3dCmdDXDestroyBlendState {
1210
+
SVGA3dBlendStateId blendId;
1211
+
} SVGA3dCmdDXDestroyBlendState;
1212
+
#pragma pack(pop)
1447
1213
1448
-
typedef
1449
-
#include "vmware_pack_begin.h"
1450
-
struct {
1451
-
uint8 depthEnable;
1452
-
SVGA3dDepthWriteMask depthWriteMask;
1453
-
SVGA3dComparisonFunc depthFunc;
1454
-
uint8 stencilEnable;
1455
-
uint8 frontEnable;
1456
-
uint8 backEnable;
1457
-
uint8 stencilReadMask;
1458
-
uint8 stencilWriteMask;
1214
+
#pragma pack(push, 1)
1215
+
typedef struct {
1216
+
uint8 depthEnable;
1217
+
SVGA3dDepthWriteMask depthWriteMask;
1218
+
SVGA3dComparisonFunc depthFunc;
1219
+
uint8 stencilEnable;
1220
+
uint8 frontEnable;
1221
+
uint8 backEnable;
1222
+
uint8 stencilReadMask;
1223
+
uint8 stencilWriteMask;
1459
1224
1460
-
uint8 frontStencilFailOp;
1461
-
uint8 frontStencilDepthFailOp;
1462
-
uint8 frontStencilPassOp;
1463
-
SVGA3dComparisonFunc frontStencilFunc;
1225
+
uint8 frontStencilFailOp;
1226
+
uint8 frontStencilDepthFailOp;
1227
+
uint8 frontStencilPassOp;
1228
+
SVGA3dComparisonFunc frontStencilFunc;
1464
1229
1465
-
uint8 backStencilFailOp;
1466
-
uint8 backStencilDepthFailOp;
1467
-
uint8 backStencilPassOp;
1468
-
SVGA3dComparisonFunc backStencilFunc;
1469
-
}
1470
-
#include "vmware_pack_end.h"
1471
-
SVGACOTableDXDepthStencilEntry;
1230
+
uint8 backStencilFailOp;
1231
+
uint8 backStencilDepthFailOp;
1232
+
uint8 backStencilPassOp;
1233
+
SVGA3dComparisonFunc backStencilFunc;
1234
+
} SVGACOTableDXDepthStencilEntry;
1235
+
#pragma pack(pop)
1472
1236
1473
-
/*
1474
-
*/
1475
-
typedef
1476
-
#include "vmware_pack_begin.h"
1477
-
struct SVGA3dCmdDXDefineDepthStencilState {
1478
-
SVGA3dDepthStencilStateId depthStencilId;
1237
+
#pragma pack(push, 1)
1238
+
typedef struct SVGA3dCmdDXDefineDepthStencilState {
1239
+
SVGA3dDepthStencilStateId depthStencilId;
1479
1240
1480
-
uint8 depthEnable;
1481
-
SVGA3dDepthWriteMask depthWriteMask;
1482
-
SVGA3dComparisonFunc depthFunc;
1483
-
uint8 stencilEnable;
1484
-
uint8 frontEnable;
1485
-
uint8 backEnable;
1486
-
uint8 stencilReadMask;
1487
-
uint8 stencilWriteMask;
1241
+
uint8 depthEnable;
1242
+
SVGA3dDepthWriteMask depthWriteMask;
1243
+
SVGA3dComparisonFunc depthFunc;
1244
+
uint8 stencilEnable;
1245
+
uint8 frontEnable;
1246
+
uint8 backEnable;
1247
+
uint8 stencilReadMask;
1248
+
uint8 stencilWriteMask;
1488
1249
1489
-
uint8 frontStencilFailOp;
1490
-
uint8 frontStencilDepthFailOp;
1491
-
uint8 frontStencilPassOp;
1492
-
SVGA3dComparisonFunc frontStencilFunc;
1250
+
uint8 frontStencilFailOp;
1251
+
uint8 frontStencilDepthFailOp;
1252
+
uint8 frontStencilPassOp;
1253
+
SVGA3dComparisonFunc frontStencilFunc;
1493
1254
1494
-
uint8 backStencilFailOp;
1495
-
uint8 backStencilDepthFailOp;
1496
-
uint8 backStencilPassOp;
1497
-
SVGA3dComparisonFunc backStencilFunc;
1498
-
}
1499
-
#include "vmware_pack_end.h"
1500
-
SVGA3dCmdDXDefineDepthStencilState;
1501
-
/* SVGA_3D_CMD_DX_DEFINE_DEPTHSTENCIL_STATE */
1255
+
uint8 backStencilFailOp;
1256
+
uint8 backStencilDepthFailOp;
1257
+
uint8 backStencilPassOp;
1258
+
SVGA3dComparisonFunc backStencilFunc;
1259
+
} SVGA3dCmdDXDefineDepthStencilState;
1260
+
#pragma pack(pop)
1502
1261
1503
-
typedef
1504
-
#include "vmware_pack_begin.h"
1505
-
struct SVGA3dCmdDXDestroyDepthStencilState {
1506
-
SVGA3dDepthStencilStateId depthStencilId;
1507
-
}
1508
-
#include "vmware_pack_end.h"
1509
-
SVGA3dCmdDXDestroyDepthStencilState;
1510
-
/* SVGA_3D_CMD_DX_DESTROY_DEPTHSTENCIL_STATE */
1262
+
#pragma pack(push, 1)
1263
+
typedef struct SVGA3dCmdDXDestroyDepthStencilState {
1264
+
SVGA3dDepthStencilStateId depthStencilId;
1265
+
} SVGA3dCmdDXDestroyDepthStencilState;
1266
+
#pragma pack(pop)
1511
1267
1512
-
typedef
1513
-
#include "vmware_pack_begin.h"
1514
-
struct {
1515
-
uint8 fillMode;
1516
-
SVGA3dCullMode cullMode;
1517
-
uint8 frontCounterClockwise;
1518
-
uint8 provokingVertexLast;
1519
-
int32 depthBias;
1520
-
float depthBiasClamp;
1521
-
float slopeScaledDepthBias;
1522
-
uint8 depthClipEnable;
1523
-
uint8 scissorEnable;
1524
-
SVGA3dMultisampleRastEnable multisampleEnable;
1525
-
uint8 antialiasedLineEnable;
1526
-
float lineWidth;
1527
-
uint8 lineStippleEnable;
1528
-
uint8 lineStippleFactor;
1529
-
uint16 lineStipplePattern;
1530
-
uint8 forcedSampleCount;
1531
-
uint8 mustBeZero[3];
1532
-
}
1533
-
#include "vmware_pack_end.h"
1534
-
SVGACOTableDXRasterizerStateEntry;
1268
+
#pragma pack(push, 1)
1269
+
typedef struct {
1270
+
uint8 fillMode;
1271
+
SVGA3dCullMode cullMode;
1272
+
uint8 frontCounterClockwise;
1273
+
uint8 provokingVertexLast;
1274
+
int32 depthBias;
1275
+
float depthBiasClamp;
1276
+
float slopeScaledDepthBias;
1277
+
uint8 depthClipEnable;
1278
+
uint8 scissorEnable;
1279
+
SVGA3dMultisampleRastEnable multisampleEnable;
1280
+
uint8 antialiasedLineEnable;
1281
+
float lineWidth;
1282
+
uint8 lineStippleEnable;
1283
+
uint8 lineStippleFactor;
1284
+
uint16 lineStipplePattern;
1285
+
uint8 forcedSampleCount;
1286
+
uint8 mustBeZero[3];
1287
+
} SVGACOTableDXRasterizerStateEntry;
1288
+
#pragma pack(pop)
1535
1289
1536
-
/*
1537
-
*/
1538
-
typedef
1539
-
#include "vmware_pack_begin.h"
1540
-
struct SVGA3dCmdDXDefineRasterizerState {
1541
-
SVGA3dRasterizerStateId rasterizerId;
1290
+
#pragma pack(push, 1)
1291
+
typedef struct SVGA3dCmdDXDefineRasterizerState {
1292
+
SVGA3dRasterizerStateId rasterizerId;
1542
1293
1543
-
uint8 fillMode;
1544
-
SVGA3dCullMode cullMode;
1545
-
uint8 frontCounterClockwise;
1546
-
uint8 provokingVertexLast;
1547
-
int32 depthBias;
1548
-
float depthBiasClamp;
1549
-
float slopeScaledDepthBias;
1550
-
uint8 depthClipEnable;
1551
-
uint8 scissorEnable;
1552
-
SVGA3dMultisampleRastEnable multisampleEnable;
1553
-
uint8 antialiasedLineEnable;
1554
-
float lineWidth;
1555
-
uint8 lineStippleEnable;
1556
-
uint8 lineStippleFactor;
1557
-
uint16 lineStipplePattern;
1558
-
}
1559
-
#include "vmware_pack_end.h"
1560
-
SVGA3dCmdDXDefineRasterizerState;
1561
-
/* SVGA_3D_CMD_DX_DEFINE_RASTERIZER_STATE */
1294
+
uint8 fillMode;
1295
+
SVGA3dCullMode cullMode;
1296
+
uint8 frontCounterClockwise;
1297
+
uint8 provokingVertexLast;
1298
+
int32 depthBias;
1299
+
float depthBiasClamp;
1300
+
float slopeScaledDepthBias;
1301
+
uint8 depthClipEnable;
1302
+
uint8 scissorEnable;
1303
+
SVGA3dMultisampleRastEnable multisampleEnable;
1304
+
uint8 antialiasedLineEnable;
1305
+
float lineWidth;
1306
+
uint8 lineStippleEnable;
1307
+
uint8 lineStippleFactor;
1308
+
uint16 lineStipplePattern;
1309
+
} SVGA3dCmdDXDefineRasterizerState;
1310
+
#pragma pack(pop)
1562
1311
1563
-
typedef
1564
-
#include "vmware_pack_begin.h"
1565
-
struct SVGA3dCmdDXDestroyRasterizerState {
1566
-
SVGA3dRasterizerStateId rasterizerId;
1567
-
}
1568
-
#include "vmware_pack_end.h"
1569
-
SVGA3dCmdDXDestroyRasterizerState;
1570
-
/* SVGA_3D_CMD_DX_DESTROY_RASTERIZER_STATE */
1312
+
#pragma pack(push, 1)
1313
+
typedef struct SVGA3dCmdDXDefineRasterizerState_v2 {
1314
+
SVGA3dRasterizerStateId rasterizerId;
1571
1315
1572
-
typedef
1573
-
#include "vmware_pack_begin.h"
1574
-
struct {
1575
-
SVGA3dFilter filter;
1576
-
uint8 addressU;
1577
-
uint8 addressV;
1578
-
uint8 addressW;
1579
-
uint8 pad0;
1580
-
float mipLODBias;
1581
-
uint8 maxAnisotropy;
1582
-
SVGA3dComparisonFunc comparisonFunc;
1583
-
uint16 pad1;
1584
-
SVGA3dRGBAFloat borderColor;
1585
-
float minLOD;
1586
-
float maxLOD;
1587
-
uint32 pad2[6];
1588
-
}
1589
-
#include "vmware_pack_end.h"
1590
-
SVGACOTableDXSamplerEntry;
1316
+
uint8 fillMode;
1317
+
SVGA3dCullMode cullMode;
1318
+
uint8 frontCounterClockwise;
1319
+
uint8 provokingVertexLast;
1320
+
int32 depthBias;
1321
+
float depthBiasClamp;
1322
+
float slopeScaledDepthBias;
1323
+
uint8 depthClipEnable;
1324
+
uint8 scissorEnable;
1325
+
SVGA3dMultisampleRastEnable multisampleEnable;
1326
+
uint8 antialiasedLineEnable;
1327
+
float lineWidth;
1328
+
uint8 lineStippleEnable;
1329
+
uint8 lineStippleFactor;
1330
+
uint16 lineStipplePattern;
1331
+
uint32 forcedSampleCount;
1332
+
} SVGA3dCmdDXDefineRasterizerState_v2;
1333
+
#pragma pack(pop)
1591
1334
1592
-
/*
1593
-
*/
1594
-
typedef
1595
-
#include "vmware_pack_begin.h"
1596
-
struct SVGA3dCmdDXDefineSamplerState {
1597
-
SVGA3dSamplerId samplerId;
1598
-
SVGA3dFilter filter;
1599
-
uint8 addressU;
1600
-
uint8 addressV;
1601
-
uint8 addressW;
1602
-
uint8 pad0;
1603
-
float mipLODBias;
1604
-
uint8 maxAnisotropy;
1605
-
SVGA3dComparisonFunc comparisonFunc;
1606
-
uint16 pad1;
1607
-
SVGA3dRGBAFloat borderColor;
1608
-
float minLOD;
1609
-
float maxLOD;
1610
-
}
1611
-
#include "vmware_pack_end.h"
1612
-
SVGA3dCmdDXDefineSamplerState; /* SVGA_3D_CMD_DX_DEFINE_SAMPLER_STATE */
1335
+
#pragma pack(push, 1)
1336
+
typedef struct SVGA3dCmdDXDestroyRasterizerState {
1337
+
SVGA3dRasterizerStateId rasterizerId;
1338
+
} SVGA3dCmdDXDestroyRasterizerState;
1339
+
#pragma pack(pop)
1613
1340
1614
-
typedef
1615
-
#include "vmware_pack_begin.h"
1616
-
struct SVGA3dCmdDXDestroySamplerState {
1617
-
SVGA3dSamplerId samplerId;
1618
-
}
1619
-
#include "vmware_pack_end.h"
1620
-
SVGA3dCmdDXDestroySamplerState; /* SVGA_3D_CMD_DX_DESTROY_SAMPLER_STATE */
1341
+
#pragma pack(push, 1)
1342
+
typedef struct {
1343
+
SVGA3dFilter filter;
1344
+
uint8 addressU;
1345
+
uint8 addressV;
1346
+
uint8 addressW;
1347
+
uint8 pad0;
1348
+
float mipLODBias;
1349
+
uint8 maxAnisotropy;
1350
+
SVGA3dComparisonFunc comparisonFunc;
1351
+
uint16 pad1;
1352
+
SVGA3dRGBAFloat borderColor;
1353
+
float minLOD;
1354
+
float maxLOD;
1355
+
uint32 pad2[6];
1356
+
} SVGACOTableDXSamplerEntry;
1357
+
#pragma pack(pop)
1621
1358
1359
+
#pragma pack(push, 1)
1360
+
typedef struct SVGA3dCmdDXDefineSamplerState {
1361
+
SVGA3dSamplerId samplerId;
1362
+
SVGA3dFilter filter;
1363
+
uint8 addressU;
1364
+
uint8 addressV;
1365
+
uint8 addressW;
1366
+
uint8 pad0;
1367
+
float mipLODBias;
1368
+
uint8 maxAnisotropy;
1369
+
SVGA3dComparisonFunc comparisonFunc;
1370
+
uint16 pad1;
1371
+
SVGA3dRGBAFloat borderColor;
1372
+
float minLOD;
1373
+
float maxLOD;
1374
+
} SVGA3dCmdDXDefineSamplerState;
1375
+
#pragma pack(pop)
1622
1376
1623
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
1624
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
1625
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
1626
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
1627
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
1628
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
1629
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
1630
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
1631
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
1632
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
1633
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
1634
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
1635
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
1636
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
1637
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
1638
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
1639
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
1640
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
1641
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
1642
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
1643
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
1644
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
1645
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
1646
-
#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23
1377
+
#pragma pack(push, 1)
1378
+
typedef struct SVGA3dCmdDXDestroySamplerState {
1379
+
SVGA3dSamplerId samplerId;
1380
+
} SVGA3dCmdDXDestroySamplerState;
1381
+
#pragma pack(pop)
1382
+
1383
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_UNDEFINED 0
1384
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_POSITION 1
1385
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CLIP_DISTANCE 2
1386
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_CULL_DISTANCE 3
1387
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_RENDER_TARGET_ARRAY_INDEX 4
1388
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VIEWPORT_ARRAY_INDEX 5
1389
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_VERTEX_ID 6
1390
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_PRIMITIVE_ID 7
1391
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_INSTANCE_ID 8
1392
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_IS_FRONT_FACE 9
1393
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_SAMPLE_INDEX 10
1394
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_0_EDGE_TESSFACTOR 11
1395
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_0_EDGE_TESSFACTOR 12
1396
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_EQ_1_EDGE_TESSFACTOR 13
1397
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_EQ_1_EDGE_TESSFACTOR 14
1398
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_U_INSIDE_TESSFACTOR 15
1399
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_QUAD_V_INSIDE_TESSFACTOR 16
1400
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_U_EQ_0_EDGE_TESSFACTOR 17
1401
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_V_EQ_0_EDGE_TESSFACTOR 18
1402
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_W_EQ_0_EDGE_TESSFACTOR 19
1403
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_TRI_INSIDE_TESSFACTOR 20
1404
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DETAIL_TESSFACTOR 21
1405
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_FINAL_LINE_DENSITY_TESSFACTOR 22
1406
+
#define SVGADX_SIGNATURE_SEMANTIC_NAME_MAX 23
1647
1407
typedef uint32 SVGA3dDXSignatureSemanticName;
1648
1408
1649
1409
#define SVGADX_SIGNATURE_REGISTER_COMPONENT_UNKNOWN 0
···
1394
1670
#define SVGADX_SIGNATURE_MIN_PRECISION_DEFAULT 0
1395
1671
typedef uint32 SVGA3dDXSignatureMinPrecision;
1396
1672
1397
-
typedef
1398
-
#include "vmware_pack_begin.h"
1399
-
struct SVGA3dDXSignatureEntry {
1400
-
uint32 registerIndex;
1401
-
SVGA3dDXSignatureSemanticName semanticName;
1402
-
uint32 mask; /* Lower 4 bits represent X, Y, Z, W channels */
1403
-
SVGA3dDXSignatureRegisterComponentType componentType;
1404
-
SVGA3dDXSignatureMinPrecision minPrecision;
1405
-
}
1406
-
#include "vmware_pack_end.h"
1407
-
SVGA3dDXShaderSignatureEntry;
1673
+
#pragma pack(push, 1)
1674
+
typedef struct SVGA3dDXSignatureEntry {
1675
+
uint32 registerIndex;
1676
+
SVGA3dDXSignatureSemanticName semanticName;
1677
+
uint32 mask;
1678
+
SVGA3dDXSignatureRegisterComponentType componentType;
1679
+
SVGA3dDXSignatureMinPrecision minPrecision;
1680
+
} SVGA3dDXShaderSignatureEntry;
1681
+
#pragma pack(pop)
1408
1682
1409
1683
#define SVGADX_SIGNATURE_HEADER_VERSION_0 0x08a92d12
1410
1684
1411
-
/*
1412
-
* The SVGA3dDXSignatureHeader structure is added after the shader
1413
-
* body in the mob that is bound to the shader. It is followed by the
1414
-
* specified number of SVGA3dDXSignatureEntry structures for each of
1415
-
* the three types of signatures in the order (input, output, patch
1416
-
* constants).
1417
-
*/
1418
-
typedef
1419
-
#include "vmware_pack_begin.h"
1420
-
struct SVGA3dDXSignatureHeader {
1421
-
uint32 headerVersion;
1422
-
uint32 numInputSignatures;
1423
-
uint32 numOutputSignatures;
1424
-
uint32 numPatchConstantSignatures;
1425
-
}
1426
-
#include "vmware_pack_end.h"
1427
-
SVGA3dDXShaderSignatureHeader;
1685
+
#pragma pack(push, 1)
1686
+
typedef struct SVGA3dDXSignatureHeader {
1687
+
uint32 headerVersion;
1688
+
uint32 numInputSignatures;
1689
+
uint32 numOutputSignatures;
1690
+
uint32 numPatchConstantSignatures;
1691
+
} SVGA3dDXShaderSignatureHeader;
1692
+
#pragma pack(pop)
1428
1693
1429
-
typedef
1430
-
#include "vmware_pack_begin.h"
1431
-
struct SVGA3dCmdDXDefineShader {
1432
-
SVGA3dShaderId shaderId;
1433
-
SVGA3dShaderType type;
1434
-
uint32 sizeInBytes; /* Number of bytes of shader text. */
1435
-
}
1436
-
#include "vmware_pack_end.h"
1437
-
SVGA3dCmdDXDefineShader; /* SVGA_3D_CMD_DX_DEFINE_SHADER */
1694
+
#pragma pack(push, 1)
1695
+
typedef struct SVGA3dCmdDXDefineShader {
1696
+
SVGA3dShaderId shaderId;
1697
+
SVGA3dShaderType type;
1698
+
uint32 sizeInBytes;
1699
+
} SVGA3dCmdDXDefineShader;
1700
+
#pragma pack(pop)
1438
1701
1439
-
typedef
1440
-
#include "vmware_pack_begin.h"
1441
-
struct SVGACOTableDXShaderEntry {
1442
-
SVGA3dShaderType type;
1443
-
uint32 sizeInBytes;
1444
-
uint32 offsetInBytes;
1445
-
SVGAMobId mobid;
1446
-
uint32 pad[4];
1447
-
}
1448
-
#include "vmware_pack_end.h"
1449
-
SVGACOTableDXShaderEntry;
1702
+
#pragma pack(push, 1)
1703
+
typedef struct SVGACOTableDXShaderEntry {
1704
+
SVGA3dShaderType type;
1705
+
uint32 sizeInBytes;
1706
+
uint32 offsetInBytes;
1707
+
SVGAMobId mobid;
1708
+
uint32 pad[4];
1709
+
} SVGACOTableDXShaderEntry;
1710
+
#pragma pack(pop)
1450
1711
1451
-
typedef
1452
-
#include "vmware_pack_begin.h"
1453
-
struct SVGA3dCmdDXDestroyShader {
1454
-
SVGA3dShaderId shaderId;
1455
-
}
1456
-
#include "vmware_pack_end.h"
1457
-
SVGA3dCmdDXDestroyShader; /* SVGA_3D_CMD_DX_DESTROY_SHADER */
1712
+
#pragma pack(push, 1)
1713
+
typedef struct SVGA3dCmdDXDestroyShader {
1714
+
SVGA3dShaderId shaderId;
1715
+
} SVGA3dCmdDXDestroyShader;
1716
+
#pragma pack(pop)
1458
1717
1459
-
typedef
1460
-
#include "vmware_pack_begin.h"
1461
-
struct SVGA3dCmdDXBindShader {
1462
-
uint32 cid;
1463
-
uint32 shid;
1464
-
SVGAMobId mobid;
1465
-
uint32 offsetInBytes;
1466
-
}
1467
-
#include "vmware_pack_end.h"
1468
-
SVGA3dCmdDXBindShader; /* SVGA_3D_CMD_DX_BIND_SHADER */
1718
+
#pragma pack(push, 1)
1719
+
typedef struct SVGA3dCmdDXBindShader {
1720
+
uint32 cid;
1721
+
uint32 shid;
1722
+
SVGAMobId mobid;
1723
+
uint32 offsetInBytes;
1724
+
} SVGA3dCmdDXBindShader;
1725
+
#pragma pack(pop)
1469
1726
1470
-
typedef
1471
-
#include "vmware_pack_begin.h"
1472
-
struct SVGA3dCmdDXBindAllShader {
1473
-
uint32 cid;
1474
-
SVGAMobId mobid;
1475
-
}
1476
-
#include "vmware_pack_end.h"
1477
-
SVGA3dCmdDXBindAllShader; /* SVGA_3D_CMD_DX_BIND_ALL_SHADER */
1727
+
#pragma pack(push, 1)
1728
+
typedef struct SVGA3dCmdDXBindAllShader {
1729
+
uint32 cid;
1730
+
SVGAMobId mobid;
1731
+
} SVGA3dCmdDXBindAllShader;
1732
+
#pragma pack(pop)
1478
1733
1479
-
typedef
1480
-
#include "vmware_pack_begin.h"
1481
-
struct SVGA3dCmdDXCondBindAllShader {
1482
-
uint32 cid;
1483
-
SVGAMobId testMobid;
1484
-
SVGAMobId mobid;
1485
-
}
1486
-
#include "vmware_pack_end.h"
1487
-
SVGA3dCmdDXCondBindAllShader; /* SVGA_3D_CMD_DX_COND_BIND_ALL_SHADER */
1734
+
#pragma pack(push, 1)
1735
+
typedef struct SVGA3dCmdDXCondBindAllShader {
1736
+
uint32 cid;
1737
+
SVGAMobId testMobid;
1738
+
SVGAMobId mobid;
1739
+
} SVGA3dCmdDXCondBindAllShader;
1740
+
#pragma pack(pop)
1488
1741
1489
-
/*
1490
-
* The maximum number of streamout decl's in each streamout entry.
1491
-
*/
1492
1742
#define SVGA3D_MAX_DX10_STREAMOUT_DECLS 64
1493
1743
#define SVGA3D_MAX_STREAMOUT_DECLS 512
1494
1744
1495
-
typedef
1496
-
#include "vmware_pack_begin.h"
1497
-
struct SVGA3dStreamOutputDeclarationEntry {
1498
-
uint32 outputSlot;
1499
-
uint32 registerIndex;
1500
-
uint8 registerMask;
1501
-
uint8 pad0;
1502
-
uint16 pad1;
1503
-
uint32 stream;
1504
-
}
1505
-
#include "vmware_pack_end.h"
1506
-
SVGA3dStreamOutputDeclarationEntry;
1745
+
#pragma pack(push, 1)
1746
+
typedef struct SVGA3dStreamOutputDeclarationEntry {
1747
+
uint32 outputSlot;
1748
+
uint32 registerIndex;
1749
+
uint8 registerMask;
1750
+
uint8 pad0;
1751
+
uint16 pad1;
1752
+
uint32 stream;
1753
+
} SVGA3dStreamOutputDeclarationEntry;
1754
+
#pragma pack(pop)
1507
1755
1508
-
typedef
1509
-
#include "vmware_pack_begin.h"
1510
-
struct SVGAOTableStreamOutputEntry {
1511
-
uint32 numOutputStreamEntries;
1512
-
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
1513
-
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1514
-
uint32 rasterizedStream;
1515
-
uint32 numOutputStreamStrides;
1516
-
uint32 mobid;
1517
-
uint32 offsetInBytes;
1518
-
uint8 usesMob;
1519
-
uint8 pad0;
1520
-
uint16 pad1;
1521
-
uint32 pad2[246];
1522
-
}
1523
-
#include "vmware_pack_end.h"
1524
-
SVGACOTableDXStreamOutputEntry;
1756
+
#pragma pack(push, 1)
1757
+
typedef struct SVGAOTableStreamOutputEntry {
1758
+
uint32 numOutputStreamEntries;
1759
+
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
1760
+
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1761
+
uint32 rasterizedStream;
1762
+
uint32 numOutputStreamStrides;
1763
+
uint32 mobid;
1764
+
uint32 offsetInBytes;
1765
+
uint8 usesMob;
1766
+
uint8 pad0;
1767
+
uint16 pad1;
1768
+
uint32 pad2[246];
1769
+
} SVGACOTableDXStreamOutputEntry;
1770
+
#pragma pack(pop)
1525
1771
1526
-
typedef
1527
-
#include "vmware_pack_begin.h"
1528
-
struct SVGA3dCmdDXDefineStreamOutput {
1529
-
SVGA3dStreamOutputId soid;
1530
-
uint32 numOutputStreamEntries;
1531
-
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
1532
-
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1533
-
uint32 rasterizedStream;
1534
-
}
1535
-
#include "vmware_pack_end.h"
1536
-
SVGA3dCmdDXDefineStreamOutput; /* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT */
1537
-
1538
-
/*
1539
-
* Version 2 needed in order to start validating and using the
1540
-
* rasterizedStream field. Unfortunately the device wasn't validating
1541
-
* or using this field and the driver wasn't initializing it in shipped
1542
-
* code, so a new version of the command is needed to allow that code
1543
-
* to continue to work. Also added new numOutputStreamStrides field.
1544
-
*/
1772
+
#pragma pack(push, 1)
1773
+
typedef struct SVGA3dCmdDXDefineStreamOutput {
1774
+
SVGA3dStreamOutputId soid;
1775
+
uint32 numOutputStreamEntries;
1776
+
SVGA3dStreamOutputDeclarationEntry decl[SVGA3D_MAX_DX10_STREAMOUT_DECLS];
1777
+
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1778
+
uint32 rasterizedStream;
1779
+
} SVGA3dCmdDXDefineStreamOutput;
1780
+
#pragma pack(pop)
1545
1781
1546
1782
#define SVGA3D_DX_SO_NO_RASTERIZED_STREAM 0xFFFFFFFF
1547
1783
1548
-
typedef
1549
-
#include "vmware_pack_begin.h"
1550
-
struct SVGA3dCmdDXDefineStreamOutputWithMob {
1551
-
SVGA3dStreamOutputId soid;
1552
-
uint32 numOutputStreamEntries;
1553
-
uint32 numOutputStreamStrides;
1554
-
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1555
-
uint32 rasterizedStream;
1556
-
}
1557
-
#include "vmware_pack_end.h"
1558
-
SVGA3dCmdDXDefineStreamOutputWithMob;
1559
-
/* SVGA_3D_CMD_DX_DEFINE_STREAMOUTPUT_WITH_MOB */
1784
+
#pragma pack(push, 1)
1785
+
typedef struct SVGA3dCmdDXDefineStreamOutputWithMob {
1786
+
SVGA3dStreamOutputId soid;
1787
+
uint32 numOutputStreamEntries;
1788
+
uint32 numOutputStreamStrides;
1789
+
uint32 streamOutputStrideInBytes[SVGA3D_DX_MAX_SOTARGETS];
1790
+
uint32 rasterizedStream;
1791
+
} SVGA3dCmdDXDefineStreamOutputWithMob;
1792
+
#pragma pack(pop)
1560
1793
1561
-
typedef
1562
-
#include "vmware_pack_begin.h"
1563
-
struct SVGA3dCmdDXBindStreamOutput {
1564
-
SVGA3dStreamOutputId soid;
1565
-
uint32 mobid;
1566
-
uint32 offsetInBytes;
1567
-
uint32 sizeInBytes;
1568
-
}
1569
-
#include "vmware_pack_end.h"
1570
-
SVGA3dCmdDXBindStreamOutput; /* SVGA_3D_CMD_DX_BIND_STREAMOUTPUT */
1794
+
#pragma pack(push, 1)
1795
+
typedef struct SVGA3dCmdDXBindStreamOutput {
1796
+
SVGA3dStreamOutputId soid;
1797
+
uint32 mobid;
1798
+
uint32 offsetInBytes;
1799
+
uint32 sizeInBytes;
1800
+
} SVGA3dCmdDXBindStreamOutput;
1801
+
#pragma pack(pop)
1571
1802
1572
-
typedef
1573
-
#include "vmware_pack_begin.h"
1574
-
struct SVGA3dCmdDXDestroyStreamOutput {
1575
-
SVGA3dStreamOutputId soid;
1576
-
}
1577
-
#include "vmware_pack_end.h"
1578
-
SVGA3dCmdDXDestroyStreamOutput; /* SVGA_3D_CMD_DX_DESTROY_STREAMOUTPUT */
1803
+
#pragma pack(push, 1)
1804
+
typedef struct SVGA3dCmdDXDestroyStreamOutput {
1805
+
SVGA3dStreamOutputId soid;
1806
+
} SVGA3dCmdDXDestroyStreamOutput;
1807
+
#pragma pack(pop)
1579
1808
1580
-
typedef
1581
-
#include "vmware_pack_begin.h"
1582
-
struct SVGA3dCmdDXSetStreamOutput {
1583
-
SVGA3dStreamOutputId soid;
1584
-
}
1585
-
#include "vmware_pack_end.h"
1586
-
SVGA3dCmdDXSetStreamOutput; /* SVGA_3D_CMD_DX_SET_STREAMOUTPUT */
1809
+
#pragma pack(push, 1)
1810
+
typedef struct SVGA3dCmdDXSetStreamOutput {
1811
+
SVGA3dStreamOutputId soid;
1812
+
} SVGA3dCmdDXSetStreamOutput;
1813
+
#pragma pack(pop)
1587
1814
1588
-
typedef
1589
-
#include "vmware_pack_begin.h"
1590
-
struct SVGA3dCmdDXSetMinLOD {
1591
-
SVGA3dSurfaceId sid;
1592
-
float minLOD;
1593
-
}
1594
-
#include "vmware_pack_end.h"
1595
-
SVGA3dCmdDXSetMinLOD; /* SVGA_3D_CMD_DX_SET_MIN_LOD */
1815
+
#pragma pack(push, 1)
1816
+
typedef struct SVGA3dCmdDXSetMinLOD {
1817
+
SVGA3dSurfaceId sid;
1818
+
float minLOD;
1819
+
} SVGA3dCmdDXSetMinLOD;
1820
+
#pragma pack(pop)
1596
1821
1597
-
typedef
1598
-
#include "vmware_pack_begin.h"
1599
-
struct {
1600
-
uint64 value;
1601
-
uint32 mobId;
1602
-
uint32 mobOffset;
1603
-
}
1604
-
#include "vmware_pack_end.h"
1605
-
SVGA3dCmdDXMobFence64; /* SVGA_3D_CMD_DX_MOB_FENCE_64 */
1822
+
#pragma pack(push, 1)
1823
+
typedef struct {
1824
+
uint64 value;
1825
+
uint32 mobId;
1826
+
uint32 mobOffset;
1827
+
} SVGA3dCmdDXMobFence64;
1828
+
#pragma pack(pop)
1606
1829
1607
-
/*
1608
-
* SVGA3dCmdSetCOTable --
1609
-
*
1610
-
* This command allows the guest to bind a mob to a context-object table.
1611
-
*/
1612
-
typedef
1613
-
#include "vmware_pack_begin.h"
1614
-
struct SVGA3dCmdDXSetCOTable {
1615
-
uint32 cid;
1616
-
uint32 mobid;
1617
-
SVGACOTableType type;
1618
-
uint32 validSizeInBytes;
1619
-
}
1620
-
#include "vmware_pack_end.h"
1621
-
SVGA3dCmdDXSetCOTable; /* SVGA_3D_CMD_DX_SET_COTABLE */
1830
+
#pragma pack(push, 1)
1831
+
typedef struct SVGA3dCmdDXSetCOTable {
1832
+
uint32 cid;
1833
+
uint32 mobid;
1834
+
SVGACOTableType type;
1835
+
uint32 validSizeInBytes;
1836
+
} SVGA3dCmdDXSetCOTable;
1837
+
#pragma pack(pop)
1622
1838
1623
-
/*
1624
-
* Guests using SVGA_3D_CMD_DX_GROW_COTABLE are promising that
1625
-
* the new COTable contains the same contents as the old one, except possibly
1626
-
* for some new invalid entries at the end.
1627
-
*
1628
-
* If there is an old cotable mob bound, it also has to still be valid.
1629
-
*
1630
-
* (Otherwise, guests should use the DXSetCOTableBase command.)
1631
-
*/
1632
-
typedef
1633
-
#include "vmware_pack_begin.h"
1634
-
struct SVGA3dCmdDXGrowCOTable {
1635
-
uint32 cid;
1636
-
uint32 mobid;
1637
-
SVGACOTableType type;
1638
-
uint32 validSizeInBytes;
1639
-
}
1640
-
#include "vmware_pack_end.h"
1641
-
SVGA3dCmdDXGrowCOTable; /* SVGA_3D_CMD_DX_GROW_COTABLE */
1839
+
#pragma pack(push, 1)
1840
+
typedef struct SVGA3dCmdDXGrowCOTable {
1841
+
uint32 cid;
1842
+
uint32 mobid;
1843
+
SVGACOTableType type;
1844
+
uint32 validSizeInBytes;
1845
+
} SVGA3dCmdDXGrowCOTable;
1846
+
#pragma pack(pop)
1642
1847
1643
-
typedef
1644
-
#include "vmware_pack_begin.h"
1645
-
struct SVGA3dCmdDXReadbackCOTable {
1646
-
uint32 cid;
1647
-
SVGACOTableType type;
1648
-
}
1649
-
#include "vmware_pack_end.h"
1650
-
SVGA3dCmdDXReadbackCOTable; /* SVGA_3D_CMD_DX_READBACK_COTABLE */
1848
+
#pragma pack(push, 1)
1849
+
typedef struct SVGA3dCmdDXReadbackCOTable {
1850
+
uint32 cid;
1851
+
SVGACOTableType type;
1852
+
} SVGA3dCmdDXReadbackCOTable;
1853
+
#pragma pack(pop)
1651
1854
1652
-
typedef
1653
-
#include "vmware_pack_begin.h"
1654
-
struct SVGA3dCOTableData {
1655
-
uint32 mobid;
1656
-
}
1657
-
#include "vmware_pack_end.h"
1658
-
SVGA3dCOTableData;
1855
+
#pragma pack(push, 1)
1856
+
typedef struct SVGA3dCmdDXCopyCOTableIntoMob {
1857
+
uint32 cid;
1858
+
SVGACOTableType type;
1859
+
uint32 mobid;
1860
+
} SVGA3dCmdDXCopyCOTableIntoMob;
1861
+
#pragma pack(pop)
1659
1862
1660
-
typedef
1661
-
#include "vmware_pack_begin.h"
1662
-
struct SVGA3dBufferBinding {
1663
-
uint32 bufferId;
1664
-
uint32 stride;
1665
-
uint32 offset;
1666
-
}
1667
-
#include "vmware_pack_end.h"
1668
-
SVGA3dBufferBinding;
1863
+
#pragma pack(push, 1)
1864
+
typedef struct SVGA3dCmdDXPredStagingCopy {
1865
+
SVGA3dSurfaceId dstSid;
1866
+
SVGA3dSurfaceId srcSid;
1867
+
uint8 readback;
1868
+
uint8 unsynchronized;
1869
+
uint8 mustBeZero[2];
1669
1870
1670
-
typedef
1671
-
#include "vmware_pack_begin.h"
1672
-
struct SVGA3dConstantBufferBinding {
1673
-
uint32 sid;
1674
-
uint32 offsetInBytes;
1675
-
uint32 sizeInBytes;
1676
-
}
1677
-
#include "vmware_pack_end.h"
1678
-
SVGA3dConstantBufferBinding;
1871
+
} SVGA3dCmdDXPredStagingCopy;
1872
+
#pragma pack(pop)
1679
1873
1680
-
typedef
1681
-
#include "vmware_pack_begin.h"
1682
-
struct SVGADXInputAssemblyMobFormat {
1683
-
uint32 layoutId;
1684
-
SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
1685
-
uint32 indexBufferSid;
1686
-
uint32 pad;
1687
-
uint32 indexBufferOffset;
1688
-
uint32 indexBufferFormat;
1689
-
uint32 topology;
1690
-
}
1691
-
#include "vmware_pack_end.h"
1692
-
SVGADXInputAssemblyMobFormat;
1874
+
#pragma pack(push, 1)
1875
+
typedef struct SVGA3dCmdDXStagingCopy {
1876
+
SVGA3dSurfaceId dstSid;
1877
+
SVGA3dSurfaceId srcSid;
1878
+
uint8 readback;
1879
+
uint8 unsynchronized;
1880
+
uint8 mustBeZero[2];
1693
1881
1694
-
typedef
1695
-
#include "vmware_pack_begin.h"
1696
-
struct SVGADXContextMobFormat {
1697
-
SVGADXInputAssemblyMobFormat inputAssembly;
1882
+
} SVGA3dCmdDXStagingCopy;
1883
+
#pragma pack(pop)
1698
1884
1699
-
struct {
1700
-
uint32 blendStateId;
1701
-
uint32 blendFactor[4];
1702
-
uint32 sampleMask;
1703
-
uint32 depthStencilStateId;
1704
-
uint32 stencilRef;
1705
-
uint32 rasterizerStateId;
1706
-
uint32 depthStencilViewId;
1707
-
uint32 renderTargetViewIds[SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS];
1708
-
} renderState;
1885
+
#pragma pack(push, 1)
1886
+
typedef struct SVGA3dCOTableData {
1887
+
uint32 mobid;
1888
+
} SVGA3dCOTableData;
1889
+
#pragma pack(pop)
1709
1890
1710
-
uint32 pad0[8];
1891
+
#pragma pack(push, 1)
1892
+
typedef struct SVGA3dBufferBinding {
1893
+
uint32 bufferId;
1894
+
uint32 stride;
1895
+
uint32 offset;
1896
+
} SVGA3dBufferBinding;
1897
+
#pragma pack(pop)
1711
1898
1712
-
struct {
1713
-
uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
1714
-
uint32 soid;
1715
-
} streamOut;
1899
+
#pragma pack(push, 1)
1900
+
typedef struct SVGA3dConstantBufferBinding {
1901
+
uint32 sid;
1902
+
uint32 offsetInBytes;
1903
+
uint32 sizeInBytes;
1904
+
} SVGA3dConstantBufferBinding;
1905
+
#pragma pack(pop)
1716
1906
1717
-
uint32 pad1[10];
1907
+
#pragma pack(push, 1)
1908
+
typedef struct SVGADXInputAssemblyMobFormat {
1909
+
uint32 layoutId;
1910
+
SVGA3dBufferBinding vertexBuffers[SVGA3D_DX_MAX_VERTEXBUFFERS];
1911
+
uint32 indexBufferSid;
1912
+
uint32 pad;
1913
+
uint32 indexBufferOffset;
1914
+
uint32 indexBufferFormat;
1915
+
uint32 topology;
1916
+
} SVGADXInputAssemblyMobFormat;
1917
+
#pragma pack(pop)
1718
1918
1719
-
uint32 uavSpliceIndex;
1919
+
#pragma pack(push, 1)
1920
+
typedef struct SVGADXContextMobFormat {
1921
+
SVGADXInputAssemblyMobFormat inputAssembly;
1720
1922
1721
-
uint8 numViewports;
1722
-
uint8 numScissorRects;
1723
-
uint16 pad2[1];
1923
+
struct {
1924
+
uint32 blendStateId;
1925
+
uint32 blendFactor[4];
1926
+
uint32 sampleMask;
1927
+
uint32 depthStencilStateId;
1928
+
uint32 stencilRef;
1929
+
uint32 rasterizerStateId;
1930
+
uint32 depthStencilViewId;
1931
+
uint32 renderTargetViewIds[SVGA3D_DX_MAX_RENDER_TARGETS];
1932
+
} renderState;
1724
1933
1725
-
uint32 pad3[3];
1934
+
uint32 pad0[8];
1726
1935
1727
-
SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
1728
-
uint32 pad4[32];
1936
+
struct {
1937
+
uint32 targets[SVGA3D_DX_MAX_SOTARGETS];
1938
+
uint32 soid;
1939
+
} streamOut;
1729
1940
1730
-
SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
1731
-
uint32 pad5[64];
1941
+
uint32 pad1[10];
1732
1942
1733
-
struct {
1734
-
uint32 queryID;
1735
-
uint32 value;
1736
-
} predication;
1943
+
uint32 uavSpliceIndex;
1737
1944
1738
-
SVGAMobId shaderIfaceMobid;
1739
-
uint32 shaderIfaceOffset;
1740
-
struct {
1741
-
uint32 shaderId;
1742
-
SVGA3dConstantBufferBinding constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
1743
-
uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
1744
-
uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
1745
-
} shaderState[SVGA3D_NUM_SHADERTYPE];
1746
-
uint32 pad6[26];
1945
+
uint8 numViewports;
1946
+
uint8 numScissorRects;
1947
+
uint16 pad2[1];
1747
1948
1748
-
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
1949
+
uint32 pad3[3];
1749
1950
1750
-
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
1951
+
SVGA3dViewport viewports[SVGA3D_DX_MAX_VIEWPORTS];
1952
+
uint32 pad4[32];
1751
1953
1752
-
uint32 pad7[64];
1954
+
SVGASignedRect scissorRects[SVGA3D_DX_MAX_SCISSORRECTS];
1955
+
uint32 pad5[64];
1753
1956
1754
-
uint32 uaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
1755
-
uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
1957
+
struct {
1958
+
uint32 queryID;
1959
+
uint32 value;
1960
+
} predication;
1756
1961
1757
-
uint32 pad8[188];
1758
-
}
1759
-
#include "vmware_pack_end.h"
1760
-
SVGADXContextMobFormat;
1962
+
SVGAMobId shaderIfaceMobid;
1963
+
uint32 shaderIfaceOffset;
1964
+
struct {
1965
+
uint32 shaderId;
1966
+
SVGA3dConstantBufferBinding
1967
+
constantBuffers[SVGA3D_DX_MAX_CONSTBUFFERS];
1968
+
uint32 shaderResources[SVGA3D_DX_MAX_SRVIEWS];
1969
+
uint32 samplers[SVGA3D_DX_MAX_SAMPLERS];
1970
+
} shaderState[SVGA3D_NUM_SHADERTYPE];
1971
+
uint32 pad6[26];
1761
1972
1762
-
/*
1763
-
* There is conflicting documentation on max class instances (253 vs 256). The
1764
-
* lower value is the one used throughout the device, but since mob format is
1765
-
* more involved to increase if needed, conservatively use the higher one here.
1766
-
*/
1973
+
SVGA3dQueryId queryID[SVGA3D_MAX_QUERY];
1974
+
1975
+
SVGA3dCOTableData cotables[SVGA_COTABLE_MAX];
1976
+
1977
+
uint32 pad7[64];
1978
+
1979
+
uint32 uaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
1980
+
uint32 csuaViewIds[SVGA3D_DX11_1_MAX_UAVIEWS];
1981
+
1982
+
uint32 pad8[188];
1983
+
} SVGADXContextMobFormat;
1984
+
#pragma pack(pop)
1985
+
1767
1986
#define SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED 256
1768
1987
1769
-
typedef
1770
-
#include "vmware_pack_begin.h"
1771
-
struct SVGADXShaderIfaceMobFormat {
1772
-
struct {
1773
-
uint32 numClassInstances;
1774
-
uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
1775
-
SVGA3dIfaceData data[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
1776
-
} shaderIfaceState[SVGA3D_NUM_SHADERTYPE];
1988
+
#pragma pack(push, 1)
1989
+
typedef struct SVGADXShaderIfaceMobFormat {
1990
+
struct {
1991
+
uint32 numClassInstances;
1992
+
uint32 iface[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
1993
+
SVGA3dIfaceData data[SVGA3D_DX_MAX_CLASS_INSTANCES_PADDED];
1994
+
} shaderIfaceState[SVGA3D_NUM_SHADERTYPE];
1777
1995
1778
-
uint32 pad0[1018];
1779
-
}
1780
-
#include "vmware_pack_end.h"
1781
-
SVGADXShaderIfaceMobFormat;
1996
+
uint32 pad0[1018];
1997
+
} SVGADXShaderIfaceMobFormat;
1998
+
#pragma pack(pop)
1782
1999
1783
-
typedef
1784
-
#include "vmware_pack_begin.h"
1785
-
struct SVGA3dCmdDXTempSetContext {
1786
-
uint32 dxcid;
1787
-
}
1788
-
#include "vmware_pack_end.h"
1789
-
SVGA3dCmdDXTempSetContext; /* SVGA_3D_CMD_DX_TEMP_SET_CONTEXT */
1790
-
1791
-
#endif /* _SVGA3D_DX_H_ */
2000
+
#endif
+28
-73
drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
+28
-73
drivers/gpu/drm/vmwgfx/device_include/svga3d_limits.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 2007-2019 VMware, Inc.
2
+
* Copyright 2012-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_limits.h --
29
29
*
30
-
* SVGA 3d hardware limits
30
+
* SVGA 3d hardware limits
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_LIMITS_H_
34
36
#define _SVGA3D_LIMITS_H_
35
37
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
38
+
#define SVGA3D_HB_MAX_CONTEXT_IDS 256
39
+
#define SVGA3D_HB_MAX_SURFACE_IDS (32 * 1024)
39
40
40
-
#include "includeCheck.h"
41
+
#define SVGA3D_DX_MAX_RENDER_TARGETS 8
42
+
#define SVGA3D_DX11_MAX_UAVIEWS 8
43
+
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
44
+
#define SVGA3D_MAX_UAVIEWS (SVGA3D_DX11_1_MAX_UAVIEWS)
45
+
#define SVGA3D_DX11_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_MAX_UAVIEWS)
46
+
#define SVGA3D_DX11_1_MAX_SIMULTANEOUS_RTUAV (SVGA3D_DX11_1_MAX_UAVIEWS)
47
+
#define SVGA3D_MAX_SIMULTANEOUS_RTUAV (SVGA3D_MAX_UAVIEWS)
41
48
42
-
#define SVGA3D_NUM_CLIPPLANES 6
43
-
#define SVGA3D_MAX_CONTEXT_IDS 256
44
-
#define SVGA3D_MAX_SURFACE_IDS (32 * 1024)
45
-
46
-
/*
47
-
* While there are separate bind-points for RenderTargetViews and
48
-
* UnorderedAccessViews in a DXContext, there is in fact one shared
49
-
* semantic space that the guest-driver can use on any given draw call.
50
-
* So there are really only 8 slots that can be spilt up between them, with the
51
-
* spliceIndex controlling where the UAV's sit in the collapsed array.
52
-
*/
53
-
#define SVGA3D_MAX_RENDER_TARGETS 8
54
-
#define SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS (SVGA3D_MAX_RENDER_TARGETS)
55
-
#define SVGA3D_MAX_UAVIEWS 8
56
-
#define SVGA3D_DX11_1_MAX_UAVIEWS 64
57
-
58
-
/*
59
-
* Maximum canonical size of a surface in host-backed mode (pre-GBObjects).
60
-
*/
61
49
#define SVGA3D_HB_MAX_SURFACE_SIZE MBYTES_2_BYTES(128)
62
50
63
-
/*
64
-
* Maximum ID a shader can be assigned on a given context.
65
-
*/
66
-
#define SVGA3D_MAX_SHADERIDS 5000
67
-
/*
68
-
* Maximum number of shaders of a given type that can be defined
69
-
* (including all contexts).
70
-
*/
71
-
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
51
+
#define SVGA3D_MAX_SHADERIDS 5000
72
52
73
-
#define SVGA3D_NUM_TEXTURE_UNITS 32
74
-
#define SVGA3D_NUM_LIGHTS 8
53
+
#define SVGA3D_MAX_SIMULTANEOUS_SHADERS 20000
75
54
76
-
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
55
+
#define SVGA3D_NUM_TEXTURE_UNITS 32
56
+
#define SVGA3D_NUM_LIGHTS 8
77
57
78
-
/*
79
-
* Maximum size in dwords of shader text the SVGA device will allow.
80
-
* Currently 8 MB.
81
-
*/
58
+
#define SVGA3D_MAX_VIDEOPROCESSOR_SAMPLERS 32
59
+
82
60
#define SVGA3D_MAX_SHADER_MEMORY_BYTES (8 * 1024 * 1024)
83
-
#define SVGA3D_MAX_SHADER_MEMORY (SVGA3D_MAX_SHADER_MEMORY_BYTES / \
84
-
sizeof(uint32))
61
+
#define SVGA3D_MAX_SHADER_MEMORY \
62
+
(SVGA3D_MAX_SHADER_MEMORY_BYTES / sizeof(uint32))
85
63
86
-
/*
87
-
* The maximum value of threadGroupCount in each dimension
88
-
*/
89
64
#define SVGA3D_MAX_SHADER_THREAD_GROUPS 65535
90
65
91
-
#define SVGA3D_MAX_CLIP_PLANES 6
66
+
#define SVGA3D_MAX_CLIP_PLANES 6
92
67
93
-
/*
94
-
* This is the limit to the number of fixed-function texture
95
-
* transforms and texture coordinates we can support. It does *not*
96
-
* correspond to the number of texture image units (samplers) we
97
-
* support!
98
-
*/
99
68
#define SVGA3D_MAX_TEXTURE_COORDS 8
100
69
101
-
/*
102
-
* Number of faces in a cubemap.
103
-
*/
104
70
#define SVGA3D_MAX_SURFACE_FACES 6
105
71
106
-
/*
107
-
* Maximum number of array indexes in a GB surface (with DX enabled).
108
-
*/
109
72
#define SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE 512
110
73
#define SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE 2048
111
74
#define SVGA3D_MAX_SURFACE_ARRAYSIZE SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
112
75
113
-
/*
114
-
* The maximum number of vertex arrays we're guaranteed to support in
115
-
* SVGA_3D_CMD_DRAWPRIMITIVES.
116
-
*/
117
-
#define SVGA3D_MAX_VERTEX_ARRAYS 32
76
+
#define SVGA3D_MAX_VERTEX_ARRAYS 32
118
77
119
-
/*
120
-
* The maximum number of primitive ranges we're guaranteed to support
121
-
* in SVGA_3D_CMD_DRAWPRIMITIVES.
122
-
*/
123
78
#define SVGA3D_MAX_DRAW_PRIMITIVE_RANGES 32
124
79
125
-
/*
126
-
* The maximum number of samples that can be contained in a surface.
127
-
*/
128
80
#define SVGA3D_MAX_SAMPLES 8
129
81
130
-
#endif /* _SVGA3D_LIMITS_H_ */
82
+
#define SVGA3D_MIN_SBX_DATA_SIZE (GBYTES_2_BYTES(1))
83
+
#define SVGA3D_MAX_SBX_DATA_SIZE (GBYTES_2_BYTES(4))
84
+
85
+
#endif
+5
-10
drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
+5
-10
drivers/gpu/drm/vmwgfx/device_include/svga3d_reg.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
2
* Copyright 1998-2015 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_reg.h --
29
29
*
30
-
* SVGA 3d hardware definitions
30
+
* SVGA 3d hardware definitions
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_REG_H_
34
36
#define _SVGA3D_REG_H_
35
-
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
39
-
40
-
#include "includeCheck.h"
41
37
42
38
#include "svga_reg.h"
43
39
···
43
47
#include "svga3d_dx.h"
44
48
#include "svga3d_devcaps.h"
45
49
46
-
47
-
#endif /* _SVGA3D_REG_H_ */
50
+
#endif
+1495
-1601
drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
+1495
-1601
drivers/gpu/drm/vmwgfx/device_include/svga3d_surfacedefs.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
-
/**************************************************************************
1
+
/**********************************************************
2
+
* Copyright 2008-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
3
4
*
4
-
* Copyright 2008-2015 VMware, Inc., Palo Alto, CA., USA
5
+
* Permission is hereby granted, free of charge, to any person
6
+
* obtaining a copy of this software and associated documentation
7
+
* files (the "Software"), to deal in the Software without
8
+
* restriction, including without limitation the rights to use, copy,
9
+
* modify, merge, publish, distribute, sublicense, and/or sell copies
10
+
* of the Software, and to permit persons to whom the Software is
11
+
* furnished to do so, subject to the following conditions:
5
12
*
6
-
* Permission is hereby granted, free of charge, to any person obtaining a
7
-
* copy of this software and associated documentation files (the
8
-
* "Software"), to deal in the Software without restriction, including
9
-
* without limitation the rights to use, copy, modify, merge, publish,
10
-
* distribute, sub license, and/or sell copies of the Software, and to
11
-
* permit persons to whom the Software is furnished to do so, subject to
12
-
* the following conditions:
13
+
* The above copyright notice and this permission notice shall be
14
+
* included in all copies or substantial portions of the Software.
13
15
*
14
-
* The above copyright notice and this permission notice (including the
15
-
* next paragraph) shall be included in all copies or substantial portions
16
-
* of the Software.
16
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
+
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
20
+
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
21
+
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22
+
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23
+
* SOFTWARE.
17
24
*
18
-
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19
-
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20
-
* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21
-
* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22
-
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23
-
* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24
-
* USE OR OTHER DEALINGS IN THE SOFTWARE.
25
-
*
26
-
**************************************************************************/
25
+
**********************************************************/
27
26
28
27
/*
29
28
* svga3d_surfacedefs.h --
30
29
*
31
-
* Surface definitions and inlineable utilities for SVGA3d.
30
+
* Surface definitions for SVGA3d.
32
31
*/
32
+
33
+
33
34
34
35
#ifndef _SVGA3D_SURFACEDEFS_H_
35
36
#define _SVGA3D_SURFACEDEFS_H_
36
37
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_MODULE
39
-
#include "includeCheck.h"
38
+
#include "svga3d_types.h"
40
39
41
-
#include <linux/kernel.h>
42
-
#include <drm/vmwgfx_drm.h>
40
+
#ifdef __cplusplus
41
+
extern "C" {
42
+
#endif
43
43
44
-
#include "svga3d_reg.h"
44
+
struct SVGAUseCaps;
45
45
46
-
#define surf_size_struct struct drm_vmw_size
46
+
#if defined(_WIN32) && !defined(__GNUC__)
47
47
48
-
/*
49
-
* enum svga3d_block_desc - describes generic properties about formats.
50
-
*/
51
-
enum svga3d_block_desc {
52
-
/* Nothing special can be said about this format. */
53
-
SVGA3DBLOCKDESC_NONE = 0,
48
+
#define STATIC_CONST __declspec(selectany) extern const
49
+
#else
50
+
#define STATIC_CONST static const
51
+
#endif
54
52
55
-
/* Format contains Blue/U data */
56
-
SVGA3DBLOCKDESC_BLUE = 1 << 0,
57
-
SVGA3DBLOCKDESC_W = 1 << 0,
58
-
SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
53
+
typedef enum SVGA3dBlockDesc {
59
54
60
-
/* Format contains Green/V data */
61
-
SVGA3DBLOCKDESC_GREEN = 1 << 1,
62
-
SVGA3DBLOCKDESC_V = 1 << 1,
55
+
SVGA3DBLOCKDESC_NONE = 0,
63
56
64
-
/* Format contains Red/W/Luminance data */
65
-
SVGA3DBLOCKDESC_RED = 1 << 2,
66
-
SVGA3DBLOCKDESC_U = 1 << 2,
67
-
SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
57
+
SVGA3DBLOCKDESC_BLUE = 1 << 0,
58
+
SVGA3DBLOCKDESC_W = 1 << 0,
59
+
SVGA3DBLOCKDESC_BUMP_L = 1 << 0,
68
60
69
-
/* Format contains Alpha/Q data */
70
-
SVGA3DBLOCKDESC_ALPHA = 1 << 3,
71
-
SVGA3DBLOCKDESC_Q = 1 << 3,
61
+
SVGA3DBLOCKDESC_GREEN = 1 << 1,
62
+
SVGA3DBLOCKDESC_V = 1 << 1,
72
63
73
-
/* Format is a buffer */
74
-
SVGA3DBLOCKDESC_BUFFER = 1 << 4,
64
+
SVGA3DBLOCKDESC_RED = 1 << 2,
65
+
SVGA3DBLOCKDESC_U = 1 << 2,
66
+
SVGA3DBLOCKDESC_LUMINANCE = 1 << 2,
75
67
76
-
/* Format is compressed */
77
-
SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
68
+
SVGA3DBLOCKDESC_ALPHA = 1 << 3,
69
+
SVGA3DBLOCKDESC_Q = 1 << 3,
78
70
79
-
/* Format uses IEEE floating point */
80
-
SVGA3DBLOCKDESC_FP = 1 << 6,
71
+
SVGA3DBLOCKDESC_BUFFER = 1 << 4,
81
72
82
-
/* Three separate blocks store data. */
83
-
SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
73
+
SVGA3DBLOCKDESC_COMPRESSED = 1 << 5,
84
74
85
-
/* 2 planes of Y, UV, e.g., NV12. */
75
+
SVGA3DBLOCKDESC_FP = 1 << 6,
76
+
77
+
SVGA3DBLOCKDESC_PLANAR_YUV = 1 << 7,
78
+
86
79
SVGA3DBLOCKDESC_2PLANAR_YUV = 1 << 8,
87
80
88
-
/* 3 planes of separate Y, U, V, e.g., YV12. */
89
81
SVGA3DBLOCKDESC_3PLANAR_YUV = 1 << 9,
90
82
91
-
/* Block with a stencil channel */
92
-
SVGA3DBLOCKDESC_STENCIL = 1 << 11,
83
+
SVGA3DBLOCKDESC_STENCIL = 1 << 11,
93
84
94
-
/* Typeless format */
95
-
SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
85
+
SVGA3DBLOCKDESC_TYPELESS = 1 << 12,
96
86
97
-
/* Channels are signed integers */
98
-
SVGA3DBLOCKDESC_SINT = 1 << 13,
87
+
SVGA3DBLOCKDESC_SINT = 1 << 13,
99
88
100
-
/* Channels are unsigned integers */
101
-
SVGA3DBLOCKDESC_UINT = 1 << 14,
89
+
SVGA3DBLOCKDESC_UINT = 1 << 14,
102
90
103
-
/* Channels are normalized (when sampling) */
104
-
SVGA3DBLOCKDESC_NORM = 1 << 15,
91
+
SVGA3DBLOCKDESC_NORM = 1 << 15,
105
92
106
-
/* Channels are in SRGB */
107
-
SVGA3DBLOCKDESC_SRGB = 1 << 16,
93
+
SVGA3DBLOCKDESC_SRGB = 1 << 16,
108
94
109
-
/* Shared exponent */
110
-
SVGA3DBLOCKDESC_EXP = 1 << 17,
95
+
SVGA3DBLOCKDESC_EXP = 1 << 17,
111
96
112
-
/* Format contains color data. */
113
-
SVGA3DBLOCKDESC_COLOR = 1 << 18,
114
-
/* Format contains depth data. */
115
-
SVGA3DBLOCKDESC_DEPTH = 1 << 19,
116
-
/* Format contains bump data. */
117
-
SVGA3DBLOCKDESC_BUMP = 1 << 20,
97
+
SVGA3DBLOCKDESC_COLOR = 1 << 18,
118
98
119
-
/* Format contains YUV video data. */
120
-
SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
99
+
SVGA3DBLOCKDESC_DEPTH = 1 << 19,
121
100
122
-
/* For mixed unsigned/signed formats. */
123
-
SVGA3DBLOCKDESC_MIXED = 1 << 22,
101
+
SVGA3DBLOCKDESC_BUMP = 1 << 20,
124
102
125
-
/* For distingushing CxV8U8. */
126
-
SVGA3DBLOCKDESC_CX = 1 << 23,
103
+
SVGA3DBLOCKDESC_YUV_VIDEO = 1 << 21,
127
104
128
-
/* Different compressed format groups. */
129
-
SVGA3DBLOCKDESC_BC1 = 1 << 24,
130
-
SVGA3DBLOCKDESC_BC2 = 1 << 25,
131
-
SVGA3DBLOCKDESC_BC3 = 1 << 26,
132
-
SVGA3DBLOCKDESC_BC4 = 1 << 27,
133
-
SVGA3DBLOCKDESC_BC5 = 1 << 28,
134
-
SVGA3DBLOCKDESC_BC6H = 1 << 29,
135
-
SVGA3DBLOCKDESC_BC7 = 1 << 30,
105
+
SVGA3DBLOCKDESC_MIXED = 1 << 22,
136
106
137
-
SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA |
138
-
SVGA3DBLOCKDESC_UINT |
139
-
SVGA3DBLOCKDESC_COLOR,
140
-
SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT |
141
-
SVGA3DBLOCKDESC_NORM,
142
-
SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED |
143
-
SVGA3DBLOCKDESC_UINT |
144
-
SVGA3DBLOCKDESC_COLOR,
145
-
SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT |
146
-
SVGA3DBLOCKDESC_NORM,
147
-
SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED |
148
-
SVGA3DBLOCKDESC_SINT |
149
-
SVGA3DBLOCKDESC_COLOR,
150
-
SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT |
151
-
SVGA3DBLOCKDESC_NORM,
152
-
SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN |
153
-
SVGA3DBLOCKDESC_UINT |
154
-
SVGA3DBLOCKDESC_COLOR,
155
-
SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED |
156
-
SVGA3DBLOCKDESC_GREEN |
157
-
SVGA3DBLOCKDESC_UINT |
158
-
SVGA3DBLOCKDESC_COLOR,
159
-
SVGA3DBLOCKDESC_RG_UNORM = SVGA3DBLOCKDESC_RG_UINT |
160
-
SVGA3DBLOCKDESC_NORM,
161
-
SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED |
162
-
SVGA3DBLOCKDESC_GREEN |
163
-
SVGA3DBLOCKDESC_SINT |
164
-
SVGA3DBLOCKDESC_COLOR,
165
-
SVGA3DBLOCKDESC_RG_SNORM = SVGA3DBLOCKDESC_RG_SINT |
166
-
SVGA3DBLOCKDESC_NORM,
167
-
SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED |
168
-
SVGA3DBLOCKDESC_GREEN |
169
-
SVGA3DBLOCKDESC_BLUE |
170
-
SVGA3DBLOCKDESC_UINT |
171
-
SVGA3DBLOCKDESC_COLOR,
172
-
SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED |
173
-
SVGA3DBLOCKDESC_GREEN |
174
-
SVGA3DBLOCKDESC_BLUE |
175
-
SVGA3DBLOCKDESC_SINT |
176
-
SVGA3DBLOCKDESC_COLOR,
177
-
SVGA3DBLOCKDESC_RGB_UNORM = SVGA3DBLOCKDESC_RGB_UINT |
178
-
SVGA3DBLOCKDESC_NORM,
179
-
SVGA3DBLOCKDESC_RGB_UNORM_SRGB = SVGA3DBLOCKDESC_RGB_UNORM |
180
-
SVGA3DBLOCKDESC_SRGB,
181
-
SVGA3DBLOCKDESC_RGBA_UINT = SVGA3DBLOCKDESC_RED |
182
-
SVGA3DBLOCKDESC_GREEN |
183
-
SVGA3DBLOCKDESC_BLUE |
184
-
SVGA3DBLOCKDESC_ALPHA |
185
-
SVGA3DBLOCKDESC_UINT |
186
-
SVGA3DBLOCKDESC_COLOR,
187
-
SVGA3DBLOCKDESC_RGBA_UNORM = SVGA3DBLOCKDESC_RGBA_UINT |
188
-
SVGA3DBLOCKDESC_NORM,
189
-
SVGA3DBLOCKDESC_RGBA_UNORM_SRGB = SVGA3DBLOCKDESC_RGBA_UNORM |
190
-
SVGA3DBLOCKDESC_SRGB,
191
-
SVGA3DBLOCKDESC_RGBA_SINT = SVGA3DBLOCKDESC_RED |
192
-
SVGA3DBLOCKDESC_GREEN |
193
-
SVGA3DBLOCKDESC_BLUE |
194
-
SVGA3DBLOCKDESC_ALPHA |
195
-
SVGA3DBLOCKDESC_SINT |
196
-
SVGA3DBLOCKDESC_COLOR,
197
-
SVGA3DBLOCKDESC_RGBA_SNORM = SVGA3DBLOCKDESC_RGBA_SINT |
198
-
SVGA3DBLOCKDESC_NORM,
199
-
SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED |
200
-
SVGA3DBLOCKDESC_GREEN |
201
-
SVGA3DBLOCKDESC_BLUE |
202
-
SVGA3DBLOCKDESC_ALPHA |
203
-
SVGA3DBLOCKDESC_FP |
204
-
SVGA3DBLOCKDESC_COLOR,
205
-
SVGA3DBLOCKDESC_UV = SVGA3DBLOCKDESC_U |
206
-
SVGA3DBLOCKDESC_V |
207
-
SVGA3DBLOCKDESC_BUMP,
208
-
SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV |
209
-
SVGA3DBLOCKDESC_BUMP_L |
210
-
SVGA3DBLOCKDESC_MIXED |
211
-
SVGA3DBLOCKDESC_BUMP,
212
-
SVGA3DBLOCKDESC_UVW = SVGA3DBLOCKDESC_UV |
213
-
SVGA3DBLOCKDESC_W |
214
-
SVGA3DBLOCKDESC_BUMP,
215
-
SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW |
216
-
SVGA3DBLOCKDESC_ALPHA |
217
-
SVGA3DBLOCKDESC_MIXED |
218
-
SVGA3DBLOCKDESC_BUMP,
219
-
SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U |
220
-
SVGA3DBLOCKDESC_V |
221
-
SVGA3DBLOCKDESC_W |
222
-
SVGA3DBLOCKDESC_Q |
223
-
SVGA3DBLOCKDESC_BUMP,
224
-
SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
225
-
SVGA3DBLOCKDESC_UINT |
226
-
SVGA3DBLOCKDESC_NORM |
227
-
SVGA3DBLOCKDESC_COLOR,
228
-
SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
229
-
SVGA3DBLOCKDESC_ALPHA |
230
-
SVGA3DBLOCKDESC_UINT |
231
-
SVGA3DBLOCKDESC_NORM |
232
-
SVGA3DBLOCKDESC_COLOR,
233
-
SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED |
234
-
SVGA3DBLOCKDESC_FP |
235
-
SVGA3DBLOCKDESC_COLOR,
236
-
SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP |
237
-
SVGA3DBLOCKDESC_GREEN |
238
-
SVGA3DBLOCKDESC_COLOR,
239
-
SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP |
240
-
SVGA3DBLOCKDESC_BLUE |
241
-
SVGA3DBLOCKDESC_COLOR,
242
-
SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO |
243
-
SVGA3DBLOCKDESC_COLOR,
244
-
SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
245
-
SVGA3DBLOCKDESC_YUV_VIDEO |
246
-
SVGA3DBLOCKDESC_COLOR,
247
-
SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED |
248
-
SVGA3DBLOCKDESC_GREEN |
249
-
SVGA3DBLOCKDESC_BLUE |
250
-
SVGA3DBLOCKDESC_EXP |
251
-
SVGA3DBLOCKDESC_COLOR,
107
+
SVGA3DBLOCKDESC_CX = 1 << 23,
252
108
253
-
SVGA3DBLOCKDESC_COMP_TYPELESS = SVGA3DBLOCKDESC_COMPRESSED |
254
-
SVGA3DBLOCKDESC_TYPELESS,
255
-
SVGA3DBLOCKDESC_COMP_UNORM = SVGA3DBLOCKDESC_COMPRESSED |
256
-
SVGA3DBLOCKDESC_UINT |
257
-
SVGA3DBLOCKDESC_NORM |
258
-
SVGA3DBLOCKDESC_COLOR,
259
-
SVGA3DBLOCKDESC_COMP_SNORM = SVGA3DBLOCKDESC_COMPRESSED |
260
-
SVGA3DBLOCKDESC_SINT |
261
-
SVGA3DBLOCKDESC_NORM |
262
-
SVGA3DBLOCKDESC_COLOR,
263
-
SVGA3DBLOCKDESC_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_COMP_UNORM |
264
-
SVGA3DBLOCKDESC_SRGB,
265
-
SVGA3DBLOCKDESC_BC1_COMP_TYPELESS = SVGA3DBLOCKDESC_BC1 |
266
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
267
-
SVGA3DBLOCKDESC_BC1_COMP_UNORM = SVGA3DBLOCKDESC_BC1 |
268
-
SVGA3DBLOCKDESC_COMP_UNORM,
269
-
SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC1_COMP_UNORM |
270
-
SVGA3DBLOCKDESC_SRGB,
271
-
SVGA3DBLOCKDESC_BC2_COMP_TYPELESS = SVGA3DBLOCKDESC_BC2 |
272
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
273
-
SVGA3DBLOCKDESC_BC2_COMP_UNORM = SVGA3DBLOCKDESC_BC2 |
274
-
SVGA3DBLOCKDESC_COMP_UNORM,
275
-
SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC2_COMP_UNORM |
276
-
SVGA3DBLOCKDESC_SRGB,
277
-
SVGA3DBLOCKDESC_BC3_COMP_TYPELESS = SVGA3DBLOCKDESC_BC3 |
278
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
279
-
SVGA3DBLOCKDESC_BC3_COMP_UNORM = SVGA3DBLOCKDESC_BC3 |
280
-
SVGA3DBLOCKDESC_COMP_UNORM,
281
-
SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC3_COMP_UNORM |
282
-
SVGA3DBLOCKDESC_SRGB,
283
-
SVGA3DBLOCKDESC_BC4_COMP_TYPELESS = SVGA3DBLOCKDESC_BC4 |
284
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
285
-
SVGA3DBLOCKDESC_BC4_COMP_UNORM = SVGA3DBLOCKDESC_BC4 |
286
-
SVGA3DBLOCKDESC_COMP_UNORM,
287
-
SVGA3DBLOCKDESC_BC4_COMP_SNORM = SVGA3DBLOCKDESC_BC4 |
288
-
SVGA3DBLOCKDESC_COMP_SNORM,
289
-
SVGA3DBLOCKDESC_BC5_COMP_TYPELESS = SVGA3DBLOCKDESC_BC5 |
290
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
291
-
SVGA3DBLOCKDESC_BC5_COMP_UNORM = SVGA3DBLOCKDESC_BC5 |
292
-
SVGA3DBLOCKDESC_COMP_UNORM,
293
-
SVGA3DBLOCKDESC_BC5_COMP_SNORM = SVGA3DBLOCKDESC_BC5 |
294
-
SVGA3DBLOCKDESC_COMP_SNORM,
295
-
SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS = SVGA3DBLOCKDESC_BC6H |
296
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
297
-
SVGA3DBLOCKDESC_BC6H_COMP_UF16 = SVGA3DBLOCKDESC_BC6H |
298
-
SVGA3DBLOCKDESC_COMPRESSED,
299
-
SVGA3DBLOCKDESC_BC6H_COMP_SF16 = SVGA3DBLOCKDESC_BC6H |
300
-
SVGA3DBLOCKDESC_COMPRESSED,
301
-
SVGA3DBLOCKDESC_BC7_COMP_TYPELESS = SVGA3DBLOCKDESC_BC7 |
302
-
SVGA3DBLOCKDESC_COMP_TYPELESS,
303
-
SVGA3DBLOCKDESC_BC7_COMP_UNORM = SVGA3DBLOCKDESC_BC7 |
304
-
SVGA3DBLOCKDESC_COMP_UNORM,
305
-
SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB = SVGA3DBLOCKDESC_BC7_COMP_UNORM |
306
-
SVGA3DBLOCKDESC_SRGB,
109
+
SVGA3DBLOCKDESC_BC1 = 1 << 24,
110
+
SVGA3DBLOCKDESC_BC2 = 1 << 25,
111
+
SVGA3DBLOCKDESC_BC3 = 1 << 26,
112
+
SVGA3DBLOCKDESC_BC4 = 1 << 27,
113
+
SVGA3DBLOCKDESC_BC5 = 1 << 28,
114
+
SVGA3DBLOCKDESC_BC6H = 1 << 29,
115
+
SVGA3DBLOCKDESC_BC7 = 1 << 30,
116
+
SVGA3DBLOCKDESC_COMPRESSED_MASK =
117
+
SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_BC2 |
118
+
SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_BC4 |
119
+
SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_BC6H |
120
+
SVGA3DBLOCKDESC_BC7,
307
121
308
-
SVGA3DBLOCKDESC_NV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
309
-
SVGA3DBLOCKDESC_PLANAR_YUV |
310
-
SVGA3DBLOCKDESC_2PLANAR_YUV |
311
-
SVGA3DBLOCKDESC_COLOR,
312
-
SVGA3DBLOCKDESC_YV12 = SVGA3DBLOCKDESC_YUV_VIDEO |
313
-
SVGA3DBLOCKDESC_PLANAR_YUV |
314
-
SVGA3DBLOCKDESC_3PLANAR_YUV |
315
-
SVGA3DBLOCKDESC_COLOR,
122
+
SVGA3DBLOCKDESC_A_UINT = SVGA3DBLOCKDESC_ALPHA | SVGA3DBLOCKDESC_UINT |
123
+
SVGA3DBLOCKDESC_COLOR,
124
+
SVGA3DBLOCKDESC_A_UNORM = SVGA3DBLOCKDESC_A_UINT | SVGA3DBLOCKDESC_NORM,
125
+
SVGA3DBLOCKDESC_R_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_UINT |
126
+
SVGA3DBLOCKDESC_COLOR,
127
+
SVGA3DBLOCKDESC_R_UNORM = SVGA3DBLOCKDESC_R_UINT | SVGA3DBLOCKDESC_NORM,
128
+
SVGA3DBLOCKDESC_R_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_SINT |
129
+
SVGA3DBLOCKDESC_COLOR,
130
+
SVGA3DBLOCKDESC_R_SNORM = SVGA3DBLOCKDESC_R_SINT | SVGA3DBLOCKDESC_NORM,
131
+
SVGA3DBLOCKDESC_G_UINT = SVGA3DBLOCKDESC_GREEN | SVGA3DBLOCKDESC_UINT |
132
+
SVGA3DBLOCKDESC_COLOR,
133
+
SVGA3DBLOCKDESC_RG_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
134
+
SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR,
135
+
SVGA3DBLOCKDESC_RG_UNORM =
136
+
SVGA3DBLOCKDESC_RG_UINT | SVGA3DBLOCKDESC_NORM,
137
+
SVGA3DBLOCKDESC_RG_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
138
+
SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR,
139
+
SVGA3DBLOCKDESC_RG_SNORM =
140
+
SVGA3DBLOCKDESC_RG_SINT | SVGA3DBLOCKDESC_NORM,
141
+
SVGA3DBLOCKDESC_RGB_UINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
142
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_UINT |
143
+
SVGA3DBLOCKDESC_COLOR,
144
+
SVGA3DBLOCKDESC_RGB_SINT = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
145
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_SINT |
146
+
SVGA3DBLOCKDESC_COLOR,
147
+
SVGA3DBLOCKDESC_RGB_UNORM =
148
+
SVGA3DBLOCKDESC_RGB_UINT | SVGA3DBLOCKDESC_NORM,
149
+
SVGA3DBLOCKDESC_RGB_UNORM_SRGB =
150
+
SVGA3DBLOCKDESC_RGB_UNORM | SVGA3DBLOCKDESC_SRGB,
151
+
SVGA3DBLOCKDESC_RGBA_UINT =
152
+
SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
153
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
154
+
SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_COLOR,
155
+
SVGA3DBLOCKDESC_RGBA_UNORM =
156
+
SVGA3DBLOCKDESC_RGBA_UINT | SVGA3DBLOCKDESC_NORM,
157
+
SVGA3DBLOCKDESC_RGBA_UNORM_SRGB =
158
+
SVGA3DBLOCKDESC_RGBA_UNORM | SVGA3DBLOCKDESC_SRGB,
159
+
SVGA3DBLOCKDESC_RGBA_SINT =
160
+
SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
161
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
162
+
SVGA3DBLOCKDESC_SINT | SVGA3DBLOCKDESC_COLOR,
163
+
SVGA3DBLOCKDESC_RGBA_SNORM =
164
+
SVGA3DBLOCKDESC_RGBA_SINT | SVGA3DBLOCKDESC_NORM,
165
+
SVGA3DBLOCKDESC_RGBA_FP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
166
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_ALPHA |
167
+
SVGA3DBLOCKDESC_FP | SVGA3DBLOCKDESC_COLOR,
168
+
SVGA3DBLOCKDESC_UV =
169
+
SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V | SVGA3DBLOCKDESC_BUMP,
170
+
SVGA3DBLOCKDESC_UVL = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_BUMP_L |
171
+
SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP,
172
+
SVGA3DBLOCKDESC_UVW =
173
+
SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_BUMP,
174
+
SVGA3DBLOCKDESC_UVWA = SVGA3DBLOCKDESC_UVW | SVGA3DBLOCKDESC_ALPHA |
175
+
SVGA3DBLOCKDESC_MIXED | SVGA3DBLOCKDESC_BUMP,
176
+
SVGA3DBLOCKDESC_UVWQ = SVGA3DBLOCKDESC_U | SVGA3DBLOCKDESC_V |
177
+
SVGA3DBLOCKDESC_W | SVGA3DBLOCKDESC_Q |
178
+
SVGA3DBLOCKDESC_BUMP,
179
+
SVGA3DBLOCKDESC_L_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
180
+
SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_NORM |
181
+
SVGA3DBLOCKDESC_COLOR,
182
+
SVGA3DBLOCKDESC_LA_UNORM = SVGA3DBLOCKDESC_LUMINANCE |
183
+
SVGA3DBLOCKDESC_ALPHA |
184
+
SVGA3DBLOCKDESC_UINT | SVGA3DBLOCKDESC_NORM |
185
+
SVGA3DBLOCKDESC_COLOR,
186
+
SVGA3DBLOCKDESC_R_FP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_FP |
187
+
SVGA3DBLOCKDESC_COLOR,
188
+
SVGA3DBLOCKDESC_RG_FP = SVGA3DBLOCKDESC_R_FP | SVGA3DBLOCKDESC_GREEN |
189
+
SVGA3DBLOCKDESC_COLOR,
190
+
SVGA3DBLOCKDESC_RGB_FP = SVGA3DBLOCKDESC_RG_FP | SVGA3DBLOCKDESC_BLUE |
191
+
SVGA3DBLOCKDESC_COLOR,
192
+
SVGA3DBLOCKDESC_YUV = SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_COLOR,
193
+
SVGA3DBLOCKDESC_AYUV = SVGA3DBLOCKDESC_ALPHA |
194
+
SVGA3DBLOCKDESC_YUV_VIDEO |
195
+
SVGA3DBLOCKDESC_COLOR,
196
+
SVGA3DBLOCKDESC_RGB_EXP = SVGA3DBLOCKDESC_RED | SVGA3DBLOCKDESC_GREEN |
197
+
SVGA3DBLOCKDESC_BLUE | SVGA3DBLOCKDESC_EXP |
198
+
SVGA3DBLOCKDESC_COLOR,
316
199
317
-
SVGA3DBLOCKDESC_DEPTH_UINT = SVGA3DBLOCKDESC_DEPTH |
318
-
SVGA3DBLOCKDESC_UINT,
319
-
SVGA3DBLOCKDESC_DEPTH_UNORM = SVGA3DBLOCKDESC_DEPTH_UINT |
320
-
SVGA3DBLOCKDESC_NORM,
321
-
SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH |
322
-
SVGA3DBLOCKDESC_STENCIL,
323
-
SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH |
324
-
SVGA3DBLOCKDESC_STENCIL |
325
-
SVGA3DBLOCKDESC_UINT,
326
-
SVGA3DBLOCKDESC_DS_UNORM = SVGA3DBLOCKDESC_DS_UINT |
327
-
SVGA3DBLOCKDESC_NORM,
328
-
SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH |
329
-
SVGA3DBLOCKDESC_FP,
200
+
SVGA3DBLOCKDESC_COMP_TYPELESS =
201
+
SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_TYPELESS,
202
+
SVGA3DBLOCKDESC_COMP_UNORM =
203
+
SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_UINT |
204
+
SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR,
205
+
SVGA3DBLOCKDESC_COMP_SNORM =
206
+
SVGA3DBLOCKDESC_COMPRESSED | SVGA3DBLOCKDESC_SINT |
207
+
SVGA3DBLOCKDESC_NORM | SVGA3DBLOCKDESC_COLOR,
208
+
SVGA3DBLOCKDESC_COMP_UNORM_SRGB =
209
+
SVGA3DBLOCKDESC_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
210
+
SVGA3DBLOCKDESC_BC1_COMP_TYPELESS =
211
+
SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_TYPELESS,
212
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM =
213
+
SVGA3DBLOCKDESC_BC1 | SVGA3DBLOCKDESC_COMP_UNORM,
214
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB =
215
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
216
+
SVGA3DBLOCKDESC_BC2_COMP_TYPELESS =
217
+
SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_TYPELESS,
218
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM =
219
+
SVGA3DBLOCKDESC_BC2 | SVGA3DBLOCKDESC_COMP_UNORM,
220
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB =
221
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
222
+
SVGA3DBLOCKDESC_BC3_COMP_TYPELESS =
223
+
SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_TYPELESS,
224
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM =
225
+
SVGA3DBLOCKDESC_BC3 | SVGA3DBLOCKDESC_COMP_UNORM,
226
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB =
227
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
228
+
SVGA3DBLOCKDESC_BC4_COMP_TYPELESS =
229
+
SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_TYPELESS,
230
+
SVGA3DBLOCKDESC_BC4_COMP_UNORM =
231
+
SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_UNORM,
232
+
SVGA3DBLOCKDESC_BC4_COMP_SNORM =
233
+
SVGA3DBLOCKDESC_BC4 | SVGA3DBLOCKDESC_COMP_SNORM,
234
+
SVGA3DBLOCKDESC_BC5_COMP_TYPELESS =
235
+
SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_TYPELESS,
236
+
SVGA3DBLOCKDESC_BC5_COMP_UNORM =
237
+
SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_UNORM,
238
+
SVGA3DBLOCKDESC_BC5_COMP_SNORM =
239
+
SVGA3DBLOCKDESC_BC5 | SVGA3DBLOCKDESC_COMP_SNORM,
240
+
SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS =
241
+
SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMP_TYPELESS,
242
+
SVGA3DBLOCKDESC_BC6H_COMP_UF16 =
243
+
SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED,
244
+
SVGA3DBLOCKDESC_BC6H_COMP_SF16 =
245
+
SVGA3DBLOCKDESC_BC6H | SVGA3DBLOCKDESC_COMPRESSED,
246
+
SVGA3DBLOCKDESC_BC7_COMP_TYPELESS =
247
+
SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_TYPELESS,
248
+
SVGA3DBLOCKDESC_BC7_COMP_UNORM =
249
+
SVGA3DBLOCKDESC_BC7 | SVGA3DBLOCKDESC_COMP_UNORM,
250
+
SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB =
251
+
SVGA3DBLOCKDESC_BC7_COMP_UNORM | SVGA3DBLOCKDESC_SRGB,
330
252
331
-
SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV |
332
-
SVGA3DBLOCKDESC_UINT,
333
-
SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV |
334
-
SVGA3DBLOCKDESC_SINT |
335
-
SVGA3DBLOCKDESC_NORM,
336
-
SVGA3DBLOCKDESC_UVCX_SNORM = SVGA3DBLOCKDESC_UV_SNORM |
337
-
SVGA3DBLOCKDESC_CX,
253
+
SVGA3DBLOCKDESC_NV12 =
254
+
SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_PLANAR_YUV |
255
+
SVGA3DBLOCKDESC_2PLANAR_YUV | SVGA3DBLOCKDESC_COLOR,
256
+
SVGA3DBLOCKDESC_YV12 =
257
+
SVGA3DBLOCKDESC_YUV_VIDEO | SVGA3DBLOCKDESC_PLANAR_YUV |
258
+
SVGA3DBLOCKDESC_3PLANAR_YUV | SVGA3DBLOCKDESC_COLOR,
259
+
260
+
SVGA3DBLOCKDESC_DEPTH_UINT =
261
+
SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_UINT,
262
+
SVGA3DBLOCKDESC_DEPTH_UNORM =
263
+
SVGA3DBLOCKDESC_DEPTH_UINT | SVGA3DBLOCKDESC_NORM,
264
+
SVGA3DBLOCKDESC_DS = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_STENCIL,
265
+
SVGA3DBLOCKDESC_DS_UINT = SVGA3DBLOCKDESC_DEPTH |
266
+
SVGA3DBLOCKDESC_STENCIL |
267
+
SVGA3DBLOCKDESC_UINT,
268
+
SVGA3DBLOCKDESC_DS_UNORM =
269
+
SVGA3DBLOCKDESC_DS_UINT | SVGA3DBLOCKDESC_NORM,
270
+
SVGA3DBLOCKDESC_DEPTH_FP = SVGA3DBLOCKDESC_DEPTH | SVGA3DBLOCKDESC_FP,
271
+
272
+
SVGA3DBLOCKDESC_UV_UINT = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_UINT,
273
+
SVGA3DBLOCKDESC_UV_SNORM = SVGA3DBLOCKDESC_UV | SVGA3DBLOCKDESC_SINT |
274
+
SVGA3DBLOCKDESC_NORM,
275
+
SVGA3DBLOCKDESC_UVCX_SNORM =
276
+
SVGA3DBLOCKDESC_UV_SNORM | SVGA3DBLOCKDESC_CX,
338
277
SVGA3DBLOCKDESC_UVWQ_SNORM = SVGA3DBLOCKDESC_UVWQ |
339
278
SVGA3DBLOCKDESC_SINT |
340
279
SVGA3DBLOCKDESC_NORM,
341
-
};
280
+
} SVGA3dBlockDesc;
342
281
343
-
struct svga3d_channel_def {
282
+
typedef struct SVGA3dChannelDef {
344
283
union {
345
-
u8 blue;
346
-
u8 w_bump;
347
-
u8 l_bump;
348
-
u8 uv_video;
349
-
u8 u_video;
284
+
uint8 blue;
285
+
uint8 w_bump;
286
+
uint8 l_bump;
287
+
uint8 uv_video;
288
+
uint8 u_video;
350
289
};
351
290
union {
352
-
u8 green;
353
-
u8 stencil;
354
-
u8 v_bump;
355
-
u8 v_video;
291
+
uint8 green;
292
+
uint8 stencil;
293
+
uint8 v_bump;
294
+
uint8 v_video;
356
295
};
357
296
union {
358
-
u8 red;
359
-
u8 u_bump;
360
-
u8 luminance;
361
-
u8 y_video;
362
-
u8 depth;
363
-
u8 data;
297
+
uint8 red;
298
+
uint8 u_bump;
299
+
uint8 luminance;
300
+
uint8 y_video;
301
+
uint8 depth;
302
+
uint8 data;
364
303
};
365
304
union {
366
-
u8 alpha;
367
-
u8 q_bump;
368
-
u8 exp;
305
+
uint8 alpha;
306
+
uint8 q_bump;
307
+
uint8 exp;
369
308
};
370
-
};
309
+
} SVGA3dChannelDef;
371
310
372
-
/*
373
-
* struct svga3d_surface_desc - describes the actual pixel data.
374
-
*
375
-
* @format: Format
376
-
* @block_desc: Block description
377
-
* @block_size: Dimensions in pixels of a block
378
-
* @bytes_per_block: Size of block in bytes
379
-
* @pitch_bytes_per_block: Size of a block in bytes for purposes of pitch
380
-
* @bit_depth: Channel bit depths
381
-
* @bit_offset: Channel bit masks (in bits offset from the start of the pointer)
382
-
*/
383
-
struct svga3d_surface_desc {
311
+
typedef struct SVGA3dSurfaceDesc {
384
312
SVGA3dSurfaceFormat format;
385
-
enum svga3d_block_desc block_desc;
313
+
SVGA3dBlockDesc blockDesc;
386
314
387
-
surf_size_struct block_size;
388
-
u32 bytes_per_block;
389
-
u32 pitch_bytes_per_block;
315
+
SVGA3dSize blockSize;
316
+
uint32 bytesPerBlock;
317
+
uint32 pitchBytesPerBlock;
390
318
391
-
struct svga3d_channel_def bit_depth;
392
-
struct svga3d_channel_def bit_offset;
319
+
SVGA3dChannelDef bitDepth;
320
+
SVGA3dChannelDef bitOffset;
321
+
} SVGA3dSurfaceDesc;
322
+
323
+
STATIC_CONST SVGA3dSurfaceDesc g_SVGA3dSurfaceDescs[] = {
324
+
{ SVGA3D_FORMAT_INVALID,
325
+
SVGA3DBLOCKDESC_NONE,
326
+
{ 1, 1, 1 },
327
+
0,
328
+
0,
329
+
{ { 0 }, { 0 }, { 0 }, { 0 } },
330
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
331
+
332
+
{ SVGA3D_X8R8G8B8,
333
+
SVGA3DBLOCKDESC_RGB_UNORM,
334
+
{ 1, 1, 1 },
335
+
4,
336
+
4,
337
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
338
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
339
+
340
+
{ SVGA3D_A8R8G8B8,
341
+
SVGA3DBLOCKDESC_RGBA_UNORM,
342
+
{ 1, 1, 1 },
343
+
4,
344
+
4,
345
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
346
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
347
+
348
+
{ SVGA3D_R5G6B5,
349
+
SVGA3DBLOCKDESC_RGB_UNORM,
350
+
{ 1, 1, 1 },
351
+
2,
352
+
2,
353
+
{ { 5 }, { 6 }, { 5 }, { 0 } },
354
+
{ { 0 }, { 5 }, { 11 }, { 0 } } },
355
+
356
+
{ SVGA3D_X1R5G5B5,
357
+
SVGA3DBLOCKDESC_RGB_UNORM,
358
+
{ 1, 1, 1 },
359
+
2,
360
+
2,
361
+
{ { 5 }, { 5 }, { 5 }, { 0 } },
362
+
{ { 0 }, { 5 }, { 10 }, { 0 } } },
363
+
364
+
{ SVGA3D_A1R5G5B5,
365
+
SVGA3DBLOCKDESC_RGBA_UNORM,
366
+
{ 1, 1, 1 },
367
+
2,
368
+
2,
369
+
{ { 5 }, { 5 }, { 5 }, { 1 } },
370
+
{ { 0 }, { 5 }, { 10 }, { 15 } } },
371
+
372
+
{ SVGA3D_A4R4G4B4,
373
+
SVGA3DBLOCKDESC_RGBA_UNORM,
374
+
{ 1, 1, 1 },
375
+
2,
376
+
2,
377
+
{ { 4 }, { 4 }, { 4 }, { 4 } },
378
+
{ { 0 }, { 4 }, { 8 }, { 12 } } },
379
+
380
+
{ SVGA3D_Z_D32,
381
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
382
+
{ 1, 1, 1 },
383
+
4,
384
+
4,
385
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
386
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
387
+
388
+
{ SVGA3D_Z_D16,
389
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
390
+
{ 1, 1, 1 },
391
+
2,
392
+
2,
393
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
394
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
395
+
396
+
{ SVGA3D_Z_D24S8,
397
+
SVGA3DBLOCKDESC_DS_UNORM,
398
+
{ 1, 1, 1 },
399
+
4,
400
+
4,
401
+
{ { 0 }, { 8 }, { 24 }, { 0 } },
402
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
403
+
404
+
{ SVGA3D_Z_D15S1,
405
+
SVGA3DBLOCKDESC_DS_UNORM,
406
+
{ 1, 1, 1 },
407
+
2,
408
+
2,
409
+
{ { 0 }, { 1 }, { 15 }, { 0 } },
410
+
{ { 0 }, { 0 }, { 1 }, { 0 } } },
411
+
412
+
{ SVGA3D_LUMINANCE8,
413
+
SVGA3DBLOCKDESC_L_UNORM,
414
+
{ 1, 1, 1 },
415
+
1,
416
+
1,
417
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
418
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
419
+
420
+
{ SVGA3D_LUMINANCE4_ALPHA4,
421
+
SVGA3DBLOCKDESC_LA_UNORM,
422
+
{ 1, 1, 1 },
423
+
1,
424
+
1,
425
+
{ { 0 }, { 0 }, { 4 }, { 4 } },
426
+
{ { 0 }, { 0 }, { 0 }, { 4 } } },
427
+
428
+
{ SVGA3D_LUMINANCE16,
429
+
SVGA3DBLOCKDESC_L_UNORM,
430
+
{ 1, 1, 1 },
431
+
2,
432
+
2,
433
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
434
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
435
+
436
+
{ SVGA3D_LUMINANCE8_ALPHA8,
437
+
SVGA3DBLOCKDESC_LA_UNORM,
438
+
{ 1, 1, 1 },
439
+
2,
440
+
2,
441
+
{ { 0 }, { 0 }, { 8 }, { 8 } },
442
+
{ { 0 }, { 0 }, { 0 }, { 8 } } },
443
+
444
+
{ SVGA3D_DXT1,
445
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM,
446
+
{ 4, 4, 1 },
447
+
8,
448
+
8,
449
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
450
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
451
+
452
+
{ SVGA3D_DXT2,
453
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM,
454
+
{ 4, 4, 1 },
455
+
16,
456
+
16,
457
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
458
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
459
+
460
+
{ SVGA3D_DXT3,
461
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM,
462
+
{ 4, 4, 1 },
463
+
16,
464
+
16,
465
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
466
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
467
+
468
+
{ SVGA3D_DXT4,
469
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM,
470
+
{ 4, 4, 1 },
471
+
16,
472
+
16,
473
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
474
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
475
+
476
+
{ SVGA3D_DXT5,
477
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM,
478
+
{ 4, 4, 1 },
479
+
16,
480
+
16,
481
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
482
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
483
+
484
+
{ SVGA3D_BUMPU8V8,
485
+
SVGA3DBLOCKDESC_UV_SNORM,
486
+
{ 1, 1, 1 },
487
+
2,
488
+
2,
489
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
490
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
491
+
492
+
{ SVGA3D_BUMPL6V5U5,
493
+
SVGA3DBLOCKDESC_UVL,
494
+
{ 1, 1, 1 },
495
+
2,
496
+
2,
497
+
{ { 6 }, { 5 }, { 5 }, { 0 } },
498
+
{ { 10 }, { 5 }, { 0 }, { 0 } } },
499
+
500
+
{ SVGA3D_BUMPX8L8V8U8,
501
+
SVGA3DBLOCKDESC_UVL,
502
+
{ 1, 1, 1 },
503
+
4,
504
+
4,
505
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
506
+
{ { 16 }, { 8 }, { 0 }, { 0 } } },
507
+
508
+
{ SVGA3D_FORMAT_DEAD1,
509
+
SVGA3DBLOCKDESC_NONE,
510
+
{ 1, 1, 1 },
511
+
3,
512
+
3,
513
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
514
+
{ { 16 }, { 8 }, { 0 }, { 0 } } },
515
+
516
+
{ SVGA3D_ARGB_S10E5,
517
+
SVGA3DBLOCKDESC_RGBA_FP,
518
+
{ 1, 1, 1 },
519
+
8,
520
+
8,
521
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
522
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
523
+
524
+
{ SVGA3D_ARGB_S23E8,
525
+
SVGA3DBLOCKDESC_RGBA_FP,
526
+
{ 1, 1, 1 },
527
+
16,
528
+
16,
529
+
{ { 32 }, { 32 }, { 32 }, { 32 } },
530
+
{ { 64 }, { 32 }, { 0 }, { 96 } } },
531
+
532
+
{ SVGA3D_A2R10G10B10,
533
+
SVGA3DBLOCKDESC_RGBA_UNORM,
534
+
{ 1, 1, 1 },
535
+
4,
536
+
4,
537
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
538
+
{ { 0 }, { 10 }, { 20 }, { 30 } } },
539
+
540
+
{ SVGA3D_V8U8,
541
+
SVGA3DBLOCKDESC_UV_SNORM,
542
+
{ 1, 1, 1 },
543
+
2,
544
+
2,
545
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
546
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
547
+
548
+
{ SVGA3D_Q8W8V8U8,
549
+
SVGA3DBLOCKDESC_UVWQ_SNORM,
550
+
{ 1, 1, 1 },
551
+
4,
552
+
4,
553
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
554
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
555
+
556
+
{ SVGA3D_CxV8U8,
557
+
SVGA3DBLOCKDESC_UVCX_SNORM,
558
+
{ 1, 1, 1 },
559
+
2,
560
+
2,
561
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
562
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
563
+
564
+
{ SVGA3D_X8L8V8U8,
565
+
SVGA3DBLOCKDESC_UVL,
566
+
{ 1, 1, 1 },
567
+
4,
568
+
4,
569
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
570
+
{ { 16 }, { 8 }, { 0 }, { 0 } } },
571
+
572
+
{ SVGA3D_A2W10V10U10,
573
+
SVGA3DBLOCKDESC_UVWA,
574
+
{ 1, 1, 1 },
575
+
4,
576
+
4,
577
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
578
+
{ { 20 }, { 10 }, { 0 }, { 30 } } },
579
+
580
+
{ SVGA3D_ALPHA8,
581
+
SVGA3DBLOCKDESC_A_UNORM,
582
+
{ 1, 1, 1 },
583
+
1,
584
+
1,
585
+
{ { 0 }, { 0 }, { 0 }, { 8 } },
586
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
587
+
588
+
{ SVGA3D_R_S10E5,
589
+
SVGA3DBLOCKDESC_R_FP,
590
+
{ 1, 1, 1 },
591
+
2,
592
+
2,
593
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
594
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
595
+
596
+
{ SVGA3D_R_S23E8,
597
+
SVGA3DBLOCKDESC_R_FP,
598
+
{ 1, 1, 1 },
599
+
4,
600
+
4,
601
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
602
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
603
+
604
+
{ SVGA3D_RG_S10E5,
605
+
SVGA3DBLOCKDESC_RG_FP,
606
+
{ 1, 1, 1 },
607
+
4,
608
+
4,
609
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
610
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
611
+
612
+
{ SVGA3D_RG_S23E8,
613
+
SVGA3DBLOCKDESC_RG_FP,
614
+
{ 1, 1, 1 },
615
+
8,
616
+
8,
617
+
{ { 0 }, { 32 }, { 32 }, { 0 } },
618
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
619
+
620
+
{ SVGA3D_BUFFER,
621
+
SVGA3DBLOCKDESC_BUFFER,
622
+
{ 1, 1, 1 },
623
+
1,
624
+
1,
625
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
626
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
627
+
628
+
{ SVGA3D_Z_D24X8,
629
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
630
+
{ 1, 1, 1 },
631
+
4,
632
+
4,
633
+
{ { 0 }, { 0 }, { 24 }, { 0 } },
634
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
635
+
636
+
{ SVGA3D_V16U16,
637
+
SVGA3DBLOCKDESC_UV_SNORM,
638
+
{ 1, 1, 1 },
639
+
4,
640
+
4,
641
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
642
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
643
+
644
+
{ SVGA3D_G16R16,
645
+
SVGA3DBLOCKDESC_RG_UNORM,
646
+
{ 1, 1, 1 },
647
+
4,
648
+
4,
649
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
650
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
651
+
652
+
{ SVGA3D_A16B16G16R16,
653
+
SVGA3DBLOCKDESC_RGBA_UNORM,
654
+
{ 1, 1, 1 },
655
+
8,
656
+
8,
657
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
658
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
659
+
660
+
{ SVGA3D_UYVY,
661
+
SVGA3DBLOCKDESC_YUV,
662
+
{ 2, 1, 1 },
663
+
4,
664
+
4,
665
+
{ { 8 }, { 0 }, { 8 }, { 0 } },
666
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
667
+
668
+
{ SVGA3D_YUY2,
669
+
SVGA3DBLOCKDESC_YUV,
670
+
{ 2, 1, 1 },
671
+
4,
672
+
4,
673
+
{ { 8 }, { 0 }, { 8 }, { 0 } },
674
+
{ { 8 }, { 0 }, { 0 }, { 0 } } },
675
+
676
+
{ SVGA3D_NV12,
677
+
SVGA3DBLOCKDESC_NV12,
678
+
{ 2, 2, 1 },
679
+
6,
680
+
2,
681
+
{ { 0 }, { 0 }, { 48 }, { 0 } },
682
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
683
+
684
+
{ SVGA3D_FORMAT_DEAD2,
685
+
SVGA3DBLOCKDESC_NONE,
686
+
{ 1, 1, 1 },
687
+
4,
688
+
4,
689
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
690
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
691
+
692
+
{ SVGA3D_R32G32B32A32_TYPELESS,
693
+
SVGA3DBLOCKDESC_TYPELESS,
694
+
{ 1, 1, 1 },
695
+
16,
696
+
16,
697
+
{ { 32 }, { 32 }, { 32 }, { 32 } },
698
+
{ { 64 }, { 32 }, { 0 }, { 96 } } },
699
+
700
+
{ SVGA3D_R32G32B32A32_UINT,
701
+
SVGA3DBLOCKDESC_RGBA_UINT,
702
+
{ 1, 1, 1 },
703
+
16,
704
+
16,
705
+
{ { 32 }, { 32 }, { 32 }, { 32 } },
706
+
{ { 64 }, { 32 }, { 0 }, { 96 } } },
707
+
708
+
{ SVGA3D_R32G32B32A32_SINT,
709
+
SVGA3DBLOCKDESC_RGBA_SINT,
710
+
{ 1, 1, 1 },
711
+
16,
712
+
16,
713
+
{ { 32 }, { 32 }, { 32 }, { 32 } },
714
+
{ { 64 }, { 32 }, { 0 }, { 96 } } },
715
+
716
+
{ SVGA3D_R32G32B32_TYPELESS,
717
+
SVGA3DBLOCKDESC_TYPELESS,
718
+
{ 1, 1, 1 },
719
+
12,
720
+
12,
721
+
{ { 32 }, { 32 }, { 32 }, { 0 } },
722
+
{ { 64 }, { 32 }, { 0 }, { 0 } } },
723
+
724
+
{ SVGA3D_R32G32B32_FLOAT,
725
+
SVGA3DBLOCKDESC_RGB_FP,
726
+
{ 1, 1, 1 },
727
+
12,
728
+
12,
729
+
{ { 32 }, { 32 }, { 32 }, { 0 } },
730
+
{ { 64 }, { 32 }, { 0 }, { 0 } } },
731
+
732
+
{ SVGA3D_R32G32B32_UINT,
733
+
SVGA3DBLOCKDESC_RGB_UINT,
734
+
{ 1, 1, 1 },
735
+
12,
736
+
12,
737
+
{ { 32 }, { 32 }, { 32 }, { 0 } },
738
+
{ { 64 }, { 32 }, { 0 }, { 0 } } },
739
+
740
+
{ SVGA3D_R32G32B32_SINT,
741
+
SVGA3DBLOCKDESC_RGB_SINT,
742
+
{ 1, 1, 1 },
743
+
12,
744
+
12,
745
+
{ { 32 }, { 32 }, { 32 }, { 0 } },
746
+
{ { 64 }, { 32 }, { 0 }, { 0 } } },
747
+
748
+
{ SVGA3D_R16G16B16A16_TYPELESS,
749
+
SVGA3DBLOCKDESC_TYPELESS,
750
+
{ 1, 1, 1 },
751
+
8,
752
+
8,
753
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
754
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
755
+
756
+
{ SVGA3D_R16G16B16A16_UINT,
757
+
SVGA3DBLOCKDESC_RGBA_UINT,
758
+
{ 1, 1, 1 },
759
+
8,
760
+
8,
761
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
762
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
763
+
764
+
{ SVGA3D_R16G16B16A16_SNORM,
765
+
SVGA3DBLOCKDESC_RGBA_SNORM,
766
+
{ 1, 1, 1 },
767
+
8,
768
+
8,
769
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
770
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
771
+
772
+
{ SVGA3D_R16G16B16A16_SINT,
773
+
SVGA3DBLOCKDESC_RGBA_SINT,
774
+
{ 1, 1, 1 },
775
+
8,
776
+
8,
777
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
778
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
779
+
780
+
{ SVGA3D_R32G32_TYPELESS,
781
+
SVGA3DBLOCKDESC_TYPELESS,
782
+
{ 1, 1, 1 },
783
+
8,
784
+
8,
785
+
{ { 0 }, { 32 }, { 32 }, { 0 } },
786
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
787
+
788
+
{ SVGA3D_R32G32_UINT,
789
+
SVGA3DBLOCKDESC_RG_UINT,
790
+
{ 1, 1, 1 },
791
+
8,
792
+
8,
793
+
{ { 0 }, { 32 }, { 32 }, { 0 } },
794
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
795
+
796
+
{ SVGA3D_R32G32_SINT,
797
+
SVGA3DBLOCKDESC_RG_SINT,
798
+
{ 1, 1, 1 },
799
+
8,
800
+
8,
801
+
{ { 0 }, { 32 }, { 32 }, { 0 } },
802
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
803
+
804
+
{ SVGA3D_R32G8X24_TYPELESS,
805
+
SVGA3DBLOCKDESC_TYPELESS,
806
+
{ 1, 1, 1 },
807
+
8,
808
+
8,
809
+
{ { 0 }, { 8 }, { 32 }, { 0 } },
810
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
811
+
812
+
{ SVGA3D_D32_FLOAT_S8X24_UINT,
813
+
SVGA3DBLOCKDESC_DS,
814
+
{ 1, 1, 1 },
815
+
8,
816
+
8,
817
+
{ { 0 }, { 8 }, { 32 }, { 0 } },
818
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
819
+
820
+
{ SVGA3D_R32_FLOAT_X8X24,
821
+
SVGA3DBLOCKDESC_R_FP,
822
+
{ 1, 1, 1 },
823
+
8,
824
+
8,
825
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
826
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
827
+
828
+
{ SVGA3D_X32_G8X24_UINT,
829
+
SVGA3DBLOCKDESC_G_UINT,
830
+
{ 1, 1, 1 },
831
+
8,
832
+
8,
833
+
{ { 0 }, { 8 }, { 0 }, { 0 } },
834
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
835
+
836
+
{ SVGA3D_R10G10B10A2_TYPELESS,
837
+
SVGA3DBLOCKDESC_TYPELESS,
838
+
{ 1, 1, 1 },
839
+
4,
840
+
4,
841
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
842
+
{ { 20 }, { 10 }, { 0 }, { 30 } } },
843
+
844
+
{ SVGA3D_R10G10B10A2_UINT,
845
+
SVGA3DBLOCKDESC_RGBA_UINT,
846
+
{ 1, 1, 1 },
847
+
4,
848
+
4,
849
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
850
+
{ { 20 }, { 10 }, { 0 }, { 30 } } },
851
+
852
+
{ SVGA3D_R11G11B10_FLOAT,
853
+
SVGA3DBLOCKDESC_RGB_FP,
854
+
{ 1, 1, 1 },
855
+
4,
856
+
4,
857
+
{ { 10 }, { 11 }, { 11 }, { 0 } },
858
+
{ { 22 }, { 11 }, { 0 }, { 0 } } },
859
+
860
+
{ SVGA3D_R8G8B8A8_TYPELESS,
861
+
SVGA3DBLOCKDESC_TYPELESS,
862
+
{ 1, 1, 1 },
863
+
4,
864
+
4,
865
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
866
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
867
+
868
+
{ SVGA3D_R8G8B8A8_UNORM,
869
+
SVGA3DBLOCKDESC_RGBA_UNORM,
870
+
{ 1, 1, 1 },
871
+
4,
872
+
4,
873
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
874
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
875
+
876
+
{ SVGA3D_R8G8B8A8_UNORM_SRGB,
877
+
SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
878
+
{ 1, 1, 1 },
879
+
4,
880
+
4,
881
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
882
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
883
+
884
+
{ SVGA3D_R8G8B8A8_UINT,
885
+
SVGA3DBLOCKDESC_RGBA_UINT,
886
+
{ 1, 1, 1 },
887
+
4,
888
+
4,
889
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
890
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
891
+
892
+
{ SVGA3D_R8G8B8A8_SINT,
893
+
SVGA3DBLOCKDESC_RGBA_SINT,
894
+
{ 1, 1, 1 },
895
+
4,
896
+
4,
897
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
898
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
899
+
900
+
{ SVGA3D_R16G16_TYPELESS,
901
+
SVGA3DBLOCKDESC_TYPELESS,
902
+
{ 1, 1, 1 },
903
+
4,
904
+
4,
905
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
906
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
907
+
908
+
{ SVGA3D_R16G16_UINT,
909
+
SVGA3DBLOCKDESC_RG_UINT,
910
+
{ 1, 1, 1 },
911
+
4,
912
+
4,
913
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
914
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
915
+
916
+
{ SVGA3D_R16G16_SINT,
917
+
SVGA3DBLOCKDESC_RG_SINT,
918
+
{ 1, 1, 1 },
919
+
4,
920
+
4,
921
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
922
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
923
+
924
+
{ SVGA3D_R32_TYPELESS,
925
+
SVGA3DBLOCKDESC_TYPELESS,
926
+
{ 1, 1, 1 },
927
+
4,
928
+
4,
929
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
930
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
931
+
932
+
{ SVGA3D_D32_FLOAT,
933
+
SVGA3DBLOCKDESC_DEPTH_FP,
934
+
{ 1, 1, 1 },
935
+
4,
936
+
4,
937
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
938
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
939
+
940
+
{ SVGA3D_R32_UINT,
941
+
SVGA3DBLOCKDESC_R_UINT,
942
+
{ 1, 1, 1 },
943
+
4,
944
+
4,
945
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
946
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
947
+
948
+
{ SVGA3D_R32_SINT,
949
+
SVGA3DBLOCKDESC_R_SINT,
950
+
{ 1, 1, 1 },
951
+
4,
952
+
4,
953
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
954
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
955
+
956
+
{ SVGA3D_R24G8_TYPELESS,
957
+
SVGA3DBLOCKDESC_TYPELESS,
958
+
{ 1, 1, 1 },
959
+
4,
960
+
4,
961
+
{ { 0 }, { 8 }, { 24 }, { 0 } },
962
+
{ { 0 }, { 24 }, { 0 }, { 0 } } },
963
+
964
+
{ SVGA3D_D24_UNORM_S8_UINT,
965
+
SVGA3DBLOCKDESC_DS_UNORM,
966
+
{ 1, 1, 1 },
967
+
4,
968
+
4,
969
+
{ { 0 }, { 8 }, { 24 }, { 0 } },
970
+
{ { 0 }, { 24 }, { 0 }, { 0 } } },
971
+
972
+
{ SVGA3D_R24_UNORM_X8,
973
+
SVGA3DBLOCKDESC_R_UNORM,
974
+
{ 1, 1, 1 },
975
+
4,
976
+
4,
977
+
{ { 0 }, { 0 }, { 24 }, { 0 } },
978
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
979
+
980
+
{ SVGA3D_X24_G8_UINT,
981
+
SVGA3DBLOCKDESC_G_UINT,
982
+
{ 1, 1, 1 },
983
+
4,
984
+
4,
985
+
{ { 0 }, { 8 }, { 0 }, { 0 } },
986
+
{ { 0 }, { 24 }, { 0 }, { 0 } } },
987
+
988
+
{ SVGA3D_R8G8_TYPELESS,
989
+
SVGA3DBLOCKDESC_TYPELESS,
990
+
{ 1, 1, 1 },
991
+
2,
992
+
2,
993
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
994
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
995
+
996
+
{ SVGA3D_R8G8_UNORM,
997
+
SVGA3DBLOCKDESC_RG_UNORM,
998
+
{ 1, 1, 1 },
999
+
2,
1000
+
2,
1001
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1002
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
1003
+
1004
+
{ SVGA3D_R8G8_UINT,
1005
+
SVGA3DBLOCKDESC_RG_UINT,
1006
+
{ 1, 1, 1 },
1007
+
2,
1008
+
2,
1009
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1010
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
1011
+
1012
+
{ SVGA3D_R8G8_SINT,
1013
+
SVGA3DBLOCKDESC_RG_SINT,
1014
+
{ 1, 1, 1 },
1015
+
2,
1016
+
2,
1017
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1018
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
1019
+
1020
+
{ SVGA3D_R16_TYPELESS,
1021
+
SVGA3DBLOCKDESC_TYPELESS,
1022
+
{ 1, 1, 1 },
1023
+
2,
1024
+
2,
1025
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1026
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1027
+
1028
+
{ SVGA3D_R16_UNORM,
1029
+
SVGA3DBLOCKDESC_R_UNORM,
1030
+
{ 1, 1, 1 },
1031
+
2,
1032
+
2,
1033
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1034
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1035
+
1036
+
{ SVGA3D_R16_UINT,
1037
+
SVGA3DBLOCKDESC_R_UINT,
1038
+
{ 1, 1, 1 },
1039
+
2,
1040
+
2,
1041
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1042
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1043
+
1044
+
{ SVGA3D_R16_SNORM,
1045
+
SVGA3DBLOCKDESC_R_SNORM,
1046
+
{ 1, 1, 1 },
1047
+
2,
1048
+
2,
1049
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1050
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1051
+
1052
+
{ SVGA3D_R16_SINT,
1053
+
SVGA3DBLOCKDESC_R_SINT,
1054
+
{ 1, 1, 1 },
1055
+
2,
1056
+
2,
1057
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1058
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1059
+
1060
+
{ SVGA3D_R8_TYPELESS,
1061
+
SVGA3DBLOCKDESC_TYPELESS,
1062
+
{ 1, 1, 1 },
1063
+
1,
1064
+
1,
1065
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1066
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1067
+
1068
+
{ SVGA3D_R8_UNORM,
1069
+
SVGA3DBLOCKDESC_R_UNORM,
1070
+
{ 1, 1, 1 },
1071
+
1,
1072
+
1,
1073
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1074
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1075
+
1076
+
{ SVGA3D_R8_UINT,
1077
+
SVGA3DBLOCKDESC_R_UINT,
1078
+
{ 1, 1, 1 },
1079
+
1,
1080
+
1,
1081
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1082
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1083
+
1084
+
{ SVGA3D_R8_SNORM,
1085
+
SVGA3DBLOCKDESC_R_SNORM,
1086
+
{ 1, 1, 1 },
1087
+
1,
1088
+
1,
1089
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1090
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1091
+
1092
+
{ SVGA3D_R8_SINT,
1093
+
SVGA3DBLOCKDESC_R_SINT,
1094
+
{ 1, 1, 1 },
1095
+
1,
1096
+
1,
1097
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1098
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1099
+
1100
+
{ SVGA3D_P8,
1101
+
SVGA3DBLOCKDESC_NONE,
1102
+
{ 1, 1, 1 },
1103
+
1,
1104
+
1,
1105
+
{ { 0 }, { 0 }, { 8 }, { 0 } },
1106
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1107
+
1108
+
{ SVGA3D_R9G9B9E5_SHAREDEXP,
1109
+
SVGA3DBLOCKDESC_RGB_EXP,
1110
+
{ 1, 1, 1 },
1111
+
4,
1112
+
4,
1113
+
{ { 9 }, { 9 }, { 9 }, { 5 } },
1114
+
{ { 18 }, { 9 }, { 0 }, { 27 } } },
1115
+
1116
+
{ SVGA3D_R8G8_B8G8_UNORM,
1117
+
SVGA3DBLOCKDESC_NONE,
1118
+
{ 2, 1, 1 },
1119
+
4,
1120
+
4,
1121
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1122
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
1123
+
1124
+
{ SVGA3D_G8R8_G8B8_UNORM,
1125
+
SVGA3DBLOCKDESC_NONE,
1126
+
{ 2, 1, 1 },
1127
+
4,
1128
+
4,
1129
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1130
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
1131
+
1132
+
{ SVGA3D_BC1_TYPELESS,
1133
+
SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
1134
+
{ 4, 4, 1 },
1135
+
8,
1136
+
8,
1137
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1138
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1139
+
1140
+
{ SVGA3D_BC1_UNORM_SRGB,
1141
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
1142
+
{ 4, 4, 1 },
1143
+
8,
1144
+
8,
1145
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1146
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1147
+
1148
+
{ SVGA3D_BC2_TYPELESS,
1149
+
SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
1150
+
{ 4, 4, 1 },
1151
+
16,
1152
+
16,
1153
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1154
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1155
+
1156
+
{ SVGA3D_BC2_UNORM_SRGB,
1157
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
1158
+
{ 4, 4, 1 },
1159
+
16,
1160
+
16,
1161
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1162
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1163
+
1164
+
{ SVGA3D_BC3_TYPELESS,
1165
+
SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
1166
+
{ 4, 4, 1 },
1167
+
16,
1168
+
16,
1169
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1170
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1171
+
1172
+
{ SVGA3D_BC3_UNORM_SRGB,
1173
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
1174
+
{ 4, 4, 1 },
1175
+
16,
1176
+
16,
1177
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1178
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1179
+
1180
+
{ SVGA3D_BC4_TYPELESS,
1181
+
SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
1182
+
{ 4, 4, 1 },
1183
+
8,
1184
+
8,
1185
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1186
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1187
+
1188
+
{ SVGA3D_ATI1,
1189
+
SVGA3DBLOCKDESC_BC4_COMP_UNORM,
1190
+
{ 4, 4, 1 },
1191
+
8,
1192
+
8,
1193
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1194
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1195
+
1196
+
{ SVGA3D_BC4_SNORM,
1197
+
SVGA3DBLOCKDESC_BC4_COMP_SNORM,
1198
+
{ 4, 4, 1 },
1199
+
8,
1200
+
8,
1201
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1202
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1203
+
1204
+
{ SVGA3D_BC5_TYPELESS,
1205
+
SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
1206
+
{ 4, 4, 1 },
1207
+
16,
1208
+
16,
1209
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1210
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1211
+
1212
+
{ SVGA3D_ATI2,
1213
+
SVGA3DBLOCKDESC_BC5_COMP_UNORM,
1214
+
{ 4, 4, 1 },
1215
+
16,
1216
+
16,
1217
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1218
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1219
+
1220
+
{ SVGA3D_BC5_SNORM,
1221
+
SVGA3DBLOCKDESC_BC5_COMP_SNORM,
1222
+
{ 4, 4, 1 },
1223
+
16,
1224
+
16,
1225
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1226
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1227
+
1228
+
{ SVGA3D_R10G10B10_XR_BIAS_A2_UNORM,
1229
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1230
+
{ 1, 1, 1 },
1231
+
4,
1232
+
4,
1233
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
1234
+
{ { 20 }, { 10 }, { 0 }, { 30 } } },
1235
+
1236
+
{ SVGA3D_B8G8R8A8_TYPELESS,
1237
+
SVGA3DBLOCKDESC_TYPELESS,
1238
+
{ 1, 1, 1 },
1239
+
4,
1240
+
4,
1241
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
1242
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1243
+
1244
+
{ SVGA3D_B8G8R8A8_UNORM_SRGB,
1245
+
SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
1246
+
{ 1, 1, 1 },
1247
+
4,
1248
+
4,
1249
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
1250
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1251
+
1252
+
{ SVGA3D_B8G8R8X8_TYPELESS,
1253
+
SVGA3DBLOCKDESC_TYPELESS,
1254
+
{ 1, 1, 1 },
1255
+
4,
1256
+
4,
1257
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
1258
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1259
+
1260
+
{ SVGA3D_B8G8R8X8_UNORM_SRGB,
1261
+
SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
1262
+
{ 1, 1, 1 },
1263
+
4,
1264
+
4,
1265
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
1266
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1267
+
1268
+
{ SVGA3D_Z_DF16,
1269
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
1270
+
{ 1, 1, 1 },
1271
+
2,
1272
+
2,
1273
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1274
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1275
+
1276
+
{ SVGA3D_Z_DF24,
1277
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
1278
+
{ 1, 1, 1 },
1279
+
4,
1280
+
4,
1281
+
{ { 0 }, { 0 }, { 24 }, { 0 } },
1282
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
1283
+
1284
+
{ SVGA3D_Z_D24S8_INT,
1285
+
SVGA3DBLOCKDESC_DS_UNORM,
1286
+
{ 1, 1, 1 },
1287
+
4,
1288
+
4,
1289
+
{ { 0 }, { 8 }, { 24 }, { 0 } },
1290
+
{ { 0 }, { 0 }, { 8 }, { 0 } } },
1291
+
1292
+
{ SVGA3D_YV12,
1293
+
SVGA3DBLOCKDESC_YV12,
1294
+
{ 2, 2, 1 },
1295
+
6,
1296
+
2,
1297
+
{ { 0 }, { 0 }, { 48 }, { 0 } },
1298
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1299
+
1300
+
{ SVGA3D_R32G32B32A32_FLOAT,
1301
+
SVGA3DBLOCKDESC_RGBA_FP,
1302
+
{ 1, 1, 1 },
1303
+
16,
1304
+
16,
1305
+
{ { 32 }, { 32 }, { 32 }, { 32 } },
1306
+
{ { 64 }, { 32 }, { 0 }, { 96 } } },
1307
+
1308
+
{ SVGA3D_R16G16B16A16_FLOAT,
1309
+
SVGA3DBLOCKDESC_RGBA_FP,
1310
+
{ 1, 1, 1 },
1311
+
8,
1312
+
8,
1313
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
1314
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
1315
+
1316
+
{ SVGA3D_R16G16B16A16_UNORM,
1317
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1318
+
{ 1, 1, 1 },
1319
+
8,
1320
+
8,
1321
+
{ { 16 }, { 16 }, { 16 }, { 16 } },
1322
+
{ { 32 }, { 16 }, { 0 }, { 48 } } },
1323
+
1324
+
{ SVGA3D_R32G32_FLOAT,
1325
+
SVGA3DBLOCKDESC_RG_FP,
1326
+
{ 1, 1, 1 },
1327
+
8,
1328
+
8,
1329
+
{ { 0 }, { 32 }, { 32 }, { 0 } },
1330
+
{ { 0 }, { 32 }, { 0 }, { 0 } } },
1331
+
1332
+
{ SVGA3D_R10G10B10A2_UNORM,
1333
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1334
+
{ 1, 1, 1 },
1335
+
4,
1336
+
4,
1337
+
{ { 10 }, { 10 }, { 10 }, { 2 } },
1338
+
{ { 20 }, { 10 }, { 0 }, { 30 } } },
1339
+
1340
+
{ SVGA3D_R8G8B8A8_SNORM,
1341
+
SVGA3DBLOCKDESC_RGBA_SNORM,
1342
+
{ 1, 1, 1 },
1343
+
4,
1344
+
4,
1345
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
1346
+
{ { 16 }, { 8 }, { 0 }, { 24 } } },
1347
+
1348
+
{ SVGA3D_R16G16_FLOAT,
1349
+
SVGA3DBLOCKDESC_RG_FP,
1350
+
{ 1, 1, 1 },
1351
+
4,
1352
+
4,
1353
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
1354
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
1355
+
1356
+
{ SVGA3D_R16G16_UNORM,
1357
+
SVGA3DBLOCKDESC_RG_UNORM,
1358
+
{ 1, 1, 1 },
1359
+
4,
1360
+
4,
1361
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
1362
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
1363
+
1364
+
{ SVGA3D_R16G16_SNORM,
1365
+
SVGA3DBLOCKDESC_RG_SNORM,
1366
+
{ 1, 1, 1 },
1367
+
4,
1368
+
4,
1369
+
{ { 0 }, { 16 }, { 16 }, { 0 } },
1370
+
{ { 0 }, { 16 }, { 0 }, { 0 } } },
1371
+
1372
+
{ SVGA3D_R32_FLOAT,
1373
+
SVGA3DBLOCKDESC_R_FP,
1374
+
{ 1, 1, 1 },
1375
+
4,
1376
+
4,
1377
+
{ { 0 }, { 0 }, { 32 }, { 0 } },
1378
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1379
+
1380
+
{ SVGA3D_R8G8_SNORM,
1381
+
SVGA3DBLOCKDESC_RG_SNORM,
1382
+
{ 1, 1, 1 },
1383
+
2,
1384
+
2,
1385
+
{ { 0 }, { 8 }, { 8 }, { 0 } },
1386
+
{ { 0 }, { 8 }, { 0 }, { 0 } } },
1387
+
1388
+
{ SVGA3D_R16_FLOAT,
1389
+
SVGA3DBLOCKDESC_R_FP,
1390
+
{ 1, 1, 1 },
1391
+
2,
1392
+
2,
1393
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1394
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1395
+
1396
+
{ SVGA3D_D16_UNORM,
1397
+
SVGA3DBLOCKDESC_DEPTH_UNORM,
1398
+
{ 1, 1, 1 },
1399
+
2,
1400
+
2,
1401
+
{ { 0 }, { 0 }, { 16 }, { 0 } },
1402
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1403
+
1404
+
{ SVGA3D_A8_UNORM,
1405
+
SVGA3DBLOCKDESC_A_UNORM,
1406
+
{ 1, 1, 1 },
1407
+
1,
1408
+
1,
1409
+
{ { 0 }, { 0 }, { 0 }, { 8 } },
1410
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1411
+
1412
+
{ SVGA3D_BC1_UNORM,
1413
+
SVGA3DBLOCKDESC_BC1_COMP_UNORM,
1414
+
{ 4, 4, 1 },
1415
+
8,
1416
+
8,
1417
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1418
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1419
+
1420
+
{ SVGA3D_BC2_UNORM,
1421
+
SVGA3DBLOCKDESC_BC2_COMP_UNORM,
1422
+
{ 4, 4, 1 },
1423
+
16,
1424
+
16,
1425
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1426
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1427
+
1428
+
{ SVGA3D_BC3_UNORM,
1429
+
SVGA3DBLOCKDESC_BC3_COMP_UNORM,
1430
+
{ 4, 4, 1 },
1431
+
16,
1432
+
16,
1433
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1434
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1435
+
1436
+
{ SVGA3D_B5G6R5_UNORM,
1437
+
SVGA3DBLOCKDESC_RGB_UNORM,
1438
+
{ 1, 1, 1 },
1439
+
2,
1440
+
2,
1441
+
{ { 5 }, { 6 }, { 5 }, { 0 } },
1442
+
{ { 0 }, { 5 }, { 11 }, { 0 } } },
1443
+
1444
+
{ SVGA3D_B5G5R5A1_UNORM,
1445
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1446
+
{ 1, 1, 1 },
1447
+
2,
1448
+
2,
1449
+
{ { 5 }, { 5 }, { 5 }, { 1 } },
1450
+
{ { 0 }, { 5 }, { 10 }, { 15 } } },
1451
+
1452
+
{ SVGA3D_B8G8R8A8_UNORM,
1453
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1454
+
{ 1, 1, 1 },
1455
+
4,
1456
+
4,
1457
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
1458
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1459
+
1460
+
{ SVGA3D_B8G8R8X8_UNORM,
1461
+
SVGA3DBLOCKDESC_RGB_UNORM,
1462
+
{ 1, 1, 1 },
1463
+
4,
1464
+
4,
1465
+
{ { 8 }, { 8 }, { 8 }, { 0 } },
1466
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1467
+
1468
+
{ SVGA3D_BC4_UNORM,
1469
+
SVGA3DBLOCKDESC_BC4_COMP_UNORM,
1470
+
{ 4, 4, 1 },
1471
+
8,
1472
+
8,
1473
+
{ { 0 }, { 0 }, { 64 }, { 0 } },
1474
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1475
+
1476
+
{ SVGA3D_BC5_UNORM,
1477
+
SVGA3DBLOCKDESC_BC5_COMP_UNORM,
1478
+
{ 4, 4, 1 },
1479
+
16,
1480
+
16,
1481
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1482
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1483
+
1484
+
{ SVGA3D_B4G4R4A4_UNORM,
1485
+
SVGA3DBLOCKDESC_RGBA_UNORM,
1486
+
{ 1, 1, 1 },
1487
+
2,
1488
+
2,
1489
+
{ { 4 }, { 4 }, { 4 }, { 4 } },
1490
+
{ { 0 }, { 4 }, { 8 }, { 12 } } },
1491
+
1492
+
{ SVGA3D_BC6H_TYPELESS,
1493
+
SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
1494
+
{ 4, 4, 1 },
1495
+
16,
1496
+
16,
1497
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1498
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1499
+
1500
+
{ SVGA3D_BC6H_UF16,
1501
+
SVGA3DBLOCKDESC_BC6H_COMP_UF16,
1502
+
{ 4, 4, 1 },
1503
+
16,
1504
+
16,
1505
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1506
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1507
+
1508
+
{ SVGA3D_BC6H_SF16,
1509
+
SVGA3DBLOCKDESC_BC6H_COMP_SF16,
1510
+
{ 4, 4, 1 },
1511
+
16,
1512
+
16,
1513
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1514
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1515
+
1516
+
{ SVGA3D_BC7_TYPELESS,
1517
+
SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
1518
+
{ 4, 4, 1 },
1519
+
16,
1520
+
16,
1521
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1522
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1523
+
1524
+
{ SVGA3D_BC7_UNORM,
1525
+
SVGA3DBLOCKDESC_BC7_COMP_UNORM,
1526
+
{ 4, 4, 1 },
1527
+
16,
1528
+
16,
1529
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1530
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1531
+
1532
+
{ SVGA3D_BC7_UNORM_SRGB,
1533
+
SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
1534
+
{ 4, 4, 1 },
1535
+
16,
1536
+
16,
1537
+
{ { 0 }, { 0 }, { 128 }, { 0 } },
1538
+
{ { 0 }, { 0 }, { 0 }, { 0 } } },
1539
+
1540
+
{ SVGA3D_AYUV,
1541
+
SVGA3DBLOCKDESC_AYUV,
1542
+
{ 1, 1, 1 },
1543
+
4,
1544
+
4,
1545
+
{ { 8 }, { 8 }, { 8 }, { 8 } },
1546
+
{ { 0 }, { 8 }, { 16 }, { 24 } } },
1547
+
1548
+
{ SVGA3D_R11G11B10_TYPELESS,
1549
+
SVGA3DBLOCKDESC_TYPELESS,
1550
+
{ 1, 1, 1 },
1551
+
4,
1552
+
4,
1553
+
{ { 10 }, { 11 }, { 11 }, { 0 } },
1554
+
{ { 22 }, { 11 }, { 0 }, { 0 } } },
393
1555
};
394
1556
395
-
static const struct svga3d_surface_desc svga3d_surface_descs[] = {
396
-
{SVGA3D_FORMAT_INVALID, SVGA3DBLOCKDESC_NONE,
397
-
{1, 1, 1}, 0, 0,
398
-
{{0}, {0}, {0}, {0}},
399
-
{{0}, {0}, {0}, {0}}},
400
-
401
-
{SVGA3D_X8R8G8B8, SVGA3DBLOCKDESC_RGB_UNORM,
402
-
{1, 1, 1}, 4, 4,
403
-
{{8}, {8}, {8}, {0}},
404
-
{{0}, {8}, {16}, {24}}},
405
-
406
-
{SVGA3D_A8R8G8B8, SVGA3DBLOCKDESC_RGBA_UNORM,
407
-
{1, 1, 1}, 4, 4,
408
-
{{8}, {8}, {8}, {8}},
409
-
{{0}, {8}, {16}, {24}}},
410
-
411
-
{SVGA3D_R5G6B5, SVGA3DBLOCKDESC_RGB_UNORM,
412
-
{1, 1, 1}, 2, 2,
413
-
{{5}, {6}, {5}, {0}},
414
-
{{0}, {5}, {11}, {0}}},
415
-
416
-
{SVGA3D_X1R5G5B5, SVGA3DBLOCKDESC_RGB_UNORM,
417
-
{1, 1, 1}, 2, 2,
418
-
{{5}, {5}, {5}, {0}},
419
-
{{0}, {5}, {10}, {0}}},
420
-
421
-
{SVGA3D_A1R5G5B5, SVGA3DBLOCKDESC_RGBA_UNORM,
422
-
{1, 1, 1}, 2, 2,
423
-
{{5}, {5}, {5}, {1}},
424
-
{{0}, {5}, {10}, {15}}},
425
-
426
-
{SVGA3D_A4R4G4B4, SVGA3DBLOCKDESC_RGBA_UNORM,
427
-
{1, 1, 1}, 2, 2,
428
-
{{4}, {4}, {4}, {4}},
429
-
{{0}, {4}, {8}, {12}}},
430
-
431
-
{SVGA3D_Z_D32, SVGA3DBLOCKDESC_DEPTH_UNORM,
432
-
{1, 1, 1}, 4, 4,
433
-
{{0}, {0}, {32}, {0}},
434
-
{{0}, {0}, {0}, {0}}},
435
-
436
-
{SVGA3D_Z_D16, SVGA3DBLOCKDESC_DEPTH_UNORM,
437
-
{1, 1, 1}, 2, 2,
438
-
{{0}, {0}, {16}, {0}},
439
-
{{0}, {0}, {0}, {0}}},
440
-
441
-
{SVGA3D_Z_D24S8, SVGA3DBLOCKDESC_DS_UNORM,
442
-
{1, 1, 1}, 4, 4,
443
-
{{0}, {8}, {24}, {0}},
444
-
{{0}, {0}, {8}, {0}}},
445
-
446
-
{SVGA3D_Z_D15S1, SVGA3DBLOCKDESC_DS_UNORM,
447
-
{1, 1, 1}, 2, 2,
448
-
{{0}, {1}, {15}, {0}},
449
-
{{0}, {0}, {1}, {0}}},
450
-
451
-
{SVGA3D_LUMINANCE8, SVGA3DBLOCKDESC_L_UNORM,
452
-
{1, 1, 1}, 1, 1,
453
-
{{0}, {0}, {8}, {0}},
454
-
{{0}, {0}, {0}, {0}}},
455
-
456
-
{SVGA3D_LUMINANCE4_ALPHA4, SVGA3DBLOCKDESC_LA_UNORM,
457
-
{1, 1, 1}, 1, 1,
458
-
{{0}, {0}, {4}, {4}},
459
-
{{0}, {0}, {0}, {4}}},
460
-
461
-
{SVGA3D_LUMINANCE16, SVGA3DBLOCKDESC_L_UNORM,
462
-
{1, 1, 1}, 2, 2,
463
-
{{0}, {0}, {16}, {0}},
464
-
{{0}, {0}, {0}, {0}}},
465
-
466
-
{SVGA3D_LUMINANCE8_ALPHA8, SVGA3DBLOCKDESC_LA_UNORM,
467
-
{1, 1, 1}, 2, 2,
468
-
{{0}, {0}, {8}, {8}},
469
-
{{0}, {0}, {0}, {8}}},
470
-
471
-
{SVGA3D_DXT1, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
472
-
{4, 4, 1}, 8, 8,
473
-
{{0}, {0}, {64}, {0}},
474
-
{{0}, {0}, {0}, {0}}},
475
-
476
-
{SVGA3D_DXT2, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
477
-
{4, 4, 1}, 16, 16,
478
-
{{0}, {0}, {128}, {0}},
479
-
{{0}, {0}, {0}, {0}}},
480
-
481
-
{SVGA3D_DXT3, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
482
-
{4, 4, 1}, 16, 16,
483
-
{{0}, {0}, {128}, {0}},
484
-
{{0}, {0}, {0}, {0}}},
485
-
486
-
{SVGA3D_DXT4, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
487
-
{4, 4, 1}, 16, 16,
488
-
{{0}, {0}, {128}, {0}},
489
-
{{0}, {0}, {0}, {0}}},
490
-
491
-
{SVGA3D_DXT5, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
492
-
{4, 4, 1}, 16, 16,
493
-
{{0}, {0}, {128}, {0}},
494
-
{{0}, {0}, {0}, {0}}},
495
-
496
-
{SVGA3D_BUMPU8V8, SVGA3DBLOCKDESC_UV_SNORM,
497
-
{1, 1, 1}, 2, 2,
498
-
{{0}, {8}, {8}, {0}},
499
-
{{0}, {8}, {0}, {0}}},
500
-
501
-
{SVGA3D_BUMPL6V5U5, SVGA3DBLOCKDESC_UVL,
502
-
{1, 1, 1}, 2, 2,
503
-
{{6}, {5}, {5}, {0}},
504
-
{{10}, {5}, {0}, {0}}},
505
-
506
-
{SVGA3D_BUMPX8L8V8U8, SVGA3DBLOCKDESC_UVL,
507
-
{1, 1, 1}, 4, 4,
508
-
{{8}, {8}, {8}, {0}},
509
-
{{16}, {8}, {0}, {0}}},
510
-
511
-
{SVGA3D_FORMAT_DEAD1, SVGA3DBLOCKDESC_NONE,
512
-
{1, 1, 1}, 3, 3,
513
-
{{8}, {8}, {8}, {0}},
514
-
{{16}, {8}, {0}, {0}}},
515
-
516
-
{SVGA3D_ARGB_S10E5, SVGA3DBLOCKDESC_RGBA_FP,
517
-
{1, 1, 1}, 8, 8,
518
-
{{16}, {16}, {16}, {16}},
519
-
{{32}, {16}, {0}, {48}}},
520
-
521
-
{SVGA3D_ARGB_S23E8, SVGA3DBLOCKDESC_RGBA_FP,
522
-
{1, 1, 1}, 16, 16,
523
-
{{32}, {32}, {32}, {32}},
524
-
{{64}, {32}, {0}, {96}}},
525
-
526
-
{SVGA3D_A2R10G10B10, SVGA3DBLOCKDESC_RGBA_UNORM,
527
-
{1, 1, 1}, 4, 4,
528
-
{{10}, {10}, {10}, {2}},
529
-
{{0}, {10}, {20}, {30}}},
530
-
531
-
{SVGA3D_V8U8, SVGA3DBLOCKDESC_UV_SNORM,
532
-
{1, 1, 1}, 2, 2,
533
-
{{0}, {8}, {8}, {0}},
534
-
{{0}, {8}, {0}, {0}}},
535
-
536
-
{SVGA3D_Q8W8V8U8, SVGA3DBLOCKDESC_UVWQ_SNORM,
537
-
{1, 1, 1}, 4, 4,
538
-
{{8}, {8}, {8}, {8}},
539
-
{{16}, {8}, {0}, {24}}},
540
-
541
-
{SVGA3D_CxV8U8, SVGA3DBLOCKDESC_UVCX_SNORM,
542
-
{1, 1, 1}, 2, 2,
543
-
{{0}, {8}, {8}, {0}},
544
-
{{0}, {8}, {0}, {0}}},
545
-
546
-
{SVGA3D_X8L8V8U8, SVGA3DBLOCKDESC_UVL,
547
-
{1, 1, 1}, 4, 4,
548
-
{{8}, {8}, {8}, {0}},
549
-
{{16}, {8}, {0}, {0}}},
550
-
551
-
{SVGA3D_A2W10V10U10, SVGA3DBLOCKDESC_UVWA,
552
-
{1, 1, 1}, 4, 4,
553
-
{{10}, {10}, {10}, {2}},
554
-
{{20}, {10}, {0}, {30}}},
555
-
556
-
{SVGA3D_ALPHA8, SVGA3DBLOCKDESC_A_UNORM,
557
-
{1, 1, 1}, 1, 1,
558
-
{{0}, {0}, {0}, {8}},
559
-
{{0}, {0}, {0}, {0}}},
560
-
561
-
{SVGA3D_R_S10E5, SVGA3DBLOCKDESC_R_FP,
562
-
{1, 1, 1}, 2, 2,
563
-
{{0}, {0}, {16}, {0}},
564
-
{{0}, {0}, {0}, {0}}},
565
-
566
-
{SVGA3D_R_S23E8, SVGA3DBLOCKDESC_R_FP,
567
-
{1, 1, 1}, 4, 4,
568
-
{{0}, {0}, {32}, {0}},
569
-
{{0}, {0}, {0}, {0}}},
570
-
571
-
{SVGA3D_RG_S10E5, SVGA3DBLOCKDESC_RG_FP,
572
-
{1, 1, 1}, 4, 4,
573
-
{{0}, {16}, {16}, {0}},
574
-
{{0}, {16}, {0}, {0}}},
575
-
576
-
{SVGA3D_RG_S23E8, SVGA3DBLOCKDESC_RG_FP,
577
-
{1, 1, 1}, 8, 8,
578
-
{{0}, {32}, {32}, {0}},
579
-
{{0}, {32}, {0}, {0}}},
580
-
581
-
{SVGA3D_BUFFER, SVGA3DBLOCKDESC_BUFFER,
582
-
{1, 1, 1}, 1, 1,
583
-
{{0}, {0}, {8}, {0}},
584
-
{{0}, {0}, {0}, {0}}},
585
-
586
-
{SVGA3D_Z_D24X8, SVGA3DBLOCKDESC_DEPTH_UNORM,
587
-
{1, 1, 1}, 4, 4,
588
-
{{0}, {0}, {24}, {0}},
589
-
{{0}, {0}, {8}, {0}}},
590
-
591
-
{SVGA3D_V16U16, SVGA3DBLOCKDESC_UV_SNORM,
592
-
{1, 1, 1}, 4, 4,
593
-
{{0}, {16}, {16}, {0}},
594
-
{{0}, {16}, {0}, {0}}},
595
-
596
-
{SVGA3D_G16R16, SVGA3DBLOCKDESC_RG_UNORM,
597
-
{1, 1, 1}, 4, 4,
598
-
{{0}, {16}, {16}, {0}},
599
-
{{0}, {16}, {0}, {0}}},
600
-
601
-
{SVGA3D_A16B16G16R16, SVGA3DBLOCKDESC_RGBA_UNORM,
602
-
{1, 1, 1}, 8, 8,
603
-
{{16}, {16}, {16}, {16}},
604
-
{{32}, {16}, {0}, {48}}},
605
-
606
-
{SVGA3D_UYVY, SVGA3DBLOCKDESC_YUV,
607
-
{2, 1, 1}, 4, 4,
608
-
{{8}, {0}, {8}, {0}},
609
-
{{0}, {0}, {8}, {0}}},
610
-
611
-
{SVGA3D_YUY2, SVGA3DBLOCKDESC_YUV,
612
-
{2, 1, 1}, 4, 4,
613
-
{{8}, {0}, {8}, {0}},
614
-
{{8}, {0}, {0}, {0}}},
615
-
616
-
{SVGA3D_NV12, SVGA3DBLOCKDESC_NV12,
617
-
{2, 2, 1}, 6, 2,
618
-
{{0}, {0}, {48}, {0}},
619
-
{{0}, {0}, {0}, {0}}},
620
-
621
-
{SVGA3D_FORMAT_DEAD2, SVGA3DBLOCKDESC_NONE,
622
-
{1, 1, 1}, 4, 4,
623
-
{{8}, {8}, {8}, {8}},
624
-
{{0}, {8}, {16}, {24}}},
625
-
626
-
{SVGA3D_R32G32B32A32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
627
-
{1, 1, 1}, 16, 16,
628
-
{{32}, {32}, {32}, {32}},
629
-
{{64}, {32}, {0}, {96}}},
630
-
631
-
{SVGA3D_R32G32B32A32_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
632
-
{1, 1, 1}, 16, 16,
633
-
{{32}, {32}, {32}, {32}},
634
-
{{64}, {32}, {0}, {96}}},
635
-
636
-
{SVGA3D_R32G32B32A32_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
637
-
{1, 1, 1}, 16, 16,
638
-
{{32}, {32}, {32}, {32}},
639
-
{{64}, {32}, {0}, {96}}},
640
-
641
-
{SVGA3D_R32G32B32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
642
-
{1, 1, 1}, 12, 12,
643
-
{{32}, {32}, {32}, {0}},
644
-
{{64}, {32}, {0}, {0}}},
645
-
646
-
{SVGA3D_R32G32B32_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
647
-
{1, 1, 1}, 12, 12,
648
-
{{32}, {32}, {32}, {0}},
649
-
{{64}, {32}, {0}, {0}}},
650
-
651
-
{SVGA3D_R32G32B32_UINT, SVGA3DBLOCKDESC_RGB_UINT,
652
-
{1, 1, 1}, 12, 12,
653
-
{{32}, {32}, {32}, {0}},
654
-
{{64}, {32}, {0}, {0}}},
655
-
656
-
{SVGA3D_R32G32B32_SINT, SVGA3DBLOCKDESC_RGB_SINT,
657
-
{1, 1, 1}, 12, 12,
658
-
{{32}, {32}, {32}, {0}},
659
-
{{64}, {32}, {0}, {0}}},
660
-
661
-
{SVGA3D_R16G16B16A16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
662
-
{1, 1, 1}, 8, 8,
663
-
{{16}, {16}, {16}, {16}},
664
-
{{32}, {16}, {0}, {48}}},
665
-
666
-
{SVGA3D_R16G16B16A16_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
667
-
{1, 1, 1}, 8, 8,
668
-
{{16}, {16}, {16}, {16}},
669
-
{{32}, {16}, {0}, {48}}},
670
-
671
-
{SVGA3D_R16G16B16A16_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
672
-
{1, 1, 1}, 8, 8,
673
-
{{16}, {16}, {16}, {16}},
674
-
{{32}, {16}, {0}, {48}}},
675
-
676
-
{SVGA3D_R16G16B16A16_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
677
-
{1, 1, 1}, 8, 8,
678
-
{{16}, {16}, {16}, {16}},
679
-
{{32}, {16}, {0}, {48}}},
680
-
681
-
{SVGA3D_R32G32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
682
-
{1, 1, 1}, 8, 8,
683
-
{{0}, {32}, {32}, {0}},
684
-
{{0}, {32}, {0}, {0}}},
685
-
686
-
{SVGA3D_R32G32_UINT, SVGA3DBLOCKDESC_RG_UINT,
687
-
{1, 1, 1}, 8, 8,
688
-
{{0}, {32}, {32}, {0}},
689
-
{{0}, {32}, {0}, {0}}},
690
-
691
-
{SVGA3D_R32G32_SINT, SVGA3DBLOCKDESC_RG_SINT,
692
-
{1, 1, 1}, 8, 8,
693
-
{{0}, {32}, {32}, {0}},
694
-
{{0}, {32}, {0}, {0}}},
695
-
696
-
{SVGA3D_R32G8X24_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
697
-
{1, 1, 1}, 8, 8,
698
-
{{0}, {8}, {32}, {0}},
699
-
{{0}, {32}, {0}, {0}}},
700
-
701
-
{SVGA3D_D32_FLOAT_S8X24_UINT, SVGA3DBLOCKDESC_DS,
702
-
{1, 1, 1}, 8, 8,
703
-
{{0}, {8}, {32}, {0}},
704
-
{{0}, {32}, {0}, {0}}},
705
-
706
-
{SVGA3D_R32_FLOAT_X8X24, SVGA3DBLOCKDESC_R_FP,
707
-
{1, 1, 1}, 8, 8,
708
-
{{0}, {0}, {32}, {0}},
709
-
{{0}, {0}, {0}, {0}}},
710
-
711
-
{SVGA3D_X32_G8X24_UINT, SVGA3DBLOCKDESC_G_UINT,
712
-
{1, 1, 1}, 8, 8,
713
-
{{0}, {8}, {0}, {0}},
714
-
{{0}, {32}, {0}, {0}}},
715
-
716
-
{SVGA3D_R10G10B10A2_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
717
-
{1, 1, 1}, 4, 4,
718
-
{{10}, {10}, {10}, {2}},
719
-
{{20}, {10}, {0}, {30}}},
720
-
721
-
{SVGA3D_R10G10B10A2_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
722
-
{1, 1, 1}, 4, 4,
723
-
{{10}, {10}, {10}, {2}},
724
-
{{20}, {10}, {0}, {30}}},
725
-
726
-
{SVGA3D_R11G11B10_FLOAT, SVGA3DBLOCKDESC_RGB_FP,
727
-
{1, 1, 1}, 4, 4,
728
-
{{10}, {11}, {11}, {0}},
729
-
{{22}, {11}, {0}, {0}}},
730
-
731
-
{SVGA3D_R8G8B8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
732
-
{1, 1, 1}, 4, 4,
733
-
{{8}, {8}, {8}, {8}},
734
-
{{16}, {8}, {0}, {24}}},
735
-
736
-
{SVGA3D_R8G8B8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
737
-
{1, 1, 1}, 4, 4,
738
-
{{8}, {8}, {8}, {8}},
739
-
{{16}, {8}, {0}, {24}}},
740
-
741
-
{SVGA3D_R8G8B8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
742
-
{1, 1, 1}, 4, 4,
743
-
{{8}, {8}, {8}, {8}},
744
-
{{16}, {8}, {0}, {24}}},
745
-
746
-
{SVGA3D_R8G8B8A8_UINT, SVGA3DBLOCKDESC_RGBA_UINT,
747
-
{1, 1, 1}, 4, 4,
748
-
{{8}, {8}, {8}, {8}},
749
-
{{16}, {8}, {0}, {24}}},
750
-
751
-
{SVGA3D_R8G8B8A8_SINT, SVGA3DBLOCKDESC_RGBA_SINT,
752
-
{1, 1, 1}, 4, 4,
753
-
{{8}, {8}, {8}, {8}},
754
-
{{16}, {8}, {0}, {24}}},
755
-
756
-
{SVGA3D_R16G16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
757
-
{1, 1, 1}, 4, 4,
758
-
{{0}, {16}, {16}, {0}},
759
-
{{0}, {16}, {0}, {0}}},
760
-
761
-
{SVGA3D_R16G16_UINT, SVGA3DBLOCKDESC_RG_UINT,
762
-
{1, 1, 1}, 4, 4,
763
-
{{0}, {16}, {16}, {0}},
764
-
{{0}, {16}, {0}, {0}}},
765
-
766
-
{SVGA3D_R16G16_SINT, SVGA3DBLOCKDESC_RG_SINT,
767
-
{1, 1, 1}, 4, 4,
768
-
{{0}, {16}, {16}, {0}},
769
-
{{0}, {16}, {0}, {0}}},
770
-
771
-
{SVGA3D_R32_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
772
-
{1, 1, 1}, 4, 4,
773
-
{{0}, {0}, {32}, {0}},
774
-
{{0}, {0}, {0}, {0}}},
775
-
776
-
{SVGA3D_D32_FLOAT, SVGA3DBLOCKDESC_DEPTH_FP,
777
-
{1, 1, 1}, 4, 4,
778
-
{{0}, {0}, {32}, {0}},
779
-
{{0}, {0}, {0}, {0}}},
780
-
781
-
{SVGA3D_R32_UINT, SVGA3DBLOCKDESC_R_UINT,
782
-
{1, 1, 1}, 4, 4,
783
-
{{0}, {0}, {32}, {0}},
784
-
{{0}, {0}, {0}, {0}}},
785
-
786
-
{SVGA3D_R32_SINT, SVGA3DBLOCKDESC_R_SINT,
787
-
{1, 1, 1}, 4, 4,
788
-
{{0}, {0}, {32}, {0}},
789
-
{{0}, {0}, {0}, {0}}},
790
-
791
-
{SVGA3D_R24G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
792
-
{1, 1, 1}, 4, 4,
793
-
{{0}, {8}, {24}, {0}},
794
-
{{0}, {24}, {0}, {0}}},
795
-
796
-
{SVGA3D_D24_UNORM_S8_UINT, SVGA3DBLOCKDESC_DS_UNORM,
797
-
{1, 1, 1}, 4, 4,
798
-
{{0}, {8}, {24}, {0}},
799
-
{{0}, {24}, {0}, {0}}},
800
-
801
-
{SVGA3D_R24_UNORM_X8, SVGA3DBLOCKDESC_R_UNORM,
802
-
{1, 1, 1}, 4, 4,
803
-
{{0}, {0}, {24}, {0}},
804
-
{{0}, {0}, {0}, {0}}},
805
-
806
-
{SVGA3D_X24_G8_UINT, SVGA3DBLOCKDESC_G_UINT,
807
-
{1, 1, 1}, 4, 4,
808
-
{{0}, {8}, {0}, {0}},
809
-
{{0}, {24}, {0}, {0}}},
810
-
811
-
{SVGA3D_R8G8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
812
-
{1, 1, 1}, 2, 2,
813
-
{{0}, {8}, {8}, {0}},
814
-
{{0}, {8}, {0}, {0}}},
815
-
816
-
{SVGA3D_R8G8_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
817
-
{1, 1, 1}, 2, 2,
818
-
{{0}, {8}, {8}, {0}},
819
-
{{0}, {8}, {0}, {0}}},
820
-
821
-
{SVGA3D_R8G8_UINT, SVGA3DBLOCKDESC_RG_UINT,
822
-
{1, 1, 1}, 2, 2,
823
-
{{0}, {8}, {8}, {0}},
824
-
{{0}, {8}, {0}, {0}}},
825
-
826
-
{SVGA3D_R8G8_SINT, SVGA3DBLOCKDESC_RG_SINT,
827
-
{1, 1, 1}, 2, 2,
828
-
{{0}, {8}, {8}, {0}},
829
-
{{0}, {8}, {0}, {0}}},
830
-
831
-
{SVGA3D_R16_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
832
-
{1, 1, 1}, 2, 2,
833
-
{{0}, {0}, {16}, {0}},
834
-
{{0}, {0}, {0}, {0}}},
835
-
836
-
{SVGA3D_R16_UNORM, SVGA3DBLOCKDESC_R_UNORM,
837
-
{1, 1, 1}, 2, 2,
838
-
{{0}, {0}, {16}, {0}},
839
-
{{0}, {0}, {0}, {0}}},
840
-
841
-
{SVGA3D_R16_UINT, SVGA3DBLOCKDESC_R_UINT,
842
-
{1, 1, 1}, 2, 2,
843
-
{{0}, {0}, {16}, {0}},
844
-
{{0}, {0}, {0}, {0}}},
845
-
846
-
{SVGA3D_R16_SNORM, SVGA3DBLOCKDESC_R_SNORM,
847
-
{1, 1, 1}, 2, 2,
848
-
{{0}, {0}, {16}, {0}},
849
-
{{0}, {0}, {0}, {0}}},
850
-
851
-
{SVGA3D_R16_SINT, SVGA3DBLOCKDESC_R_SINT,
852
-
{1, 1, 1}, 2, 2,
853
-
{{0}, {0}, {16}, {0}},
854
-
{{0}, {0}, {0}, {0}}},
855
-
856
-
{SVGA3D_R8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
857
-
{1, 1, 1}, 1, 1,
858
-
{{0}, {0}, {8}, {0}},
859
-
{{0}, {0}, {0}, {0}}},
860
-
861
-
{SVGA3D_R8_UNORM, SVGA3DBLOCKDESC_R_UNORM,
862
-
{1, 1, 1}, 1, 1,
863
-
{{0}, {0}, {8}, {0}},
864
-
{{0}, {0}, {0}, {0}}},
865
-
866
-
{SVGA3D_R8_UINT, SVGA3DBLOCKDESC_R_UINT,
867
-
{1, 1, 1}, 1, 1,
868
-
{{0}, {0}, {8}, {0}},
869
-
{{0}, {0}, {0}, {0}}},
870
-
871
-
{SVGA3D_R8_SNORM, SVGA3DBLOCKDESC_R_SNORM,
872
-
{1, 1, 1}, 1, 1,
873
-
{{0}, {0}, {8}, {0}},
874
-
{{0}, {0}, {0}, {0}}},
875
-
876
-
{SVGA3D_R8_SINT, SVGA3DBLOCKDESC_R_SINT,
877
-
{1, 1, 1}, 1, 1,
878
-
{{0}, {0}, {8}, {0}},
879
-
{{0}, {0}, {0}, {0}}},
880
-
881
-
{SVGA3D_P8, SVGA3DBLOCKDESC_NONE,
882
-
{1, 1, 1}, 1, 1,
883
-
{{0}, {0}, {8}, {0}},
884
-
{{0}, {0}, {0}, {0}}},
885
-
886
-
{SVGA3D_R9G9B9E5_SHAREDEXP, SVGA3DBLOCKDESC_RGB_EXP,
887
-
{1, 1, 1}, 4, 4,
888
-
{{9}, {9}, {9}, {5}},
889
-
{{18}, {9}, {0}, {27}}},
890
-
891
-
{SVGA3D_R8G8_B8G8_UNORM, SVGA3DBLOCKDESC_NONE,
892
-
{2, 1, 1}, 4, 4,
893
-
{{0}, {8}, {8}, {0}},
894
-
{{0}, {0}, {8}, {0}}},
895
-
896
-
{SVGA3D_G8R8_G8B8_UNORM, SVGA3DBLOCKDESC_NONE,
897
-
{2, 1, 1}, 4, 4,
898
-
{{0}, {8}, {8}, {0}},
899
-
{{0}, {8}, {0}, {0}}},
900
-
901
-
{SVGA3D_BC1_TYPELESS, SVGA3DBLOCKDESC_BC1_COMP_TYPELESS,
902
-
{4, 4, 1}, 8, 8,
903
-
{{0}, {0}, {64}, {0}},
904
-
{{0}, {0}, {0}, {0}}},
905
-
906
-
{SVGA3D_BC1_UNORM_SRGB, SVGA3DBLOCKDESC_BC1_COMP_UNORM_SRGB,
907
-
{4, 4, 1}, 8, 8,
908
-
{{0}, {0}, {64}, {0}},
909
-
{{0}, {0}, {0}, {0}}},
910
-
911
-
{SVGA3D_BC2_TYPELESS, SVGA3DBLOCKDESC_BC2_COMP_TYPELESS,
912
-
{4, 4, 1}, 16, 16,
913
-
{{0}, {0}, {128}, {0}},
914
-
{{0}, {0}, {0}, {0}}},
915
-
916
-
{SVGA3D_BC2_UNORM_SRGB, SVGA3DBLOCKDESC_BC2_COMP_UNORM_SRGB,
917
-
{4, 4, 1}, 16, 16,
918
-
{{0}, {0}, {128}, {0}},
919
-
{{0}, {0}, {0}, {0}}},
920
-
921
-
{SVGA3D_BC3_TYPELESS, SVGA3DBLOCKDESC_BC3_COMP_TYPELESS,
922
-
{4, 4, 1}, 16, 16,
923
-
{{0}, {0}, {128}, {0}},
924
-
{{0}, {0}, {0}, {0}}},
925
-
926
-
{SVGA3D_BC3_UNORM_SRGB, SVGA3DBLOCKDESC_BC3_COMP_UNORM_SRGB,
927
-
{4, 4, 1}, 16, 16,
928
-
{{0}, {0}, {128}, {0}},
929
-
{{0}, {0}, {0}, {0}}},
930
-
931
-
{SVGA3D_BC4_TYPELESS, SVGA3DBLOCKDESC_BC4_COMP_TYPELESS,
932
-
{4, 4, 1}, 8, 8,
933
-
{{0}, {0}, {64}, {0}},
934
-
{{0}, {0}, {0}, {0}}},
935
-
936
-
{SVGA3D_ATI1, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
937
-
{4, 4, 1}, 8, 8,
938
-
{{0}, {0}, {64}, {0}},
939
-
{{0}, {0}, {0}, {0}}},
940
-
941
-
{SVGA3D_BC4_SNORM, SVGA3DBLOCKDESC_BC4_COMP_SNORM,
942
-
{4, 4, 1}, 8, 8,
943
-
{{0}, {0}, {64}, {0}},
944
-
{{0}, {0}, {0}, {0}}},
945
-
946
-
{SVGA3D_BC5_TYPELESS, SVGA3DBLOCKDESC_BC5_COMP_TYPELESS,
947
-
{4, 4, 1}, 16, 16,
948
-
{{0}, {0}, {128}, {0}},
949
-
{{0}, {0}, {0}, {0}}},
950
-
951
-
{SVGA3D_ATI2, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
952
-
{4, 4, 1}, 16, 16,
953
-
{{0}, {0}, {128}, {0}},
954
-
{{0}, {0}, {0}, {0}}},
955
-
956
-
{SVGA3D_BC5_SNORM, SVGA3DBLOCKDESC_BC5_COMP_SNORM,
957
-
{4, 4, 1}, 16, 16,
958
-
{{0}, {0}, {128}, {0}},
959
-
{{0}, {0}, {0}, {0}}},
960
-
961
-
{SVGA3D_R10G10B10_XR_BIAS_A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
962
-
{1, 1, 1}, 4, 4,
963
-
{{10}, {10}, {10}, {2}},
964
-
{{20}, {10}, {0}, {30}}},
965
-
966
-
{SVGA3D_B8G8R8A8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
967
-
{1, 1, 1}, 4, 4,
968
-
{{8}, {8}, {8}, {8}},
969
-
{{0}, {8}, {16}, {24}}},
970
-
971
-
{SVGA3D_B8G8R8A8_UNORM_SRGB, SVGA3DBLOCKDESC_RGBA_UNORM_SRGB,
972
-
{1, 1, 1}, 4, 4,
973
-
{{8}, {8}, {8}, {8}},
974
-
{{0}, {8}, {16}, {24}}},
975
-
976
-
{SVGA3D_B8G8R8X8_TYPELESS, SVGA3DBLOCKDESC_TYPELESS,
977
-
{1, 1, 1}, 4, 4,
978
-
{{8}, {8}, {8}, {0}},
979
-
{{0}, {8}, {16}, {24}}},
980
-
981
-
{SVGA3D_B8G8R8X8_UNORM_SRGB, SVGA3DBLOCKDESC_RGB_UNORM_SRGB,
982
-
{1, 1, 1}, 4, 4,
983
-
{{8}, {8}, {8}, {0}},
984
-
{{0}, {8}, {16}, {24}}},
985
-
986
-
{SVGA3D_Z_DF16, SVGA3DBLOCKDESC_DEPTH_UNORM,
987
-
{1, 1, 1}, 2, 2,
988
-
{{0}, {0}, {16}, {0}},
989
-
{{0}, {0}, {0}, {0}}},
990
-
991
-
{SVGA3D_Z_DF24, SVGA3DBLOCKDESC_DEPTH_UNORM,
992
-
{1, 1, 1}, 4, 4,
993
-
{{0}, {0}, {24}, {0}},
994
-
{{0}, {0}, {8}, {0}}},
995
-
996
-
{SVGA3D_Z_D24S8_INT, SVGA3DBLOCKDESC_DS_UNORM,
997
-
{1, 1, 1}, 4, 4,
998
-
{{0}, {8}, {24}, {0}},
999
-
{{0}, {0}, {8}, {0}}},
1000
-
1001
-
{SVGA3D_YV12, SVGA3DBLOCKDESC_YV12,
1002
-
{2, 2, 1}, 6, 2,
1003
-
{{0}, {0}, {48}, {0}},
1004
-
{{0}, {0}, {0}, {0}}},
1005
-
1006
-
{SVGA3D_R32G32B32A32_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
1007
-
{1, 1, 1}, 16, 16,
1008
-
{{32}, {32}, {32}, {32}},
1009
-
{{64}, {32}, {0}, {96}}},
1010
-
1011
-
{SVGA3D_R16G16B16A16_FLOAT, SVGA3DBLOCKDESC_RGBA_FP,
1012
-
{1, 1, 1}, 8, 8,
1013
-
{{16}, {16}, {16}, {16}},
1014
-
{{32}, {16}, {0}, {48}}},
1015
-
1016
-
{SVGA3D_R16G16B16A16_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1017
-
{1, 1, 1}, 8, 8,
1018
-
{{16}, {16}, {16}, {16}},
1019
-
{{32}, {16}, {0}, {48}}},
1020
-
1021
-
{SVGA3D_R32G32_FLOAT, SVGA3DBLOCKDESC_RG_FP,
1022
-
{1, 1, 1}, 8, 8,
1023
-
{{0}, {32}, {32}, {0}},
1024
-
{{0}, {32}, {0}, {0}}},
1025
-
1026
-
{SVGA3D_R10G10B10A2_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1027
-
{1, 1, 1}, 4, 4,
1028
-
{{10}, {10}, {10}, {2}},
1029
-
{{20}, {10}, {0}, {30}}},
1030
-
1031
-
{SVGA3D_R8G8B8A8_SNORM, SVGA3DBLOCKDESC_RGBA_SNORM,
1032
-
{1, 1, 1}, 4, 4,
1033
-
{{8}, {8}, {8}, {8}},
1034
-
{{16}, {8}, {0}, {24}}},
1035
-
1036
-
{SVGA3D_R16G16_FLOAT, SVGA3DBLOCKDESC_RG_FP,
1037
-
{1, 1, 1}, 4, 4,
1038
-
{{0}, {16}, {16}, {0}},
1039
-
{{0}, {16}, {0}, {0}}},
1040
-
1041
-
{SVGA3D_R16G16_UNORM, SVGA3DBLOCKDESC_RG_UNORM,
1042
-
{1, 1, 1}, 4, 4,
1043
-
{{0}, {16}, {16}, {0}},
1044
-
{{0}, {16}, {0}, {0}}},
1045
-
1046
-
{SVGA3D_R16G16_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
1047
-
{1, 1, 1}, 4, 4,
1048
-
{{0}, {16}, {16}, {0}},
1049
-
{{0}, {16}, {0}, {0}}},
1050
-
1051
-
{SVGA3D_R32_FLOAT, SVGA3DBLOCKDESC_R_FP,
1052
-
{1, 1, 1}, 4, 4,
1053
-
{{0}, {0}, {32}, {0}},
1054
-
{{0}, {0}, {0}, {0}}},
1055
-
1056
-
{SVGA3D_R8G8_SNORM, SVGA3DBLOCKDESC_RG_SNORM,
1057
-
{1, 1, 1}, 2, 2,
1058
-
{{0}, {8}, {8}, {0}},
1059
-
{{0}, {8}, {0}, {0}}},
1060
-
1061
-
{SVGA3D_R16_FLOAT, SVGA3DBLOCKDESC_R_FP,
1062
-
{1, 1, 1}, 2, 2,
1063
-
{{0}, {0}, {16}, {0}},
1064
-
{{0}, {0}, {0}, {0}}},
1065
-
1066
-
{SVGA3D_D16_UNORM, SVGA3DBLOCKDESC_DEPTH_UNORM,
1067
-
{1, 1, 1}, 2, 2,
1068
-
{{0}, {0}, {16}, {0}},
1069
-
{{0}, {0}, {0}, {0}}},
1070
-
1071
-
{SVGA3D_A8_UNORM, SVGA3DBLOCKDESC_A_UNORM,
1072
-
{1, 1, 1}, 1, 1,
1073
-
{{0}, {0}, {0}, {8}},
1074
-
{{0}, {0}, {0}, {0}}},
1075
-
1076
-
{SVGA3D_BC1_UNORM, SVGA3DBLOCKDESC_BC1_COMP_UNORM,
1077
-
{4, 4, 1}, 8, 8,
1078
-
{{0}, {0}, {64}, {0}},
1079
-
{{0}, {0}, {0}, {0}}},
1080
-
1081
-
{SVGA3D_BC2_UNORM, SVGA3DBLOCKDESC_BC2_COMP_UNORM,
1082
-
{4, 4, 1}, 16, 16,
1083
-
{{0}, {0}, {128}, {0}},
1084
-
{{0}, {0}, {0}, {0}}},
1085
-
1086
-
{SVGA3D_BC3_UNORM, SVGA3DBLOCKDESC_BC3_COMP_UNORM,
1087
-
{4, 4, 1}, 16, 16,
1088
-
{{0}, {0}, {128}, {0}},
1089
-
{{0}, {0}, {0}, {0}}},
1090
-
1091
-
{SVGA3D_B5G6R5_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
1092
-
{1, 1, 1}, 2, 2,
1093
-
{{5}, {6}, {5}, {0}},
1094
-
{{0}, {5}, {11}, {0}}},
1095
-
1096
-
{SVGA3D_B5G5R5A1_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1097
-
{1, 1, 1}, 2, 2,
1098
-
{{5}, {5}, {5}, {1}},
1099
-
{{0}, {5}, {10}, {15}}},
1100
-
1101
-
{SVGA3D_B8G8R8A8_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1102
-
{1, 1, 1}, 4, 4,
1103
-
{{8}, {8}, {8}, {8}},
1104
-
{{0}, {8}, {16}, {24}}},
1105
-
1106
-
{SVGA3D_B8G8R8X8_UNORM, SVGA3DBLOCKDESC_RGB_UNORM,
1107
-
{1, 1, 1}, 4, 4,
1108
-
{{8}, {8}, {8}, {0}},
1109
-
{{0}, {8}, {16}, {24}}},
1110
-
1111
-
{SVGA3D_BC4_UNORM, SVGA3DBLOCKDESC_BC4_COMP_UNORM,
1112
-
{4, 4, 1}, 8, 8,
1113
-
{{0}, {0}, {64}, {0}},
1114
-
{{0}, {0}, {0}, {0}}},
1115
-
1116
-
{SVGA3D_BC5_UNORM, SVGA3DBLOCKDESC_BC5_COMP_UNORM,
1117
-
{4, 4, 1}, 16, 16,
1118
-
{{0}, {0}, {128}, {0}},
1119
-
{{0}, {0}, {0}, {0}}},
1120
-
1121
-
{SVGA3D_B4G4R4A4_UNORM, SVGA3DBLOCKDESC_RGBA_UNORM,
1122
-
{1, 1, 1}, 2, 2,
1123
-
{{4}, {4}, {4}, {4}},
1124
-
{{0}, {4}, {8}, {12}}},
1125
-
1126
-
{SVGA3D_BC6H_TYPELESS, SVGA3DBLOCKDESC_BC6H_COMP_TYPELESS,
1127
-
{4, 4, 1}, 16, 16,
1128
-
{{0}, {0}, {128}, {0}},
1129
-
{{0}, {0}, {0}, {0}}},
1130
-
1131
-
{SVGA3D_BC6H_UF16, SVGA3DBLOCKDESC_BC6H_COMP_UF16,
1132
-
{4, 4, 1}, 16, 16,
1133
-
{{0}, {0}, {128}, {0}},
1134
-
{{0}, {0}, {0}, {0}}},
1135
-
1136
-
{SVGA3D_BC6H_SF16, SVGA3DBLOCKDESC_BC6H_COMP_SF16,
1137
-
{4, 4, 1}, 16, 16,
1138
-
{{0}, {0}, {128}, {0}},
1139
-
{{0}, {0}, {0}, {0}}},
1140
-
1141
-
{SVGA3D_BC7_TYPELESS, SVGA3DBLOCKDESC_BC7_COMP_TYPELESS,
1142
-
{4, 4, 1}, 16, 16,
1143
-
{{0}, {0}, {128}, {0}},
1144
-
{{0}, {0}, {0}, {0}}},
1145
-
1146
-
{SVGA3D_BC7_UNORM, SVGA3DBLOCKDESC_BC7_COMP_UNORM,
1147
-
{4, 4, 1}, 16, 16,
1148
-
{{0}, {0}, {128}, {0}},
1149
-
{{0}, {0}, {0}, {0}}},
1150
-
1151
-
{SVGA3D_BC7_UNORM_SRGB, SVGA3DBLOCKDESC_BC7_COMP_UNORM_SRGB,
1152
-
{4, 4, 1}, 16, 16,
1153
-
{{0}, {0}, {128}, {0}},
1154
-
{{0}, {0}, {0}, {0}}},
1155
-
1156
-
{SVGA3D_AYUV, SVGA3DBLOCKDESC_AYUV,
1157
-
{1, 1, 1}, 4, 4,
1158
-
{{8}, {8}, {8}, {8}},
1159
-
{{0}, {8}, {16}, {24}}},
1160
-
};
1161
-
1162
-
static inline u32 clamped_umul32(u32 a, u32 b)
1163
-
{
1164
-
uint64_t tmp = (uint64_t) a*b;
1165
-
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
1557
+
#ifdef __cplusplus
1166
1558
}
1559
+
#endif
1167
1560
1168
-
/**
1169
-
* svga3dsurface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
1170
-
* given format.
1171
-
*/
1172
-
static inline const struct svga3d_surface_desc *
1173
-
svga3dsurface_get_desc(SVGA3dSurfaceFormat format)
1174
-
{
1175
-
if (format < ARRAY_SIZE(svga3d_surface_descs))
1176
-
return &svga3d_surface_descs[format];
1177
-
1178
-
return &svga3d_surface_descs[SVGA3D_FORMAT_INVALID];
1179
-
}
1180
-
1181
-
/**
1182
-
* svga3dsurface_get_mip_size - Given a base level size and the mip level,
1183
-
* compute the size of the mip level.
1184
-
*/
1185
-
static inline surf_size_struct
1186
-
svga3dsurface_get_mip_size(surf_size_struct base_level, u32 mip_level)
1187
-
{
1188
-
surf_size_struct size;
1189
-
1190
-
size.width = max_t(u32, base_level.width >> mip_level, 1);
1191
-
size.height = max_t(u32, base_level.height >> mip_level, 1);
1192
-
size.depth = max_t(u32, base_level.depth >> mip_level, 1);
1193
-
size.pad64 = 0;
1194
-
1195
-
return size;
1196
-
}
1197
-
1198
-
static inline void
1199
-
svga3dsurface_get_size_in_blocks(const struct svga3d_surface_desc *desc,
1200
-
const surf_size_struct *pixel_size,
1201
-
surf_size_struct *block_size)
1202
-
{
1203
-
block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
1204
-
desc->block_size.width);
1205
-
block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
1206
-
desc->block_size.height);
1207
-
block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
1208
-
desc->block_size.depth);
1209
-
}
1210
-
1211
-
static inline bool
1212
-
svga3dsurface_is_planar_surface(const struct svga3d_surface_desc *desc)
1213
-
{
1214
-
return (desc->block_desc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
1215
-
}
1216
-
1217
-
static inline u32
1218
-
svga3dsurface_calculate_pitch(const struct svga3d_surface_desc *desc,
1219
-
const surf_size_struct *size)
1220
-
{
1221
-
u32 pitch;
1222
-
surf_size_struct blocks;
1223
-
1224
-
svga3dsurface_get_size_in_blocks(desc, size, &blocks);
1225
-
1226
-
pitch = blocks.width * desc->pitch_bytes_per_block;
1227
-
1228
-
return pitch;
1229
-
}
1230
-
1231
-
/**
1232
-
* svga3dsurface_get_image_buffer_size - Calculates image buffer size.
1233
-
*
1234
-
* Return the number of bytes of buffer space required to store one image of a
1235
-
* surface, optionally using the specified pitch.
1236
-
*
1237
-
* If pitch is zero, it is assumed that rows are tightly packed.
1238
-
*
1239
-
* This function is overflow-safe. If the result would have overflowed, instead
1240
-
* we return MAX_UINT32.
1241
-
*/
1242
-
static inline u32
1243
-
svga3dsurface_get_image_buffer_size(const struct svga3d_surface_desc *desc,
1244
-
const surf_size_struct *size,
1245
-
u32 pitch)
1246
-
{
1247
-
surf_size_struct image_blocks;
1248
-
u32 slice_size, total_size;
1249
-
1250
-
svga3dsurface_get_size_in_blocks(desc, size, &image_blocks);
1251
-
1252
-
if (svga3dsurface_is_planar_surface(desc)) {
1253
-
total_size = clamped_umul32(image_blocks.width,
1254
-
image_blocks.height);
1255
-
total_size = clamped_umul32(total_size, image_blocks.depth);
1256
-
total_size = clamped_umul32(total_size, desc->bytes_per_block);
1257
-
return total_size;
1258
-
}
1259
-
1260
-
if (pitch == 0)
1261
-
pitch = svga3dsurface_calculate_pitch(desc, size);
1262
-
1263
-
slice_size = clamped_umul32(image_blocks.height, pitch);
1264
-
total_size = clamped_umul32(slice_size, image_blocks.depth);
1265
-
1266
-
return total_size;
1267
-
}
1268
-
1269
-
/**
1270
-
* svga3dsurface_get_serialized_size - Get the serialized size for the image.
1271
-
*/
1272
-
static inline u32
1273
-
svga3dsurface_get_serialized_size(SVGA3dSurfaceFormat format,
1274
-
surf_size_struct base_level_size,
1275
-
u32 num_mip_levels,
1276
-
u32 num_layers)
1277
-
{
1278
-
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1279
-
u32 total_size = 0;
1280
-
u32 mip;
1281
-
1282
-
for (mip = 0; mip < num_mip_levels; mip++) {
1283
-
surf_size_struct size =
1284
-
svga3dsurface_get_mip_size(base_level_size, mip);
1285
-
total_size += svga3dsurface_get_image_buffer_size(desc,
1286
-
&size, 0);
1287
-
}
1288
-
1289
-
return total_size * num_layers;
1290
-
}
1291
-
1292
-
/**
1293
-
* svga3dsurface_get_serialized_size_extended - Returns the number of bytes
1294
-
* required for a surface with given parameters. Support for sample count.
1295
-
*/
1296
-
static inline u32
1297
-
svga3dsurface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
1298
-
surf_size_struct base_level_size,
1299
-
u32 num_mip_levels,
1300
-
u32 num_layers,
1301
-
u32 num_samples)
1302
-
{
1303
-
uint64_t total_size =
1304
-
svga3dsurface_get_serialized_size(format,
1305
-
base_level_size,
1306
-
num_mip_levels,
1307
-
num_layers);
1308
-
total_size *= max_t(u32, 1, num_samples);
1309
-
1310
-
return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
1311
-
}
1312
-
1313
-
/**
1314
-
* svga3dsurface_get_pixel_offset - Compute the offset (in bytes) to a pixel
1315
-
* in an image (or volume).
1316
-
*
1317
-
* @width: The image width in pixels.
1318
-
* @height: The image height in pixels
1319
-
*/
1320
-
static inline u32
1321
-
svga3dsurface_get_pixel_offset(SVGA3dSurfaceFormat format,
1322
-
u32 width, u32 height,
1323
-
u32 x, u32 y, u32 z)
1324
-
{
1325
-
const struct svga3d_surface_desc *desc = svga3dsurface_get_desc(format);
1326
-
const u32 bw = desc->block_size.width, bh = desc->block_size.height;
1327
-
const u32 bd = desc->block_size.depth;
1328
-
const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
1329
-
desc->bytes_per_block;
1330
-
const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
1331
-
const u32 offset = (z / bd * imgstride +
1332
-
y / bh * rowstride +
1333
-
x / bw * desc->bytes_per_block);
1334
-
return offset;
1335
-
}
1336
-
1337
-
static inline u32
1338
-
svga3dsurface_get_image_offset(SVGA3dSurfaceFormat format,
1339
-
surf_size_struct baseLevelSize,
1340
-
u32 numMipLevels,
1341
-
u32 face,
1342
-
u32 mip)
1343
-
1344
-
{
1345
-
u32 offset;
1346
-
u32 mipChainBytes;
1347
-
u32 mipChainBytesToLevel;
1348
-
u32 i;
1349
-
const struct svga3d_surface_desc *desc;
1350
-
surf_size_struct mipSize;
1351
-
u32 bytes;
1352
-
1353
-
desc = svga3dsurface_get_desc(format);
1354
-
1355
-
mipChainBytes = 0;
1356
-
mipChainBytesToLevel = 0;
1357
-
for (i = 0; i < numMipLevels; i++) {
1358
-
mipSize = svga3dsurface_get_mip_size(baseLevelSize, i);
1359
-
bytes = svga3dsurface_get_image_buffer_size(desc, &mipSize, 0);
1360
-
mipChainBytes += bytes;
1361
-
if (i < mip)
1362
-
mipChainBytesToLevel += bytes;
1363
-
}
1364
-
1365
-
offset = mipChainBytes * face + mipChainBytesToLevel;
1366
-
1367
-
return offset;
1368
-
}
1369
-
1370
-
1371
-
/**
1372
-
* svga3dsurface_is_gb_screen_target_format - Is the specified format usable as
1373
-
* a ScreenTarget?
1374
-
* (with just the GBObjects cap-bit
1375
-
* set)
1376
-
* @format: format to queried
1377
-
*
1378
-
* RETURNS:
1379
-
* true if queried format is valid for screen targets
1380
-
*/
1381
-
static inline bool
1382
-
svga3dsurface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
1383
-
{
1384
-
return (format == SVGA3D_X8R8G8B8 ||
1385
-
format == SVGA3D_A8R8G8B8 ||
1386
-
format == SVGA3D_R5G6B5 ||
1387
-
format == SVGA3D_X1R5G5B5 ||
1388
-
format == SVGA3D_A1R5G5B5 ||
1389
-
format == SVGA3D_P8);
1390
-
}
1391
-
1392
-
1393
-
/**
1394
-
* svga3dsurface_is_dx_screen_target_format - Is the specified format usable as
1395
-
* a ScreenTarget?
1396
-
* (with DX10 enabled)
1397
-
*
1398
-
* @format: format to queried
1399
-
*
1400
-
* Results:
1401
-
* true if queried format is valid for screen targets
1402
-
*/
1403
-
static inline bool
1404
-
svga3dsurface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
1405
-
{
1406
-
return (format == SVGA3D_R8G8B8A8_UNORM ||
1407
-
format == SVGA3D_B8G8R8A8_UNORM ||
1408
-
format == SVGA3D_B8G8R8X8_UNORM);
1409
-
}
1410
-
1411
-
1412
-
/**
1413
-
* svga3dsurface_is_screen_target_format - Is the specified format usable as a
1414
-
* ScreenTarget?
1415
-
* (for some combination of caps)
1416
-
*
1417
-
* @format: format to queried
1418
-
*
1419
-
* Results:
1420
-
* true if queried format is valid for screen targets
1421
-
*/
1422
-
static inline bool
1423
-
svga3dsurface_is_screen_target_format(SVGA3dSurfaceFormat format)
1424
-
{
1425
-
if (svga3dsurface_is_gb_screen_target_format(format)) {
1426
-
return true;
1427
-
}
1428
-
return svga3dsurface_is_dx_screen_target_format(format);
1429
-
}
1430
-
1431
-
/**
1432
-
* struct svga3dsurface_mip - Mimpmap level information
1433
-
* @bytes: Bytes required in the backing store of this mipmap level.
1434
-
* @img_stride: Byte stride per image.
1435
-
* @row_stride: Byte stride per block row.
1436
-
* @size: The size of the mipmap.
1437
-
*/
1438
-
struct svga3dsurface_mip {
1439
-
size_t bytes;
1440
-
size_t img_stride;
1441
-
size_t row_stride;
1442
-
struct drm_vmw_size size;
1443
-
1444
-
};
1445
-
1446
-
/**
1447
-
* struct svga3dsurface_cache - Cached surface information
1448
-
* @desc: Pointer to the surface descriptor
1449
-
* @mip: Array of mipmap level information. Valid size is @num_mip_levels.
1450
-
* @mip_chain_bytes: Bytes required in the backing store for the whole chain
1451
-
* of mip levels.
1452
-
* @sheet_bytes: Bytes required in the backing store for a sheet
1453
-
* representing a single sample.
1454
-
* @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
1455
-
* a chain.
1456
-
* @num_layers: Number of slices in an array texture or number of faces in
1457
-
* a cubemap texture.
1458
-
*/
1459
-
struct svga3dsurface_cache {
1460
-
const struct svga3d_surface_desc *desc;
1461
-
struct svga3dsurface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
1462
-
size_t mip_chain_bytes;
1463
-
size_t sheet_bytes;
1464
-
u32 num_mip_levels;
1465
-
u32 num_layers;
1466
-
};
1467
-
1468
-
/**
1469
-
* struct svga3dsurface_loc - Surface location
1470
-
* @sheet: The multisample sheet.
1471
-
* @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
1472
-
* mip_level.
1473
-
* @x: X coordinate.
1474
-
* @y: Y coordinate.
1475
-
* @z: Z coordinate.
1476
-
*/
1477
-
struct svga3dsurface_loc {
1478
-
u32 sheet;
1479
-
u32 sub_resource;
1480
-
u32 x, y, z;
1481
-
};
1482
-
1483
-
/**
1484
-
* svga3dsurface_subres - Compute the subresource from layer and mipmap.
1485
-
* @cache: Surface layout data.
1486
-
* @mip_level: The mipmap level.
1487
-
* @layer: The surface layer (face or array slice).
1488
-
*
1489
-
* Return: The subresource.
1490
-
*/
1491
-
static inline u32 svga3dsurface_subres(const struct svga3dsurface_cache *cache,
1492
-
u32 mip_level, u32 layer)
1493
-
{
1494
-
return cache->num_mip_levels * layer + mip_level;
1495
-
}
1496
-
1497
-
/**
1498
-
* svga3dsurface_setup_cache - Build a surface cache entry
1499
-
* @size: The surface base level dimensions.
1500
-
* @format: The surface format.
1501
-
* @num_mip_levels: Number of mipmap levels.
1502
-
* @num_layers: Number of layers.
1503
-
* @cache: Pointer to a struct svga3dsurface_cach object to be filled in.
1504
-
*
1505
-
* Return: Zero on success, -EINVAL on invalid surface layout.
1506
-
*/
1507
-
static inline int svga3dsurface_setup_cache(const struct drm_vmw_size *size,
1508
-
SVGA3dSurfaceFormat format,
1509
-
u32 num_mip_levels,
1510
-
u32 num_layers,
1511
-
u32 num_samples,
1512
-
struct svga3dsurface_cache *cache)
1513
-
{
1514
-
const struct svga3d_surface_desc *desc;
1515
-
u32 i;
1516
-
1517
-
memset(cache, 0, sizeof(*cache));
1518
-
cache->desc = desc = svga3dsurface_get_desc(format);
1519
-
cache->num_mip_levels = num_mip_levels;
1520
-
cache->num_layers = num_layers;
1521
-
for (i = 0; i < cache->num_mip_levels; i++) {
1522
-
struct svga3dsurface_mip *mip = &cache->mip[i];
1523
-
1524
-
mip->size = svga3dsurface_get_mip_size(*size, i);
1525
-
mip->bytes = svga3dsurface_get_image_buffer_size
1526
-
(desc, &mip->size, 0);
1527
-
mip->row_stride =
1528
-
__KERNEL_DIV_ROUND_UP(mip->size.width,
1529
-
desc->block_size.width) *
1530
-
desc->bytes_per_block * num_samples;
1531
-
if (!mip->row_stride)
1532
-
goto invalid_dim;
1533
-
1534
-
mip->img_stride =
1535
-
__KERNEL_DIV_ROUND_UP(mip->size.height,
1536
-
desc->block_size.height) *
1537
-
mip->row_stride;
1538
-
if (!mip->img_stride)
1539
-
goto invalid_dim;
1540
-
1541
-
cache->mip_chain_bytes += mip->bytes;
1542
-
}
1543
-
cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
1544
-
if (!cache->sheet_bytes)
1545
-
goto invalid_dim;
1546
-
1547
-
return 0;
1548
-
1549
-
invalid_dim:
1550
-
VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
1551
-
return -EINVAL;
1552
-
}
1553
-
1554
-
/**
1555
-
* svga3dsurface_get_loc - Get a surface location from an offset into the
1556
-
* backing store
1557
-
* @cache: Surface layout data.
1558
-
* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1559
-
* @offset: Offset into the surface backing store.
1560
-
*/
1561
-
static inline void
1562
-
svga3dsurface_get_loc(const struct svga3dsurface_cache *cache,
1563
-
struct svga3dsurface_loc *loc,
1564
-
size_t offset)
1565
-
{
1566
-
const struct svga3dsurface_mip *mip = &cache->mip[0];
1567
-
const struct svga3d_surface_desc *desc = cache->desc;
1568
-
u32 layer;
1569
-
int i;
1570
-
1571
-
loc->sheet = offset / cache->sheet_bytes;
1572
-
offset -= loc->sheet * cache->sheet_bytes;
1573
-
1574
-
layer = offset / cache->mip_chain_bytes;
1575
-
offset -= layer * cache->mip_chain_bytes;
1576
-
for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
1577
-
if (mip->bytes > offset)
1578
-
break;
1579
-
offset -= mip->bytes;
1580
-
}
1581
-
1582
-
loc->sub_resource = svga3dsurface_subres(cache, i, layer);
1583
-
loc->z = offset / mip->img_stride;
1584
-
offset -= loc->z * mip->img_stride;
1585
-
loc->z *= desc->block_size.depth;
1586
-
loc->y = offset / mip->row_stride;
1587
-
offset -= loc->y * mip->row_stride;
1588
-
loc->y *= desc->block_size.height;
1589
-
loc->x = offset / desc->bytes_per_block;
1590
-
loc->x *= desc->block_size.width;
1591
-
}
1592
-
1593
-
/**
1594
-
* svga3dsurface_inc_loc - Clamp increment a surface location with one block
1595
-
* size
1596
-
* in each dimension.
1597
-
* @loc: Pointer to a struct svga3dsurface_loc to be incremented.
1598
-
*
1599
-
* When computing the size of a range as size = end - start, the range does not
1600
-
* include the end element. However a location representing the last byte
1601
-
* of a touched region in the backing store *is* included in the range.
1602
-
* This function modifies such a location to match the end definition
1603
-
* given as start + size which is the one used in a SVGA3dBox.
1604
-
*/
1605
-
static inline void
1606
-
svga3dsurface_inc_loc(const struct svga3dsurface_cache *cache,
1607
-
struct svga3dsurface_loc *loc)
1608
-
{
1609
-
const struct svga3d_surface_desc *desc = cache->desc;
1610
-
u32 mip = loc->sub_resource % cache->num_mip_levels;
1611
-
const struct drm_vmw_size *size = &cache->mip[mip].size;
1612
-
1613
-
loc->sub_resource++;
1614
-
loc->x += desc->block_size.width;
1615
-
if (loc->x > size->width)
1616
-
loc->x = size->width;
1617
-
loc->y += desc->block_size.height;
1618
-
if (loc->y > size->height)
1619
-
loc->y = size->height;
1620
-
loc->z += desc->block_size.depth;
1621
-
if (loc->z > size->depth)
1622
-
loc->z = size->depth;
1623
-
}
1624
-
1625
-
/**
1626
-
* svga3dsurface_min_loc - The start location in a subresource
1627
-
* @cache: Surface layout data.
1628
-
* @sub_resource: The subresource.
1629
-
* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1630
-
*/
1631
-
static inline void
1632
-
svga3dsurface_min_loc(const struct svga3dsurface_cache *cache,
1633
-
u32 sub_resource,
1634
-
struct svga3dsurface_loc *loc)
1635
-
{
1636
-
loc->sheet = 0;
1637
-
loc->sub_resource = sub_resource;
1638
-
loc->x = loc->y = loc->z = 0;
1639
-
}
1640
-
1641
-
/**
1642
-
* svga3dsurface_min_loc - The end location in a subresource
1643
-
* @cache: Surface layout data.
1644
-
* @sub_resource: The subresource.
1645
-
* @loc: Pointer to a struct svga3dsurface_loc to be filled in.
1646
-
*
1647
-
* Following the end definition given in svga3dsurface_inc_loc(),
1648
-
* Compute the end location of a surface subresource.
1649
-
*/
1650
-
static inline void
1651
-
svga3dsurface_max_loc(const struct svga3dsurface_cache *cache,
1652
-
u32 sub_resource,
1653
-
struct svga3dsurface_loc *loc)
1654
-
{
1655
-
const struct drm_vmw_size *size;
1656
-
u32 mip;
1657
-
1658
-
loc->sheet = 0;
1659
-
loc->sub_resource = sub_resource + 1;
1660
-
mip = sub_resource % cache->num_mip_levels;
1661
-
size = &cache->mip[mip].size;
1662
-
loc->x = size->width;
1663
-
loc->y = size->height;
1664
-
loc->z = size->depth;
1665
-
}
1666
-
1667
-
#endif /* _SVGA3D_SURFACEDEFS_H_ */
1561
+
#endif
+1218
-1662
drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
+1218
-1662
drivers/gpu/drm/vmwgfx/device_include/svga3d_types.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 2012-2015 VMware, Inc.
2
+
* Copyright 2012-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
27
27
/*
28
28
* svga3d_types.h --
29
29
*
30
-
* SVGA 3d hardware definitions for basic types
30
+
* SVGA 3d hardware definitions for basic types
31
31
*/
32
+
33
+
32
34
33
35
#ifndef _SVGA3D_TYPES_H_
34
36
#define _SVGA3D_TYPES_H_
35
37
36
-
#define INCLUDE_ALLOW_MODULE
37
-
#define INCLUDE_ALLOW_USERLEVEL
38
-
#define INCLUDE_ALLOW_VMCORE
38
+
#include "vm_basic_types.h"
39
39
40
-
#include "includeCheck.h"
40
+
#define SVGA3D_INVALID_ID ((uint32)-1)
41
41
42
-
/*
43
-
* Generic Types
44
-
*/
42
+
#define SVGA3D_RESOURCE_TYPE_MIN 1
43
+
#define SVGA3D_RESOURCE_BUFFER 1
44
+
#define SVGA3D_RESOURCE_TEXTURE1D 2
45
+
#define SVGA3D_RESOURCE_TEXTURE2D 3
46
+
#define SVGA3D_RESOURCE_TEXTURE3D 4
47
+
#define SVGA3D_RESOURCE_TEXTURECUBE 5
48
+
#define SVGA3D_RESOURCE_TYPE_DX10_MAX 6
49
+
#define SVGA3D_RESOURCE_BUFFEREX 6
50
+
#define SVGA3D_RESOURCE_TYPE_MAX 7
51
+
typedef uint32 SVGA3dResourceType;
45
52
46
-
#define SVGA3D_INVALID_ID ((uint32)-1)
47
-
48
-
typedef uint8 SVGABool8; /* 8-bit Bool definition */
49
-
typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
50
-
typedef uint32 SVGA3dColor; /* a, r, g, b */
53
+
typedef uint8 SVGABool8;
54
+
typedef uint32 SVGA3dBool;
55
+
typedef uint32 SVGA3dColor;
51
56
52
57
typedef uint32 SVGA3dSurfaceId;
53
58
54
-
typedef
55
-
#include "vmware_pack_begin.h"
56
-
struct {
57
-
uint32 numerator;
58
-
uint32 denominator;
59
-
}
60
-
#include "vmware_pack_end.h"
61
-
SVGA3dFraction64;
59
+
#pragma pack(push, 1)
60
+
typedef struct {
61
+
uint32 numerator;
62
+
uint32 denominator;
63
+
} SVGA3dFraction64;
64
+
#pragma pack(pop)
62
65
63
-
typedef
64
-
#include "vmware_pack_begin.h"
65
-
struct SVGA3dCopyRect {
66
-
uint32 x;
67
-
uint32 y;
68
-
uint32 w;
69
-
uint32 h;
70
-
uint32 srcx;
71
-
uint32 srcy;
72
-
}
73
-
#include "vmware_pack_end.h"
74
-
SVGA3dCopyRect;
66
+
#pragma pack(push, 1)
67
+
typedef struct SVGA3dCopyRect {
68
+
uint32 x;
69
+
uint32 y;
70
+
uint32 w;
71
+
uint32 h;
72
+
uint32 srcx;
73
+
uint32 srcy;
74
+
} SVGA3dCopyRect;
75
+
#pragma pack(pop)
75
76
76
-
typedef
77
-
#include "vmware_pack_begin.h"
78
-
struct SVGA3dCopyBox {
79
-
uint32 x;
80
-
uint32 y;
81
-
uint32 z;
82
-
uint32 w;
83
-
uint32 h;
84
-
uint32 d;
85
-
uint32 srcx;
86
-
uint32 srcy;
87
-
uint32 srcz;
88
-
}
89
-
#include "vmware_pack_end.h"
90
-
SVGA3dCopyBox;
77
+
#pragma pack(push, 1)
78
+
typedef struct SVGA3dCopyBox {
79
+
uint32 x;
80
+
uint32 y;
81
+
uint32 z;
82
+
uint32 w;
83
+
uint32 h;
84
+
uint32 d;
85
+
uint32 srcx;
86
+
uint32 srcy;
87
+
uint32 srcz;
88
+
} SVGA3dCopyBox;
89
+
#pragma pack(pop)
91
90
92
-
typedef
93
-
#include "vmware_pack_begin.h"
94
-
struct SVGA3dRect {
95
-
uint32 x;
96
-
uint32 y;
97
-
uint32 w;
98
-
uint32 h;
99
-
}
100
-
#include "vmware_pack_end.h"
101
-
SVGA3dRect;
91
+
#pragma pack(push, 1)
92
+
typedef struct SVGA3dRect {
93
+
uint32 x;
94
+
uint32 y;
95
+
uint32 w;
96
+
uint32 h;
97
+
} SVGA3dRect;
98
+
#pragma pack(pop)
102
99
103
-
typedef
104
-
#include "vmware_pack_begin.h"
105
-
struct {
106
-
uint32 x;
107
-
uint32 y;
108
-
uint32 z;
109
-
uint32 w;
110
-
uint32 h;
111
-
uint32 d;
112
-
}
113
-
#include "vmware_pack_end.h"
114
-
SVGA3dBox;
100
+
#pragma pack(push, 1)
101
+
typedef struct {
102
+
uint32 x;
103
+
uint32 y;
104
+
uint32 z;
105
+
uint32 w;
106
+
uint32 h;
107
+
uint32 d;
108
+
} SVGA3dBox;
109
+
#pragma pack(pop)
115
110
116
-
typedef
117
-
#include "vmware_pack_begin.h"
118
-
struct {
119
-
int32 x;
120
-
int32 y;
121
-
int32 z;
122
-
int32 w;
123
-
int32 h;
124
-
int32 d;
125
-
}
126
-
#include "vmware_pack_end.h"
127
-
SVGA3dSignedBox;
111
+
#pragma pack(push, 1)
112
+
typedef struct {
113
+
int32 x;
114
+
int32 y;
115
+
int32 z;
116
+
int32 w;
117
+
int32 h;
118
+
int32 d;
119
+
} SVGA3dSignedBox;
120
+
#pragma pack(pop)
128
121
129
-
typedef
130
-
#include "vmware_pack_begin.h"
131
-
struct {
132
-
uint32 x;
133
-
uint32 y;
134
-
uint32 z;
135
-
}
136
-
#include "vmware_pack_end.h"
137
-
SVGA3dPoint;
122
+
#pragma pack(push, 1)
123
+
typedef struct {
124
+
uint32 x;
125
+
uint32 y;
126
+
uint32 z;
127
+
} SVGA3dPoint;
128
+
#pragma pack(pop)
138
129
139
-
/*
140
-
* Surface formats.
141
-
*/
130
+
#pragma pack(push, 1)
131
+
typedef union {
132
+
struct {
133
+
float r;
134
+
float g;
135
+
float b;
136
+
float a;
137
+
};
138
+
139
+
float value[4];
140
+
} SVGA3dRGBAFloat;
141
+
#pragma pack(pop)
142
+
142
143
typedef enum SVGA3dSurfaceFormat {
143
-
SVGA3D_FORMAT_INVALID = 0,
144
+
SVGA3D_FORMAT_INVALID = 0,
144
145
145
-
SVGA3D_X8R8G8B8 = 1,
146
-
SVGA3D_FORMAT_MIN = 1,
146
+
SVGA3D_X8R8G8B8 = 1,
147
+
SVGA3D_FORMAT_MIN = 1,
147
148
148
-
SVGA3D_A8R8G8B8 = 2,
149
+
SVGA3D_A8R8G8B8 = 2,
149
150
150
-
SVGA3D_R5G6B5 = 3,
151
-
SVGA3D_X1R5G5B5 = 4,
152
-
SVGA3D_A1R5G5B5 = 5,
153
-
SVGA3D_A4R4G4B4 = 6,
151
+
SVGA3D_R5G6B5 = 3,
152
+
SVGA3D_X1R5G5B5 = 4,
153
+
SVGA3D_A1R5G5B5 = 5,
154
+
SVGA3D_A4R4G4B4 = 6,
154
155
155
-
SVGA3D_Z_D32 = 7,
156
-
SVGA3D_Z_D16 = 8,
157
-
SVGA3D_Z_D24S8 = 9,
158
-
SVGA3D_Z_D15S1 = 10,
156
+
SVGA3D_Z_D32 = 7,
157
+
SVGA3D_Z_D16 = 8,
158
+
SVGA3D_Z_D24S8 = 9,
159
+
SVGA3D_Z_D15S1 = 10,
159
160
160
-
SVGA3D_LUMINANCE8 = 11,
161
-
SVGA3D_LUMINANCE4_ALPHA4 = 12,
162
-
SVGA3D_LUMINANCE16 = 13,
163
-
SVGA3D_LUMINANCE8_ALPHA8 = 14,
161
+
SVGA3D_LUMINANCE8 = 11,
162
+
SVGA3D_LUMINANCE4_ALPHA4 = 12,
163
+
SVGA3D_LUMINANCE16 = 13,
164
+
SVGA3D_LUMINANCE8_ALPHA8 = 14,
164
165
165
-
SVGA3D_DXT1 = 15,
166
-
SVGA3D_DXT2 = 16,
167
-
SVGA3D_DXT3 = 17,
168
-
SVGA3D_DXT4 = 18,
169
-
SVGA3D_DXT5 = 19,
166
+
SVGA3D_DXT1 = 15,
167
+
SVGA3D_DXT2 = 16,
168
+
SVGA3D_DXT3 = 17,
169
+
SVGA3D_DXT4 = 18,
170
+
SVGA3D_DXT5 = 19,
170
171
171
-
SVGA3D_BUMPU8V8 = 20,
172
-
SVGA3D_BUMPL6V5U5 = 21,
173
-
SVGA3D_BUMPX8L8V8U8 = 22,
174
-
SVGA3D_FORMAT_DEAD1 = 23,
172
+
SVGA3D_BUMPU8V8 = 20,
173
+
SVGA3D_BUMPL6V5U5 = 21,
174
+
SVGA3D_BUMPX8L8V8U8 = 22,
175
+
SVGA3D_FORMAT_DEAD1 = 23,
175
176
176
-
SVGA3D_ARGB_S10E5 = 24, /* 16-bit floating-point ARGB */
177
-
SVGA3D_ARGB_S23E8 = 25, /* 32-bit floating-point ARGB */
177
+
SVGA3D_ARGB_S10E5 = 24,
178
+
SVGA3D_ARGB_S23E8 = 25,
178
179
179
-
SVGA3D_A2R10G10B10 = 26,
180
+
SVGA3D_A2R10G10B10 = 26,
180
181
181
-
/* signed formats */
182
-
SVGA3D_V8U8 = 27,
183
-
SVGA3D_Q8W8V8U8 = 28,
184
-
SVGA3D_CxV8U8 = 29,
182
+
SVGA3D_V8U8 = 27,
183
+
SVGA3D_Q8W8V8U8 = 28,
184
+
SVGA3D_CxV8U8 = 29,
185
185
186
-
/* mixed formats */
187
-
SVGA3D_X8L8V8U8 = 30,
188
-
SVGA3D_A2W10V10U10 = 31,
186
+
SVGA3D_X8L8V8U8 = 30,
187
+
SVGA3D_A2W10V10U10 = 31,
189
188
190
-
SVGA3D_ALPHA8 = 32,
189
+
SVGA3D_ALPHA8 = 32,
191
190
192
-
/* Single- and dual-component floating point formats */
193
-
SVGA3D_R_S10E5 = 33,
194
-
SVGA3D_R_S23E8 = 34,
195
-
SVGA3D_RG_S10E5 = 35,
196
-
SVGA3D_RG_S23E8 = 36,
191
+
SVGA3D_R_S10E5 = 33,
192
+
SVGA3D_R_S23E8 = 34,
193
+
SVGA3D_RG_S10E5 = 35,
194
+
SVGA3D_RG_S23E8 = 36,
197
195
198
-
SVGA3D_BUFFER = 37,
196
+
SVGA3D_BUFFER = 37,
199
197
200
-
SVGA3D_Z_D24X8 = 38,
198
+
SVGA3D_Z_D24X8 = 38,
201
199
202
-
SVGA3D_V16U16 = 39,
200
+
SVGA3D_V16U16 = 39,
203
201
204
-
SVGA3D_G16R16 = 40,
205
-
SVGA3D_A16B16G16R16 = 41,
202
+
SVGA3D_G16R16 = 40,
203
+
SVGA3D_A16B16G16R16 = 41,
206
204
207
-
/* Packed Video formats */
208
-
SVGA3D_UYVY = 42,
209
-
SVGA3D_YUY2 = 43,
205
+
SVGA3D_UYVY = 42,
206
+
SVGA3D_YUY2 = 43,
210
207
211
-
/* Planar video formats */
212
-
SVGA3D_NV12 = 44,
208
+
SVGA3D_NV12 = 44,
213
209
214
-
SVGA3D_FORMAT_DEAD2 = 45,
210
+
SVGA3D_FORMAT_DEAD2 = 45,
215
211
216
-
SVGA3D_R32G32B32A32_TYPELESS = 46,
217
-
SVGA3D_R32G32B32A32_UINT = 47,
218
-
SVGA3D_R32G32B32A32_SINT = 48,
219
-
SVGA3D_R32G32B32_TYPELESS = 49,
220
-
SVGA3D_R32G32B32_FLOAT = 50,
221
-
SVGA3D_R32G32B32_UINT = 51,
222
-
SVGA3D_R32G32B32_SINT = 52,
223
-
SVGA3D_R16G16B16A16_TYPELESS = 53,
224
-
SVGA3D_R16G16B16A16_UINT = 54,
225
-
SVGA3D_R16G16B16A16_SNORM = 55,
226
-
SVGA3D_R16G16B16A16_SINT = 56,
227
-
SVGA3D_R32G32_TYPELESS = 57,
228
-
SVGA3D_R32G32_UINT = 58,
229
-
SVGA3D_R32G32_SINT = 59,
230
-
SVGA3D_R32G8X24_TYPELESS = 60,
231
-
SVGA3D_D32_FLOAT_S8X24_UINT = 61,
232
-
SVGA3D_R32_FLOAT_X8X24 = 62,
233
-
SVGA3D_X32_G8X24_UINT = 63,
234
-
SVGA3D_R10G10B10A2_TYPELESS = 64,
235
-
SVGA3D_R10G10B10A2_UINT = 65,
236
-
SVGA3D_R11G11B10_FLOAT = 66,
237
-
SVGA3D_R8G8B8A8_TYPELESS = 67,
238
-
SVGA3D_R8G8B8A8_UNORM = 68,
239
-
SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
240
-
SVGA3D_R8G8B8A8_UINT = 70,
241
-
SVGA3D_R8G8B8A8_SINT = 71,
242
-
SVGA3D_R16G16_TYPELESS = 72,
243
-
SVGA3D_R16G16_UINT = 73,
244
-
SVGA3D_R16G16_SINT = 74,
245
-
SVGA3D_R32_TYPELESS = 75,
246
-
SVGA3D_D32_FLOAT = 76,
247
-
SVGA3D_R32_UINT = 77,
248
-
SVGA3D_R32_SINT = 78,
249
-
SVGA3D_R24G8_TYPELESS = 79,
250
-
SVGA3D_D24_UNORM_S8_UINT = 80,
251
-
SVGA3D_R24_UNORM_X8 = 81,
252
-
SVGA3D_X24_G8_UINT = 82,
253
-
SVGA3D_R8G8_TYPELESS = 83,
254
-
SVGA3D_R8G8_UNORM = 84,
255
-
SVGA3D_R8G8_UINT = 85,
256
-
SVGA3D_R8G8_SINT = 86,
257
-
SVGA3D_R16_TYPELESS = 87,
258
-
SVGA3D_R16_UNORM = 88,
259
-
SVGA3D_R16_UINT = 89,
260
-
SVGA3D_R16_SNORM = 90,
261
-
SVGA3D_R16_SINT = 91,
262
-
SVGA3D_R8_TYPELESS = 92,
263
-
SVGA3D_R8_UNORM = 93,
264
-
SVGA3D_R8_UINT = 94,
265
-
SVGA3D_R8_SNORM = 95,
266
-
SVGA3D_R8_SINT = 96,
267
-
SVGA3D_P8 = 97,
268
-
SVGA3D_R9G9B9E5_SHAREDEXP = 98,
269
-
SVGA3D_R8G8_B8G8_UNORM = 99,
270
-
SVGA3D_G8R8_G8B8_UNORM = 100,
271
-
SVGA3D_BC1_TYPELESS = 101,
272
-
SVGA3D_BC1_UNORM_SRGB = 102,
273
-
SVGA3D_BC2_TYPELESS = 103,
274
-
SVGA3D_BC2_UNORM_SRGB = 104,
275
-
SVGA3D_BC3_TYPELESS = 105,
276
-
SVGA3D_BC3_UNORM_SRGB = 106,
277
-
SVGA3D_BC4_TYPELESS = 107,
278
-
SVGA3D_ATI1 = 108, /* DX9-specific BC4_UNORM */
279
-
SVGA3D_BC4_SNORM = 109,
280
-
SVGA3D_BC5_TYPELESS = 110,
281
-
SVGA3D_ATI2 = 111, /* DX9-specific BC5_UNORM */
282
-
SVGA3D_BC5_SNORM = 112,
283
-
SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
284
-
SVGA3D_B8G8R8A8_TYPELESS = 114,
285
-
SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
286
-
SVGA3D_B8G8R8X8_TYPELESS = 116,
287
-
SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
212
+
SVGA3D_R32G32B32A32_TYPELESS = 46,
213
+
SVGA3D_R32G32B32A32_UINT = 47,
214
+
SVGA3D_R32G32B32A32_SINT = 48,
215
+
SVGA3D_R32G32B32_TYPELESS = 49,
216
+
SVGA3D_R32G32B32_FLOAT = 50,
217
+
SVGA3D_R32G32B32_UINT = 51,
218
+
SVGA3D_R32G32B32_SINT = 52,
219
+
SVGA3D_R16G16B16A16_TYPELESS = 53,
220
+
SVGA3D_R16G16B16A16_UINT = 54,
221
+
SVGA3D_R16G16B16A16_SNORM = 55,
222
+
SVGA3D_R16G16B16A16_SINT = 56,
223
+
SVGA3D_R32G32_TYPELESS = 57,
224
+
SVGA3D_R32G32_UINT = 58,
225
+
SVGA3D_R32G32_SINT = 59,
226
+
SVGA3D_R32G8X24_TYPELESS = 60,
227
+
SVGA3D_D32_FLOAT_S8X24_UINT = 61,
228
+
SVGA3D_R32_FLOAT_X8X24 = 62,
229
+
SVGA3D_X32_G8X24_UINT = 63,
230
+
SVGA3D_R10G10B10A2_TYPELESS = 64,
231
+
SVGA3D_R10G10B10A2_UINT = 65,
232
+
SVGA3D_R11G11B10_FLOAT = 66,
233
+
SVGA3D_R8G8B8A8_TYPELESS = 67,
234
+
SVGA3D_R8G8B8A8_UNORM = 68,
235
+
SVGA3D_R8G8B8A8_UNORM_SRGB = 69,
236
+
SVGA3D_R8G8B8A8_UINT = 70,
237
+
SVGA3D_R8G8B8A8_SINT = 71,
238
+
SVGA3D_R16G16_TYPELESS = 72,
239
+
SVGA3D_R16G16_UINT = 73,
240
+
SVGA3D_R16G16_SINT = 74,
241
+
SVGA3D_R32_TYPELESS = 75,
242
+
SVGA3D_D32_FLOAT = 76,
243
+
SVGA3D_R32_UINT = 77,
244
+
SVGA3D_R32_SINT = 78,
245
+
SVGA3D_R24G8_TYPELESS = 79,
246
+
SVGA3D_D24_UNORM_S8_UINT = 80,
247
+
SVGA3D_R24_UNORM_X8 = 81,
248
+
SVGA3D_X24_G8_UINT = 82,
249
+
SVGA3D_R8G8_TYPELESS = 83,
250
+
SVGA3D_R8G8_UNORM = 84,
251
+
SVGA3D_R8G8_UINT = 85,
252
+
SVGA3D_R8G8_SINT = 86,
253
+
SVGA3D_R16_TYPELESS = 87,
254
+
SVGA3D_R16_UNORM = 88,
255
+
SVGA3D_R16_UINT = 89,
256
+
SVGA3D_R16_SNORM = 90,
257
+
SVGA3D_R16_SINT = 91,
258
+
SVGA3D_R8_TYPELESS = 92,
259
+
SVGA3D_R8_UNORM = 93,
260
+
SVGA3D_R8_UINT = 94,
261
+
SVGA3D_R8_SNORM = 95,
262
+
SVGA3D_R8_SINT = 96,
263
+
SVGA3D_P8 = 97,
264
+
SVGA3D_R9G9B9E5_SHAREDEXP = 98,
265
+
SVGA3D_R8G8_B8G8_UNORM = 99,
266
+
SVGA3D_G8R8_G8B8_UNORM = 100,
267
+
SVGA3D_BC1_TYPELESS = 101,
268
+
SVGA3D_BC1_UNORM_SRGB = 102,
269
+
SVGA3D_BC2_TYPELESS = 103,
270
+
SVGA3D_BC2_UNORM_SRGB = 104,
271
+
SVGA3D_BC3_TYPELESS = 105,
272
+
SVGA3D_BC3_UNORM_SRGB = 106,
273
+
SVGA3D_BC4_TYPELESS = 107,
274
+
SVGA3D_ATI1 = 108,
275
+
SVGA3D_BC4_SNORM = 109,
276
+
SVGA3D_BC5_TYPELESS = 110,
277
+
SVGA3D_ATI2 = 111,
278
+
SVGA3D_BC5_SNORM = 112,
279
+
SVGA3D_R10G10B10_XR_BIAS_A2_UNORM = 113,
280
+
SVGA3D_B8G8R8A8_TYPELESS = 114,
281
+
SVGA3D_B8G8R8A8_UNORM_SRGB = 115,
282
+
SVGA3D_B8G8R8X8_TYPELESS = 116,
283
+
SVGA3D_B8G8R8X8_UNORM_SRGB = 117,
288
284
289
-
/* Advanced depth formats. */
290
-
SVGA3D_Z_DF16 = 118,
291
-
SVGA3D_Z_DF24 = 119,
292
-
SVGA3D_Z_D24S8_INT = 120,
285
+
SVGA3D_Z_DF16 = 118,
286
+
SVGA3D_Z_DF24 = 119,
287
+
SVGA3D_Z_D24S8_INT = 120,
293
288
294
-
/* Planar video formats. */
295
-
SVGA3D_YV12 = 121,
289
+
SVGA3D_YV12 = 121,
296
290
297
-
SVGA3D_R32G32B32A32_FLOAT = 122,
298
-
SVGA3D_R16G16B16A16_FLOAT = 123,
299
-
SVGA3D_R16G16B16A16_UNORM = 124,
300
-
SVGA3D_R32G32_FLOAT = 125,
301
-
SVGA3D_R10G10B10A2_UNORM = 126,
302
-
SVGA3D_R8G8B8A8_SNORM = 127,
303
-
SVGA3D_R16G16_FLOAT = 128,
304
-
SVGA3D_R16G16_UNORM = 129,
305
-
SVGA3D_R16G16_SNORM = 130,
306
-
SVGA3D_R32_FLOAT = 131,
307
-
SVGA3D_R8G8_SNORM = 132,
308
-
SVGA3D_R16_FLOAT = 133,
309
-
SVGA3D_D16_UNORM = 134,
310
-
SVGA3D_A8_UNORM = 135,
311
-
SVGA3D_BC1_UNORM = 136,
312
-
SVGA3D_BC2_UNORM = 137,
313
-
SVGA3D_BC3_UNORM = 138,
314
-
SVGA3D_B5G6R5_UNORM = 139,
315
-
SVGA3D_B5G5R5A1_UNORM = 140,
316
-
SVGA3D_B8G8R8A8_UNORM = 141,
317
-
SVGA3D_B8G8R8X8_UNORM = 142,
318
-
SVGA3D_BC4_UNORM = 143,
319
-
SVGA3D_BC5_UNORM = 144,
320
-
SVGA3D_B4G4R4A4_UNORM = 145,
321
-
322
-
/* DX11 compressed formats */
323
-
SVGA3D_BC6H_TYPELESS = 146,
324
-
SVGA3D_BC6H_UF16 = 147,
325
-
SVGA3D_BC6H_SF16 = 148,
326
-
SVGA3D_BC7_TYPELESS = 149,
327
-
SVGA3D_BC7_UNORM = 150,
328
-
SVGA3D_BC7_UNORM_SRGB = 151,
291
+
SVGA3D_R32G32B32A32_FLOAT = 122,
292
+
SVGA3D_R16G16B16A16_FLOAT = 123,
293
+
SVGA3D_R16G16B16A16_UNORM = 124,
294
+
SVGA3D_R32G32_FLOAT = 125,
295
+
SVGA3D_R10G10B10A2_UNORM = 126,
296
+
SVGA3D_R8G8B8A8_SNORM = 127,
297
+
SVGA3D_R16G16_FLOAT = 128,
298
+
SVGA3D_R16G16_UNORM = 129,
299
+
SVGA3D_R16G16_SNORM = 130,
300
+
SVGA3D_R32_FLOAT = 131,
301
+
SVGA3D_R8G8_SNORM = 132,
302
+
SVGA3D_R16_FLOAT = 133,
303
+
SVGA3D_D16_UNORM = 134,
304
+
SVGA3D_A8_UNORM = 135,
305
+
SVGA3D_BC1_UNORM = 136,
306
+
SVGA3D_BC2_UNORM = 137,
307
+
SVGA3D_BC3_UNORM = 138,
308
+
SVGA3D_B5G6R5_UNORM = 139,
309
+
SVGA3D_B5G5R5A1_UNORM = 140,
310
+
SVGA3D_B8G8R8A8_UNORM = 141,
311
+
SVGA3D_B8G8R8X8_UNORM = 142,
312
+
SVGA3D_BC4_UNORM = 143,
313
+
SVGA3D_BC5_UNORM = 144,
314
+
SVGA3D_B4G4R4A4_UNORM = 145,
329
315
330
-
/* Video format with alpha */
331
-
SVGA3D_AYUV = 152,
316
+
SVGA3D_BC6H_TYPELESS = 146,
317
+
SVGA3D_BC6H_UF16 = 147,
318
+
SVGA3D_BC6H_SF16 = 148,
319
+
SVGA3D_BC7_TYPELESS = 149,
320
+
SVGA3D_BC7_UNORM = 150,
321
+
SVGA3D_BC7_UNORM_SRGB = 151,
332
322
333
-
SVGA3D_FORMAT_MAX
323
+
SVGA3D_AYUV = 152,
324
+
325
+
SVGA3D_R11G11B10_TYPELESS = 153,
326
+
327
+
SVGA3D_FORMAT_MAX
334
328
} SVGA3dSurfaceFormat;
335
329
336
-
/*
337
-
* SVGA3d Surface Flags --
338
-
*/
339
-
#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
330
+
#define SVGA3D_SURFACE_CUBEMAP (1 << 0)
340
331
341
-
/*
342
-
* HINT flags are not enforced by the device but are useful for
343
-
* performance.
344
-
*/
345
-
#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
346
-
#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
347
-
#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
348
-
#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
349
-
#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
350
-
#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
351
-
#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
352
-
#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
353
-
#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9)
354
-
#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
332
+
#define SVGA3D_SURFACE_HINT_STATIC (CONST64U(1) << 1)
333
+
#define SVGA3D_SURFACE_HINT_DYNAMIC (CONST64U(1) << 2)
334
+
#define SVGA3D_SURFACE_HINT_INDEXBUFFER (CONST64U(1) << 3)
335
+
#define SVGA3D_SURFACE_HINT_VERTEXBUFFER (CONST64U(1) << 4)
336
+
#define SVGA3D_SURFACE_HINT_TEXTURE (CONST64U(1) << 5)
337
+
#define SVGA3D_SURFACE_HINT_RENDERTARGET (CONST64U(1) << 6)
338
+
#define SVGA3D_SURFACE_HINT_DEPTHSTENCIL (CONST64U(1) << 7)
339
+
#define SVGA3D_SURFACE_HINT_WRITEONLY (CONST64U(1) << 8)
340
+
#define SVGA3D_SURFACE_DEAD2 (CONST64U(1) << 9)
341
+
#define SVGA3D_SURFACE_AUTOGENMIPMAPS (CONST64U(1) << 10)
355
342
356
-
#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11)
343
+
#define SVGA3D_SURFACE_DEAD1 (CONST64U(1) << 11)
357
344
358
-
/*
359
-
* Is this surface using a base-level pitch for it's mob backing?
360
-
*
361
-
* This flag is not intended to be set by guest-drivers, but is instead
362
-
* set by the device when the surface is bound to a mob with a specified
363
-
* pitch.
364
-
*/
365
-
#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
345
+
#define SVGA3D_SURFACE_MOB_PITCH (CONST64U(1) << 12)
366
346
367
-
#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
368
-
#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
369
-
#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
347
+
#define SVGA3D_SURFACE_INACTIVE (CONST64U(1) << 13)
348
+
#define SVGA3D_SURFACE_HINT_RT_LOCKABLE (CONST64U(1) << 14)
349
+
#define SVGA3D_SURFACE_VOLUME (CONST64U(1) << 15)
370
350
371
-
/*
372
-
* Required to be set on a surface to bind it to a screen target.
373
-
*/
374
-
#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
351
+
#define SVGA3D_SURFACE_SCREENTARGET (CONST64U(1) << 16)
375
352
376
-
/*
377
-
* Align images in the guest-backing mob to 16-bytes.
378
-
*/
379
-
#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
353
+
#define SVGA3D_SURFACE_ALIGN16 (CONST64U(1) << 17)
380
354
381
-
#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
382
-
#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
355
+
#define SVGA3D_SURFACE_1D (CONST64U(1) << 18)
356
+
#define SVGA3D_SURFACE_ARRAY (CONST64U(1) << 19)
383
357
384
-
/*
385
-
* Bind flags.
386
-
* These are enforced for any surface defined with DefineGBSurface_v2.
387
-
*/
388
-
#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
389
-
#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
390
-
#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
391
-
#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
392
-
#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
393
-
#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
394
-
#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
358
+
#define SVGA3D_SURFACE_BIND_VERTEX_BUFFER (CONST64U(1) << 20)
359
+
#define SVGA3D_SURFACE_BIND_INDEX_BUFFER (CONST64U(1) << 21)
360
+
#define SVGA3D_SURFACE_BIND_CONSTANT_BUFFER (CONST64U(1) << 22)
361
+
#define SVGA3D_SURFACE_BIND_SHADER_RESOURCE (CONST64U(1) << 23)
362
+
#define SVGA3D_SURFACE_BIND_RENDER_TARGET (CONST64U(1) << 24)
363
+
#define SVGA3D_SURFACE_BIND_DEPTH_STENCIL (CONST64U(1) << 25)
364
+
#define SVGA3D_SURFACE_BIND_STREAM_OUTPUT (CONST64U(1) << 26)
395
365
396
-
/*
397
-
* The STAGING flags notes that the surface will not be used directly by the
398
-
* drawing pipeline, i.e. that it will not be bound to any bind point.
399
-
* Staging surfaces may be used by copy operations to move data in and out
400
-
* of other surfaces. No bind flags may be set on surfaces with this flag.
401
-
*
402
-
* The HINT_INDIRECT_UPDATE flag suggests that the surface will receive
403
-
* updates indirectly, i.e. the surface will not be updated directly, but
404
-
* will receive copies from staging surfaces.
405
-
*/
406
-
#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
407
-
#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
408
-
#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
366
+
#define SVGA3D_SURFACE_STAGING_UPLOAD (CONST64U(1) << 27)
367
+
#define SVGA3D_SURFACE_STAGING_DOWNLOAD (CONST64U(1) << 28)
368
+
#define SVGA3D_SURFACE_HINT_INDIRECT_UPDATE (CONST64U(1) << 29)
409
369
410
-
/*
411
-
* Setting this flag allow this surface to be used with the
412
-
* SVGA_3D_CMD_DX_TRANSFER_FROM_BUFFER command. It is only valid for
413
-
* buffer surfaces, and no bind flags are allowed to be set on surfaces
414
-
* with this flag except SVGA3D_SURFACE_TRANSFER_TO_BUFFER.
415
-
*/
416
-
#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
370
+
#define SVGA3D_SURFACE_TRANSFER_FROM_BUFFER (CONST64U(1) << 30)
417
371
418
-
/*
419
-
* Reserved for video operations.
420
-
*/
421
-
#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
372
+
#define SVGA3D_SURFACE_RESERVED1 (CONST64U(1) << 31)
373
+
#define SVGA3D_SURFACE_VADECODE SVGA3D_SURFACE_RESERVED1
422
374
423
-
/*
424
-
* Specifies that a surface is multisample, and therefore requires the full
425
-
* mob-backing to store all the samples.
426
-
*/
427
-
#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
375
+
#define SVGA3D_SURFACE_MULTISAMPLE (CONST64U(1) << 32)
428
376
429
-
/*
430
-
* Specified that the surface is allowed to be bound to a UAView.
431
-
*/
432
-
#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33)
377
+
#define SVGA3D_SURFACE_BIND_UAVIEW (CONST64U(1) << 33)
433
378
434
-
/*
435
-
* Setting this flag allow this surface to be used with the
436
-
* SVGA_3D_CMD_DX_TRANSFER_TO_BUFFER command. It is only valid for
437
-
* buffer surfaces, and no bind flags are allowed to be set on surfaces
438
-
* with this flag except SVGA3D_SURFACE_TRANSFER_FROM_BUFFER.
439
-
*/
440
-
#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34)
379
+
#define SVGA3D_SURFACE_TRANSFER_TO_BUFFER (CONST64U(1) << 34)
441
380
442
-
#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35)
381
+
#define SVGA3D_SURFACE_BIND_LOGICOPS (CONST64U(1) << 35)
443
382
444
-
/*
445
-
* Optional flags for use with SVGA3D_SURFACE_BIND_UAVIEW
446
-
*/
447
-
#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36)
448
-
#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37)
383
+
#define SVGA3D_SURFACE_BIND_RAW_VIEWS (CONST64U(1) << 36)
384
+
#define SVGA3D_SURFACE_BUFFER_STRUCTURED (CONST64U(1) << 37)
449
385
450
-
#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38)
451
-
#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39)
386
+
#define SVGA3D_SURFACE_DRAWINDIRECT_ARGS (CONST64U(1) << 38)
387
+
#define SVGA3D_SURFACE_RESOURCE_CLAMP (CONST64U(1) << 39)
452
388
453
-
#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 40)
389
+
#define SVGA3D_SURFACE_STAGING_COPY (CONST64U(1) << 40)
454
390
455
-
/*
456
-
* Surface flags types:
457
-
*
458
-
* SVGA3dSurface1Flags: Lower 32-bits of flags.
459
-
* SVGA3dSurface2Flags: Upper 32-bits of flags.
460
-
* SVGA3dSurfaceAllFlags: Full 64-bits of flags.
461
-
*/
391
+
#define SVGA3D_SURFACE_FLAG_MAX (CONST64U(1) << 44)
392
+
462
393
typedef uint32 SVGA3dSurface1Flags;
463
394
typedef uint32 SVGA3dSurface2Flags;
464
395
typedef uint64 SVGA3dSurfaceAllFlags;
465
396
466
-
#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64_t)MAX_UINT32)
397
+
#define SVGA3D_SURFACE_FLAGS1_MASK ((uint64)MAX_UINT32)
467
398
#define SVGA3D_SURFACE_FLAGS2_MASK (MAX_UINT64 & ~SVGA3D_SURFACE_FLAGS1_MASK)
468
399
469
-
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
470
-
( SVGA3D_SURFACE_MOB_PITCH | \
471
-
SVGA3D_SURFACE_SCREENTARGET | \
472
-
SVGA3D_SURFACE_ALIGN16 | \
473
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
474
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
475
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
476
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
477
-
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
478
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
479
-
SVGA3D_SURFACE_RESERVED1 | \
480
-
SVGA3D_SURFACE_MULTISAMPLE | \
481
-
SVGA3D_SURFACE_BIND_UAVIEW | \
482
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
483
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
484
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
485
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
486
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
487
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
488
-
)
400
+
#define SVGA3D_SURFACE_HB_DISALLOWED_MASK \
401
+
(SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_SCREENTARGET | \
402
+
SVGA3D_SURFACE_ALIGN16 | SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
403
+
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \
404
+
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
405
+
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
406
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
407
+
SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
408
+
SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
409
+
SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
410
+
SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \
411
+
SVGA3D_SURFACE_RESTRICT_UPDATE | SVGA3D_SURFACE_BIND_TENSOR | \
412
+
SVGA3D_SURFACE_LO_STAGING)
489
413
490
-
#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
491
-
( SVGA3D_SURFACE_1D | \
492
-
SVGA3D_SURFACE_RESERVED1 | \
493
-
SVGA3D_SURFACE_MULTISAMPLE \
494
-
)
414
+
#define SVGA3D_SURFACE_HB_PRESENT_DISALLOWED_MASK \
415
+
(SVGA3D_SURFACE_1D | SVGA3D_SURFACE_MULTISAMPLE | \
416
+
SVGA3D_SURFACE_STAGING_COPY)
495
417
496
-
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
497
-
( SVGA3D_SURFACE_CUBEMAP | \
498
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
499
-
SVGA3D_SURFACE_VOLUME | \
500
-
SVGA3D_SURFACE_1D | \
501
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
502
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
503
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
504
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
505
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
506
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
507
-
SVGA3D_SURFACE_RESERVED1 | \
508
-
SVGA3D_SURFACE_MULTISAMPLE | \
509
-
SVGA3D_SURFACE_BIND_UAVIEW | \
510
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
511
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
512
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
513
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
514
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
515
-
)
418
+
#define SVGA3D_SURFACE_2D_DISALLOWED_MASK \
419
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
420
+
SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
421
+
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
422
+
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
423
+
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
424
+
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
425
+
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
426
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
427
+
SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
428
+
SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
429
+
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
430
+
SVGA3D_SURFACE_BIND_TENSOR)
516
431
517
-
#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
518
-
( SVGA3D_SURFACE_CUBEMAP | \
519
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
520
-
SVGA3D_SURFACE_VOLUME | \
521
-
SVGA3D_SURFACE_1D | \
522
-
SVGA3D_SURFACE_RESERVED1 | \
523
-
SVGA3D_SURFACE_MULTISAMPLE \
524
-
)
432
+
#define SVGA3D_SURFACE_BASICOPS_DISALLOWED_MASK \
433
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
434
+
SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
435
+
SVGA3D_SURFACE_MULTISAMPLE)
525
436
526
-
#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
527
-
( SVGA3D_SURFACE_CUBEMAP | \
528
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
529
-
SVGA3D_SURFACE_VOLUME | \
530
-
SVGA3D_SURFACE_1D | \
531
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
532
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
533
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
534
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
535
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
536
-
SVGA3D_SURFACE_INACTIVE | \
537
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
538
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
539
-
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
540
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
541
-
SVGA3D_SURFACE_RESERVED1 | \
542
-
SVGA3D_SURFACE_MULTISAMPLE | \
543
-
SVGA3D_SURFACE_BIND_UAVIEW | \
544
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
545
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
546
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
547
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
548
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
549
-
)
437
+
#define SVGA3D_SURFACE_SCREENTARGET_DISALLOWED_MASK \
438
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
439
+
SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
440
+
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
441
+
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
442
+
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
443
+
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
444
+
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_INACTIVE | \
445
+
SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \
446
+
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
447
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
448
+
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
449
+
SVGA3D_SURFACE_BUFFER_STRUCTURED | SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
450
+
SVGA3D_SURFACE_RESOURCE_CLAMP | SVGA3D_SURFACE_STAGING_COPY | \
451
+
SVGA3D_SURFACE_BIND_TENSOR | SVGA3D_SURFACE_LO_STAGING)
550
452
551
-
#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
552
-
( SVGA3D_SURFACE_CUBEMAP | \
553
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
554
-
SVGA3D_SURFACE_VOLUME | \
555
-
SVGA3D_SURFACE_1D | \
556
-
SVGA3D_SURFACE_DEAD2 | \
557
-
SVGA3D_SURFACE_ARRAY | \
558
-
SVGA3D_SURFACE_MULTISAMPLE | \
559
-
SVGA3D_SURFACE_MOB_PITCH | \
560
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
561
-
)
453
+
#define SVGA3D_SURFACE_BUFFER_DISALLOWED_MASK \
454
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
455
+
SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | SVGA3D_SURFACE_DEAD2 | \
456
+
SVGA3D_SURFACE_ARRAY | SVGA3D_SURFACE_MULTISAMPLE | \
457
+
SVGA3D_SURFACE_MOB_PITCH | SVGA3D_SURFACE_RESOURCE_CLAMP)
562
458
563
-
#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
564
-
( SVGA3D_SURFACE_CUBEMAP | \
565
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
566
-
SVGA3D_SURFACE_VOLUME | \
567
-
SVGA3D_SURFACE_1D | \
568
-
SVGA3D_SURFACE_SCREENTARGET | \
569
-
SVGA3D_SURFACE_MOB_PITCH | \
570
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
571
-
SVGA3D_SURFACE_RESERVED1 | \
572
-
SVGA3D_SURFACE_BIND_UAVIEW | \
573
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
574
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
575
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
576
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
577
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS \
578
-
)
459
+
#define SVGA3D_SURFACE_MULTISAMPLE_DISALLOWED_MASK \
460
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
461
+
SVGA3D_SURFACE_VOLUME | SVGA3D_SURFACE_1D | \
462
+
SVGA3D_SURFACE_SCREENTARGET | SVGA3D_SURFACE_MOB_PITCH | \
463
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_BIND_UAVIEW | \
464
+
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | SVGA3D_SURFACE_BIND_LOGICOPS | \
465
+
SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
466
+
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_STAGING_COPY)
579
467
580
-
#define SVGA3D_SURFACE_DX_ONLY_MASK \
581
-
( SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
582
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
583
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
584
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
585
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER \
586
-
)
468
+
#define SVGA3D_SURFACE_DX_ONLY_MASK \
469
+
(SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_STAGING_UPLOAD | \
470
+
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
471
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
472
+
SVGA3D_SURFACE_TRANSFER_TO_BUFFER)
587
473
588
-
#define SVGA3D_SURFACE_STAGING_MASK \
589
-
( SVGA3D_SURFACE_STAGING_UPLOAD | \
590
-
SVGA3D_SURFACE_STAGING_DOWNLOAD \
591
-
)
474
+
#define SVGA3D_SURFACE_ANY_STAGING_MASK \
475
+
(SVGA3D_SURFACE_STAGING_UPLOAD | SVGA3D_SURFACE_STAGING_DOWNLOAD | \
476
+
SVGA3D_SURFACE_STAGING_COPY | SVGA3D_SURFACE_LO_STAGING)
592
477
593
-
#define SVGA3D_SURFACE_BIND_MASK \
594
-
( SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
595
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
596
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
597
-
SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
598
-
SVGA3D_SURFACE_BIND_RENDER_TARGET | \
599
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
600
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
601
-
SVGA3D_SURFACE_BIND_UAVIEW | \
602
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
603
-
SVGA3D_SURFACE_BIND_RAW_VIEWS \
604
-
)
478
+
#define SVGA3D_SURFACE_ANY_NONHINT_STAGING_MASK \
479
+
(SVGA3D_SURFACE_ANY_STAGING_MASK & ~(SVGA3D_SURFACE_LO_STAGING))
605
480
606
-
#define SVGA3D_SURFACE_VADECODE_DISALLOWED_MASK \
607
-
( SVGA3D_SURFACE_CUBEMAP | \
608
-
SVGA3D_SURFACE_HINT_STATIC | \
609
-
SVGA3D_SURFACE_HINT_DYNAMIC | \
610
-
SVGA3D_SURFACE_HINT_INDEXBUFFER | \
611
-
SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
612
-
SVGA3D_SURFACE_HINT_TEXTURE | \
613
-
SVGA3D_SURFACE_HINT_RENDERTARGET | \
614
-
SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
615
-
SVGA3D_SURFACE_HINT_WRITEONLY | \
616
-
SVGA3D_SURFACE_DEAD2 | \
617
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
618
-
SVGA3D_SURFACE_HINT_RT_LOCKABLE | \
619
-
SVGA3D_SURFACE_VOLUME | \
620
-
SVGA3D_SURFACE_SCREENTARGET | \
621
-
SVGA3D_SURFACE_1D | \
622
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
623
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
624
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
625
-
SVGA3D_SURFACE_BIND_RENDER_TARGET | \
626
-
SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
627
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
628
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
629
-
SVGA3D_SURFACE_INACTIVE | \
630
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
631
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
632
-
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | \
633
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
634
-
SVGA3D_SURFACE_MULTISAMPLE | \
635
-
SVGA3D_SURFACE_BIND_UAVIEW | \
636
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
637
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
638
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
639
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
640
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
641
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
642
-
)
481
+
#define SVGA3D_SURFACE_BIND_MASK \
482
+
(SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
483
+
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
484
+
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
485
+
SVGA3D_SURFACE_BIND_SHADER_RESOURCE | \
486
+
SVGA3D_SURFACE_BIND_RENDER_TARGET | \
487
+
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
488
+
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | SVGA3D_SURFACE_BIND_UAVIEW | \
489
+
SVGA3D_SURFACE_BIND_LOGICOPS | SVGA3D_SURFACE_BIND_RAW_VIEWS | \
490
+
SVGA3D_SURFACE_BIND_TENSOR)
643
491
644
-
#define SVGA3D_SURFACE_VAPROCESSFRAME_OUTPUT_DISALLOWED_MASK \
645
-
( SVGA3D_SURFACE_HINT_INDEXBUFFER | \
646
-
SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
647
-
SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
648
-
SVGA3D_SURFACE_DEAD2 | \
649
-
SVGA3D_SURFACE_VOLUME | \
650
-
SVGA3D_SURFACE_1D | \
651
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
652
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
653
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
654
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
655
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
656
-
SVGA3D_SURFACE_INACTIVE | \
657
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
658
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
659
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
660
-
SVGA3D_SURFACE_VADECODE | \
661
-
SVGA3D_SURFACE_MULTISAMPLE | \
662
-
SVGA3D_SURFACE_BIND_UAVIEW | \
663
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
664
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
665
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
666
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
667
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
668
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
669
-
)
492
+
#define SVGA3D_SURFACE_STAGING_DISALLOWED_MASK \
493
+
(SVGA3D_SURFACE_BIND_MASK | SVGA3D_SURFACE_AUTOGENMIPMAPS | \
494
+
SVGA3D_SURFACE_SCREENTARGET | SVGA3D_SURFACE_HINT_RENDERTARGET | \
495
+
SVGA3D_SURFACE_HINT_INDIRECT_UPDATE | SVGA3D_SURFACE_MULTISAMPLE | \
496
+
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
497
+
SVGA3D_SURFACE_BIND_TENSOR)
670
498
671
-
#define SVGA3D_SURFACE_VAPROCESSFRAME_INPUT_DISALLOWED_MASK \
672
-
( SVGA3D_SURFACE_CUBEMAP | \
673
-
SVGA3D_SURFACE_HINT_INDEXBUFFER | \
674
-
SVGA3D_SURFACE_HINT_VERTEXBUFFER | \
675
-
SVGA3D_SURFACE_HINT_DEPTHSTENCIL | \
676
-
SVGA3D_SURFACE_DEAD2 | \
677
-
SVGA3D_SURFACE_VOLUME | \
678
-
SVGA3D_SURFACE_SCREENTARGET | \
679
-
SVGA3D_SURFACE_1D | \
680
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
681
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
682
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
683
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
684
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
685
-
SVGA3D_SURFACE_STAGING_UPLOAD | \
686
-
SVGA3D_SURFACE_STAGING_DOWNLOAD | \
687
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
688
-
SVGA3D_SURFACE_MULTISAMPLE | \
689
-
SVGA3D_SURFACE_BIND_UAVIEW | \
690
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
691
-
SVGA3D_SURFACE_BIND_LOGICOPS | \
692
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
693
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
694
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
695
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
696
-
)
499
+
#define SVGA3D_SURFACE_STAGING_COPY_DISALLOWED_MASK \
500
+
(SVGA3D_SURFACE_STAGING_DISALLOWED_MASK | \
501
+
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
502
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER)
697
503
698
-
#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \
699
-
( SVGA3D_SURFACE_CUBEMAP | \
700
-
SVGA3D_SURFACE_DEAD2 | \
701
-
SVGA3D_SURFACE_AUTOGENMIPMAPS | \
702
-
SVGA3D_SURFACE_VOLUME | \
703
-
SVGA3D_SURFACE_1D | \
704
-
SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
705
-
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
706
-
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
707
-
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
708
-
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
709
-
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | \
710
-
SVGA3D_SURFACE_VADECODE | \
711
-
SVGA3D_SURFACE_MULTISAMPLE | \
712
-
SVGA3D_SURFACE_BIND_UAVIEW | \
713
-
SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
714
-
SVGA3D_SURFACE_BIND_RAW_VIEWS | \
715
-
SVGA3D_SURFACE_BUFFER_STRUCTURED | \
716
-
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | \
717
-
SVGA3D_SURFACE_RESOURCE_CLAMP \
718
-
)
504
+
#define SVGA3D_SURFACE_LOGICOPS_DISALLOWED_MASK \
505
+
(SVGA3D_SURFACE_CUBEMAP | SVGA3D_SURFACE_DEAD2 | \
506
+
SVGA3D_SURFACE_AUTOGENMIPMAPS | SVGA3D_SURFACE_VOLUME | \
507
+
SVGA3D_SURFACE_1D | SVGA3D_SURFACE_BIND_VERTEX_BUFFER | \
508
+
SVGA3D_SURFACE_BIND_INDEX_BUFFER | \
509
+
SVGA3D_SURFACE_BIND_CONSTANT_BUFFER | \
510
+
SVGA3D_SURFACE_BIND_DEPTH_STENCIL | \
511
+
SVGA3D_SURFACE_BIND_STREAM_OUTPUT | \
512
+
SVGA3D_SURFACE_TRANSFER_FROM_BUFFER | SVGA3D_SURFACE_MULTISAMPLE | \
513
+
SVGA3D_SURFACE_BIND_UAVIEW | SVGA3D_SURFACE_TRANSFER_TO_BUFFER | \
514
+
SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
515
+
SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_RESOURCE_CLAMP | \
516
+
SVGA3D_SURFACE_STAGING_COPY)
517
+
518
+
#define SVGA3D_SURFACE_SM5_MASK \
519
+
(SVGA3D_SURFACE_DRAWINDIRECT_ARGS | SVGA3D_SURFACE_BUFFER_STRUCTURED | \
520
+
SVGA3D_SURFACE_BIND_RAW_VIEWS | SVGA3D_SURFACE_BIND_UAVIEW | \
521
+
SVGA3D_SURFACE_RESOURCE_CLAMP)
719
522
720
523
#define SVGA3D_BUFFER_STRUCTURED_STRIDE_MAX 2048
721
524
722
-
723
-
/*
724
-
* These are really the D3DFORMAT_OP defines from the wdk. We need
725
-
* them so that we can query the host for what the supported surface
726
-
* operations are (when we're using the D3D backend, in particular),
727
-
* and so we can send those operations to the guest.
728
-
*/
729
525
typedef enum {
730
-
SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
731
-
SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
732
-
SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
733
-
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
734
-
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
735
-
SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
736
-
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
526
+
SVGA3DFORMAT_OP_TEXTURE = 0x00000001,
527
+
SVGA3DFORMAT_OP_VOLUMETEXTURE = 0x00000002,
528
+
SVGA3DFORMAT_OP_CUBETEXTURE = 0x00000004,
529
+
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET = 0x00000008,
530
+
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET = 0x00000010,
531
+
SVGA3DFORMAT_OP_ZSTENCIL = 0x00000040,
532
+
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH = 0x00000080,
737
533
738
-
/*
739
-
* This format can be used as a render target if the current display mode
740
-
* is the same depth if the alpha channel is ignored. e.g. if the device
741
-
* can render to A8R8G8B8 when the display mode is X8R8G8B8, then the
742
-
* format op list entry for A8R8G8B8 should have this cap.
743
-
*/
744
-
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
534
+
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET = 0x00000100,
745
535
746
-
/*
747
-
* This format contains DirectDraw support (including Flip). This flag
748
-
* should not to be set on alpha formats.
749
-
*/
750
-
SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
536
+
SVGA3DFORMAT_OP_DISPLAYMODE = 0x00000400,
751
537
752
-
/*
753
-
* The rasterizer can support some level of Direct3D support in this format
754
-
* and implies that the driver can create a Context in this mode (for some
755
-
* render target format). When this flag is set, the SVGA3DFORMAT_OP_DISPLAYMODE
756
-
* flag must also be set.
757
-
*/
758
-
SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
538
+
SVGA3DFORMAT_OP_3DACCELERATION = 0x00000800,
759
539
760
-
/*
761
-
* This is set for a private format when the driver has put the bpp in
762
-
* the structure.
763
-
*/
764
-
SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
540
+
SVGA3DFORMAT_OP_PIXELSIZE = 0x00001000,
765
541
766
-
/*
767
-
* Indicates that this format can be converted to any RGB format for which
768
-
* SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB is specified.
769
-
*/
770
-
SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
542
+
SVGA3DFORMAT_OP_CONVERT_TO_ARGB = 0x00002000,
771
543
772
-
/*
773
-
* Indicates that this format can be used to create offscreen plain surfaces.
774
-
*/
775
-
SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
544
+
SVGA3DFORMAT_OP_OFFSCREENPLAIN = 0x00004000,
776
545
777
-
/*
778
-
* Indicated that this format can be read as an SRGB texture (meaning that the
779
-
* sampler will linearize the looked up data).
780
-
*/
781
-
SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
546
+
SVGA3DFORMAT_OP_SRGBREAD = 0x00008000,
782
547
783
-
/*
784
-
* Indicates that this format can be used in the bumpmap instructions.
785
-
*/
786
-
SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
548
+
SVGA3DFORMAT_OP_BUMPMAP = 0x00010000,
787
549
788
-
/*
789
-
* Indicates that this format can be sampled by the displacement map sampler.
790
-
*/
791
-
SVGA3DFORMAT_OP_DMAP = 0x00020000,
550
+
SVGA3DFORMAT_OP_DMAP = 0x00020000,
792
551
793
-
/*
794
-
* Indicates that this format cannot be used with texture filtering.
795
-
*/
796
-
SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
552
+
SVGA3DFORMAT_OP_NOFILTER = 0x00040000,
797
553
798
-
/*
799
-
* Indicates that format conversions are supported to this RGB format if
800
-
* SVGA3DFORMAT_OP_CONVERT_TO_ARGB is specified in the source format.
801
-
*/
802
-
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
554
+
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB = 0x00080000,
803
555
804
-
/*
805
-
* Indicated that this format can be written as an SRGB target
806
-
* (meaning that the pixel pipe will DE-linearize data on output to format)
807
-
*/
808
-
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
556
+
SVGA3DFORMAT_OP_SRGBWRITE = 0x00100000,
809
557
810
-
/*
811
-
* Indicates that this format cannot be used with alpha blending.
812
-
*/
813
-
SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
558
+
SVGA3DFORMAT_OP_NOALPHABLEND = 0x00200000,
814
559
815
-
/*
816
-
* Indicates that the device can auto-generated sublevels for resources
817
-
* of this format.
818
-
*/
819
-
SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
560
+
SVGA3DFORMAT_OP_AUTOGENMIPMAP = 0x00400000,
820
561
821
-
/*
822
-
* Indicates that this format can be used by vertex texture sampler.
823
-
*/
824
-
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
562
+
SVGA3DFORMAT_OP_VERTEXTEXTURE = 0x00800000,
825
563
826
-
/*
827
-
* Indicates that this format supports neither texture coordinate
828
-
* wrap modes, nor mipmapping.
829
-
*/
830
-
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
564
+
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP = 0x01000000
831
565
} SVGA3dFormatOp;
832
566
833
-
#define SVGA3D_FORMAT_POSITIVE \
834
-
(SVGA3DFORMAT_OP_TEXTURE | \
835
-
SVGA3DFORMAT_OP_VOLUMETEXTURE | \
836
-
SVGA3DFORMAT_OP_CUBETEXTURE | \
837
-
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
838
-
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | \
839
-
SVGA3DFORMAT_OP_ZSTENCIL | \
840
-
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
841
-
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
842
-
SVGA3DFORMAT_OP_DISPLAYMODE | \
843
-
SVGA3DFORMAT_OP_3DACCELERATION | \
844
-
SVGA3DFORMAT_OP_PIXELSIZE | \
845
-
SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
846
-
SVGA3DFORMAT_OP_OFFSCREENPLAIN | \
847
-
SVGA3DFORMAT_OP_SRGBREAD | \
848
-
SVGA3DFORMAT_OP_BUMPMAP | \
849
-
SVGA3DFORMAT_OP_DMAP | \
850
-
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | \
851
-
SVGA3DFORMAT_OP_SRGBWRITE | \
852
-
SVGA3DFORMAT_OP_AUTOGENMIPMAP | \
853
-
SVGA3DFORMAT_OP_VERTEXTEXTURE)
567
+
#define SVGA3D_FORMAT_POSITIVE \
568
+
(SVGA3DFORMAT_OP_TEXTURE | SVGA3DFORMAT_OP_VOLUMETEXTURE | \
569
+
SVGA3DFORMAT_OP_CUBETEXTURE | \
570
+
SVGA3DFORMAT_OP_OFFSCREEN_RENDERTARGET | \
571
+
SVGA3DFORMAT_OP_SAME_FORMAT_RENDERTARGET | SVGA3DFORMAT_OP_ZSTENCIL | \
572
+
SVGA3DFORMAT_OP_ZSTENCIL_WITH_ARBITRARY_COLOR_DEPTH | \
573
+
SVGA3DFORMAT_OP_SAME_FORMAT_UP_TO_ALPHA_RENDERTARGET | \
574
+
SVGA3DFORMAT_OP_DISPLAYMODE | SVGA3DFORMAT_OP_3DACCELERATION | \
575
+
SVGA3DFORMAT_OP_PIXELSIZE | SVGA3DFORMAT_OP_CONVERT_TO_ARGB | \
576
+
SVGA3DFORMAT_OP_OFFSCREENPLAIN | SVGA3DFORMAT_OP_SRGBREAD | \
577
+
SVGA3DFORMAT_OP_BUMPMAP | SVGA3DFORMAT_OP_DMAP | \
578
+
SVGA3DFORMAT_OP_MEMBEROFGROUP_ARGB | SVGA3DFORMAT_OP_SRGBWRITE | \
579
+
SVGA3DFORMAT_OP_AUTOGENMIPMAP | SVGA3DFORMAT_OP_VERTEXTEXTURE)
854
580
855
-
#define SVGA3D_FORMAT_NEGATIVE \
856
-
(SVGA3DFORMAT_OP_NOFILTER | \
857
-
SVGA3DFORMAT_OP_NOALPHABLEND | \
858
-
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
581
+
#define SVGA3D_FORMAT_NEGATIVE \
582
+
(SVGA3DFORMAT_OP_NOFILTER | SVGA3DFORMAT_OP_NOALPHABLEND | \
583
+
SVGA3DFORMAT_OP_NOTEXCOORDWRAPNORMIP)
859
584
860
-
/*
861
-
* This structure is a conversion of SVGA3DFORMAT_OP_*
862
-
* Entries must be located at the same position.
863
-
*/
864
585
typedef union {
865
-
uint32 value;
866
-
struct {
867
-
uint32 texture : 1;
868
-
uint32 volumeTexture : 1;
869
-
uint32 cubeTexture : 1;
870
-
uint32 offscreenRenderTarget : 1;
871
-
uint32 sameFormatRenderTarget : 1;
872
-
uint32 unknown1 : 1;
873
-
uint32 zStencil : 1;
874
-
uint32 zStencilArbitraryDepth : 1;
875
-
uint32 sameFormatUpToAlpha : 1;
876
-
uint32 unknown2 : 1;
877
-
uint32 displayMode : 1;
878
-
uint32 acceleration3d : 1;
879
-
uint32 pixelSize : 1;
880
-
uint32 convertToARGB : 1;
881
-
uint32 offscreenPlain : 1;
882
-
uint32 sRGBRead : 1;
883
-
uint32 bumpMap : 1;
884
-
uint32 dmap : 1;
885
-
uint32 noFilter : 1;
886
-
uint32 memberOfGroupARGB : 1;
887
-
uint32 sRGBWrite : 1;
888
-
uint32 noAlphaBlend : 1;
889
-
uint32 autoGenMipMap : 1;
890
-
uint32 vertexTexture : 1;
891
-
uint32 noTexCoordWrapNorMip : 1;
892
-
};
586
+
uint32 value;
587
+
struct {
588
+
uint32 texture : 1;
589
+
uint32 volumeTexture : 1;
590
+
uint32 cubeTexture : 1;
591
+
uint32 offscreenRenderTarget : 1;
592
+
uint32 sameFormatRenderTarget : 1;
593
+
uint32 unknown1 : 1;
594
+
uint32 zStencil : 1;
595
+
uint32 zStencilArbitraryDepth : 1;
596
+
uint32 sameFormatUpToAlpha : 1;
597
+
uint32 unknown2 : 1;
598
+
uint32 displayMode : 1;
599
+
uint32 acceleration3d : 1;
600
+
uint32 pixelSize : 1;
601
+
uint32 convertToARGB : 1;
602
+
uint32 offscreenPlain : 1;
603
+
uint32 sRGBRead : 1;
604
+
uint32 bumpMap : 1;
605
+
uint32 dmap : 1;
606
+
uint32 noFilter : 1;
607
+
uint32 memberOfGroupARGB : 1;
608
+
uint32 sRGBWrite : 1;
609
+
uint32 noAlphaBlend : 1;
610
+
uint32 autoGenMipMap : 1;
611
+
uint32 vertexTexture : 1;
612
+
uint32 noTexCoordWrapNorMip : 1;
613
+
};
893
614
} SVGA3dSurfaceFormatCaps;
894
615
895
-
/*
896
-
* SVGA_3D_CMD_SETRENDERSTATE Types. All value types
897
-
* must fit in a uint32.
898
-
*/
899
-
900
616
typedef enum {
901
-
SVGA3D_RS_INVALID = 0,
902
-
SVGA3D_RS_MIN = 1,
903
-
SVGA3D_RS_ZENABLE = 1, /* SVGA3dBool */
904
-
SVGA3D_RS_ZWRITEENABLE = 2, /* SVGA3dBool */
905
-
SVGA3D_RS_ALPHATESTENABLE = 3, /* SVGA3dBool */
906
-
SVGA3D_RS_DITHERENABLE = 4, /* SVGA3dBool */
907
-
SVGA3D_RS_BLENDENABLE = 5, /* SVGA3dBool */
908
-
SVGA3D_RS_FOGENABLE = 6, /* SVGA3dBool */
909
-
SVGA3D_RS_SPECULARENABLE = 7, /* SVGA3dBool */
910
-
SVGA3D_RS_STENCILENABLE = 8, /* SVGA3dBool */
911
-
SVGA3D_RS_LIGHTINGENABLE = 9, /* SVGA3dBool */
912
-
SVGA3D_RS_NORMALIZENORMALS = 10, /* SVGA3dBool */
913
-
SVGA3D_RS_POINTSPRITEENABLE = 11, /* SVGA3dBool */
914
-
SVGA3D_RS_POINTSCALEENABLE = 12, /* SVGA3dBool */
915
-
SVGA3D_RS_STENCILREF = 13, /* uint32 */
916
-
SVGA3D_RS_STENCILMASK = 14, /* uint32 */
917
-
SVGA3D_RS_STENCILWRITEMASK = 15, /* uint32 */
918
-
SVGA3D_RS_FOGSTART = 16, /* float */
919
-
SVGA3D_RS_FOGEND = 17, /* float */
920
-
SVGA3D_RS_FOGDENSITY = 18, /* float */
921
-
SVGA3D_RS_POINTSIZE = 19, /* float */
922
-
SVGA3D_RS_POINTSIZEMIN = 20, /* float */
923
-
SVGA3D_RS_POINTSIZEMAX = 21, /* float */
924
-
SVGA3D_RS_POINTSCALE_A = 22, /* float */
925
-
SVGA3D_RS_POINTSCALE_B = 23, /* float */
926
-
SVGA3D_RS_POINTSCALE_C = 24, /* float */
927
-
SVGA3D_RS_FOGCOLOR = 25, /* SVGA3dColor */
928
-
SVGA3D_RS_AMBIENT = 26, /* SVGA3dColor */
929
-
SVGA3D_RS_CLIPPLANEENABLE = 27, /* SVGA3dClipPlanes */
930
-
SVGA3D_RS_FOGMODE = 28, /* SVGA3dFogMode */
931
-
SVGA3D_RS_FILLMODE = 29, /* SVGA3dFillMode */
932
-
SVGA3D_RS_SHADEMODE = 30, /* SVGA3dShadeMode */
933
-
SVGA3D_RS_LINEPATTERN = 31, /* SVGA3dLinePattern */
934
-
SVGA3D_RS_SRCBLEND = 32, /* SVGA3dBlendOp */
935
-
SVGA3D_RS_DSTBLEND = 33, /* SVGA3dBlendOp */
936
-
SVGA3D_RS_BLENDEQUATION = 34, /* SVGA3dBlendEquation */
937
-
SVGA3D_RS_CULLMODE = 35, /* SVGA3dFace */
938
-
SVGA3D_RS_ZFUNC = 36, /* SVGA3dCmpFunc */
939
-
SVGA3D_RS_ALPHAFUNC = 37, /* SVGA3dCmpFunc */
940
-
SVGA3D_RS_STENCILFUNC = 38, /* SVGA3dCmpFunc */
941
-
SVGA3D_RS_STENCILFAIL = 39, /* SVGA3dStencilOp */
942
-
SVGA3D_RS_STENCILZFAIL = 40, /* SVGA3dStencilOp */
943
-
SVGA3D_RS_STENCILPASS = 41, /* SVGA3dStencilOp */
944
-
SVGA3D_RS_ALPHAREF = 42, /* float (0.0 .. 1.0) */
945
-
SVGA3D_RS_FRONTWINDING = 43, /* SVGA3dFrontWinding */
946
-
SVGA3D_RS_COORDINATETYPE = 44, /* SVGA3dCoordinateType */
947
-
SVGA3D_RS_ZBIAS = 45, /* float */
948
-
SVGA3D_RS_RANGEFOGENABLE = 46, /* SVGA3dBool */
949
-
SVGA3D_RS_COLORWRITEENABLE = 47, /* SVGA3dColorMask */
950
-
SVGA3D_RS_VERTEXMATERIALENABLE = 48, /* SVGA3dBool */
951
-
SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49, /* SVGA3dVertexMaterial */
952
-
SVGA3D_RS_SPECULARMATERIALSOURCE = 50, /* SVGA3dVertexMaterial */
953
-
SVGA3D_RS_AMBIENTMATERIALSOURCE = 51, /* SVGA3dVertexMaterial */
954
-
SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52, /* SVGA3dVertexMaterial */
955
-
SVGA3D_RS_TEXTUREFACTOR = 53, /* SVGA3dColor */
956
-
SVGA3D_RS_LOCALVIEWER = 54, /* SVGA3dBool */
957
-
SVGA3D_RS_SCISSORTESTENABLE = 55, /* SVGA3dBool */
958
-
SVGA3D_RS_BLENDCOLOR = 56, /* SVGA3dColor */
959
-
SVGA3D_RS_STENCILENABLE2SIDED = 57, /* SVGA3dBool */
960
-
SVGA3D_RS_CCWSTENCILFUNC = 58, /* SVGA3dCmpFunc */
961
-
SVGA3D_RS_CCWSTENCILFAIL = 59, /* SVGA3dStencilOp */
962
-
SVGA3D_RS_CCWSTENCILZFAIL = 60, /* SVGA3dStencilOp */
963
-
SVGA3D_RS_CCWSTENCILPASS = 61, /* SVGA3dStencilOp */
964
-
SVGA3D_RS_VERTEXBLEND = 62, /* SVGA3dVertexBlendFlags */
965
-
SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63, /* float */
966
-
SVGA3D_RS_DEPTHBIAS = 64, /* float */
617
+
SVGA3D_RS_INVALID = 0,
618
+
SVGA3D_RS_MIN = 1,
619
+
SVGA3D_RS_ZENABLE = 1,
620
+
SVGA3D_RS_ZWRITEENABLE = 2,
621
+
SVGA3D_RS_ALPHATESTENABLE = 3,
622
+
SVGA3D_RS_DITHERENABLE = 4,
623
+
SVGA3D_RS_BLENDENABLE = 5,
624
+
SVGA3D_RS_FOGENABLE = 6,
625
+
SVGA3D_RS_SPECULARENABLE = 7,
626
+
SVGA3D_RS_STENCILENABLE = 8,
627
+
SVGA3D_RS_LIGHTINGENABLE = 9,
628
+
SVGA3D_RS_NORMALIZENORMALS = 10,
629
+
SVGA3D_RS_POINTSPRITEENABLE = 11,
630
+
SVGA3D_RS_POINTSCALEENABLE = 12,
631
+
SVGA3D_RS_STENCILREF = 13,
632
+
SVGA3D_RS_STENCILMASK = 14,
633
+
SVGA3D_RS_STENCILWRITEMASK = 15,
634
+
SVGA3D_RS_FOGSTART = 16,
635
+
SVGA3D_RS_FOGEND = 17,
636
+
SVGA3D_RS_FOGDENSITY = 18,
637
+
SVGA3D_RS_POINTSIZE = 19,
638
+
SVGA3D_RS_POINTSIZEMIN = 20,
639
+
SVGA3D_RS_POINTSIZEMAX = 21,
640
+
SVGA3D_RS_POINTSCALE_A = 22,
641
+
SVGA3D_RS_POINTSCALE_B = 23,
642
+
SVGA3D_RS_POINTSCALE_C = 24,
643
+
SVGA3D_RS_FOGCOLOR = 25,
644
+
SVGA3D_RS_AMBIENT = 26,
645
+
SVGA3D_RS_CLIPPLANEENABLE = 27,
646
+
SVGA3D_RS_FOGMODE = 28,
647
+
SVGA3D_RS_FILLMODE = 29,
648
+
SVGA3D_RS_SHADEMODE = 30,
649
+
SVGA3D_RS_LINEPATTERN = 31,
650
+
SVGA3D_RS_SRCBLEND = 32,
651
+
SVGA3D_RS_DSTBLEND = 33,
652
+
SVGA3D_RS_BLENDEQUATION = 34,
653
+
SVGA3D_RS_CULLMODE = 35,
654
+
SVGA3D_RS_ZFUNC = 36,
655
+
SVGA3D_RS_ALPHAFUNC = 37,
656
+
SVGA3D_RS_STENCILFUNC = 38,
657
+
SVGA3D_RS_STENCILFAIL = 39,
658
+
SVGA3D_RS_STENCILZFAIL = 40,
659
+
SVGA3D_RS_STENCILPASS = 41,
660
+
SVGA3D_RS_ALPHAREF = 42,
661
+
SVGA3D_RS_FRONTWINDING = 43,
662
+
SVGA3D_RS_COORDINATETYPE = 44,
663
+
SVGA3D_RS_ZBIAS = 45,
664
+
SVGA3D_RS_RANGEFOGENABLE = 46,
665
+
SVGA3D_RS_COLORWRITEENABLE = 47,
666
+
SVGA3D_RS_VERTEXMATERIALENABLE = 48,
667
+
SVGA3D_RS_DIFFUSEMATERIALSOURCE = 49,
668
+
SVGA3D_RS_SPECULARMATERIALSOURCE = 50,
669
+
SVGA3D_RS_AMBIENTMATERIALSOURCE = 51,
670
+
SVGA3D_RS_EMISSIVEMATERIALSOURCE = 52,
671
+
SVGA3D_RS_TEXTUREFACTOR = 53,
672
+
SVGA3D_RS_LOCALVIEWER = 54,
673
+
SVGA3D_RS_SCISSORTESTENABLE = 55,
674
+
SVGA3D_RS_BLENDCOLOR = 56,
675
+
SVGA3D_RS_STENCILENABLE2SIDED = 57,
676
+
SVGA3D_RS_CCWSTENCILFUNC = 58,
677
+
SVGA3D_RS_CCWSTENCILFAIL = 59,
678
+
SVGA3D_RS_CCWSTENCILZFAIL = 60,
679
+
SVGA3D_RS_CCWSTENCILPASS = 61,
680
+
SVGA3D_RS_VERTEXBLEND = 62,
681
+
SVGA3D_RS_SLOPESCALEDEPTHBIAS = 63,
682
+
SVGA3D_RS_DEPTHBIAS = 64,
967
683
968
-
969
-
/*
970
-
* Output Gamma Level
971
-
*
972
-
* Output gamma effects the gamma curve of colors that are output from the
973
-
* rendering pipeline. A value of 1.0 specifies a linear color space. If the
974
-
* value is <= 0.0, gamma correction is ignored and linear color space is
975
-
* used.
976
-
*/
977
-
978
-
SVGA3D_RS_OUTPUTGAMMA = 65, /* float */
979
-
SVGA3D_RS_ZVISIBLE = 66, /* SVGA3dBool */
980
-
SVGA3D_RS_LASTPIXEL = 67, /* SVGA3dBool */
981
-
SVGA3D_RS_CLIPPING = 68, /* SVGA3dBool */
982
-
SVGA3D_RS_WRAP0 = 69, /* SVGA3dWrapFlags */
983
-
SVGA3D_RS_WRAP1 = 70, /* SVGA3dWrapFlags */
984
-
SVGA3D_RS_WRAP2 = 71, /* SVGA3dWrapFlags */
985
-
SVGA3D_RS_WRAP3 = 72, /* SVGA3dWrapFlags */
986
-
SVGA3D_RS_WRAP4 = 73, /* SVGA3dWrapFlags */
987
-
SVGA3D_RS_WRAP5 = 74, /* SVGA3dWrapFlags */
988
-
SVGA3D_RS_WRAP6 = 75, /* SVGA3dWrapFlags */
989
-
SVGA3D_RS_WRAP7 = 76, /* SVGA3dWrapFlags */
990
-
SVGA3D_RS_WRAP8 = 77, /* SVGA3dWrapFlags */
991
-
SVGA3D_RS_WRAP9 = 78, /* SVGA3dWrapFlags */
992
-
SVGA3D_RS_WRAP10 = 79, /* SVGA3dWrapFlags */
993
-
SVGA3D_RS_WRAP11 = 80, /* SVGA3dWrapFlags */
994
-
SVGA3D_RS_WRAP12 = 81, /* SVGA3dWrapFlags */
995
-
SVGA3D_RS_WRAP13 = 82, /* SVGA3dWrapFlags */
996
-
SVGA3D_RS_WRAP14 = 83, /* SVGA3dWrapFlags */
997
-
SVGA3D_RS_WRAP15 = 84, /* SVGA3dWrapFlags */
998
-
SVGA3D_RS_MULTISAMPLEANTIALIAS = 85, /* SVGA3dBool */
999
-
SVGA3D_RS_MULTISAMPLEMASK = 86, /* uint32 */
1000
-
SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87, /* SVGA3dBool */
1001
-
SVGA3D_RS_TWEENFACTOR = 88, /* float */
1002
-
SVGA3D_RS_ANTIALIASEDLINEENABLE = 89, /* SVGA3dBool */
1003
-
SVGA3D_RS_COLORWRITEENABLE1 = 90, /* SVGA3dColorMask */
1004
-
SVGA3D_RS_COLORWRITEENABLE2 = 91, /* SVGA3dColorMask */
1005
-
SVGA3D_RS_COLORWRITEENABLE3 = 92, /* SVGA3dColorMask */
1006
-
SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93, /* SVGA3dBool */
1007
-
SVGA3D_RS_SRCBLENDALPHA = 94, /* SVGA3dBlendOp */
1008
-
SVGA3D_RS_DSTBLENDALPHA = 95, /* SVGA3dBlendOp */
1009
-
SVGA3D_RS_BLENDEQUATIONALPHA = 96, /* SVGA3dBlendEquation */
1010
-
SVGA3D_RS_TRANSPARENCYANTIALIAS = 97, /* SVGA3dTransparencyAntialiasType */
1011
-
SVGA3D_RS_LINEWIDTH = 98, /* float */
1012
-
SVGA3D_RS_MAX
684
+
SVGA3D_RS_OUTPUTGAMMA = 65,
685
+
SVGA3D_RS_ZVISIBLE = 66,
686
+
SVGA3D_RS_LASTPIXEL = 67,
687
+
SVGA3D_RS_CLIPPING = 68,
688
+
SVGA3D_RS_WRAP0 = 69,
689
+
SVGA3D_RS_WRAP1 = 70,
690
+
SVGA3D_RS_WRAP2 = 71,
691
+
SVGA3D_RS_WRAP3 = 72,
692
+
SVGA3D_RS_WRAP4 = 73,
693
+
SVGA3D_RS_WRAP5 = 74,
694
+
SVGA3D_RS_WRAP6 = 75,
695
+
SVGA3D_RS_WRAP7 = 76,
696
+
SVGA3D_RS_WRAP8 = 77,
697
+
SVGA3D_RS_WRAP9 = 78,
698
+
SVGA3D_RS_WRAP10 = 79,
699
+
SVGA3D_RS_WRAP11 = 80,
700
+
SVGA3D_RS_WRAP12 = 81,
701
+
SVGA3D_RS_WRAP13 = 82,
702
+
SVGA3D_RS_WRAP14 = 83,
703
+
SVGA3D_RS_WRAP15 = 84,
704
+
SVGA3D_RS_MULTISAMPLEANTIALIAS = 85,
705
+
SVGA3D_RS_MULTISAMPLEMASK = 86,
706
+
SVGA3D_RS_INDEXEDVERTEXBLENDENABLE = 87,
707
+
SVGA3D_RS_TWEENFACTOR = 88,
708
+
SVGA3D_RS_ANTIALIASEDLINEENABLE = 89,
709
+
SVGA3D_RS_COLORWRITEENABLE1 = 90,
710
+
SVGA3D_RS_COLORWRITEENABLE2 = 91,
711
+
SVGA3D_RS_COLORWRITEENABLE3 = 92,
712
+
SVGA3D_RS_SEPARATEALPHABLENDENABLE = 93,
713
+
SVGA3D_RS_SRCBLENDALPHA = 94,
714
+
SVGA3D_RS_DSTBLENDALPHA = 95,
715
+
SVGA3D_RS_BLENDEQUATIONALPHA = 96,
716
+
SVGA3D_RS_TRANSPARENCYANTIALIAS = 97,
717
+
SVGA3D_RS_LINEWIDTH = 98,
718
+
SVGA3D_RS_MAX
1013
719
} SVGA3dRenderStateName;
1014
720
1015
721
typedef enum {
1016
-
SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
1017
-
SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
1018
-
SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
1019
-
SVGA3D_TRANSPARENCYANTIALIAS_MAX
722
+
SVGA3D_TRANSPARENCYANTIALIAS_NORMAL = 0,
723
+
SVGA3D_TRANSPARENCYANTIALIAS_ALPHATOCOVERAGE = 1,
724
+
SVGA3D_TRANSPARENCYANTIALIAS_SUPERSAMPLE = 2,
725
+
SVGA3D_TRANSPARENCYANTIALIAS_MAX
1020
726
} SVGA3dTransparencyAntialiasType;
1021
727
1022
728
typedef enum {
1023
-
SVGA3D_VERTEXMATERIAL_NONE = 0, /* Use the value in the current material */
1024
-
SVGA3D_VERTEXMATERIAL_DIFFUSE = 1, /* Use the value in the diffuse component */
1025
-
SVGA3D_VERTEXMATERIAL_SPECULAR = 2, /* Use the value in the specular component */
1026
-
SVGA3D_VERTEXMATERIAL_MAX = 3,
729
+
SVGA3D_VERTEXMATERIAL_NONE = 0,
730
+
SVGA3D_VERTEXMATERIAL_DIFFUSE = 1,
731
+
SVGA3D_VERTEXMATERIAL_SPECULAR = 2,
732
+
SVGA3D_VERTEXMATERIAL_MAX = 3,
1027
733
} SVGA3dVertexMaterial;
1028
734
1029
735
typedef enum {
1030
-
SVGA3D_FILLMODE_INVALID = 0,
1031
-
SVGA3D_FILLMODE_MIN = 1,
1032
-
SVGA3D_FILLMODE_POINT = 1,
1033
-
SVGA3D_FILLMODE_LINE = 2,
1034
-
SVGA3D_FILLMODE_FILL = 3,
1035
-
SVGA3D_FILLMODE_MAX
736
+
SVGA3D_FILLMODE_INVALID = 0,
737
+
SVGA3D_FILLMODE_MIN = 1,
738
+
SVGA3D_FILLMODE_POINT = 1,
739
+
SVGA3D_FILLMODE_LINE = 2,
740
+
SVGA3D_FILLMODE_FILL = 3,
741
+
SVGA3D_FILLMODE_MAX
1036
742
} SVGA3dFillModeType;
1037
743
1038
-
1039
-
typedef
1040
-
#include "vmware_pack_begin.h"
1041
-
union {
1042
-
struct {
1043
-
uint16 mode; /* SVGA3dFillModeType */
1044
-
uint16 face; /* SVGA3dFace */
1045
-
};
1046
-
uint32 uintValue;
1047
-
}
1048
-
#include "vmware_pack_end.h"
1049
-
SVGA3dFillMode;
744
+
#pragma pack(push, 1)
745
+
typedef union {
746
+
struct {
747
+
uint16 mode;
748
+
uint16 face;
749
+
};
750
+
uint32 uintValue;
751
+
} SVGA3dFillMode;
752
+
#pragma pack(pop)
1050
753
1051
754
typedef enum {
1052
-
SVGA3D_SHADEMODE_INVALID = 0,
1053
-
SVGA3D_SHADEMODE_FLAT = 1,
1054
-
SVGA3D_SHADEMODE_SMOOTH = 2,
1055
-
SVGA3D_SHADEMODE_PHONG = 3, /* Not supported */
1056
-
SVGA3D_SHADEMODE_MAX
755
+
SVGA3D_SHADEMODE_INVALID = 0,
756
+
SVGA3D_SHADEMODE_FLAT = 1,
757
+
SVGA3D_SHADEMODE_SMOOTH = 2,
758
+
SVGA3D_SHADEMODE_PHONG = 3,
759
+
SVGA3D_SHADEMODE_MAX
1057
760
} SVGA3dShadeMode;
1058
761
1059
-
typedef
1060
-
#include "vmware_pack_begin.h"
1061
-
union {
1062
-
struct {
1063
-
uint16 repeat;
1064
-
uint16 pattern;
1065
-
};
1066
-
uint32 uintValue;
1067
-
}
1068
-
#include "vmware_pack_end.h"
1069
-
SVGA3dLinePattern;
762
+
#pragma pack(push, 1)
763
+
typedef union {
764
+
struct {
765
+
uint16 repeat;
766
+
uint16 pattern;
767
+
};
768
+
uint32 uintValue;
769
+
} SVGA3dLinePattern;
770
+
#pragma pack(pop)
1070
771
1071
772
typedef enum {
1072
-
SVGA3D_BLENDOP_INVALID = 0,
1073
-
SVGA3D_BLENDOP_MIN = 1,
1074
-
SVGA3D_BLENDOP_ZERO = 1,
1075
-
SVGA3D_BLENDOP_ONE = 2,
1076
-
SVGA3D_BLENDOP_SRCCOLOR = 3,
1077
-
SVGA3D_BLENDOP_INVSRCCOLOR = 4,
1078
-
SVGA3D_BLENDOP_SRCALPHA = 5,
1079
-
SVGA3D_BLENDOP_INVSRCALPHA = 6,
1080
-
SVGA3D_BLENDOP_DESTALPHA = 7,
1081
-
SVGA3D_BLENDOP_INVDESTALPHA = 8,
1082
-
SVGA3D_BLENDOP_DESTCOLOR = 9,
1083
-
SVGA3D_BLENDOP_INVDESTCOLOR = 10,
1084
-
SVGA3D_BLENDOP_SRCALPHASAT = 11,
1085
-
SVGA3D_BLENDOP_BLENDFACTOR = 12,
1086
-
SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
1087
-
SVGA3D_BLENDOP_SRC1COLOR = 14,
1088
-
SVGA3D_BLENDOP_INVSRC1COLOR = 15,
1089
-
SVGA3D_BLENDOP_SRC1ALPHA = 16,
1090
-
SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
1091
-
SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
1092
-
SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
1093
-
SVGA3D_BLENDOP_MAX
773
+
SVGA3D_BLENDOP_INVALID = 0,
774
+
SVGA3D_BLENDOP_MIN = 1,
775
+
SVGA3D_BLENDOP_ZERO = 1,
776
+
SVGA3D_BLENDOP_ONE = 2,
777
+
SVGA3D_BLENDOP_SRCCOLOR = 3,
778
+
SVGA3D_BLENDOP_INVSRCCOLOR = 4,
779
+
SVGA3D_BLENDOP_SRCALPHA = 5,
780
+
SVGA3D_BLENDOP_INVSRCALPHA = 6,
781
+
SVGA3D_BLENDOP_DESTALPHA = 7,
782
+
SVGA3D_BLENDOP_INVDESTALPHA = 8,
783
+
SVGA3D_BLENDOP_DESTCOLOR = 9,
784
+
SVGA3D_BLENDOP_INVDESTCOLOR = 10,
785
+
SVGA3D_BLENDOP_SRCALPHASAT = 11,
786
+
SVGA3D_BLENDOP_BLENDFACTOR = 12,
787
+
SVGA3D_BLENDOP_INVBLENDFACTOR = 13,
788
+
SVGA3D_BLENDOP_SRC1COLOR = 14,
789
+
SVGA3D_BLENDOP_INVSRC1COLOR = 15,
790
+
SVGA3D_BLENDOP_SRC1ALPHA = 16,
791
+
SVGA3D_BLENDOP_INVSRC1ALPHA = 17,
792
+
SVGA3D_BLENDOP_BLENDFACTORALPHA = 18,
793
+
SVGA3D_BLENDOP_INVBLENDFACTORALPHA = 19,
794
+
SVGA3D_BLENDOP_MAX
1094
795
} SVGA3dBlendOp;
1095
796
1096
797
typedef enum {
1097
-
SVGA3D_BLENDEQ_INVALID = 0,
1098
-
SVGA3D_BLENDEQ_MIN = 1,
1099
-
SVGA3D_BLENDEQ_ADD = 1,
1100
-
SVGA3D_BLENDEQ_SUBTRACT = 2,
1101
-
SVGA3D_BLENDEQ_REVSUBTRACT = 3,
1102
-
SVGA3D_BLENDEQ_MINIMUM = 4,
1103
-
SVGA3D_BLENDEQ_MAXIMUM = 5,
1104
-
SVGA3D_BLENDEQ_MAX
798
+
SVGA3D_BLENDEQ_INVALID = 0,
799
+
SVGA3D_BLENDEQ_MIN = 1,
800
+
SVGA3D_BLENDEQ_ADD = 1,
801
+
SVGA3D_BLENDEQ_SUBTRACT = 2,
802
+
SVGA3D_BLENDEQ_REVSUBTRACT = 3,
803
+
SVGA3D_BLENDEQ_MINIMUM = 4,
804
+
SVGA3D_BLENDEQ_MAXIMUM = 5,
805
+
SVGA3D_BLENDEQ_MAX
1105
806
} SVGA3dBlendEquation;
1106
807
1107
808
typedef enum {
1108
-
SVGA3D_DX11_LOGICOP_MIN = 0,
1109
-
SVGA3D_DX11_LOGICOP_CLEAR = 0,
1110
-
SVGA3D_DX11_LOGICOP_SET = 1,
1111
-
SVGA3D_DX11_LOGICOP_COPY = 2,
1112
-
SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
1113
-
SVGA3D_DX11_LOGICOP_NOOP = 4,
1114
-
SVGA3D_DX11_LOGICOP_INVERT = 5,
1115
-
SVGA3D_DX11_LOGICOP_AND = 6,
1116
-
SVGA3D_DX11_LOGICOP_NAND = 7,
1117
-
SVGA3D_DX11_LOGICOP_OR = 8,
1118
-
SVGA3D_DX11_LOGICOP_NOR = 9,
1119
-
SVGA3D_DX11_LOGICOP_XOR = 10,
1120
-
SVGA3D_DX11_LOGICOP_EQUIV = 11,
1121
-
SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
1122
-
SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
1123
-
SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
1124
-
SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
1125
-
SVGA3D_DX11_LOGICOP_MAX
809
+
SVGA3D_DX11_LOGICOP_MIN = 0,
810
+
SVGA3D_DX11_LOGICOP_CLEAR = 0,
811
+
SVGA3D_DX11_LOGICOP_SET = 1,
812
+
SVGA3D_DX11_LOGICOP_COPY = 2,
813
+
SVGA3D_DX11_LOGICOP_COPY_INVERTED = 3,
814
+
SVGA3D_DX11_LOGICOP_NOOP = 4,
815
+
SVGA3D_DX11_LOGICOP_INVERT = 5,
816
+
SVGA3D_DX11_LOGICOP_AND = 6,
817
+
SVGA3D_DX11_LOGICOP_NAND = 7,
818
+
SVGA3D_DX11_LOGICOP_OR = 8,
819
+
SVGA3D_DX11_LOGICOP_NOR = 9,
820
+
SVGA3D_DX11_LOGICOP_XOR = 10,
821
+
SVGA3D_DX11_LOGICOP_EQUIV = 11,
822
+
SVGA3D_DX11_LOGICOP_AND_REVERSE = 12,
823
+
SVGA3D_DX11_LOGICOP_AND_INVERTED = 13,
824
+
SVGA3D_DX11_LOGICOP_OR_REVERSE = 14,
825
+
SVGA3D_DX11_LOGICOP_OR_INVERTED = 15,
826
+
SVGA3D_DX11_LOGICOP_MAX
1126
827
} SVGA3dDX11LogicOp;
1127
828
1128
829
typedef enum {
1129
-
SVGA3D_FRONTWINDING_INVALID = 0,
1130
-
SVGA3D_FRONTWINDING_CW = 1,
1131
-
SVGA3D_FRONTWINDING_CCW = 2,
1132
-
SVGA3D_FRONTWINDING_MAX
830
+
SVGA3D_FRONTWINDING_INVALID = 0,
831
+
SVGA3D_FRONTWINDING_CW = 1,
832
+
SVGA3D_FRONTWINDING_MIN = 1,
833
+
SVGA3D_FRONTWINDING_CCW = 2,
834
+
SVGA3D_FRONTWINDING_MAX
1133
835
} SVGA3dFrontWinding;
1134
836
1135
837
typedef enum {
1136
-
SVGA3D_FACE_INVALID = 0,
1137
-
SVGA3D_FACE_NONE = 1,
1138
-
SVGA3D_FACE_MIN = 1,
1139
-
SVGA3D_FACE_FRONT = 2,
1140
-
SVGA3D_FACE_BACK = 3,
1141
-
SVGA3D_FACE_FRONT_BACK = 4,
1142
-
SVGA3D_FACE_MAX
838
+
SVGA3D_FACE_INVALID = 0,
839
+
SVGA3D_FACE_NONE = 1,
840
+
SVGA3D_FACE_MIN = 1,
841
+
SVGA3D_FACE_FRONT = 2,
842
+
SVGA3D_FACE_BACK = 3,
843
+
SVGA3D_FACE_FRONT_BACK = 4,
844
+
SVGA3D_FACE_MAX
1143
845
} SVGA3dFace;
1144
846
1145
-
/*
1146
-
* The order and the values should not be changed
1147
-
*/
1148
-
1149
847
typedef enum {
1150
-
SVGA3D_CMP_INVALID = 0,
1151
-
SVGA3D_CMP_NEVER = 1,
1152
-
SVGA3D_CMP_LESS = 2,
1153
-
SVGA3D_CMP_EQUAL = 3,
1154
-
SVGA3D_CMP_LESSEQUAL = 4,
1155
-
SVGA3D_CMP_GREATER = 5,
1156
-
SVGA3D_CMP_NOTEQUAL = 6,
1157
-
SVGA3D_CMP_GREATEREQUAL = 7,
1158
-
SVGA3D_CMP_ALWAYS = 8,
1159
-
SVGA3D_CMP_MAX
848
+
SVGA3D_CMP_INVALID = 0,
849
+
SVGA3D_CMP_NEVER = 1,
850
+
SVGA3D_CMP_LESS = 2,
851
+
SVGA3D_CMP_EQUAL = 3,
852
+
SVGA3D_CMP_LESSEQUAL = 4,
853
+
SVGA3D_CMP_GREATER = 5,
854
+
SVGA3D_CMP_NOTEQUAL = 6,
855
+
SVGA3D_CMP_GREATEREQUAL = 7,
856
+
SVGA3D_CMP_ALWAYS = 8,
857
+
SVGA3D_CMP_MAX
1160
858
} SVGA3dCmpFunc;
1161
859
1162
-
/*
1163
-
* SVGA3D_FOGFUNC_* specifies the fog equation, or PER_VERTEX which allows
1164
-
* the fog factor to be specified in the alpha component of the specular
1165
-
* (a.k.a. secondary) vertex color.
1166
-
*/
1167
860
typedef enum {
1168
-
SVGA3D_FOGFUNC_INVALID = 0,
1169
-
SVGA3D_FOGFUNC_EXP = 1,
1170
-
SVGA3D_FOGFUNC_EXP2 = 2,
1171
-
SVGA3D_FOGFUNC_LINEAR = 3,
1172
-
SVGA3D_FOGFUNC_PER_VERTEX = 4
861
+
SVGA3D_FOGFUNC_INVALID = 0,
862
+
SVGA3D_FOGFUNC_EXP = 1,
863
+
SVGA3D_FOGFUNC_EXP2 = 2,
864
+
SVGA3D_FOGFUNC_LINEAR = 3,
865
+
SVGA3D_FOGFUNC_PER_VERTEX = 4
1173
866
} SVGA3dFogFunction;
1174
867
1175
-
/*
1176
-
* SVGA3D_FOGTYPE_* specifies if fog factors are computed on a per-vertex
1177
-
* or per-pixel basis.
1178
-
*/
1179
868
typedef enum {
1180
-
SVGA3D_FOGTYPE_INVALID = 0,
1181
-
SVGA3D_FOGTYPE_VERTEX = 1,
1182
-
SVGA3D_FOGTYPE_PIXEL = 2,
1183
-
SVGA3D_FOGTYPE_MAX = 3
869
+
SVGA3D_FOGTYPE_INVALID = 0,
870
+
SVGA3D_FOGTYPE_VERTEX = 1,
871
+
SVGA3D_FOGTYPE_PIXEL = 2,
872
+
SVGA3D_FOGTYPE_MAX = 3
1184
873
} SVGA3dFogType;
1185
874
1186
-
/*
1187
-
* SVGA3D_FOGBASE_* selects depth or range-based fog. Depth-based fog is
1188
-
* computed using the eye Z value of each pixel (or vertex), whereas range-
1189
-
* based fog is computed using the actual distance (range) to the eye.
1190
-
*/
1191
875
typedef enum {
1192
-
SVGA3D_FOGBASE_INVALID = 0,
1193
-
SVGA3D_FOGBASE_DEPTHBASED = 1,
1194
-
SVGA3D_FOGBASE_RANGEBASED = 2,
1195
-
SVGA3D_FOGBASE_MAX = 3
876
+
SVGA3D_FOGBASE_INVALID = 0,
877
+
SVGA3D_FOGBASE_DEPTHBASED = 1,
878
+
SVGA3D_FOGBASE_RANGEBASED = 2,
879
+
SVGA3D_FOGBASE_MAX = 3
1196
880
} SVGA3dFogBase;
1197
881
1198
882
typedef enum {
1199
-
SVGA3D_STENCILOP_INVALID = 0,
1200
-
SVGA3D_STENCILOP_MIN = 1,
1201
-
SVGA3D_STENCILOP_KEEP = 1,
1202
-
SVGA3D_STENCILOP_ZERO = 2,
1203
-
SVGA3D_STENCILOP_REPLACE = 3,
1204
-
SVGA3D_STENCILOP_INCRSAT = 4,
1205
-
SVGA3D_STENCILOP_DECRSAT = 5,
1206
-
SVGA3D_STENCILOP_INVERT = 6,
1207
-
SVGA3D_STENCILOP_INCR = 7,
1208
-
SVGA3D_STENCILOP_DECR = 8,
1209
-
SVGA3D_STENCILOP_MAX
883
+
SVGA3D_STENCILOP_INVALID = 0,
884
+
SVGA3D_STENCILOP_MIN = 1,
885
+
SVGA3D_STENCILOP_KEEP = 1,
886
+
SVGA3D_STENCILOP_ZERO = 2,
887
+
SVGA3D_STENCILOP_REPLACE = 3,
888
+
SVGA3D_STENCILOP_INCRSAT = 4,
889
+
SVGA3D_STENCILOP_DECRSAT = 5,
890
+
SVGA3D_STENCILOP_INVERT = 6,
891
+
SVGA3D_STENCILOP_INCR = 7,
892
+
SVGA3D_STENCILOP_DECR = 8,
893
+
SVGA3D_STENCILOP_MAX
1210
894
} SVGA3dStencilOp;
1211
895
1212
896
typedef enum {
1213
-
SVGA3D_CLIPPLANE_0 = (1 << 0),
1214
-
SVGA3D_CLIPPLANE_1 = (1 << 1),
1215
-
SVGA3D_CLIPPLANE_2 = (1 << 2),
1216
-
SVGA3D_CLIPPLANE_3 = (1 << 3),
1217
-
SVGA3D_CLIPPLANE_4 = (1 << 4),
1218
-
SVGA3D_CLIPPLANE_5 = (1 << 5),
897
+
SVGA3D_CLIPPLANE_0 = (1 << 0),
898
+
SVGA3D_CLIPPLANE_1 = (1 << 1),
899
+
SVGA3D_CLIPPLANE_2 = (1 << 2),
900
+
SVGA3D_CLIPPLANE_3 = (1 << 3),
901
+
SVGA3D_CLIPPLANE_4 = (1 << 4),
902
+
SVGA3D_CLIPPLANE_5 = (1 << 5),
1219
903
} SVGA3dClipPlanes;
1220
904
1221
905
typedef enum {
1222
-
SVGA3D_CLEAR_COLOR = 0x1,
1223
-
SVGA3D_CLEAR_DEPTH = 0x2,
1224
-
SVGA3D_CLEAR_STENCIL = 0x4,
906
+
SVGA3D_CLEAR_COLOR = 0x1,
907
+
SVGA3D_CLEAR_DEPTH = 0x2,
908
+
SVGA3D_CLEAR_STENCIL = 0x4,
1225
909
1226
-
/*
1227
-
* Hint only, must be used together with SVGA3D_CLEAR_COLOR. If
1228
-
* SVGA3D_CLEAR_DEPTH or SVGA3D_CLEAR_STENCIL bit is set, this
1229
-
* bit will be ignored.
1230
-
*/
1231
-
SVGA3D_CLEAR_COLORFILL = 0x8
910
+
SVGA3D_CLEAR_COLORFILL = 0x8
1232
911
} SVGA3dClearFlag;
1233
912
1234
913
typedef enum {
1235
-
SVGA3D_RT_DEPTH = 0,
1236
-
SVGA3D_RT_MIN = 0,
1237
-
SVGA3D_RT_STENCIL = 1,
1238
-
SVGA3D_RT_COLOR0 = 2,
1239
-
SVGA3D_RT_COLOR1 = 3,
1240
-
SVGA3D_RT_COLOR2 = 4,
1241
-
SVGA3D_RT_COLOR3 = 5,
1242
-
SVGA3D_RT_COLOR4 = 6,
1243
-
SVGA3D_RT_COLOR5 = 7,
1244
-
SVGA3D_RT_COLOR6 = 8,
1245
-
SVGA3D_RT_COLOR7 = 9,
1246
-
SVGA3D_RT_MAX,
1247
-
SVGA3D_RT_INVALID = ((uint32)-1),
914
+
SVGA3D_RT_DEPTH = 0,
915
+
SVGA3D_RT_MIN = 0,
916
+
SVGA3D_RT_STENCIL = 1,
917
+
SVGA3D_RT_COLOR0 = 2,
918
+
SVGA3D_RT_COLOR1 = 3,
919
+
SVGA3D_RT_COLOR2 = 4,
920
+
SVGA3D_RT_COLOR3 = 5,
921
+
SVGA3D_RT_COLOR4 = 6,
922
+
SVGA3D_RT_COLOR5 = 7,
923
+
SVGA3D_RT_COLOR6 = 8,
924
+
SVGA3D_RT_COLOR7 = 9,
925
+
SVGA3D_RT_MAX,
926
+
SVGA3D_RT_INVALID = ((uint32)-1),
1248
927
} SVGA3dRenderTargetType;
1249
928
1250
929
#define SVGA3D_MAX_RT_COLOR (SVGA3D_RT_COLOR7 - SVGA3D_RT_COLOR0 + 1)
1251
930
1252
-
typedef
1253
-
#include "vmware_pack_begin.h"
1254
-
union {
1255
-
struct {
1256
-
uint32 red : 1;
1257
-
uint32 green : 1;
1258
-
uint32 blue : 1;
1259
-
uint32 alpha : 1;
1260
-
};
1261
-
uint32 uintValue;
1262
-
}
1263
-
#include "vmware_pack_end.h"
1264
-
SVGA3dColorMask;
931
+
#pragma pack(push, 1)
932
+
typedef union {
933
+
struct {
934
+
uint32 red : 1;
935
+
uint32 green : 1;
936
+
uint32 blue : 1;
937
+
uint32 alpha : 1;
938
+
};
939
+
uint32 uintValue;
940
+
} SVGA3dColorMask;
941
+
#pragma pack(pop)
1265
942
1266
943
typedef enum {
1267
-
SVGA3D_VBLEND_DISABLE = 0,
1268
-
SVGA3D_VBLEND_1WEIGHT = 1,
1269
-
SVGA3D_VBLEND_2WEIGHT = 2,
1270
-
SVGA3D_VBLEND_3WEIGHT = 3,
1271
-
SVGA3D_VBLEND_MAX = 4,
944
+
SVGA3D_VBLEND_DISABLE = 0,
945
+
SVGA3D_VBLEND_1WEIGHT = 1,
946
+
SVGA3D_VBLEND_2WEIGHT = 2,
947
+
SVGA3D_VBLEND_3WEIGHT = 3,
948
+
SVGA3D_VBLEND_MAX = 4,
1272
949
} SVGA3dVertexBlendFlags;
1273
950
1274
951
typedef enum {
1275
-
SVGA3D_WRAPCOORD_0 = 1 << 0,
1276
-
SVGA3D_WRAPCOORD_1 = 1 << 1,
1277
-
SVGA3D_WRAPCOORD_2 = 1 << 2,
1278
-
SVGA3D_WRAPCOORD_3 = 1 << 3,
1279
-
SVGA3D_WRAPCOORD_ALL = 0xF,
952
+
SVGA3D_WRAPCOORD_0 = 1 << 0,
953
+
SVGA3D_WRAPCOORD_1 = 1 << 1,
954
+
SVGA3D_WRAPCOORD_2 = 1 << 2,
955
+
SVGA3D_WRAPCOORD_3 = 1 << 3,
956
+
SVGA3D_WRAPCOORD_ALL = 0xF,
1280
957
} SVGA3dWrapFlags;
1281
958
1282
-
/*
1283
-
* SVGA_3D_CMD_TEXTURESTATE Types. All value types
1284
-
* must fit in a uint32.
1285
-
*/
1286
-
1287
959
typedef enum {
1288
-
SVGA3D_TS_INVALID = 0,
1289
-
SVGA3D_TS_MIN = 1,
1290
-
SVGA3D_TS_BIND_TEXTURE = 1, /* SVGA3dSurfaceId */
1291
-
SVGA3D_TS_COLOROP = 2, /* SVGA3dTextureCombiner */
1292
-
SVGA3D_TS_COLORARG1 = 3, /* SVGA3dTextureArgData */
1293
-
SVGA3D_TS_COLORARG2 = 4, /* SVGA3dTextureArgData */
1294
-
SVGA3D_TS_ALPHAOP = 5, /* SVGA3dTextureCombiner */
1295
-
SVGA3D_TS_ALPHAARG1 = 6, /* SVGA3dTextureArgData */
1296
-
SVGA3D_TS_ALPHAARG2 = 7, /* SVGA3dTextureArgData */
1297
-
SVGA3D_TS_ADDRESSU = 8, /* SVGA3dTextureAddress */
1298
-
SVGA3D_TS_ADDRESSV = 9, /* SVGA3dTextureAddress */
1299
-
SVGA3D_TS_MIPFILTER = 10, /* SVGA3dTextureFilter */
1300
-
SVGA3D_TS_MAGFILTER = 11, /* SVGA3dTextureFilter */
1301
-
SVGA3D_TS_MINFILTER = 12, /* SVGA3dTextureFilter */
1302
-
SVGA3D_TS_BORDERCOLOR = 13, /* SVGA3dColor */
1303
-
SVGA3D_TS_TEXCOORDINDEX = 14, /* uint32 */
1304
-
SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15, /* SVGA3dTexTransformFlags */
1305
-
SVGA3D_TS_TEXCOORDGEN = 16, /* SVGA3dTextureCoordGen */
1306
-
SVGA3D_TS_BUMPENVMAT00 = 17, /* float */
1307
-
SVGA3D_TS_BUMPENVMAT01 = 18, /* float */
1308
-
SVGA3D_TS_BUMPENVMAT10 = 19, /* float */
1309
-
SVGA3D_TS_BUMPENVMAT11 = 20, /* float */
1310
-
SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21, /* uint32 */
1311
-
SVGA3D_TS_TEXTURE_LOD_BIAS = 22, /* float */
1312
-
SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23, /* uint32 */
1313
-
SVGA3D_TS_ADDRESSW = 24, /* SVGA3dTextureAddress */
960
+
SVGA3D_TS_INVALID = 0,
961
+
SVGA3D_TS_MIN = 1,
962
+
SVGA3D_TS_BIND_TEXTURE = 1,
963
+
SVGA3D_TS_COLOROP = 2,
964
+
SVGA3D_TS_COLORARG1 = 3,
965
+
SVGA3D_TS_COLORARG2 = 4,
966
+
SVGA3D_TS_ALPHAOP = 5,
967
+
SVGA3D_TS_ALPHAARG1 = 6,
968
+
SVGA3D_TS_ALPHAARG2 = 7,
969
+
SVGA3D_TS_ADDRESSU = 8,
970
+
SVGA3D_TS_ADDRESSV = 9,
971
+
SVGA3D_TS_MIPFILTER = 10,
972
+
SVGA3D_TS_MAGFILTER = 11,
973
+
SVGA3D_TS_MINFILTER = 12,
974
+
SVGA3D_TS_BORDERCOLOR = 13,
975
+
SVGA3D_TS_TEXCOORDINDEX = 14,
976
+
SVGA3D_TS_TEXTURETRANSFORMFLAGS = 15,
977
+
SVGA3D_TS_TEXCOORDGEN = 16,
978
+
SVGA3D_TS_BUMPENVMAT00 = 17,
979
+
SVGA3D_TS_BUMPENVMAT01 = 18,
980
+
SVGA3D_TS_BUMPENVMAT10 = 19,
981
+
SVGA3D_TS_BUMPENVMAT11 = 20,
982
+
SVGA3D_TS_TEXTURE_MIPMAP_LEVEL = 21,
983
+
SVGA3D_TS_TEXTURE_LOD_BIAS = 22,
984
+
SVGA3D_TS_TEXTURE_ANISOTROPIC_LEVEL = 23,
985
+
SVGA3D_TS_ADDRESSW = 24,
1314
986
1315
-
1316
-
/*
1317
-
* Sampler Gamma Level
1318
-
*
1319
-
* Sampler gamma effects the color of samples taken from the sampler. A
1320
-
* value of 1.0 will produce linear samples. If the value is <= 0.0 the
1321
-
* gamma value is ignored and a linear space is used.
1322
-
*/
1323
-
1324
-
SVGA3D_TS_GAMMA = 25, /* float */
1325
-
SVGA3D_TS_BUMPENVLSCALE = 26, /* float */
1326
-
SVGA3D_TS_BUMPENVLOFFSET = 27, /* float */
1327
-
SVGA3D_TS_COLORARG0 = 28, /* SVGA3dTextureArgData */
1328
-
SVGA3D_TS_ALPHAARG0 = 29, /* SVGA3dTextureArgData */
1329
-
SVGA3D_TS_PREGB_MAX = 30, /* Max value before GBObjects */
1330
-
SVGA3D_TS_CONSTANT = 30, /* SVGA3dColor */
1331
-
SVGA3D_TS_COLOR_KEY_ENABLE = 31, /* SVGA3dBool */
1332
-
SVGA3D_TS_COLOR_KEY = 32, /* SVGA3dColor */
1333
-
SVGA3D_TS_MAX
987
+
SVGA3D_TS_GAMMA = 25,
988
+
SVGA3D_TS_BUMPENVLSCALE = 26,
989
+
SVGA3D_TS_BUMPENVLOFFSET = 27,
990
+
SVGA3D_TS_COLORARG0 = 28,
991
+
SVGA3D_TS_ALPHAARG0 = 29,
992
+
SVGA3D_TS_PREGB_MAX = 30,
993
+
SVGA3D_TS_CONSTANT = 30,
994
+
SVGA3D_TS_COLOR_KEY_ENABLE = 31,
995
+
SVGA3D_TS_COLOR_KEY = 32,
996
+
SVGA3D_TS_MAX
1334
997
} SVGA3dTextureStateName;
1335
998
1336
999
typedef enum {
1337
-
SVGA3D_TC_INVALID = 0,
1338
-
SVGA3D_TC_DISABLE = 1,
1339
-
SVGA3D_TC_SELECTARG1 = 2,
1340
-
SVGA3D_TC_SELECTARG2 = 3,
1341
-
SVGA3D_TC_MODULATE = 4,
1342
-
SVGA3D_TC_ADD = 5,
1343
-
SVGA3D_TC_ADDSIGNED = 6,
1344
-
SVGA3D_TC_SUBTRACT = 7,
1345
-
SVGA3D_TC_BLENDTEXTUREALPHA = 8,
1346
-
SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
1347
-
SVGA3D_TC_BLENDCURRENTALPHA = 10,
1348
-
SVGA3D_TC_BLENDFACTORALPHA = 11,
1349
-
SVGA3D_TC_MODULATE2X = 12,
1350
-
SVGA3D_TC_MODULATE4X = 13,
1351
-
SVGA3D_TC_DSDT = 14,
1352
-
SVGA3D_TC_DOTPRODUCT3 = 15,
1353
-
SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
1354
-
SVGA3D_TC_ADDSIGNED2X = 17,
1355
-
SVGA3D_TC_ADDSMOOTH = 18,
1356
-
SVGA3D_TC_PREMODULATE = 19,
1357
-
SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
1358
-
SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
1359
-
SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
1360
-
SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
1361
-
SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
1362
-
SVGA3D_TC_MULTIPLYADD = 25,
1363
-
SVGA3D_TC_LERP = 26,
1364
-
SVGA3D_TC_MAX
1000
+
SVGA3D_TC_INVALID = 0,
1001
+
SVGA3D_TC_DISABLE = 1,
1002
+
SVGA3D_TC_SELECTARG1 = 2,
1003
+
SVGA3D_TC_SELECTARG2 = 3,
1004
+
SVGA3D_TC_MODULATE = 4,
1005
+
SVGA3D_TC_ADD = 5,
1006
+
SVGA3D_TC_ADDSIGNED = 6,
1007
+
SVGA3D_TC_SUBTRACT = 7,
1008
+
SVGA3D_TC_BLENDTEXTUREALPHA = 8,
1009
+
SVGA3D_TC_BLENDDIFFUSEALPHA = 9,
1010
+
SVGA3D_TC_BLENDCURRENTALPHA = 10,
1011
+
SVGA3D_TC_BLENDFACTORALPHA = 11,
1012
+
SVGA3D_TC_MODULATE2X = 12,
1013
+
SVGA3D_TC_MODULATE4X = 13,
1014
+
SVGA3D_TC_DSDT = 14,
1015
+
SVGA3D_TC_DOTPRODUCT3 = 15,
1016
+
SVGA3D_TC_BLENDTEXTUREALPHAPM = 16,
1017
+
SVGA3D_TC_ADDSIGNED2X = 17,
1018
+
SVGA3D_TC_ADDSMOOTH = 18,
1019
+
SVGA3D_TC_PREMODULATE = 19,
1020
+
SVGA3D_TC_MODULATEALPHA_ADDCOLOR = 20,
1021
+
SVGA3D_TC_MODULATECOLOR_ADDALPHA = 21,
1022
+
SVGA3D_TC_MODULATEINVALPHA_ADDCOLOR = 22,
1023
+
SVGA3D_TC_MODULATEINVCOLOR_ADDALPHA = 23,
1024
+
SVGA3D_TC_BUMPENVMAPLUMINANCE = 24,
1025
+
SVGA3D_TC_MULTIPLYADD = 25,
1026
+
SVGA3D_TC_LERP = 26,
1027
+
SVGA3D_TC_MAX
1365
1028
} SVGA3dTextureCombiner;
1366
1029
1367
-
#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) (svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
1030
+
#define SVGA3D_TC_CAP_BIT(svga3d_tc_op) \
1031
+
(svga3d_tc_op ? (1 << (svga3d_tc_op - 1)) : 0)
1368
1032
1369
1033
typedef enum {
1370
-
SVGA3D_TEX_ADDRESS_INVALID = 0,
1371
-
SVGA3D_TEX_ADDRESS_MIN = 1,
1372
-
SVGA3D_TEX_ADDRESS_WRAP = 1,
1373
-
SVGA3D_TEX_ADDRESS_MIRROR = 2,
1374
-
SVGA3D_TEX_ADDRESS_CLAMP = 3,
1375
-
SVGA3D_TEX_ADDRESS_BORDER = 4,
1376
-
SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
1377
-
SVGA3D_TEX_ADDRESS_EDGE = 6,
1378
-
SVGA3D_TEX_ADDRESS_MAX
1034
+
SVGA3D_TEX_ADDRESS_INVALID = 0,
1035
+
SVGA3D_TEX_ADDRESS_MIN = 1,
1036
+
SVGA3D_TEX_ADDRESS_WRAP = 1,
1037
+
SVGA3D_TEX_ADDRESS_MIRROR = 2,
1038
+
SVGA3D_TEX_ADDRESS_CLAMP = 3,
1039
+
SVGA3D_TEX_ADDRESS_BORDER = 4,
1040
+
SVGA3D_TEX_ADDRESS_MIRRORONCE = 5,
1041
+
SVGA3D_TEX_ADDRESS_EDGE = 6,
1042
+
SVGA3D_TEX_ADDRESS_MAX
1379
1043
} SVGA3dTextureAddress;
1380
1044
1381
-
/*
1382
-
* SVGA3D_TEX_FILTER_NONE as the minification filter means mipmapping is
1383
-
* disabled, and the rasterizer should use the magnification filter instead.
1384
-
*/
1385
1045
typedef enum {
1386
-
SVGA3D_TEX_FILTER_NONE = 0,
1387
-
SVGA3D_TEX_FILTER_MIN = 0,
1388
-
SVGA3D_TEX_FILTER_NEAREST = 1,
1389
-
SVGA3D_TEX_FILTER_LINEAR = 2,
1390
-
SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
1391
-
SVGA3D_TEX_FILTER_FLATCUBIC = 4, /* Deprecated, not implemented */
1392
-
SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5, /* Deprecated, not implemented */
1393
-
SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6, /* Not currently implemented */
1394
-
SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7, /* Not currently implemented */
1395
-
SVGA3D_TEX_FILTER_MAX
1046
+
SVGA3D_TEX_FILTER_NONE = 0,
1047
+
SVGA3D_TEX_FILTER_MIN = 0,
1048
+
SVGA3D_TEX_FILTER_NEAREST = 1,
1049
+
SVGA3D_TEX_FILTER_LINEAR = 2,
1050
+
SVGA3D_TEX_FILTER_ANISOTROPIC = 3,
1051
+
SVGA3D_TEX_FILTER_FLATCUBIC = 4,
1052
+
SVGA3D_TEX_FILTER_GAUSSIANCUBIC = 5,
1053
+
SVGA3D_TEX_FILTER_PYRAMIDALQUAD = 6,
1054
+
SVGA3D_TEX_FILTER_GAUSSIANQUAD = 7,
1055
+
SVGA3D_TEX_FILTER_MAX
1396
1056
} SVGA3dTextureFilter;
1397
1057
1398
1058
typedef enum {
1399
-
SVGA3D_TEX_TRANSFORM_OFF = 0,
1400
-
SVGA3D_TEX_TRANSFORM_S = (1 << 0),
1401
-
SVGA3D_TEX_TRANSFORM_T = (1 << 1),
1402
-
SVGA3D_TEX_TRANSFORM_R = (1 << 2),
1403
-
SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
1404
-
SVGA3D_TEX_PROJECTED = (1 << 15),
1059
+
SVGA3D_TEX_TRANSFORM_OFF = 0,
1060
+
SVGA3D_TEX_TRANSFORM_S = (1 << 0),
1061
+
SVGA3D_TEX_TRANSFORM_T = (1 << 1),
1062
+
SVGA3D_TEX_TRANSFORM_R = (1 << 2),
1063
+
SVGA3D_TEX_TRANSFORM_Q = (1 << 3),
1064
+
SVGA3D_TEX_PROJECTED = (1 << 15),
1405
1065
} SVGA3dTexTransformFlags;
1406
1066
1407
1067
typedef enum {
1408
-
SVGA3D_TEXCOORD_GEN_OFF = 0,
1409
-
SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
1410
-
SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
1411
-
SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
1412
-
SVGA3D_TEXCOORD_GEN_SPHERE = 4,
1413
-
SVGA3D_TEXCOORD_GEN_MAX
1068
+
SVGA3D_TEXCOORD_GEN_OFF = 0,
1069
+
SVGA3D_TEXCOORD_GEN_EYE_POSITION = 1,
1070
+
SVGA3D_TEXCOORD_GEN_EYE_NORMAL = 2,
1071
+
SVGA3D_TEXCOORD_GEN_REFLECTIONVECTOR = 3,
1072
+
SVGA3D_TEXCOORD_GEN_SPHERE = 4,
1073
+
SVGA3D_TEXCOORD_GEN_MAX
1414
1074
} SVGA3dTextureCoordGen;
1415
1075
1416
-
/*
1417
-
* Texture argument constants for texture combiner
1418
-
*/
1419
1076
typedef enum {
1420
-
SVGA3D_TA_INVALID = 0,
1421
-
SVGA3D_TA_TFACTOR = 1,
1422
-
SVGA3D_TA_PREVIOUS = 2,
1423
-
SVGA3D_TA_DIFFUSE = 3,
1424
-
SVGA3D_TA_TEXTURE = 4,
1425
-
SVGA3D_TA_SPECULAR = 5,
1426
-
SVGA3D_TA_CONSTANT = 6,
1427
-
SVGA3D_TA_MAX
1077
+
SVGA3D_TA_INVALID = 0,
1078
+
SVGA3D_TA_TFACTOR = 1,
1079
+
SVGA3D_TA_PREVIOUS = 2,
1080
+
SVGA3D_TA_DIFFUSE = 3,
1081
+
SVGA3D_TA_TEXTURE = 4,
1082
+
SVGA3D_TA_SPECULAR = 5,
1083
+
SVGA3D_TA_CONSTANT = 6,
1084
+
SVGA3D_TA_MAX
1428
1085
} SVGA3dTextureArgData;
1429
1086
1430
1087
#define SVGA3D_TM_MASK_LEN 4
1431
1088
1432
-
/* Modifiers for texture argument constants defined above. */
1433
1089
typedef enum {
1434
-
SVGA3D_TM_NONE = 0,
1435
-
SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
1436
-
SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
1090
+
SVGA3D_TM_NONE = 0,
1091
+
SVGA3D_TM_ALPHA = (1 << SVGA3D_TM_MASK_LEN),
1092
+
SVGA3D_TM_ONE_MINUS = (2 << SVGA3D_TM_MASK_LEN),
1437
1093
} SVGA3dTextureArgModifier;
1438
1094
1439
-
/*
1440
-
* Vertex declarations
1441
-
*
1442
-
* Notes:
1443
-
*
1444
-
* SVGA3D_DECLUSAGE_POSITIONT is for pre-transformed vertices. If you
1445
-
* draw with any POSITIONT vertex arrays, the programmable vertex
1446
-
* pipeline will be implicitly disabled. Drawing will take place as if
1447
-
* no vertex shader was bound.
1448
-
*/
1449
-
1450
1095
typedef enum {
1451
-
SVGA3D_DECLUSAGE_POSITION = 0,
1452
-
SVGA3D_DECLUSAGE_BLENDWEIGHT,
1453
-
SVGA3D_DECLUSAGE_BLENDINDICES,
1454
-
SVGA3D_DECLUSAGE_NORMAL,
1455
-
SVGA3D_DECLUSAGE_PSIZE,
1456
-
SVGA3D_DECLUSAGE_TEXCOORD,
1457
-
SVGA3D_DECLUSAGE_TANGENT,
1458
-
SVGA3D_DECLUSAGE_BINORMAL,
1459
-
SVGA3D_DECLUSAGE_TESSFACTOR,
1460
-
SVGA3D_DECLUSAGE_POSITIONT,
1461
-
SVGA3D_DECLUSAGE_COLOR,
1462
-
SVGA3D_DECLUSAGE_FOG,
1463
-
SVGA3D_DECLUSAGE_DEPTH,
1464
-
SVGA3D_DECLUSAGE_SAMPLE,
1465
-
SVGA3D_DECLUSAGE_MAX
1096
+
SVGA3D_DECLUSAGE_POSITION = 0,
1097
+
SVGA3D_DECLUSAGE_BLENDWEIGHT,
1098
+
SVGA3D_DECLUSAGE_BLENDINDICES,
1099
+
SVGA3D_DECLUSAGE_NORMAL,
1100
+
SVGA3D_DECLUSAGE_PSIZE,
1101
+
SVGA3D_DECLUSAGE_TEXCOORD,
1102
+
SVGA3D_DECLUSAGE_TANGENT,
1103
+
SVGA3D_DECLUSAGE_BINORMAL,
1104
+
SVGA3D_DECLUSAGE_TESSFACTOR,
1105
+
SVGA3D_DECLUSAGE_POSITIONT,
1106
+
SVGA3D_DECLUSAGE_COLOR,
1107
+
SVGA3D_DECLUSAGE_FOG,
1108
+
SVGA3D_DECLUSAGE_DEPTH,
1109
+
SVGA3D_DECLUSAGE_SAMPLE,
1110
+
SVGA3D_DECLUSAGE_MAX
1466
1111
} SVGA3dDeclUsage;
1467
1112
1468
1113
typedef enum {
1469
-
SVGA3D_DECLMETHOD_DEFAULT = 0,
1470
-
SVGA3D_DECLMETHOD_PARTIALU,
1471
-
SVGA3D_DECLMETHOD_PARTIALV,
1472
-
SVGA3D_DECLMETHOD_CROSSUV, /* Normal */
1473
-
SVGA3D_DECLMETHOD_UV,
1474
-
SVGA3D_DECLMETHOD_LOOKUP, /* Lookup a displacement map */
1475
-
SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED, /* Lookup a pre-sampled displacement */
1476
-
/* map */
1114
+
SVGA3D_DECLMETHOD_DEFAULT = 0,
1115
+
SVGA3D_DECLMETHOD_PARTIALU,
1116
+
SVGA3D_DECLMETHOD_PARTIALV,
1117
+
SVGA3D_DECLMETHOD_CROSSUV,
1118
+
SVGA3D_DECLMETHOD_UV,
1119
+
SVGA3D_DECLMETHOD_LOOKUP,
1120
+
SVGA3D_DECLMETHOD_LOOKUPPRESAMPLED,
1477
1121
} SVGA3dDeclMethod;
1478
1122
1479
1123
typedef enum {
1480
-
SVGA3D_DECLTYPE_FLOAT1 = 0,
1481
-
SVGA3D_DECLTYPE_FLOAT2 = 1,
1482
-
SVGA3D_DECLTYPE_FLOAT3 = 2,
1483
-
SVGA3D_DECLTYPE_FLOAT4 = 3,
1484
-
SVGA3D_DECLTYPE_D3DCOLOR = 4,
1485
-
SVGA3D_DECLTYPE_UBYTE4 = 5,
1486
-
SVGA3D_DECLTYPE_SHORT2 = 6,
1487
-
SVGA3D_DECLTYPE_SHORT4 = 7,
1488
-
SVGA3D_DECLTYPE_UBYTE4N = 8,
1489
-
SVGA3D_DECLTYPE_SHORT2N = 9,
1490
-
SVGA3D_DECLTYPE_SHORT4N = 10,
1491
-
SVGA3D_DECLTYPE_USHORT2N = 11,
1492
-
SVGA3D_DECLTYPE_USHORT4N = 12,
1493
-
SVGA3D_DECLTYPE_UDEC3 = 13,
1494
-
SVGA3D_DECLTYPE_DEC3N = 14,
1495
-
SVGA3D_DECLTYPE_FLOAT16_2 = 15,
1496
-
SVGA3D_DECLTYPE_FLOAT16_4 = 16,
1497
-
SVGA3D_DECLTYPE_MAX,
1124
+
SVGA3D_DECLTYPE_FLOAT1 = 0,
1125
+
SVGA3D_DECLTYPE_FLOAT2 = 1,
1126
+
SVGA3D_DECLTYPE_FLOAT3 = 2,
1127
+
SVGA3D_DECLTYPE_FLOAT4 = 3,
1128
+
SVGA3D_DECLTYPE_D3DCOLOR = 4,
1129
+
SVGA3D_DECLTYPE_UBYTE4 = 5,
1130
+
SVGA3D_DECLTYPE_SHORT2 = 6,
1131
+
SVGA3D_DECLTYPE_SHORT4 = 7,
1132
+
SVGA3D_DECLTYPE_UBYTE4N = 8,
1133
+
SVGA3D_DECLTYPE_SHORT2N = 9,
1134
+
SVGA3D_DECLTYPE_SHORT4N = 10,
1135
+
SVGA3D_DECLTYPE_USHORT2N = 11,
1136
+
SVGA3D_DECLTYPE_USHORT4N = 12,
1137
+
SVGA3D_DECLTYPE_UDEC3 = 13,
1138
+
SVGA3D_DECLTYPE_DEC3N = 14,
1139
+
SVGA3D_DECLTYPE_FLOAT16_2 = 15,
1140
+
SVGA3D_DECLTYPE_FLOAT16_4 = 16,
1141
+
SVGA3D_DECLTYPE_MAX,
1498
1142
} SVGA3dDeclType;
1499
1143
1500
-
/*
1501
-
* This structure is used for the divisor for geometry instancing;
1502
-
* it's a direct translation of the Direct3D equivalent.
1503
-
*/
1504
1144
typedef union {
1505
-
struct {
1506
-
/*
1507
-
* For index data, this number represents the number of instances to draw.
1508
-
* For instance data, this number represents the number of
1509
-
* instances/vertex in this stream
1510
-
*/
1511
-
uint32 count : 30;
1145
+
struct {
1146
+
uint32 count : 30;
1512
1147
1513
-
/*
1514
-
* This is 1 if this is supposed to be the data that is repeated for
1515
-
* every instance.
1516
-
*/
1517
-
uint32 indexedData : 1;
1148
+
uint32 indexedData : 1;
1518
1149
1519
-
/*
1520
-
* This is 1 if this is supposed to be the per-instance data.
1521
-
*/
1522
-
uint32 instanceData : 1;
1523
-
};
1150
+
uint32 instanceData : 1;
1151
+
};
1524
1152
1525
-
uint32 value;
1153
+
uint32 value;
1526
1154
} SVGA3dVertexDivisor;
1527
1155
1528
1156
typedef enum {
1529
-
/*
1530
-
* SVGA3D_PRIMITIVE_INVALID is a valid primitive type.
1531
-
*
1532
-
* List MIN second so debuggers will think INVALID is
1533
-
* the correct name.
1534
-
*/
1535
-
SVGA3D_PRIMITIVE_INVALID = 0,
1536
-
SVGA3D_PRIMITIVE_MIN = 0,
1537
-
SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1538
-
SVGA3D_PRIMITIVE_POINTLIST = 2,
1539
-
SVGA3D_PRIMITIVE_LINELIST = 3,
1540
-
SVGA3D_PRIMITIVE_LINESTRIP = 4,
1541
-
SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1542
-
SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1543
-
SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
1544
-
SVGA3D_PRIMITIVE_PREDX_MAX = 7,
1545
-
SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
1546
-
SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
1547
-
SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
1548
-
SVGA3D_PRIMITIVE_DX10_MAX = 11,
1549
-
SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11,
1550
-
SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12,
1551
-
SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13,
1552
-
SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14,
1553
-
SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15,
1554
-
SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16,
1555
-
SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17,
1556
-
SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18,
1557
-
SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19,
1558
-
SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20,
1559
-
SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21,
1560
-
SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22,
1561
-
SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23,
1562
-
SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24,
1563
-
SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25,
1564
-
SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26,
1565
-
SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27,
1566
-
SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28,
1567
-
SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29,
1568
-
SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30,
1569
-
SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31,
1570
-
SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32,
1571
-
SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33,
1572
-
SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34,
1573
-
SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35,
1574
-
SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36,
1575
-
SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37,
1576
-
SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38,
1577
-
SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39,
1578
-
SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40,
1579
-
SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41,
1580
-
SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42,
1581
-
SVGA3D_PRIMITIVE_MAX = 43
1157
+
1158
+
SVGA3D_PRIMITIVE_INVALID = 0,
1159
+
SVGA3D_PRIMITIVE_MIN = 0,
1160
+
SVGA3D_PRIMITIVE_TRIANGLELIST = 1,
1161
+
SVGA3D_PRIMITIVE_POINTLIST = 2,
1162
+
SVGA3D_PRIMITIVE_LINELIST = 3,
1163
+
SVGA3D_PRIMITIVE_LINESTRIP = 4,
1164
+
SVGA3D_PRIMITIVE_TRIANGLESTRIP = 5,
1165
+
SVGA3D_PRIMITIVE_TRIANGLEFAN = 6,
1166
+
SVGA3D_PRIMITIVE_LINELIST_ADJ = 7,
1167
+
SVGA3D_PRIMITIVE_PREDX_MAX = 7,
1168
+
SVGA3D_PRIMITIVE_LINESTRIP_ADJ = 8,
1169
+
SVGA3D_PRIMITIVE_TRIANGLELIST_ADJ = 9,
1170
+
SVGA3D_PRIMITIVE_TRIANGLESTRIP_ADJ = 10,
1171
+
SVGA3D_PRIMITIVE_DX10_MAX = 11,
1172
+
SVGA3D_PRIMITIVE_1_CONTROL_POINT_PATCH = 11,
1173
+
SVGA3D_PRIMITIVE_2_CONTROL_POINT_PATCH = 12,
1174
+
SVGA3D_PRIMITIVE_3_CONTROL_POINT_PATCH = 13,
1175
+
SVGA3D_PRIMITIVE_4_CONTROL_POINT_PATCH = 14,
1176
+
SVGA3D_PRIMITIVE_5_CONTROL_POINT_PATCH = 15,
1177
+
SVGA3D_PRIMITIVE_6_CONTROL_POINT_PATCH = 16,
1178
+
SVGA3D_PRIMITIVE_7_CONTROL_POINT_PATCH = 17,
1179
+
SVGA3D_PRIMITIVE_8_CONTROL_POINT_PATCH = 18,
1180
+
SVGA3D_PRIMITIVE_9_CONTROL_POINT_PATCH = 19,
1181
+
SVGA3D_PRIMITIVE_10_CONTROL_POINT_PATCH = 20,
1182
+
SVGA3D_PRIMITIVE_11_CONTROL_POINT_PATCH = 21,
1183
+
SVGA3D_PRIMITIVE_12_CONTROL_POINT_PATCH = 22,
1184
+
SVGA3D_PRIMITIVE_13_CONTROL_POINT_PATCH = 23,
1185
+
SVGA3D_PRIMITIVE_14_CONTROL_POINT_PATCH = 24,
1186
+
SVGA3D_PRIMITIVE_15_CONTROL_POINT_PATCH = 25,
1187
+
SVGA3D_PRIMITIVE_16_CONTROL_POINT_PATCH = 26,
1188
+
SVGA3D_PRIMITIVE_17_CONTROL_POINT_PATCH = 27,
1189
+
SVGA3D_PRIMITIVE_18_CONTROL_POINT_PATCH = 28,
1190
+
SVGA3D_PRIMITIVE_19_CONTROL_POINT_PATCH = 29,
1191
+
SVGA3D_PRIMITIVE_20_CONTROL_POINT_PATCH = 30,
1192
+
SVGA3D_PRIMITIVE_21_CONTROL_POINT_PATCH = 31,
1193
+
SVGA3D_PRIMITIVE_22_CONTROL_POINT_PATCH = 32,
1194
+
SVGA3D_PRIMITIVE_23_CONTROL_POINT_PATCH = 33,
1195
+
SVGA3D_PRIMITIVE_24_CONTROL_POINT_PATCH = 34,
1196
+
SVGA3D_PRIMITIVE_25_CONTROL_POINT_PATCH = 35,
1197
+
SVGA3D_PRIMITIVE_26_CONTROL_POINT_PATCH = 36,
1198
+
SVGA3D_PRIMITIVE_27_CONTROL_POINT_PATCH = 37,
1199
+
SVGA3D_PRIMITIVE_28_CONTROL_POINT_PATCH = 38,
1200
+
SVGA3D_PRIMITIVE_29_CONTROL_POINT_PATCH = 39,
1201
+
SVGA3D_PRIMITIVE_30_CONTROL_POINT_PATCH = 40,
1202
+
SVGA3D_PRIMITIVE_31_CONTROL_POINT_PATCH = 41,
1203
+
SVGA3D_PRIMITIVE_32_CONTROL_POINT_PATCH = 42,
1204
+
SVGA3D_PRIMITIVE_MAX = 43
1582
1205
} SVGA3dPrimitiveType;
1583
1206
1584
1207
typedef enum {
1585
-
SVGA3D_COORDINATE_INVALID = 0,
1586
-
SVGA3D_COORDINATE_LEFTHANDED = 1,
1587
-
SVGA3D_COORDINATE_RIGHTHANDED = 2,
1588
-
SVGA3D_COORDINATE_MAX
1208
+
SVGA3D_COORDINATE_INVALID = 0,
1209
+
SVGA3D_COORDINATE_LEFTHANDED = 1,
1210
+
SVGA3D_COORDINATE_RIGHTHANDED = 2,
1211
+
SVGA3D_COORDINATE_MAX
1589
1212
} SVGA3dCoordinateType;
1590
1213
1591
1214
typedef enum {
1592
-
SVGA3D_TRANSFORM_INVALID = 0,
1593
-
SVGA3D_TRANSFORM_WORLD = 1,
1594
-
SVGA3D_TRANSFORM_MIN = 1,
1595
-
SVGA3D_TRANSFORM_VIEW = 2,
1596
-
SVGA3D_TRANSFORM_PROJECTION = 3,
1597
-
SVGA3D_TRANSFORM_TEXTURE0 = 4,
1598
-
SVGA3D_TRANSFORM_TEXTURE1 = 5,
1599
-
SVGA3D_TRANSFORM_TEXTURE2 = 6,
1600
-
SVGA3D_TRANSFORM_TEXTURE3 = 7,
1601
-
SVGA3D_TRANSFORM_TEXTURE4 = 8,
1602
-
SVGA3D_TRANSFORM_TEXTURE5 = 9,
1603
-
SVGA3D_TRANSFORM_TEXTURE6 = 10,
1604
-
SVGA3D_TRANSFORM_TEXTURE7 = 11,
1605
-
SVGA3D_TRANSFORM_WORLD1 = 12,
1606
-
SVGA3D_TRANSFORM_WORLD2 = 13,
1607
-
SVGA3D_TRANSFORM_WORLD3 = 14,
1608
-
SVGA3D_TRANSFORM_MAX
1215
+
SVGA3D_TRANSFORM_INVALID = 0,
1216
+
SVGA3D_TRANSFORM_WORLD = 1,
1217
+
SVGA3D_TRANSFORM_MIN = 1,
1218
+
SVGA3D_TRANSFORM_VIEW = 2,
1219
+
SVGA3D_TRANSFORM_PROJECTION = 3,
1220
+
SVGA3D_TRANSFORM_TEXTURE0 = 4,
1221
+
SVGA3D_TRANSFORM_TEXTURE1 = 5,
1222
+
SVGA3D_TRANSFORM_TEXTURE2 = 6,
1223
+
SVGA3D_TRANSFORM_TEXTURE3 = 7,
1224
+
SVGA3D_TRANSFORM_TEXTURE4 = 8,
1225
+
SVGA3D_TRANSFORM_TEXTURE5 = 9,
1226
+
SVGA3D_TRANSFORM_TEXTURE6 = 10,
1227
+
SVGA3D_TRANSFORM_TEXTURE7 = 11,
1228
+
SVGA3D_TRANSFORM_WORLD1 = 12,
1229
+
SVGA3D_TRANSFORM_WORLD2 = 13,
1230
+
SVGA3D_TRANSFORM_WORLD3 = 14,
1231
+
SVGA3D_TRANSFORM_MAX
1609
1232
} SVGA3dTransformType;
1610
1233
1611
1234
typedef enum {
1612
-
SVGA3D_LIGHTTYPE_INVALID = 0,
1613
-
SVGA3D_LIGHTTYPE_MIN = 1,
1614
-
SVGA3D_LIGHTTYPE_POINT = 1,
1615
-
SVGA3D_LIGHTTYPE_SPOT1 = 2, /* 1-cone, in degrees */
1616
-
SVGA3D_LIGHTTYPE_SPOT2 = 3, /* 2-cone, in radians */
1617
-
SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1618
-
SVGA3D_LIGHTTYPE_MAX
1235
+
SVGA3D_LIGHTTYPE_INVALID = 0,
1236
+
SVGA3D_LIGHTTYPE_MIN = 1,
1237
+
SVGA3D_LIGHTTYPE_POINT = 1,
1238
+
SVGA3D_LIGHTTYPE_SPOT1 = 2,
1239
+
SVGA3D_LIGHTTYPE_SPOT2 = 3,
1240
+
SVGA3D_LIGHTTYPE_DIRECTIONAL = 4,
1241
+
SVGA3D_LIGHTTYPE_MAX
1619
1242
} SVGA3dLightType;
1620
1243
1621
1244
typedef enum {
1622
-
SVGA3D_CUBEFACE_POSX = 0,
1623
-
SVGA3D_CUBEFACE_NEGX = 1,
1624
-
SVGA3D_CUBEFACE_POSY = 2,
1625
-
SVGA3D_CUBEFACE_NEGY = 3,
1626
-
SVGA3D_CUBEFACE_POSZ = 4,
1627
-
SVGA3D_CUBEFACE_NEGZ = 5,
1245
+
SVGA3D_CUBEFACE_POSX = 0,
1246
+
SVGA3D_CUBEFACE_NEGX = 1,
1247
+
SVGA3D_CUBEFACE_POSY = 2,
1248
+
SVGA3D_CUBEFACE_NEGY = 3,
1249
+
SVGA3D_CUBEFACE_POSZ = 4,
1250
+
SVGA3D_CUBEFACE_NEGZ = 5,
1628
1251
} SVGA3dCubeFace;
1629
1252
1630
1253
typedef enum {
1631
-
SVGA3D_SHADERTYPE_INVALID = 0,
1632
-
SVGA3D_SHADERTYPE_MIN = 1,
1633
-
SVGA3D_SHADERTYPE_VS = 1,
1634
-
SVGA3D_SHADERTYPE_PS = 2,
1635
-
SVGA3D_SHADERTYPE_PREDX_MAX = 3,
1636
-
SVGA3D_SHADERTYPE_GS = 3,
1637
-
SVGA3D_SHADERTYPE_DX10_MAX = 4,
1638
-
SVGA3D_SHADERTYPE_HS = 4,
1639
-
SVGA3D_SHADERTYPE_DS = 5,
1640
-
SVGA3D_SHADERTYPE_CS = 6,
1641
-
SVGA3D_SHADERTYPE_MAX = 7
1254
+
SVGA3D_SHADERTYPE_INVALID = 0,
1255
+
SVGA3D_SHADERTYPE_MIN = 1,
1256
+
SVGA3D_SHADERTYPE_VS = 1,
1257
+
SVGA3D_SHADERTYPE_PS = 2,
1258
+
SVGA3D_SHADERTYPE_PREDX_MAX = 3,
1259
+
SVGA3D_SHADERTYPE_GS = 3,
1260
+
SVGA3D_SHADERTYPE_DX10_MAX = 4,
1261
+
SVGA3D_SHADERTYPE_HS = 4,
1262
+
SVGA3D_SHADERTYPE_DS = 5,
1263
+
SVGA3D_SHADERTYPE_CS = 6,
1264
+
SVGA3D_SHADERTYPE_MAX = 7
1642
1265
} SVGA3dShaderType;
1643
1266
1644
-
#define SVGA3D_NUM_SHADERTYPE_PREDX \
1645
-
(SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
1267
+
#define SVGA3D_NUM_SHADERTYPE_PREDX \
1268
+
(SVGA3D_SHADERTYPE_PREDX_MAX - SVGA3D_SHADERTYPE_MIN)
1646
1269
1647
-
#define SVGA3D_NUM_SHADERTYPE_DX10 \
1648
-
(SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
1270
+
#define SVGA3D_NUM_SHADERTYPE_DX10 \
1271
+
(SVGA3D_SHADERTYPE_DX10_MAX - SVGA3D_SHADERTYPE_MIN)
1649
1272
1650
-
#define SVGA3D_NUM_SHADERTYPE \
1651
-
(SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1273
+
#define SVGA3D_NUM_SHADERTYPE (SVGA3D_SHADERTYPE_MAX - SVGA3D_SHADERTYPE_MIN)
1652
1274
1653
1275
typedef enum {
1654
-
SVGA3D_CONST_TYPE_MIN = 0,
1655
-
SVGA3D_CONST_TYPE_FLOAT = 0,
1656
-
SVGA3D_CONST_TYPE_INT = 1,
1657
-
SVGA3D_CONST_TYPE_BOOL = 2,
1658
-
SVGA3D_CONST_TYPE_MAX = 3,
1276
+
SVGA3D_CONST_TYPE_MIN = 0,
1277
+
SVGA3D_CONST_TYPE_FLOAT = 0,
1278
+
SVGA3D_CONST_TYPE_INT = 1,
1279
+
SVGA3D_CONST_TYPE_BOOL = 2,
1280
+
SVGA3D_CONST_TYPE_MAX = 3,
1659
1281
} SVGA3dShaderConstType;
1660
1282
1661
-
/*
1662
-
* Register limits for shader consts.
1663
-
*/
1664
-
#define SVGA3D_CONSTREG_MAX 256
1665
-
#define SVGA3D_CONSTINTREG_MAX 16
1666
-
#define SVGA3D_CONSTBOOLREG_MAX 16
1283
+
#define SVGA3D_CONSTREG_MAX 256
1284
+
#define SVGA3D_CONSTINTREG_MAX 16
1285
+
#define SVGA3D_CONSTBOOLREG_MAX 16
1667
1286
1668
1287
typedef enum {
1669
-
SVGA3D_STRETCH_BLT_POINT = 0,
1670
-
SVGA3D_STRETCH_BLT_LINEAR = 1,
1671
-
SVGA3D_STRETCH_BLT_MAX
1288
+
SVGA3D_STRETCH_BLT_POINT = 0,
1289
+
SVGA3D_STRETCH_BLT_LINEAR = 1,
1290
+
SVGA3D_STRETCH_BLT_MAX
1672
1291
} SVGA3dStretchBltMode;
1673
1292
1674
1293
typedef enum {
1675
-
SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
1676
-
SVGA3D_QUERYTYPE_MIN = 0,
1677
-
SVGA3D_QUERYTYPE_OCCLUSION = 0,
1678
-
SVGA3D_QUERYTYPE_TIMESTAMP = 1,
1679
-
SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
1680
-
SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
1681
-
SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
1682
-
SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
1683
-
SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
1684
-
SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
1685
-
SVGA3D_QUERYTYPE_DX10_MAX = 8,
1686
-
SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8,
1687
-
SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9,
1688
-
SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10,
1689
-
SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11,
1690
-
SVGA3D_QUERYTYPE_SOP_STREAM0 = 12,
1691
-
SVGA3D_QUERYTYPE_SOP_STREAM1 = 13,
1692
-
SVGA3D_QUERYTYPE_SOP_STREAM2 = 14,
1693
-
SVGA3D_QUERYTYPE_SOP_STREAM3 = 15,
1694
-
SVGA3D_QUERYTYPE_MAX
1294
+
SVGA3D_QUERYTYPE_INVALID = ((uint8)-1),
1295
+
SVGA3D_QUERYTYPE_MIN = 0,
1296
+
SVGA3D_QUERYTYPE_OCCLUSION = 0,
1297
+
SVGA3D_QUERYTYPE_TIMESTAMP = 1,
1298
+
SVGA3D_QUERYTYPE_TIMESTAMPDISJOINT = 2,
1299
+
SVGA3D_QUERYTYPE_PIPELINESTATS = 3,
1300
+
SVGA3D_QUERYTYPE_OCCLUSIONPREDICATE = 4,
1301
+
SVGA3D_QUERYTYPE_STREAMOUTPUTSTATS = 5,
1302
+
SVGA3D_QUERYTYPE_STREAMOVERFLOWPREDICATE = 6,
1303
+
SVGA3D_QUERYTYPE_OCCLUSION64 = 7,
1304
+
SVGA3D_QUERYTYPE_DX10_MAX = 8,
1305
+
SVGA3D_QUERYTYPE_SOSTATS_STREAM0 = 8,
1306
+
SVGA3D_QUERYTYPE_SOSTATS_STREAM1 = 9,
1307
+
SVGA3D_QUERYTYPE_SOSTATS_STREAM2 = 10,
1308
+
SVGA3D_QUERYTYPE_SOSTATS_STREAM3 = 11,
1309
+
SVGA3D_QUERYTYPE_SOP_STREAM0 = 12,
1310
+
SVGA3D_QUERYTYPE_SOP_STREAM1 = 13,
1311
+
SVGA3D_QUERYTYPE_SOP_STREAM2 = 14,
1312
+
SVGA3D_QUERYTYPE_SOP_STREAM3 = 15,
1313
+
SVGA3D_QUERYTYPE_MAX
1695
1314
} SVGA3dQueryType;
1696
1315
1697
1316
typedef uint8 SVGA3dQueryTypeUint8;
1698
1317
1699
-
#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
1318
+
#define SVGA3D_NUM_QUERYTYPE (SVGA3D_QUERYTYPE_MAX - SVGA3D_QUERYTYPE_MIN)
1700
1319
1701
-
/*
1702
-
* This is the maximum number of queries per context that can be active
1703
-
* simultaneously between a beginQuery and endQuery.
1704
-
*/
1705
1320
#define SVGA3D_MAX_QUERY 64
1706
1321
1707
-
/*
1708
-
* Query result buffer formats
1709
-
*/
1710
-
typedef
1711
-
#include "vmware_pack_begin.h"
1712
-
struct {
1713
-
uint32 samplesRendered;
1714
-
}
1715
-
#include "vmware_pack_end.h"
1716
-
SVGADXOcclusionQueryResult;
1322
+
#pragma pack(push, 1)
1323
+
typedef struct {
1324
+
uint32 samplesRendered;
1325
+
} SVGADXOcclusionQueryResult;
1326
+
#pragma pack(pop)
1717
1327
1718
-
typedef
1719
-
#include "vmware_pack_begin.h"
1720
-
struct {
1721
-
uint32 passed;
1722
-
}
1723
-
#include "vmware_pack_end.h"
1724
-
SVGADXEventQueryResult;
1328
+
#pragma pack(push, 1)
1329
+
typedef struct {
1330
+
uint32 passed;
1331
+
} SVGADXEventQueryResult;
1332
+
#pragma pack(pop)
1725
1333
1726
-
typedef
1727
-
#include "vmware_pack_begin.h"
1728
-
struct {
1729
-
uint64 timestamp;
1730
-
}
1731
-
#include "vmware_pack_end.h"
1732
-
SVGADXTimestampQueryResult;
1334
+
#pragma pack(push, 1)
1335
+
typedef struct {
1336
+
uint64 timestamp;
1337
+
} SVGADXTimestampQueryResult;
1338
+
#pragma pack(pop)
1733
1339
1734
-
typedef
1735
-
#include "vmware_pack_begin.h"
1736
-
struct {
1737
-
uint64 realFrequency;
1738
-
uint32 disjoint;
1739
-
}
1740
-
#include "vmware_pack_end.h"
1741
-
SVGADXTimestampDisjointQueryResult;
1340
+
#pragma pack(push, 1)
1341
+
typedef struct {
1342
+
uint64 realFrequency;
1343
+
uint32 disjoint;
1344
+
} SVGADXTimestampDisjointQueryResult;
1345
+
#pragma pack(pop)
1742
1346
1743
-
typedef
1744
-
#include "vmware_pack_begin.h"
1745
-
struct {
1746
-
uint64 inputAssemblyVertices;
1747
-
uint64 inputAssemblyPrimitives;
1748
-
uint64 vertexShaderInvocations;
1749
-
uint64 geometryShaderInvocations;
1750
-
uint64 geometryShaderPrimitives;
1751
-
uint64 clipperInvocations;
1752
-
uint64 clipperPrimitives;
1753
-
uint64 pixelShaderInvocations;
1754
-
uint64 hullShaderInvocations;
1755
-
uint64 domainShaderInvocations;
1756
-
uint64 computeShaderInvocations;
1757
-
}
1758
-
#include "vmware_pack_end.h"
1759
-
SVGADXPipelineStatisticsQueryResult;
1347
+
#pragma pack(push, 1)
1348
+
typedef struct {
1349
+
uint64 inputAssemblyVertices;
1350
+
uint64 inputAssemblyPrimitives;
1351
+
uint64 vertexShaderInvocations;
1352
+
uint64 geometryShaderInvocations;
1353
+
uint64 geometryShaderPrimitives;
1354
+
uint64 clipperInvocations;
1355
+
uint64 clipperPrimitives;
1356
+
uint64 pixelShaderInvocations;
1357
+
uint64 hullShaderInvocations;
1358
+
uint64 domainShaderInvocations;
1359
+
uint64 computeShaderInvocations;
1360
+
} SVGADXPipelineStatisticsQueryResult;
1361
+
#pragma pack(pop)
1760
1362
1761
-
typedef
1762
-
#include "vmware_pack_begin.h"
1763
-
struct {
1764
-
uint32 anySamplesRendered;
1765
-
}
1766
-
#include "vmware_pack_end.h"
1767
-
SVGADXOcclusionPredicateQueryResult;
1363
+
#pragma pack(push, 1)
1364
+
typedef struct {
1365
+
uint32 anySamplesRendered;
1366
+
} SVGADXOcclusionPredicateQueryResult;
1367
+
#pragma pack(pop)
1768
1368
1769
-
typedef
1770
-
#include "vmware_pack_begin.h"
1771
-
struct {
1772
-
uint64 numPrimitivesWritten;
1773
-
uint64 numPrimitivesRequired;
1774
-
}
1775
-
#include "vmware_pack_end.h"
1776
-
SVGADXStreamOutStatisticsQueryResult;
1369
+
#pragma pack(push, 1)
1370
+
typedef struct {
1371
+
uint64 numPrimitivesWritten;
1372
+
uint64 numPrimitivesRequired;
1373
+
} SVGADXStreamOutStatisticsQueryResult;
1374
+
#pragma pack(pop)
1777
1375
1778
-
typedef
1779
-
#include "vmware_pack_begin.h"
1780
-
struct {
1781
-
uint32 overflowed;
1782
-
}
1783
-
#include "vmware_pack_end.h"
1784
-
SVGADXStreamOutPredicateQueryResult;
1376
+
#pragma pack(push, 1)
1377
+
typedef struct {
1378
+
uint32 overflowed;
1379
+
} SVGADXStreamOutPredicateQueryResult;
1380
+
#pragma pack(pop)
1785
1381
1786
-
typedef
1787
-
#include "vmware_pack_begin.h"
1788
-
struct {
1789
-
uint64 samplesRendered;
1790
-
}
1791
-
#include "vmware_pack_end.h"
1792
-
SVGADXOcclusion64QueryResult;
1382
+
#pragma pack(push, 1)
1383
+
typedef struct {
1384
+
uint64 samplesRendered;
1385
+
} SVGADXOcclusion64QueryResult;
1386
+
#pragma pack(pop)
1793
1387
1794
-
/*
1795
-
* SVGADXQueryResultUnion is not intended for use in the protocol, but is
1796
-
* very helpful when working with queries generically.
1797
-
*/
1798
-
typedef
1799
-
#include "vmware_pack_begin.h"
1800
-
union SVGADXQueryResultUnion {
1801
-
SVGADXOcclusionQueryResult occ;
1802
-
SVGADXEventQueryResult event;
1803
-
SVGADXTimestampQueryResult ts;
1804
-
SVGADXTimestampDisjointQueryResult tsDisjoint;
1805
-
SVGADXPipelineStatisticsQueryResult pipelineStats;
1806
-
SVGADXOcclusionPredicateQueryResult occPred;
1807
-
SVGADXStreamOutStatisticsQueryResult soStats;
1808
-
SVGADXStreamOutPredicateQueryResult soPred;
1809
-
SVGADXOcclusion64QueryResult occ64;
1810
-
}
1811
-
#include "vmware_pack_end.h"
1812
-
SVGADXQueryResultUnion;
1388
+
#pragma pack(push, 1)
1389
+
typedef union SVGADXQueryResultUnion {
1390
+
SVGADXOcclusionQueryResult occ;
1391
+
SVGADXEventQueryResult event;
1392
+
SVGADXTimestampQueryResult ts;
1393
+
SVGADXTimestampDisjointQueryResult tsDisjoint;
1394
+
SVGADXPipelineStatisticsQueryResult pipelineStats;
1395
+
SVGADXOcclusionPredicateQueryResult occPred;
1396
+
SVGADXStreamOutStatisticsQueryResult soStats;
1397
+
SVGADXStreamOutPredicateQueryResult soPred;
1398
+
SVGADXOcclusion64QueryResult occ64;
1399
+
} SVGADXQueryResultUnion;
1400
+
#pragma pack(pop)
1813
1401
1814
1402
typedef enum {
1815
-
SVGA3D_QUERYSTATE_PENDING = 0, /* Query is not finished yet */
1816
-
SVGA3D_QUERYSTATE_SUCCEEDED = 1, /* Completed successfully */
1817
-
SVGA3D_QUERYSTATE_FAILED = 2, /* Completed unsuccessfully */
1818
-
SVGA3D_QUERYSTATE_NEW = 3, /* Never submitted (guest only) */
1403
+
SVGA3D_QUERYSTATE_PENDING = 0,
1404
+
SVGA3D_QUERYSTATE_SUCCEEDED = 1,
1405
+
SVGA3D_QUERYSTATE_FAILED = 2,
1406
+
SVGA3D_QUERYSTATE_NEW = 3,
1819
1407
} SVGA3dQueryState;
1820
1408
1821
1409
typedef enum {
1822
-
SVGA3D_WRITE_HOST_VRAM = 1,
1823
-
SVGA3D_READ_HOST_VRAM = 2,
1410
+
SVGA3D_WRITE_HOST_VRAM = 1,
1411
+
SVGA3D_READ_HOST_VRAM = 2,
1824
1412
} SVGA3dTransferType;
1825
1413
1826
-
#define SVGA3D_LOGICOP_INVALID 0
1827
-
#define SVGA3D_LOGICOP_MIN 1
1828
-
#define SVGA3D_LOGICOP_COPY 1
1829
-
#define SVGA3D_LOGICOP_NOT 2
1830
-
#define SVGA3D_LOGICOP_AND 3
1831
-
#define SVGA3D_LOGICOP_OR 4
1832
-
#define SVGA3D_LOGICOP_XOR 5
1833
-
#define SVGA3D_LOGICOP_NXOR 6
1834
-
#define SVGA3D_LOGICOP_ROP3 7
1835
-
#define SVGA3D_LOGICOP_MAX 8
1414
+
#define SVGA3D_LOGICOP_INVALID 0
1415
+
#define SVGA3D_LOGICOP_COPY 1
1416
+
1417
+
#define SVGA3D_LOGICOP_MIN 1
1418
+
#define SVGA3D_LOGICOP_NOT 2
1419
+
#define SVGA3D_LOGICOP_AND 3
1420
+
#define SVGA3D_LOGICOP_OR 4
1421
+
#define SVGA3D_LOGICOP_XOR 5
1422
+
#define SVGA3D_LOGICOP_NXOR 6
1423
+
#define SVGA3D_LOGICOP_ROP3 7
1424
+
1425
+
#define SVGA3D_LOGICOP_MAX 8
1836
1426
1837
1427
typedef uint16 SVGA3dLogicOp;
1838
1428
1839
-
#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16) -1)
1840
-
#define SVGA3D_LOGICOP_ROP3_MIN 0
1841
-
#define SVGA3D_LOGICOP_ROP3_MAX 256
1429
+
#define SVGA3D_LOGICOP_ROP3_INVALID ((uint16)-1)
1430
+
#define SVGA3D_LOGICOP_ROP3_MIN 0
1431
+
#define SVGA3D_LOGICOP_ROP3_MAX 256
1842
1432
1843
1433
typedef uint16 SVGA3dLogicOpRop3;
1844
1434
1845
-
typedef
1846
-
#include "vmware_pack_begin.h"
1847
-
struct {
1848
-
union {
1849
-
struct {
1850
-
uint16 function; // SVGA3dFogFunction
1851
-
uint8 type; // SVGA3dFogType
1852
-
uint8 base; // SVGA3dFogBase
1853
-
};
1854
-
uint32 uintValue;
1855
-
};
1856
-
}
1857
-
#include "vmware_pack_end.h"
1858
-
SVGA3dFogMode;
1435
+
#pragma pack(push, 1)
1436
+
typedef struct {
1437
+
union {
1438
+
struct {
1439
+
uint16 function;
1440
+
uint8 type;
1441
+
uint8 base;
1442
+
};
1443
+
uint32 uintValue;
1444
+
};
1445
+
} SVGA3dFogMode;
1446
+
#pragma pack(pop)
1859
1447
1860
-
/*
1861
-
* Uniquely identify one image (a 1D/2D/3D array) from a surface. This
1862
-
* is a surface ID as well as face/mipmap indices.
1863
-
*/
1864
-
typedef
1865
-
#include "vmware_pack_begin.h"
1866
-
struct SVGA3dSurfaceImageId {
1867
-
uint32 sid;
1868
-
uint32 face;
1869
-
uint32 mipmap;
1870
-
}
1871
-
#include "vmware_pack_end.h"
1872
-
SVGA3dSurfaceImageId;
1448
+
#pragma pack(push, 1)
1449
+
typedef struct SVGA3dSurfaceImageId {
1450
+
uint32 sid;
1451
+
uint32 face;
1452
+
uint32 mipmap;
1453
+
} SVGA3dSurfaceImageId;
1454
+
#pragma pack(pop)
1873
1455
1874
-
typedef
1875
-
#include "vmware_pack_begin.h"
1876
-
struct SVGA3dSubSurfaceId {
1877
-
uint32 sid;
1878
-
uint32 subResourceId;
1879
-
}
1880
-
#include "vmware_pack_end.h"
1881
-
SVGA3dSubSurfaceId;
1456
+
#pragma pack(push, 1)
1457
+
typedef struct SVGA3dSubSurfaceId {
1458
+
uint32 sid;
1459
+
uint32 subResourceId;
1460
+
} SVGA3dSubSurfaceId;
1461
+
#pragma pack(pop)
1882
1462
1883
-
typedef
1884
-
#include "vmware_pack_begin.h"
1885
-
struct {
1886
-
uint32 width;
1887
-
uint32 height;
1888
-
uint32 depth;
1889
-
}
1890
-
#include "vmware_pack_end.h"
1891
-
SVGA3dSize;
1463
+
#pragma pack(push, 1)
1464
+
typedef struct {
1465
+
uint32 width;
1466
+
uint32 height;
1467
+
uint32 depth;
1468
+
} SVGA3dSize;
1469
+
#pragma pack(pop)
1892
1470
1893
-
/*
1894
-
* Guest-backed objects definitions.
1895
-
*/
1896
1471
typedef enum {
1897
-
SVGA_OTABLE_MOB = 0,
1898
-
SVGA_OTABLE_MIN = 0,
1899
-
SVGA_OTABLE_SURFACE = 1,
1900
-
SVGA_OTABLE_CONTEXT = 2,
1901
-
SVGA_OTABLE_SHADER = 3,
1902
-
SVGA_OTABLE_SCREENTARGET = 4,
1472
+
SVGA_OTABLE_MOB = 0,
1473
+
SVGA_OTABLE_MIN = 0,
1474
+
SVGA_OTABLE_SURFACE = 1,
1475
+
SVGA_OTABLE_CONTEXT = 2,
1476
+
SVGA_OTABLE_SHADER = 3,
1477
+
SVGA_OTABLE_SCREENTARGET = 4,
1903
1478
1904
-
SVGA_OTABLE_DX9_MAX = 5,
1479
+
SVGA_OTABLE_DX9_MAX = 5,
1905
1480
1906
-
SVGA_OTABLE_DXCONTEXT = 5,
1907
-
SVGA_OTABLE_DX_MAX = 6,
1481
+
SVGA_OTABLE_DXCONTEXT = 5,
1482
+
SVGA_OTABLE_DX_MAX = 6,
1908
1483
1909
-
SVGA_OTABLE_RESERVED1 = 6,
1910
-
SVGA_OTABLE_RESERVED2 = 7,
1484
+
SVGA_OTABLE_DEVEL_MAX = 6,
1485
+
SVGA_OTABLE_MAX = 6,
1911
1486
1912
-
/*
1913
-
* Additions to this table need to be tied to HW-version features and
1914
-
* checkpointed accordingly.
1915
-
*/
1916
-
SVGA_OTABLE_DEVEL_MAX = 8,
1917
-
SVGA_OTABLE_MAX = 8
1487
+
SVGA_OTABLE_RESERVED1 = 6,
1488
+
SVGA_OTABLE_RESERVED2 = 7,
1489
+
SVGA_OTABLE_BUG_1952836_MAX = 8,
1918
1490
} SVGAOTableType;
1919
1491
1920
1492
typedef enum {
1921
-
SVGA_COTABLE_MIN = 0,
1922
-
SVGA_COTABLE_RTVIEW = 0,
1923
-
SVGA_COTABLE_DSVIEW = 1,
1924
-
SVGA_COTABLE_SRVIEW = 2,
1925
-
SVGA_COTABLE_ELEMENTLAYOUT = 3,
1926
-
SVGA_COTABLE_BLENDSTATE = 4,
1927
-
SVGA_COTABLE_DEPTHSTENCIL = 5,
1928
-
SVGA_COTABLE_RASTERIZERSTATE = 6,
1929
-
SVGA_COTABLE_SAMPLER = 7,
1930
-
SVGA_COTABLE_STREAMOUTPUT = 8,
1931
-
SVGA_COTABLE_DXQUERY = 9,
1932
-
SVGA_COTABLE_DXSHADER = 10,
1933
-
SVGA_COTABLE_DX10_MAX = 11,
1934
-
SVGA_COTABLE_UAVIEW = 11,
1935
-
SVGA_COTABLE_MAX = 12,
1493
+
SVGA_COTABLE_MIN = 0,
1494
+
SVGA_COTABLE_RTVIEW = 0,
1495
+
SVGA_COTABLE_DSVIEW = 1,
1496
+
SVGA_COTABLE_SRVIEW = 2,
1497
+
SVGA_COTABLE_ELEMENTLAYOUT = 3,
1498
+
SVGA_COTABLE_BLENDSTATE = 4,
1499
+
SVGA_COTABLE_DEPTHSTENCIL = 5,
1500
+
SVGA_COTABLE_RASTERIZERSTATE = 6,
1501
+
SVGA_COTABLE_SAMPLER = 7,
1502
+
SVGA_COTABLE_STREAMOUTPUT = 8,
1503
+
SVGA_COTABLE_DXQUERY = 9,
1504
+
SVGA_COTABLE_DXSHADER = 10,
1505
+
SVGA_COTABLE_DX10_MAX = 11,
1506
+
SVGA_COTABLE_UAVIEW = 11,
1507
+
SVGA_COTABLE_MAX = 12,
1936
1508
} SVGACOTableType;
1937
1509
1938
-
/*
1939
-
* The largest size (number of entries) allowed in a COTable.
1940
-
*/
1941
1510
#define SVGA_COTABLE_MAX_IDS (MAX_UINT16 - 2)
1942
1511
1943
1512
typedef enum SVGAMobFormat {
1944
-
SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1945
-
SVGA3D_MOBFMT_PTDEPTH_0 = 0,
1946
-
SVGA3D_MOBFMT_MIN = 0,
1947
-
SVGA3D_MOBFMT_PTDEPTH_1 = 1,
1948
-
SVGA3D_MOBFMT_PTDEPTH_2 = 2,
1949
-
SVGA3D_MOBFMT_RANGE = 3,
1950
-
SVGA3D_MOBFMT_PTDEPTH64_0 = 4,
1951
-
SVGA3D_MOBFMT_PTDEPTH64_1 = 5,
1952
-
SVGA3D_MOBFMT_PTDEPTH64_2 = 6,
1953
-
SVGA3D_MOBFMT_PREDX_MAX = 7,
1954
-
SVGA3D_MOBFMT_EMPTY = 7,
1955
-
SVGA3D_MOBFMT_MAX,
1513
+
SVGA3D_MOBFMT_INVALID = SVGA3D_INVALID_ID,
1514
+
SVGA3D_MOBFMT_PT_0 = 0,
1515
+
SVGA3D_MOBFMT_MIN = 0,
1516
+
SVGA3D_MOBFMT_PT_1 = 1,
1517
+
SVGA3D_MOBFMT_PT_2 = 2,
1518
+
SVGA3D_MOBFMT_RANGE = 3,
1519
+
SVGA3D_MOBFMT_PT64_0 = 4,
1520
+
SVGA3D_MOBFMT_PT64_1 = 5,
1521
+
SVGA3D_MOBFMT_PT64_2 = 6,
1522
+
SVGA3D_MOBFMT_PREDX_MAX = 7,
1523
+
SVGA3D_MOBFMT_EMPTY = 7,
1956
1524
1957
-
/*
1958
-
* This isn't actually used by the guest, but is a mob-format used
1959
-
* internally by the SVGA device (and is therefore not binary compatible).
1960
-
*/
1961
-
SVGA3D_MOBFMT_HB,
1525
+
SVGA3D_MOBFMT_MAX,
1526
+
1527
+
SVGA3D_MOBFMT_HB,
1962
1528
} SVGAMobFormat;
1963
1529
1964
1530
#define SVGA3D_MOB_EMPTY_BASE 1
1965
1531
1966
-
/*
1967
-
* Multisample pattern types.
1968
-
*/
1969
-
1970
1532
typedef enum SVGA3dMSPattern {
1971
-
SVGA3D_MS_PATTERN_NONE = 0,
1972
-
SVGA3D_MS_PATTERN_MIN = 0,
1973
-
SVGA3D_MS_PATTERN_STANDARD = 1,
1974
-
SVGA3D_MS_PATTERN_CENTER = 2,
1975
-
SVGA3D_MS_PATTERN_MAX = 3,
1533
+
SVGA3D_MS_PATTERN_NONE = 0,
1534
+
SVGA3D_MS_PATTERN_MIN = 0,
1535
+
SVGA3D_MS_PATTERN_STANDARD = 1,
1536
+
SVGA3D_MS_PATTERN_CENTER = 2,
1537
+
SVGA3D_MS_PATTERN_MAX = 3,
1976
1538
} SVGA3dMSPattern;
1977
1539
1978
-
/*
1979
-
* Precision settings for each sample.
1980
-
*/
1981
-
1982
1540
typedef enum SVGA3dMSQualityLevel {
1983
-
SVGA3D_MS_QUALITY_NONE = 0,
1984
-
SVGA3D_MS_QUALITY_MIN = 0,
1985
-
SVGA3D_MS_QUALITY_FULL = 1,
1986
-
SVGA3D_MS_QUALITY_MAX = 2,
1541
+
SVGA3D_MS_QUALITY_NONE = 0,
1542
+
SVGA3D_MS_QUALITY_MIN = 0,
1543
+
SVGA3D_MS_QUALITY_FULL = 1,
1544
+
SVGA3D_MS_QUALITY_RESOLVED = 2,
1545
+
SVGA3D_MS_QUALITY_MAX = 3,
1987
1546
} SVGA3dMSQualityLevel;
1988
1547
1989
-
/*
1990
-
* Screen Target Update Flags
1991
-
*/
1992
-
1993
1548
typedef enum SVGA3dFrameUpdateType {
1994
-
SVGA3D_FRAME_END = 0,
1995
-
SVGA3D_FRAME_PARTIAL = 1,
1996
-
SVGA3D_FRAME_UNKNOWN = 2,
1997
-
SVGA3D_FRAME_MAX = 3,
1549
+
SVGA3D_FRAME_END = 0,
1550
+
SVGA3D_FRAME_MIN = 0,
1551
+
SVGA3D_FRAME_PARTIAL = 1,
1552
+
SVGA3D_FRAME_UNKNOWN = 2,
1553
+
SVGA3D_FRAME_MAX = 3,
1998
1554
} SVGA3dFrameUpdateType;
1999
1555
2000
-
#endif /* _SVGA3D_TYPES_H_ */
1556
+
#endif
+17
-51
drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
+17
-51
drivers/gpu/drm/vmwgfx/device_include/svga_escape.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 2007-2015 VMware, Inc.
2
+
* Copyright 2007,2020 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
30
30
* Definitions for our own (vendor-specific) SVGA Escape commands.
31
31
*/
32
32
33
+
34
+
33
35
#ifndef _SVGA_ESCAPE_H_
34
36
#define _SVGA_ESCAPE_H_
35
37
36
-
37
-
/*
38
-
* Namespace IDs for the escape command
39
-
*/
40
-
41
38
#define SVGA_ESCAPE_NSID_VMWARE 0x00000000
42
-
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
39
+
#define SVGA_ESCAPE_NSID_DEVEL 0xFFFFFFFF
43
40
41
+
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
44
42
45
-
/*
46
-
* Within SVGA_ESCAPE_NSID_VMWARE, we multiplex commands according to
47
-
* the first DWORD of escape data (after the nsID and size). As a
48
-
* guideline we're using the high word and low word as a major and
49
-
* minor command number, respectively.
50
-
*
51
-
* Major command number allocation:
52
-
*
53
-
* 0000: Reserved
54
-
* 0001: SVGA_ESCAPE_VMWARE_LOG (svga_binary_logger.h)
55
-
* 0002: SVGA_ESCAPE_VMWARE_VIDEO (svga_overlay.h)
56
-
* 0003: SVGA_ESCAPE_VMWARE_HINT (svga_escape.h)
57
-
*/
43
+
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
44
+
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001
58
45
59
-
#define SVGA_ESCAPE_VMWARE_MAJOR_MASK 0xFFFF0000
60
-
61
-
62
-
/*
63
-
* SVGA Hint commands.
64
-
*
65
-
* These escapes let the SVGA driver provide optional information to
66
-
* he host about the state of the guest or guest applications. The
67
-
* host can use these hints to make user interface or performance
68
-
* decisions.
69
-
*
70
-
* Notes:
71
-
*
72
-
* - SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN is deprecated for guests
73
-
* that use the SVGA Screen Object extension. Instead of sending
74
-
* this escape, use the SVGA_SCREEN_FULLSCREEN_HINT flag on your
75
-
* Screen Object.
76
-
*/
77
-
78
-
#define SVGA_ESCAPE_VMWARE_HINT 0x00030000
79
-
#define SVGA_ESCAPE_VMWARE_HINT_FULLSCREEN 0x00030001 /* Deprecated */
80
-
81
-
typedef
82
-
struct {
83
-
uint32 command;
84
-
uint32 fullscreen;
85
-
struct {
86
-
int32 x, y;
87
-
} monitorPosition;
46
+
#pragma pack(push, 1)
47
+
typedef struct {
48
+
uint32 command;
49
+
uint32 fullscreen;
50
+
struct {
51
+
int32 x, y;
52
+
} monitorPosition;
88
53
} SVGAEscapeHintFullscreen;
54
+
#pragma pack(pop)
89
55
90
-
#endif /* _SVGA_ESCAPE_H_ */
56
+
#endif
+58
-141
drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
+58
-141
drivers/gpu/drm/vmwgfx/device_include/svga_overlay.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
-
* Copyright 2007-2015 VMware, Inc.
2
+
* Copyright 2007-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
30
30
* Definitions for video-overlay support.
31
31
*/
32
32
33
+
34
+
33
35
#ifndef _SVGA_OVERLAY_H_
34
36
#define _SVGA_OVERLAY_H_
35
37
36
38
#include "svga_reg.h"
37
39
38
-
/*
39
-
* Video formats we support
40
-
*/
40
+
#if defined __cplusplus
41
+
extern "C" {
42
+
#endif
41
43
42
-
#define VMWARE_FOURCC_YV12 0x32315659 /* 'Y' 'V' '1' '2' */
43
-
#define VMWARE_FOURCC_YUY2 0x32595559 /* 'Y' 'U' 'Y' '2' */
44
-
#define VMWARE_FOURCC_UYVY 0x59565955 /* 'U' 'Y' 'V' 'Y' */
44
+
#define VMWARE_FOURCC_YV12 0x32315659
45
+
#define VMWARE_FOURCC_YUY2 0x32595559
46
+
#define VMWARE_FOURCC_UYVY 0x59565955
45
47
46
48
typedef enum {
47
-
SVGA_OVERLAY_FORMAT_INVALID = 0,
48
-
SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
49
-
SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
50
-
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
49
+
SVGA_OVERLAY_FORMAT_INVALID = 0,
50
+
SVGA_OVERLAY_FORMAT_YV12 = VMWARE_FOURCC_YV12,
51
+
SVGA_OVERLAY_FORMAT_YUY2 = VMWARE_FOURCC_YUY2,
52
+
SVGA_OVERLAY_FORMAT_UYVY = VMWARE_FOURCC_UYVY,
51
53
} SVGAOverlayFormat;
52
54
53
-
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
55
+
#define SVGA_VIDEO_COLORKEY_MASK 0x00ffffff
54
56
55
-
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
57
+
#define SVGA_ESCAPE_VMWARE_VIDEO 0x00020000
56
58
57
-
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
58
-
/* FIFO escape layout:
59
-
* Type, Stream Id, (Register Id, Value) pairs */
59
+
#define SVGA_ESCAPE_VMWARE_VIDEO_SET_REGS 0x00020001
60
60
61
-
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
62
-
/* FIFO escape layout:
63
-
* Type, Stream Id */
61
+
#define SVGA_ESCAPE_VMWARE_VIDEO_FLUSH 0x00020002
64
62
65
-
typedef
66
-
struct SVGAEscapeVideoSetRegs {
67
-
struct {
68
-
uint32 cmdType;
69
-
uint32 streamId;
70
-
} header;
63
+
typedef struct SVGAEscapeVideoSetRegs {
64
+
struct {
65
+
uint32 cmdType;
66
+
uint32 streamId;
67
+
} header;
71
68
72
-
/* May include zero or more items. */
73
-
struct {
74
-
uint32 registerId;
75
-
uint32 value;
76
-
} items[1];
69
+
struct {
70
+
uint32 registerId;
71
+
uint32 value;
72
+
} items[1];
77
73
} SVGAEscapeVideoSetRegs;
78
74
79
-
typedef
80
-
struct SVGAEscapeVideoFlush {
81
-
uint32 cmdType;
82
-
uint32 streamId;
75
+
typedef struct SVGAEscapeVideoFlush {
76
+
uint32 cmdType;
77
+
uint32 streamId;
83
78
} SVGAEscapeVideoFlush;
84
79
85
-
86
-
/*
87
-
* Struct definitions for the video overlay commands built on
88
-
* SVGAFifoCmdEscape.
89
-
*/
90
-
typedef
91
-
struct {
92
-
uint32 command;
93
-
uint32 overlay;
80
+
#pragma pack(push, 1)
81
+
typedef struct {
82
+
uint32 command;
83
+
uint32 overlay;
94
84
} SVGAFifoEscapeCmdVideoBase;
85
+
#pragma pack(pop)
95
86
96
-
typedef
97
-
struct {
98
-
SVGAFifoEscapeCmdVideoBase videoCmd;
87
+
#pragma pack(push, 1)
88
+
typedef struct {
89
+
SVGAFifoEscapeCmdVideoBase videoCmd;
99
90
} SVGAFifoEscapeCmdVideoFlush;
91
+
#pragma pack(pop)
100
92
101
-
typedef
102
-
struct {
103
-
SVGAFifoEscapeCmdVideoBase videoCmd;
104
-
struct {
105
-
uint32 regId;
106
-
uint32 value;
107
-
} items[1];
93
+
#pragma pack(push, 1)
94
+
typedef struct {
95
+
SVGAFifoEscapeCmdVideoBase videoCmd;
96
+
struct {
97
+
uint32 regId;
98
+
uint32 value;
99
+
} items[1];
108
100
} SVGAFifoEscapeCmdVideoSetRegs;
101
+
#pragma pack(pop)
109
102
110
-
typedef
111
-
struct {
112
-
SVGAFifoEscapeCmdVideoBase videoCmd;
113
-
struct {
114
-
uint32 regId;
115
-
uint32 value;
116
-
} items[SVGA_VIDEO_NUM_REGS];
103
+
#pragma pack(push, 1)
104
+
typedef struct {
105
+
SVGAFifoEscapeCmdVideoBase videoCmd;
106
+
struct {
107
+
uint32 regId;
108
+
uint32 value;
109
+
} items[SVGA_VIDEO_NUM_REGS];
117
110
} SVGAFifoEscapeCmdVideoSetAllRegs;
111
+
#pragma pack(pop)
118
112
119
-
120
-
/*
121
-
*----------------------------------------------------------------------
122
-
*
123
-
* VMwareVideoGetAttributes --
124
-
*
125
-
* Computes the size, pitches and offsets for YUV frames.
126
-
*
127
-
* Results:
128
-
* TRUE on success; otherwise FALSE on failure.
129
-
*
130
-
* Side effects:
131
-
* Pitches and offsets for the given YUV frame are put in 'pitches'
132
-
* and 'offsets' respectively. They are both optional though.
133
-
*
134
-
*----------------------------------------------------------------------
135
-
*/
136
-
137
-
static inline bool
138
-
VMwareVideoGetAttributes(const SVGAOverlayFormat format, /* IN */
139
-
uint32 *width, /* IN / OUT */
140
-
uint32 *height, /* IN / OUT */
141
-
uint32 *size, /* OUT */
142
-
uint32 *pitches, /* OUT (optional) */
143
-
uint32 *offsets) /* OUT (optional) */
144
-
{
145
-
int tmp;
146
-
147
-
*width = (*width + 1) & ~1;
148
-
149
-
if (offsets) {
150
-
offsets[0] = 0;
151
-
}
152
-
153
-
switch (format) {
154
-
case VMWARE_FOURCC_YV12:
155
-
*height = (*height + 1) & ~1;
156
-
*size = (*width) * (*height);
157
-
158
-
if (pitches) {
159
-
pitches[0] = *width;
160
-
}
161
-
162
-
if (offsets) {
163
-
offsets[1] = *size;
164
-
}
165
-
166
-
tmp = *width >> 1;
167
-
168
-
if (pitches) {
169
-
pitches[1] = pitches[2] = tmp;
170
-
}
171
-
172
-
tmp *= (*height >> 1);
173
-
*size += tmp;
174
-
175
-
if (offsets) {
176
-
offsets[2] = *size;
177
-
}
178
-
179
-
*size += tmp;
180
-
break;
181
-
182
-
case VMWARE_FOURCC_YUY2:
183
-
case VMWARE_FOURCC_UYVY:
184
-
*size = *width * 2;
185
-
186
-
if (pitches) {
187
-
pitches[0] = *size;
188
-
}
189
-
190
-
*size *= *height;
191
-
break;
192
-
193
-
default:
194
-
return false;
195
-
}
196
-
197
-
return true;
113
+
#if defined __cplusplus
198
114
}
115
+
#endif
199
116
200
-
#endif /* _SVGA_OVERLAY_H_ */
117
+
#endif
+654
-2061
drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
+654
-2061
drivers/gpu/drm/vmwgfx/device_include/svga_reg.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
1
/**********************************************************
3
2
* Copyright 1998-2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
30
30
* Virtual hardware definitions for the VMware SVGA II device.
31
31
*/
32
32
33
+
34
+
33
35
#ifndef _SVGA_REG_H_
34
36
#define _SVGA_REG_H_
35
-
#include <linux/pci_ids.h>
36
37
37
-
#define INCLUDE_ALLOW_MODULE
38
-
#define INCLUDE_ALLOW_USERLEVEL
38
+
#include "vm_basic_types.h"
39
39
40
-
#define INCLUDE_ALLOW_VMCORE
41
-
#include "includeCheck.h"
42
-
43
-
#include "svga_types.h"
44
-
45
-
/*
46
-
* SVGA_REG_ENABLE bit definitions.
47
-
*/
48
40
typedef enum {
49
-
SVGA_REG_ENABLE_DISABLE = 0,
50
-
SVGA_REG_ENABLE_ENABLE = (1 << 0),
51
-
SVGA_REG_ENABLE_HIDE = (1 << 1),
41
+
SVGA_REG_ENABLE_DISABLE = 0,
42
+
SVGA_REG_ENABLE_ENABLE = (1 << 0),
43
+
SVGA_REG_ENABLE_HIDE = (1 << 1),
52
44
} SvgaRegEnable;
53
45
54
46
typedef uint32 SVGAMobId;
55
47
56
-
/*
57
-
* Arbitrary and meaningless limits. Please ignore these when writing
58
-
* new drivers.
59
-
*/
60
-
#define SVGA_MAX_WIDTH 2560
61
-
#define SVGA_MAX_HEIGHT 1600
48
+
#define SVGA_MAX_WIDTH 2560
49
+
#define SVGA_MAX_HEIGHT 1600
62
50
63
-
64
-
#define SVGA_MAX_BITS_PER_PIXEL 32
65
-
#define SVGA_MAX_DEPTH 24
66
-
#define SVGA_MAX_DISPLAYS 10
67
-
#define SVGA_MAX_SCREEN_SIZE 8192
51
+
#define SVGA_MAX_BITS_PER_PIXEL 32
52
+
#define SVGA_MAX_DEPTH 24
53
+
#define SVGA_MAX_DISPLAYS 10
54
+
#define SVGA_MAX_SCREEN_SIZE 8192
68
55
#define SVGA_SCREEN_ROOT_LIMIT (SVGA_MAX_SCREEN_SIZE * SVGA_MAX_DISPLAYS)
69
56
57
+
#define SVGA_CURSOR_ON_HIDE 0x0
58
+
#define SVGA_CURSOR_ON_SHOW 0x1
70
59
71
-
/*
72
-
* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
73
-
* cursor bypass mode.
74
-
*/
75
-
#define SVGA_CURSOR_ON_HIDE 0x0
76
-
#define SVGA_CURSOR_ON_SHOW 0x1
60
+
#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
77
61
78
-
/*
79
-
* Remove the cursor from the framebuffer
80
-
* because we need to see what's under it
81
-
*/
82
-
#define SVGA_CURSOR_ON_REMOVE_FROM_FB 0x2
62
+
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
83
63
84
-
/* Put the cursor back in the framebuffer so the user can see it */
85
-
#define SVGA_CURSOR_ON_RESTORE_TO_FB 0x3
64
+
#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
86
65
87
-
/*
88
-
* The maximum framebuffer size that can traced for guests unless the
89
-
* SVGA_CAP_GBOBJECTS is set in SVGA_REG_CAPABILITIES. In that case
90
-
* the full framebuffer can be traced independent of this limit.
91
-
*/
92
-
#define SVGA_FB_MAX_TRACEABLE_SIZE 0x1000000
66
+
#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
67
+
#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
68
+
#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
93
69
94
-
#define SVGA_MAX_PSEUDOCOLOR_DEPTH 8
95
-
#define SVGA_MAX_PSEUDOCOLORS (1 << SVGA_MAX_PSEUDOCOLOR_DEPTH)
96
-
#define SVGA_NUM_PALETTE_REGS (3 * SVGA_MAX_PSEUDOCOLORS)
70
+
#define SVGA_MAGIC 0x900000UL
71
+
#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
97
72
98
-
#define SVGA_MAGIC 0x900000UL
99
-
#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
73
+
#define SVGA_VERSION_3 3
74
+
#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3)
100
75
101
-
/* Version 3 has the control bar instead of the FIFO */
102
-
#define SVGA_VERSION_3 3
103
-
#define SVGA_ID_3 SVGA_MAKE_ID(SVGA_VERSION_3)
76
+
#define SVGA_VERSION_2 2
77
+
#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
104
78
105
-
/* Version 2 let the address of the frame buffer be unsigned on Win32 */
106
-
#define SVGA_VERSION_2 2
107
-
#define SVGA_ID_2 SVGA_MAKE_ID(SVGA_VERSION_2)
79
+
#define SVGA_VERSION_1 1
80
+
#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
108
81
109
-
/* Version 1 has new registers starting with SVGA_REG_CAPABILITIES so
110
-
PALETTE_BASE has moved */
111
-
#define SVGA_VERSION_1 1
112
-
#define SVGA_ID_1 SVGA_MAKE_ID(SVGA_VERSION_1)
82
+
#define SVGA_VERSION_0 0
83
+
#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
113
84
114
-
/* Version 0 is the initial version */
115
-
#define SVGA_VERSION_0 0
116
-
#define SVGA_ID_0 SVGA_MAKE_ID(SVGA_VERSION_0)
85
+
#define SVGA_ID_INVALID 0xFFFFFFFF
117
86
118
-
/*
119
-
* "Invalid" value for all SVGA IDs.
120
-
* (Version ID, screen object ID, surface ID...)
121
-
*/
122
-
#define SVGA_ID_INVALID 0xFFFFFFFF
87
+
#define SVGA_INDEX_PORT 0x0
88
+
#define SVGA_VALUE_PORT 0x1
89
+
#define SVGA_BIOS_PORT 0x2
90
+
#define SVGA_IRQSTATUS_PORT 0x8
123
91
124
-
/* Port offsets, relative to BAR0 */
125
-
#define SVGA_INDEX_PORT 0x0
126
-
#define SVGA_VALUE_PORT 0x1
127
-
#define SVGA_BIOS_PORT 0x2
128
-
#define SVGA_IRQSTATUS_PORT 0x8
92
+
#define SVGA_IRQFLAG_ANY_FENCE (1 << 0)
93
+
#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1)
94
+
#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2)
95
+
#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3)
96
+
#define SVGA_IRQFLAG_ERROR (1 << 4)
97
+
#define SVGA_IRQFLAG_REG_FENCE_GOAL (1 << 5)
98
+
#define SVGA_IRQFLAG_MAX (1 << 6)
129
99
130
-
/*
131
-
* Interrupt source flags for IRQSTATUS_PORT and IRQMASK.
132
-
*
133
-
* Interrupts are only supported when the
134
-
* SVGA_CAP_IRQMASK capability is present.
135
-
*/
136
-
#define SVGA_IRQFLAG_ANY_FENCE (1 << 0) /* Any fence was passed */
137
-
#define SVGA_IRQFLAG_FIFO_PROGRESS (1 << 1) /* Made forward progress in the FIFO */
138
-
#define SVGA_IRQFLAG_FENCE_GOAL (1 << 2) /* SVGA_FIFO_FENCE_GOAL reached */
139
-
#define SVGA_IRQFLAG_COMMAND_BUFFER (1 << 3) /* Command buffer completed */
140
-
#define SVGA_IRQFLAG_ERROR (1 << 4) /* Error while processing commands */
141
-
#define SVGA_IRQFLAG_MAX (1 << 5)
142
-
143
-
/*
144
-
* The byte-size is the size of the actual cursor data,
145
-
* possibly after expanding it to the current bit depth.
146
-
*
147
-
* 40K is sufficient memory for two 32-bit planes for a 64 x 64 cursor.
148
-
*
149
-
* The dimension limit is a bound on the maximum width or height.
150
-
*/
151
-
#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
100
+
#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
152
101
#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024
153
102
154
-
/*
155
-
* Registers
156
-
*/
157
-
158
103
enum {
159
-
SVGA_REG_ID = 0,
160
-
SVGA_REG_ENABLE = 1,
161
-
SVGA_REG_WIDTH = 2,
162
-
SVGA_REG_HEIGHT = 3,
163
-
SVGA_REG_MAX_WIDTH = 4,
164
-
SVGA_REG_MAX_HEIGHT = 5,
165
-
SVGA_REG_DEPTH = 6,
166
-
SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
167
-
SVGA_REG_PSEUDOCOLOR = 8,
168
-
SVGA_REG_RED_MASK = 9,
169
-
SVGA_REG_GREEN_MASK = 10,
170
-
SVGA_REG_BLUE_MASK = 11,
171
-
SVGA_REG_BYTES_PER_LINE = 12,
172
-
SVGA_REG_FB_START = 13, /* (Deprecated) */
173
-
SVGA_REG_FB_OFFSET = 14,
174
-
SVGA_REG_VRAM_SIZE = 15,
175
-
SVGA_REG_FB_SIZE = 16,
104
+
SVGA_REG_ID = 0,
105
+
SVGA_REG_ENABLE = 1,
106
+
SVGA_REG_WIDTH = 2,
107
+
SVGA_REG_HEIGHT = 3,
108
+
SVGA_REG_MAX_WIDTH = 4,
109
+
SVGA_REG_MAX_HEIGHT = 5,
110
+
SVGA_REG_DEPTH = 6,
111
+
SVGA_REG_BITS_PER_PIXEL = 7,
112
+
SVGA_REG_PSEUDOCOLOR = 8,
113
+
SVGA_REG_RED_MASK = 9,
114
+
SVGA_REG_GREEN_MASK = 10,
115
+
SVGA_REG_BLUE_MASK = 11,
116
+
SVGA_REG_BYTES_PER_LINE = 12,
117
+
SVGA_REG_FB_START = 13,
118
+
SVGA_REG_FB_OFFSET = 14,
119
+
SVGA_REG_VRAM_SIZE = 15,
120
+
SVGA_REG_FB_SIZE = 16,
176
121
177
-
/* ID 0 implementation only had the above registers, then the palette */
178
-
SVGA_REG_ID_0_TOP = 17,
122
+
SVGA_REG_ID_0_TOP = 17,
179
123
180
-
SVGA_REG_CAPABILITIES = 17,
181
-
SVGA_REG_MEM_START = 18, /* (Deprecated) */
182
-
SVGA_REG_MEM_SIZE = 19,
183
-
SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
184
-
SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
185
-
SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
186
-
SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
187
-
SVGA_REG_DEAD = 24, /* Drivers should never write this. */
188
-
SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
189
-
SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
190
-
SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
191
-
SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* (Deprecated) */
192
-
SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
193
-
SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
194
-
SVGA_REG_NUM_DISPLAYS = 31, /* (Deprecated) */
195
-
SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
196
-
SVGA_REG_IRQMASK = 33, /* Interrupt mask */
124
+
SVGA_REG_CAPABILITIES = 17,
125
+
SVGA_REG_MEM_START = 18,
126
+
SVGA_REG_MEM_SIZE = 19,
127
+
SVGA_REG_CONFIG_DONE = 20,
128
+
SVGA_REG_SYNC = 21,
129
+
SVGA_REG_BUSY = 22,
130
+
SVGA_REG_GUEST_ID = 23,
131
+
SVGA_REG_DEAD = 24,
132
+
SVGA_REG_CURSOR_X = 25,
133
+
SVGA_REG_CURSOR_Y = 26,
134
+
SVGA_REG_CURSOR_ON = 27,
135
+
SVGA_REG_HOST_BITS_PER_PIXEL = 28,
136
+
SVGA_REG_SCRATCH_SIZE = 29,
137
+
SVGA_REG_MEM_REGS = 30,
138
+
SVGA_REG_NUM_DISPLAYS = 31,
139
+
SVGA_REG_PITCHLOCK = 32,
140
+
SVGA_REG_IRQMASK = 33,
197
141
198
-
/* Legacy multi-monitor support */
199
-
SVGA_REG_NUM_GUEST_DISPLAYS = 34,/* Number of guest displays in X/Y direction */
200
-
SVGA_REG_DISPLAY_ID = 35, /* Display ID for the following display attributes */
201
-
SVGA_REG_DISPLAY_IS_PRIMARY = 36,/* Whether this is a primary display */
202
-
SVGA_REG_DISPLAY_POSITION_X = 37,/* The display position x */
203
-
SVGA_REG_DISPLAY_POSITION_Y = 38,/* The display position y */
204
-
SVGA_REG_DISPLAY_WIDTH = 39, /* The display's width */
205
-
SVGA_REG_DISPLAY_HEIGHT = 40, /* The display's height */
142
+
SVGA_REG_NUM_GUEST_DISPLAYS = 34,
143
+
SVGA_REG_DISPLAY_ID = 35,
144
+
SVGA_REG_DISPLAY_IS_PRIMARY = 36,
145
+
SVGA_REG_DISPLAY_POSITION_X = 37,
146
+
SVGA_REG_DISPLAY_POSITION_Y = 38,
147
+
SVGA_REG_DISPLAY_WIDTH = 39,
148
+
SVGA_REG_DISPLAY_HEIGHT = 40,
206
149
207
-
/* See "Guest memory regions" below. */
208
-
SVGA_REG_GMR_ID = 41,
209
-
SVGA_REG_GMR_DESCRIPTOR = 42,
210
-
SVGA_REG_GMR_MAX_IDS = 43,
211
-
SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
150
+
SVGA_REG_GMR_ID = 41,
151
+
SVGA_REG_GMR_DESCRIPTOR = 42,
152
+
SVGA_REG_GMR_MAX_IDS = 43,
153
+
SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH = 44,
212
154
213
-
SVGA_REG_TRACES = 45, /* Enable trace-based updates even when FIFO is on */
214
-
SVGA_REG_GMRS_MAX_PAGES = 46, /* Maximum number of 4KB pages for all GMRs */
215
-
SVGA_REG_MEMORY_SIZE = 47, /* Total dedicated device memory excluding FIFO */
216
-
SVGA_REG_COMMAND_LOW = 48, /* Lower 32 bits and submits commands */
217
-
SVGA_REG_COMMAND_HIGH = 49, /* Upper 32 bits of command buffer PA */
155
+
SVGA_REG_TRACES = 45,
156
+
SVGA_REG_GMRS_MAX_PAGES = 46,
157
+
SVGA_REG_MEMORY_SIZE = 47,
158
+
SVGA_REG_COMMAND_LOW = 48,
159
+
SVGA_REG_COMMAND_HIGH = 49,
218
160
219
-
/*
220
-
* Max primary memory.
221
-
* See SVGA_CAP_NO_BB_RESTRICTION.
222
-
*/
223
-
SVGA_REG_MAX_PRIMARY_MEM = 50,
224
-
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
161
+
SVGA_REG_MAX_PRIMARY_MEM = 50,
225
162
226
-
/*
227
-
* Legacy version of SVGA_REG_GBOBJECT_MEM_SIZE_KB for drivers that
228
-
* don't know how to convert to a 64-bit byte value without overflowing.
229
-
* (See SVGA_REG_GBOBJECT_MEM_SIZE_KB).
230
-
*/
231
-
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
163
+
SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
232
164
233
-
SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
234
-
SVGA_REG_CMD_PREPEND_LOW = 53,
235
-
SVGA_REG_CMD_PREPEND_HIGH = 54,
236
-
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
237
-
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
238
-
SVGA_REG_MOB_MAX_SIZE = 57,
239
-
SVGA_REG_BLANK_SCREEN_TARGETS = 58,
240
-
SVGA_REG_CAP2 = 59,
241
-
SVGA_REG_DEVEL_CAP = 60,
165
+
SVGA_REG_DEV_CAP = 52,
166
+
SVGA_REG_CMD_PREPEND_LOW = 53,
167
+
SVGA_REG_CMD_PREPEND_HIGH = 54,
168
+
SVGA_REG_SCREENTARGET_MAX_WIDTH = 55,
169
+
SVGA_REG_SCREENTARGET_MAX_HEIGHT = 56,
170
+
SVGA_REG_MOB_MAX_SIZE = 57,
171
+
SVGA_REG_BLANK_SCREEN_TARGETS = 58,
172
+
SVGA_REG_CAP2 = 59,
173
+
SVGA_REG_DEVEL_CAP = 60,
242
174
243
-
/*
244
-
* Allow the guest to hint to the device which driver is running.
245
-
*
246
-
* This should not generally change device behavior, but might be
247
-
* convenient to work-around specific bugs in guest drivers.
248
-
*
249
-
* Drivers should first write their id value into SVGA_REG_GUEST_DRIVER_ID,
250
-
* and then fill out all of the version registers that they have defined.
251
-
*
252
-
* After the driver has written all of the registers, they should
253
-
* then write the value SVGA_REG_GUEST_DRIVER_ID_SUBMIT to the
254
-
* SVGA_REG_GUEST_DRIVER_ID register, to signal that they have finished.
255
-
*
256
-
* The SVGA_REG_GUEST_DRIVER_ID values are defined below by the
257
-
* SVGARegGuestDriverId enum.
258
-
*
259
-
* The SVGA_REG_GUEST_DRIVER_VERSION fields are driver-specific,
260
-
* but ideally should encode a monotonically increasing number that allows
261
-
* the device to perform inequality checks against ranges of driver versions.
262
-
*/
263
-
SVGA_REG_GUEST_DRIVER_ID = 61,
264
-
SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
265
-
SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
266
-
SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
267
-
SVGA_REG_CURSOR_MOBID = 65,
268
-
SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
269
-
SVGA_REG_CURSOR_MAX_DIMENSION = 67,
175
+
SVGA_REG_GUEST_DRIVER_ID = 61,
176
+
SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
177
+
SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
178
+
SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
270
179
271
-
SVGA_REG_FIFO_CAPS = 68,
272
-
SVGA_REG_FENCE = 69,
180
+
SVGA_REG_CURSOR_MOBID = 65,
181
+
SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
182
+
SVGA_REG_CURSOR_MAX_DIMENSION = 67,
273
183
274
-
SVGA_REG_RESERVED1 = 70,
275
-
SVGA_REG_RESERVED2 = 71,
276
-
SVGA_REG_RESERVED3 = 72,
277
-
SVGA_REG_RESERVED4 = 73,
278
-
SVGA_REG_RESERVED5 = 74,
279
-
SVGA_REG_SCREENDMA = 75,
184
+
SVGA_REG_FIFO_CAPS = 68,
185
+
SVGA_REG_FENCE = 69,
280
186
281
-
/*
282
-
* The maximum amount of guest-backed objects that the device can have
283
-
* resident at a time. Guest-drivers should keep their working set size
284
-
* below this limit for best performance.
285
-
*
286
-
* Note that this value is in kilobytes, and not bytes, because the actual
287
-
* number of bytes might be larger than can fit in a 32-bit register.
288
-
*
289
-
* PLEASE USE A 64-BIT VALUE WHEN CONVERTING THIS INTO BYTES.
290
-
* (See SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB).
291
-
*/
292
-
SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
187
+
SVGA_REG_CURSOR4_ON = 70,
188
+
SVGA_REG_CURSOR4_X = 71,
189
+
SVGA_REG_CURSOR4_Y = 72,
190
+
SVGA_REG_CURSOR4_SCREEN_ID = 73,
191
+
SVGA_REG_CURSOR4_SUBMIT = 74,
293
192
294
-
/*
295
-
+ * These registers are for the addresses of the memory BARs for SVGA3
296
-
*/
297
-
SVGA_REG_REGS_START_HIGH32 = 77,
298
-
SVGA_REG_REGS_START_LOW32 = 78,
299
-
SVGA_REG_FB_START_HIGH32 = 79,
300
-
SVGA_REG_FB_START_LOW32 = 80,
193
+
SVGA_REG_SCREENDMA = 75,
301
194
302
-
/*
303
-
* A hint register that recommends which quality level the guest should
304
-
* currently use to define multisample surfaces.
305
-
*
306
-
* If the register is SVGA_REG_MSHINT_DISABLED,
307
-
* the guest is only allowed to use SVGA3D_MS_QUALITY_FULL.
308
-
*
309
-
* Otherwise, this is a live value that can change while the VM is
310
-
* powered on with the hint suggestion for which quality level the guest
311
-
* should be using. Guests are free to ignore the hint and use either
312
-
* RESOLVE or FULL quality.
313
-
*/
314
-
SVGA_REG_MSHINT = 81,
195
+
SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
315
196
316
-
SVGA_REG_IRQ_STATUS = 82,
317
-
SVGA_REG_DIRTY_TRACKING = 83,
197
+
SVGA_REG_REGS_START_HIGH32 = 77,
198
+
SVGA_REG_REGS_START_LOW32 = 78,
199
+
SVGA_REG_FB_START_HIGH32 = 79,
200
+
SVGA_REG_FB_START_LOW32 = 80,
318
201
319
-
SVGA_REG_TOP = 84, /* Must be 1 more than the last register */
202
+
SVGA_REG_MSHINT = 81,
320
203
321
-
SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
322
-
/* Next 768 (== 256*3) registers exist for colormap */
323
-
SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
324
-
/* Base of scratch registers */
325
-
/* Next reg[SVGA_REG_SCRATCH_SIZE] registers exist for scratch usage:
326
-
First 4 are reserved for VESA BIOS Extension; any remaining are for
327
-
the use of the current SVGA driver. */
204
+
SVGA_REG_IRQ_STATUS = 82,
205
+
206
+
SVGA_REG_DIRTY_TRACKING = 83,
207
+
SVGA_REG_FENCE_GOAL = 84,
208
+
209
+
SVGA_REG_TOP = 85,
210
+
211
+
SVGA_PALETTE_BASE = 1024,
212
+
213
+
SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + SVGA_NUM_PALETTE_REGS
214
+
328
215
};
329
216
330
-
331
-
/*
332
-
* Values for SVGA_REG_GUEST_DRIVER_ID.
333
-
*/
334
217
typedef enum SVGARegGuestDriverId {
335
-
SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
336
-
SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
337
-
SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
338
-
SVGA_REG_GUEST_DRIVER_ID_MAX,
218
+
SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
219
+
SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
220
+
SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
221
+
SVGA_REG_GUEST_DRIVER_ID_MAX,
339
222
340
-
SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
223
+
SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
341
224
} SVGARegGuestDriverId;
342
225
343
226
typedef enum SVGARegMSHint {
344
-
SVGA_REG_MSHINT_DISABLED = 0,
345
-
SVGA_REG_MSHINT_FULL = 1,
346
-
SVGA_REG_MSHINT_RESOLVED = 2,
227
+
SVGA_REG_MSHINT_DISABLED = 0,
228
+
SVGA_REG_MSHINT_FULL = 1,
229
+
SVGA_REG_MSHINT_RESOLVED = 2,
347
230
} SVGARegMSHint;
348
231
349
232
typedef enum SVGARegDirtyTracking {
350
-
SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0,
351
-
SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1,
233
+
SVGA_REG_DIRTY_TRACKING_PER_IMAGE = 0,
234
+
SVGA_REG_DIRTY_TRACKING_PER_SURFACE = 1,
352
235
} SVGARegDirtyTracking;
353
236
237
+
#define SVGA_GMR_NULL ((uint32)-1)
238
+
#define SVGA_GMR_FRAMEBUFFER ((uint32)-2)
354
239
355
-
/*
356
-
* Guest memory regions (GMRs):
357
-
*
358
-
* This is a new memory mapping feature available in SVGA devices
359
-
* which have the SVGA_CAP_GMR bit set. Previously, there were two
360
-
* fixed memory regions available with which to share data between the
361
-
* device and the driver: the FIFO ('MEM') and the framebuffer. GMRs
362
-
* are our name for an extensible way of providing arbitrary DMA
363
-
* buffers for use between the driver and the SVGA device. They are a
364
-
* new alternative to framebuffer memory, usable for both 2D and 3D
365
-
* graphics operations.
366
-
*
367
-
* Since GMR mapping must be done synchronously with guest CPU
368
-
* execution, we use a new pair of SVGA registers:
369
-
*
370
-
* SVGA_REG_GMR_ID --
371
-
*
372
-
* Read/write.
373
-
* This register holds the 32-bit ID (a small positive integer)
374
-
* of a GMR to create, delete, or redefine. Writing this register
375
-
* has no side-effects.
376
-
*
377
-
* SVGA_REG_GMR_DESCRIPTOR --
378
-
*
379
-
* Write-only.
380
-
* Writing this register will create, delete, or redefine the GMR
381
-
* specified by the above ID register. If this register is zero,
382
-
* the GMR is deleted. Any pointers into this GMR (including those
383
-
* currently being processed by FIFO commands) will be
384
-
* synchronously invalidated.
385
-
*
386
-
* If this register is nonzero, it must be the physical page
387
-
* number (PPN) of a data structure which describes the physical
388
-
* layout of the memory region this GMR should describe. The
389
-
* descriptor structure will be read synchronously by the SVGA
390
-
* device when this register is written. The descriptor need not
391
-
* remain allocated for the lifetime of the GMR.
392
-
*
393
-
* The guest driver should write SVGA_REG_GMR_ID first, then
394
-
* SVGA_REG_GMR_DESCRIPTOR.
395
-
*
396
-
* SVGA_REG_GMR_MAX_IDS --
397
-
*
398
-
* Read-only.
399
-
* The SVGA device may choose to support a maximum number of
400
-
* user-defined GMR IDs. This register holds the number of supported
401
-
* IDs. (The maximum supported ID plus 1)
402
-
*
403
-
* SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH --
404
-
*
405
-
* Read-only.
406
-
* The SVGA device may choose to put a limit on the total number
407
-
* of SVGAGuestMemDescriptor structures it will read when defining
408
-
* a single GMR.
409
-
*
410
-
* The descriptor structure is an array of SVGAGuestMemDescriptor
411
-
* structures. Each structure may do one of three things:
412
-
*
413
-
* - Terminate the GMR descriptor list.
414
-
* (ppn==0, numPages==0)
415
-
*
416
-
* - Add a PPN or range of PPNs to the GMR's virtual address space.
417
-
* (ppn != 0, numPages != 0)
418
-
*
419
-
* - Provide the PPN of the next SVGAGuestMemDescriptor, in order to
420
-
* support multi-page GMR descriptor tables without forcing the
421
-
* driver to allocate physically contiguous memory.
422
-
* (ppn != 0, numPages == 0)
423
-
*
424
-
* Note that each physical page of SVGAGuestMemDescriptor structures
425
-
* can describe at least 2MB of guest memory. If the driver needs to
426
-
* use more than one page of descriptor structures, it must use one of
427
-
* its SVGAGuestMemDescriptors to point to an additional page. The
428
-
* device will never automatically cross a page boundary.
429
-
*
430
-
* Once the driver has described a GMR, it is immediately available
431
-
* for use via any FIFO command that uses an SVGAGuestPtr structure.
432
-
* These pointers include a GMR identifier plus an offset into that
433
-
* GMR.
434
-
*
435
-
* The driver must check the SVGA_CAP_GMR bit before using the GMR
436
-
* registers.
437
-
*/
240
+
#pragma pack(push, 1)
241
+
typedef struct SVGAGuestMemDescriptor {
242
+
uint32 ppn;
243
+
uint32 numPages;
244
+
} SVGAGuestMemDescriptor;
245
+
#pragma pack(pop)
438
246
439
-
/*
440
-
* Special GMR IDs, allowing SVGAGuestPtrs to point to framebuffer
441
-
* memory as well. In the future, these IDs could even be used to
442
-
* allow legacy memory regions to be redefined by the guest as GMRs.
443
-
*
444
-
* Using the guest framebuffer (GFB) at BAR1 for general purpose DMA
445
-
* is being phased out. Please try to use user-defined GMRs whenever
446
-
* possible.
447
-
*/
448
-
#define SVGA_GMR_NULL ((uint32) -1)
449
-
#define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
247
+
#pragma pack(push, 1)
248
+
typedef struct SVGAGuestPtr {
249
+
uint32 gmrId;
250
+
uint32 offset;
251
+
} SVGAGuestPtr;
252
+
#pragma pack(pop)
450
253
451
-
typedef
452
-
#include "vmware_pack_begin.h"
453
-
struct SVGAGuestMemDescriptor {
454
-
uint32 ppn;
455
-
uint32 numPages;
456
-
}
457
-
#include "vmware_pack_end.h"
458
-
SVGAGuestMemDescriptor;
459
-
460
-
typedef
461
-
#include "vmware_pack_begin.h"
462
-
struct SVGAGuestPtr {
463
-
uint32 gmrId;
464
-
uint32 offset;
465
-
}
466
-
#include "vmware_pack_end.h"
467
-
SVGAGuestPtr;
468
-
469
-
/*
470
-
* Register based command buffers --
471
-
*
472
-
* Provide an SVGA device interface that allows the guest to submit
473
-
* command buffers to the SVGA device through an SVGA device register.
474
-
* The metadata for each command buffer is contained in the
475
-
* SVGACBHeader structure along with the return status codes.
476
-
*
477
-
* The SVGA device supports command buffers if
478
-
* SVGA_CAP_COMMAND_BUFFERS is set in the device caps register. The
479
-
* fifo must be enabled for command buffers to be submitted.
480
-
*
481
-
* Command buffers are submitted when the guest writing the 64 byte
482
-
* aligned physical address into the SVGA_REG_COMMAND_LOW and
483
-
* SVGA_REG_COMMAND_HIGH. SVGA_REG_COMMAND_HIGH contains the upper 32
484
-
* bits of the physical address. SVGA_REG_COMMAND_LOW contains the
485
-
* lower 32 bits of the physical address, since the command buffer
486
-
* headers are required to be 64 byte aligned the lower 6 bits are
487
-
* used for the SVGACBContext value. Writing to SVGA_REG_COMMAND_LOW
488
-
* submits the command buffer to the device and queues it for
489
-
* execution. The SVGA device supports at least
490
-
* SVGA_CB_MAX_QUEUED_PER_CONTEXT command buffers that can be queued
491
-
* per context and if that limit is reached the device will write the
492
-
* status SVGA_CB_STATUS_QUEUE_FULL to the status value of the command
493
-
* buffer header synchronously and not raise any IRQs.
494
-
*
495
-
* It is invalid to submit a command buffer without a valid physical
496
-
* address and results are undefined.
497
-
*
498
-
* The device guarantees that command buffers of size SVGA_CB_MAX_SIZE
499
-
* will be supported. If a larger command buffer is submitted results
500
-
* are unspecified and the device will either complete the command
501
-
* buffer or return an error.
502
-
*
503
-
* The device guarantees that any individual command in a command
504
-
* buffer can be up to SVGA_CB_MAX_COMMAND_SIZE in size which is
505
-
* enough to fit a 64x64 color-cursor definition. If the command is
506
-
* too large the device is allowed to process the command or return an
507
-
* error.
508
-
*
509
-
* The device context is a special SVGACBContext that allows for
510
-
* synchronous register like accesses with the flexibility of
511
-
* commands. There is a different command set defined by
512
-
* SVGADeviceContextCmdId. The commands in each command buffer is not
513
-
* allowed to straddle physical pages.
514
-
*
515
-
* The offset field which is available starting with the
516
-
* SVGA_CAP_CMD_BUFFERS_2 cap bit can be set by the guest to bias the
517
-
* start of command processing into the buffer. If an error is
518
-
* encountered the errorOffset will still be relative to the specific
519
-
* PA, not biased by the offset. When the command buffer is finished
520
-
* the guest should not read the offset field as there is no guarantee
521
-
* what it will set to.
522
-
*
523
-
* When the SVGA_CAP_HP_CMD_QUEUE cap bit is set a new command queue
524
-
* SVGA_CB_CONTEXT_1 is available. Commands submitted to this queue
525
-
* will be executed as quickly as possible by the SVGA device
526
-
* potentially before already queued commands on SVGA_CB_CONTEXT_0.
527
-
* The SVGA device guarantees that any command buffers submitted to
528
-
* SVGA_CB_CONTEXT_0 will be executed after any _already_ submitted
529
-
* command buffers to SVGA_CB_CONTEXT_1.
530
-
*/
531
-
532
-
#define SVGA_CB_MAX_SIZE (512 * 1024) /* 512 KB */
254
+
#define SVGA_CB_MAX_SIZE_DEFAULT (KBYTES_2_BYTES(512))
255
+
#define SVGA_CB_MAX_SIZE_4MB (MBYTES_2_BYTES(4))
256
+
#define SVGA_CB_MAX_SIZE SVGA_CB_MAX_SIZE_4MB
533
257
#define SVGA_CB_MAX_QUEUED_PER_CONTEXT 32
534
-
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024) /* 32 KB */
258
+
#define SVGA_CB_MAX_COMMAND_SIZE (32 * 1024)
535
259
536
260
#define SVGA_CB_CONTEXT_MASK 0x3f
537
261
typedef enum {
538
-
SVGA_CB_CONTEXT_DEVICE = 0x3f,
539
-
SVGA_CB_CONTEXT_0 = 0x0,
540
-
SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
541
-
SVGA_CB_CONTEXT_MAX = 0x2,
262
+
SVGA_CB_CONTEXT_DEVICE = 0x3f,
263
+
SVGA_CB_CONTEXT_0 = 0x0,
264
+
SVGA_CB_CONTEXT_1 = 0x1,
265
+
SVGA_CB_CONTEXT_MAX = 0x2,
542
266
} SVGACBContext;
543
267
544
-
545
268
typedef enum {
546
-
/*
547
-
* The guest is supposed to write SVGA_CB_STATUS_NONE to the status
548
-
* field before submitting the command buffer header, the host will
549
-
* change the value when it is done with the command buffer.
550
-
*/
551
-
SVGA_CB_STATUS_NONE = 0,
552
269
553
-
/*
554
-
* Written by the host when a command buffer completes successfully.
555
-
* The device raises an IRQ with SVGA_IRQFLAG_COMMAND_BUFFER unless
556
-
* the SVGA_CB_FLAG_NO_IRQ flag is set.
557
-
*/
558
-
SVGA_CB_STATUS_COMPLETED = 1,
270
+
SVGA_CB_STATUS_NONE = 0,
559
271
560
-
/*
561
-
* Written by the host synchronously with the command buffer
562
-
* submission to indicate the command buffer was not submitted. No
563
-
* IRQ is raised.
564
-
*/
565
-
SVGA_CB_STATUS_QUEUE_FULL = 2,
272
+
SVGA_CB_STATUS_COMPLETED = 1,
566
273
567
-
/*
568
-
* Written by the host when an error was detected parsing a command
569
-
* in the command buffer, errorOffset is written to contain the
570
-
* offset to the first byte of the failing command. The device
571
-
* raises the IRQ with both SVGA_IRQFLAG_ERROR and
572
-
* SVGA_IRQFLAG_COMMAND_BUFFER. Some of the commands may have been
573
-
* processed.
574
-
*/
575
-
SVGA_CB_STATUS_COMMAND_ERROR = 3,
274
+
SVGA_CB_STATUS_QUEUE_FULL = 2,
576
275
577
-
/*
578
-
* Written by the host if there is an error parsing the command
579
-
* buffer header. The device raises the IRQ with both
580
-
* SVGA_IRQFLAG_ERROR and SVGA_IRQFLAG_COMMAND_BUFFER. The device
581
-
* did not processes any of the command buffer.
582
-
*/
583
-
SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
276
+
SVGA_CB_STATUS_COMMAND_ERROR = 3,
584
277
585
-
/*
586
-
* Written by the host if the guest requested the host to preempt
587
-
* the command buffer. The device will not raise any IRQs and the
588
-
* command buffer was not processed.
589
-
*/
590
-
SVGA_CB_STATUS_PREEMPTED = 5,
278
+
SVGA_CB_STATUS_CB_HEADER_ERROR = 4,
591
279
592
-
/*
593
-
* Written by the host synchronously with the command buffer
594
-
* submission to indicate the the command buffer was not submitted
595
-
* due to an error. No IRQ is raised.
596
-
*/
597
-
SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
280
+
SVGA_CB_STATUS_PREEMPTED = 5,
598
281
599
-
/*
600
-
* Written by the host when the host finished a
601
-
* SVGA_DC_CMD_ASYNC_STOP_QUEUE request for this command buffer
602
-
* queue. The offset of the first byte not processed is stored in
603
-
* the errorOffset field of the command buffer header. All guest
604
-
* visible side effects of commands till that point are guaranteed
605
-
* to be finished before this is written. The
606
-
* SVGA_IRQFLAG_COMMAND_BUFFER IRQ is raised as long as the
607
-
* SVGA_CB_FLAG_NO_IRQ is not set.
608
-
*/
609
-
SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
282
+
SVGA_CB_STATUS_SUBMISSION_ERROR = 6,
283
+
284
+
SVGA_CB_STATUS_PARTIAL_COMPLETE = 7,
610
285
} SVGACBStatus;
611
286
612
287
typedef enum {
613
-
SVGA_CB_FLAG_NONE = 0,
614
-
SVGA_CB_FLAG_NO_IRQ = 1 << 0,
615
-
SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
616
-
SVGA_CB_FLAG_MOB = 1 << 2,
288
+
SVGA_CB_FLAG_NONE = 0,
289
+
SVGA_CB_FLAG_NO_IRQ = 1 << 0,
290
+
SVGA_CB_FLAG_DX_CONTEXT = 1 << 1,
291
+
SVGA_CB_FLAG_MOB = 1 << 2,
617
292
} SVGACBFlags;
618
293
619
-
typedef
620
-
#include "vmware_pack_begin.h"
621
-
struct {
622
-
volatile SVGACBStatus status; /* Modified by device. */
623
-
volatile uint32 errorOffset; /* Modified by device. */
624
-
uint64 id;
625
-
SVGACBFlags flags;
626
-
uint32 length;
627
-
union {
628
-
PA pa;
629
-
struct {
630
-
SVGAMobId mobid;
631
-
uint32 mobOffset;
632
-
} mob;
633
-
} ptr;
634
-
uint32 offset; /* Valid if CMD_BUFFERS_2 cap set, must be zero otherwise,
635
-
* modified by device.
636
-
*/
637
-
uint32 dxContext; /* Valid if DX_CONTEXT flag set, must be zero otherwise */
638
-
uint32 mustBeZero[6];
639
-
}
640
-
#include "vmware_pack_end.h"
641
-
SVGACBHeader;
294
+
#pragma pack(push, 1)
295
+
typedef struct {
296
+
volatile SVGACBStatus status;
297
+
volatile uint32 errorOffset;
298
+
uint64 id;
299
+
SVGACBFlags flags;
300
+
uint32 length;
301
+
union {
302
+
PA pa;
303
+
struct {
304
+
SVGAMobId mobid;
305
+
uint32 mobOffset;
306
+
} mob;
307
+
} ptr;
308
+
uint32 offset;
309
+
uint32 dxContext;
310
+
uint32 mustBeZero[6];
311
+
} SVGACBHeader;
312
+
#pragma pack(pop)
642
313
643
314
typedef enum {
644
-
SVGA_DC_CMD_NOP = 0,
645
-
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
646
-
SVGA_DC_CMD_PREEMPT = 2,
647
-
SVGA_DC_CMD_START_QUEUE = 3, /* Requires SVGA_CAP_HP_CMD_QUEUE */
648
-
SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4, /* Requires SVGA_CAP_HP_CMD_QUEUE */
649
-
SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5, /* Requires SVGA_CAP_HP_CMD_QUEUE */
650
-
SVGA_DC_CMD_MAX = 6,
315
+
SVGA_DC_CMD_NOP = 0,
316
+
SVGA_DC_CMD_START_STOP_CONTEXT = 1,
317
+
SVGA_DC_CMD_PREEMPT = 2,
318
+
SVGA_DC_CMD_START_QUEUE = 3,
319
+
SVGA_DC_CMD_ASYNC_STOP_QUEUE = 4,
320
+
SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE = 5,
321
+
SVGA_DC_CMD_MAX = 6
651
322
} SVGADeviceContextCmdId;
652
323
653
-
/*
654
-
* Starts or stops both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1.
655
-
*/
656
-
657
324
typedef struct SVGADCCmdStartStop {
658
-
uint32 enable;
659
-
SVGACBContext context; /* Must be zero */
325
+
uint32 enable;
326
+
SVGACBContext context;
660
327
} SVGADCCmdStartStop;
661
328
662
-
/*
663
-
* SVGADCCmdPreempt --
664
-
*
665
-
* This command allows the guest to request that all command buffers
666
-
* on SVGA_CB_CONTEXT_0 be preempted that can be. After execution
667
-
* of this command all command buffers that were preempted will
668
-
* already have SVGA_CB_STATUS_PREEMPTED written into the status
669
-
* field. The device might still be processing a command buffer,
670
-
* assuming execution of it started before the preemption request was
671
-
* received. Specifying the ignoreIDZero flag to TRUE will cause the
672
-
* device to not preempt command buffers with the id field in the
673
-
* command buffer header set to zero.
674
-
*/
675
-
676
329
typedef struct SVGADCCmdPreempt {
677
-
SVGACBContext context; /* Must be zero */
678
-
uint32 ignoreIDZero;
330
+
SVGACBContext context;
331
+
uint32 ignoreIDZero;
679
332
} SVGADCCmdPreempt;
680
333
681
-
/*
682
-
* Starts the requested command buffer processing queue. Valid only
683
-
* if the SVGA_CAP_HP_CMD_QUEUE cap is set.
684
-
*
685
-
* For a command queue to be considered runnable it must be enabled
686
-
* and any corresponding higher priority queues must also be enabled.
687
-
* For example in order for command buffers to be processed on
688
-
* SVGA_CB_CONTEXT_0 both SVGA_CB_CONTEXT_0 and SVGA_CB_CONTEXT_1 must
689
-
* be enabled. But for commands to be runnable on SVGA_CB_CONTEXT_1
690
-
* only that queue must be enabled.
691
-
*/
692
-
693
334
typedef struct SVGADCCmdStartQueue {
694
-
SVGACBContext context;
335
+
SVGACBContext context;
695
336
} SVGADCCmdStartQueue;
696
337
697
-
/*
698
-
* Requests the SVGA device to stop processing the requested command
699
-
* buffer queue as soon as possible. The guest knows the stop has
700
-
* completed when one of the following happens.
701
-
*
702
-
* 1) A command buffer status of SVGA_CB_STATUS_PARTIAL_COMPLETE is returned
703
-
* 2) A command buffer error is encountered with would stop the queue
704
-
* regardless of the async stop request.
705
-
* 3) All command buffers that have been submitted complete successfully.
706
-
* 4) The stop completes synchronously if no command buffers are
707
-
* active on the queue when it is issued.
708
-
*
709
-
* If the command queue is not in a runnable state there is no
710
-
* guarentee this async stop will finish. For instance if the high
711
-
* priority queue is not enabled and a stop is requested on the low
712
-
* priority queue, the high priority queue must be reenabled to
713
-
* guarantee that the async stop will finish.
714
-
*
715
-
* This command along with SVGA_DC_CMD_EMPTY_CONTEXT_QUEUE can be used
716
-
* to implement mid command buffer preemption.
717
-
*
718
-
* Valid only if the SVGA_CAP_HP_CMD_QUEUE cap is set.
719
-
*/
720
-
721
338
typedef struct SVGADCCmdAsyncStopQueue {
722
-
SVGACBContext context;
339
+
SVGACBContext context;
723
340
} SVGADCCmdAsyncStopQueue;
724
341
725
-
/*
726
-
* Requests the SVGA device to throw away any full command buffers on
727
-
* the requested command queue that have not been started. For a
728
-
* driver to know which command buffers were thrown away a driver
729
-
* should only issue this command when the queue is stopped, for
730
-
* whatever reason.
731
-
*/
732
-
733
342
typedef struct SVGADCCmdEmptyQueue {
734
-
SVGACBContext context;
343
+
SVGACBContext context;
735
344
} SVGADCCmdEmptyQueue;
736
345
737
-
738
-
/*
739
-
* SVGAGMRImageFormat --
740
-
*
741
-
* This is a packed representation of the source 2D image format
742
-
* for a GMR-to-screen blit. Currently it is defined as an encoding
743
-
* of the screen's color depth and bits-per-pixel, however, 16 bits
744
-
* are reserved for future use to identify other encodings (such as
745
-
* RGBA or higher-precision images).
746
-
*
747
-
* Currently supported formats:
748
-
*
749
-
* bpp depth Format Name
750
-
* --- ----- -----------
751
-
* 32 24 32-bit BGRX
752
-
* 24 24 24-bit BGR
753
-
* 16 16 RGB 5-6-5
754
-
* 16 15 RGB 5-5-5
755
-
*
756
-
*/
757
-
758
346
typedef struct SVGAGMRImageFormat {
759
-
union {
760
-
struct {
761
-
uint32 bitsPerPixel : 8;
762
-
uint32 colorDepth : 8;
763
-
uint32 reserved : 16; /* Must be zero */
764
-
};
347
+
union {
348
+
struct {
349
+
uint32 bitsPerPixel : 8;
350
+
uint32 colorDepth : 8;
351
+
uint32 reserved : 16;
352
+
};
765
353
766
-
uint32 value;
767
-
};
354
+
uint32 value;
355
+
};
768
356
} SVGAGMRImageFormat;
769
357
770
-
typedef
771
-
#include "vmware_pack_begin.h"
772
-
struct SVGAGuestImage {
773
-
SVGAGuestPtr ptr;
358
+
#pragma pack(push, 1)
359
+
typedef struct SVGAGuestImage {
360
+
SVGAGuestPtr ptr;
774
361
775
-
/*
776
-
* A note on interpretation of pitch: This value of pitch is the
777
-
* number of bytes between vertically adjacent image
778
-
* blocks. Normally this is the number of bytes between the first
779
-
* pixel of two adjacent scanlines. With compressed textures,
780
-
* however, this may represent the number of bytes between
781
-
* compression blocks rather than between rows of pixels.
782
-
*
783
-
* XXX: Compressed textures currently must be tightly packed in guest memory.
784
-
*
785
-
* If the image is 1-dimensional, pitch is ignored.
786
-
*
787
-
* If 'pitch' is zero, the SVGA3D device calculates a pitch value
788
-
* assuming each row of blocks is tightly packed.
789
-
*/
790
-
uint32 pitch;
791
-
}
792
-
#include "vmware_pack_end.h"
793
-
SVGAGuestImage;
794
-
795
-
/*
796
-
* SVGAColorBGRX --
797
-
*
798
-
* A 24-bit color format (BGRX), which does not depend on the
799
-
* format of the legacy guest framebuffer (GFB) or the current
800
-
* GMRFB state.
801
-
*/
362
+
uint32 pitch;
363
+
} SVGAGuestImage;
364
+
#pragma pack(pop)
802
365
803
366
typedef struct SVGAColorBGRX {
804
-
union {
805
-
struct {
806
-
uint32 b : 8;
807
-
uint32 g : 8;
808
-
uint32 r : 8;
809
-
uint32 x : 8; /* Unused */
810
-
};
367
+
union {
368
+
struct {
369
+
uint32 b : 8;
370
+
uint32 g : 8;
371
+
uint32 r : 8;
372
+
uint32 x : 8;
373
+
};
811
374
812
-
uint32 value;
813
-
};
375
+
uint32 value;
376
+
};
814
377
} SVGAColorBGRX;
815
378
379
+
#pragma pack(push, 1)
380
+
typedef struct {
381
+
int32 left;
382
+
int32 top;
383
+
int32 right;
384
+
int32 bottom;
385
+
} SVGASignedRect;
386
+
#pragma pack(pop)
816
387
817
-
/*
818
-
* SVGASignedRect --
819
-
* SVGASignedPoint --
820
-
*
821
-
* Signed rectangle and point primitives. These are used by the new
822
-
* 2D primitives for drawing to Screen Objects, which can occupy a
823
-
* signed virtual coordinate space.
824
-
*
825
-
* SVGASignedRect specifies a half-open interval: the (left, top)
826
-
* pixel is part of the rectangle, but the (right, bottom) pixel is
827
-
* not.
828
-
*/
388
+
#pragma pack(push, 1)
389
+
typedef struct {
390
+
int32 x;
391
+
int32 y;
392
+
} SVGASignedPoint;
393
+
#pragma pack(pop)
829
394
830
-
typedef
831
-
#include "vmware_pack_begin.h"
832
-
struct {
833
-
int32 left;
834
-
int32 top;
835
-
int32 right;
836
-
int32 bottom;
837
-
}
838
-
#include "vmware_pack_end.h"
839
-
SVGASignedRect;
395
+
#pragma pack(push, 1)
396
+
typedef struct {
397
+
uint32 x;
398
+
uint32 y;
399
+
} SVGAUnsignedPoint;
400
+
#pragma pack(pop)
840
401
841
-
typedef
842
-
#include "vmware_pack_begin.h"
843
-
struct {
844
-
int32 x;
845
-
int32 y;
846
-
}
847
-
#include "vmware_pack_end.h"
848
-
SVGASignedPoint;
402
+
#define SVGA_CAP_NONE 0x00000000
403
+
#define SVGA_CAP_RECT_COPY 0x00000002
404
+
#define SVGA_CAP_CURSOR 0x00000020
405
+
#define SVGA_CAP_CURSOR_BYPASS 0x00000040
406
+
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
407
+
#define SVGA_CAP_8BIT_EMULATION 0x00000100
408
+
#define SVGA_CAP_ALPHA_CURSOR 0x00000200
409
+
#define SVGA_CAP_3D 0x00004000
410
+
#define SVGA_CAP_EXTENDED_FIFO 0x00008000
411
+
#define SVGA_CAP_MULTIMON 0x00010000
412
+
#define SVGA_CAP_PITCHLOCK 0x00020000
413
+
#define SVGA_CAP_IRQMASK 0x00040000
414
+
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
415
+
#define SVGA_CAP_GMR 0x00100000
416
+
#define SVGA_CAP_TRACES 0x00200000
417
+
#define SVGA_CAP_GMR2 0x00400000
418
+
#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
419
+
#define SVGA_CAP_COMMAND_BUFFERS 0x01000000
420
+
#define SVGA_CAP_DEAD1 0x02000000
421
+
#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
422
+
#define SVGA_CAP_GBOBJECTS 0x08000000
423
+
#define SVGA_CAP_DX 0x10000000
424
+
#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
425
+
#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
426
+
#define SVGA_CAP_CAP2_REGISTER 0x80000000
849
427
850
-
851
-
/*
852
-
* SVGA Device Capabilities
853
-
*
854
-
* Note the holes in the bitfield. Missing bits have been deprecated,
855
-
* and must not be reused. Those capabilities will never be reported
856
-
* by new versions of the SVGA device.
857
-
*
858
-
* SVGA_CAP_IRQMASK --
859
-
* Provides device interrupts. Adds device register SVGA_REG_IRQMASK
860
-
* to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
861
-
* set/clear pending interrupts.
862
-
*
863
-
* SVGA_CAP_GMR --
864
-
* Provides synchronous mapping of guest memory regions (GMR).
865
-
* Adds device registers SVGA_REG_GMR_ID, SVGA_REG_GMR_DESCRIPTOR,
866
-
* SVGA_REG_GMR_MAX_IDS, and SVGA_REG_GMR_MAX_DESCRIPTOR_LENGTH.
867
-
*
868
-
* SVGA_CAP_TRACES --
869
-
* Allows framebuffer trace-based updates even when FIFO is enabled.
870
-
* Adds device register SVGA_REG_TRACES.
871
-
*
872
-
* SVGA_CAP_GMR2 --
873
-
* Provides asynchronous commands to define and remap guest memory
874
-
* regions. Adds device registers SVGA_REG_GMRS_MAX_PAGES and
875
-
* SVGA_REG_MEMORY_SIZE.
876
-
*
877
-
* SVGA_CAP_SCREEN_OBJECT_2 --
878
-
* Allow screen object support, and require backing stores from the
879
-
* guest for each screen object.
880
-
*
881
-
* SVGA_CAP_COMMAND_BUFFERS --
882
-
* Enable register based command buffer submission.
883
-
*
884
-
* SVGA_CAP_DEAD1 --
885
-
* This cap was incorrectly used by old drivers and should not be
886
-
* reused.
887
-
*
888
-
* SVGA_CAP_CMD_BUFFERS_2 --
889
-
* Enable support for the prepend command buffer submision
890
-
* registers. SVGA_REG_CMD_PREPEND_LOW and
891
-
* SVGA_REG_CMD_PREPEND_HIGH.
892
-
*
893
-
* SVGA_CAP_GBOBJECTS --
894
-
* Enable guest-backed objects and surfaces.
895
-
*
896
-
* SVGA_CAP_DX --
897
-
* Enable support for DX commands, and command buffers in a mob.
898
-
*
899
-
* SVGA_CAP_HP_CMD_QUEUE --
900
-
* Enable support for the high priority command queue, and the
901
-
* ScreenCopy command.
902
-
*
903
-
* SVGA_CAP_NO_BB_RESTRICTION --
904
-
* Allow ScreenTargets to be defined without regard to the 32-bpp
905
-
* bounding-box memory restrictions. ie:
906
-
*
907
-
* The summed memory usage of all screens (assuming they were defined as
908
-
* 32-bpp) must always be less than the value of the
909
-
* SVGA_REG_MAX_PRIMARY_MEM register.
910
-
*
911
-
* If this cap is not present, the 32-bpp bounding box around all screens
912
-
* must additionally be under the value of the SVGA_REG_MAX_PRIMARY_MEM
913
-
* register.
914
-
*
915
-
* If the cap is present, the bounding box restriction is lifted (and only
916
-
* the screen-sum limit applies).
917
-
*
918
-
* (Note that this is a slight lie... there is still a sanity limit on any
919
-
* dimension of the topology to be less than SVGA_SCREEN_ROOT_LIMIT, even
920
-
* when SVGA_CAP_NO_BB_RESTRICTION is present, but that should be
921
-
* large enough to express any possible topology without holes between
922
-
* monitors.)
923
-
*
924
-
* SVGA_CAP_CAP2_REGISTER --
925
-
* If this cap is present, the SVGA_REG_CAP2 register is supported.
926
-
*/
927
-
928
-
#define SVGA_CAP_NONE 0x00000000
929
-
#define SVGA_CAP_RECT_COPY 0x00000002
930
-
#define SVGA_CAP_CURSOR 0x00000020
931
-
#define SVGA_CAP_CURSOR_BYPASS 0x00000040
932
-
#define SVGA_CAP_CURSOR_BYPASS_2 0x00000080
933
-
#define SVGA_CAP_8BIT_EMULATION 0x00000100
934
-
#define SVGA_CAP_ALPHA_CURSOR 0x00000200
935
-
#define SVGA_CAP_3D 0x00004000
936
-
#define SVGA_CAP_EXTENDED_FIFO 0x00008000
937
-
#define SVGA_CAP_MULTIMON 0x00010000
938
-
#define SVGA_CAP_PITCHLOCK 0x00020000
939
-
#define SVGA_CAP_IRQMASK 0x00040000
940
-
#define SVGA_CAP_DISPLAY_TOPOLOGY 0x00080000
941
-
#define SVGA_CAP_GMR 0x00100000
942
-
#define SVGA_CAP_TRACES 0x00200000
943
-
#define SVGA_CAP_GMR2 0x00400000
944
-
#define SVGA_CAP_SCREEN_OBJECT_2 0x00800000
945
-
#define SVGA_CAP_COMMAND_BUFFERS 0x01000000
946
-
#define SVGA_CAP_DEAD1 0x02000000
947
-
#define SVGA_CAP_CMD_BUFFERS_2 0x04000000
948
-
#define SVGA_CAP_GBOBJECTS 0x08000000
949
-
#define SVGA_CAP_DX 0x10000000
950
-
#define SVGA_CAP_HP_CMD_QUEUE 0x20000000
951
-
#define SVGA_CAP_NO_BB_RESTRICTION 0x40000000
952
-
#define SVGA_CAP_CAP2_REGISTER 0x80000000
953
-
954
-
/*
955
-
* The SVGA_REG_CAP2 register is an additional set of SVGA capability bits.
956
-
*
957
-
* SVGA_CAP2_GROW_OTABLE --
958
-
* Allow the GrowOTable/DXGrowCOTable commands.
959
-
*
960
-
* SVGA_CAP2_INTRA_SURFACE_COPY --
961
-
* Allow the IntraSurfaceCopy command.
962
-
*
963
-
* SVGA_CAP2_DX2 --
964
-
* Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
965
-
* HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register.
966
-
*
967
-
* SVGA_CAP2_GB_MEMSIZE_2 --
968
-
* Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register.
969
-
*
970
-
* SVGA_CAP2_SCREENDMA_REG --
971
-
* Allow the SVGA_REG_SCREENDMA register.
972
-
*
973
-
* SVGA_CAP2_OTABLE_PTDEPTH_2 --
974
-
* Allow 2 level page tables for OTable commands.
975
-
*
976
-
* SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT --
977
-
* Allow a stretch blt from a non-multisampled surface to a multisampled
978
-
* surface.
979
-
*
980
-
* SVGA_CAP2_CURSOR_MOB --
981
-
* Allow the SVGA_REG_CURSOR_MOBID register.
982
-
*
983
-
* SVGA_CAP2_MSHINT --
984
-
* Allow the SVGA_REG_MSHINT register.
985
-
*
986
-
* SVGA_CAP2_DX3 --
987
-
* Allows the DefineGBSurface_v4 command.
988
-
* Allows the DXDefineDepthStencilView_v2, DXDefineStreamOutputWithMob,
989
-
* and DXBindStreamOutput commands if 3D is also available.
990
-
* Allows the DXPredStagingCopy and DXStagingCopy commands if SM41
991
-
* is also available.
992
-
*
993
-
* SVGA_CAP2_RESERVED --
994
-
* Reserve the last bit for extending the SVGA capabilities to some
995
-
* future mechanisms.
996
-
*/
997
-
#define SVGA_CAP2_NONE 0x00000000
998
-
#define SVGA_CAP2_GROW_OTABLE 0x00000001
999
-
#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
1000
-
#define SVGA_CAP2_DX2 0x00000004
1001
-
#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
1002
-
#define SVGA_CAP2_SCREENDMA_REG 0x00000010
1003
-
#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
428
+
#define SVGA_CAP2_NONE 0x00000000
429
+
#define SVGA_CAP2_GROW_OTABLE 0x00000001
430
+
#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
431
+
#define SVGA_CAP2_DX2 0x00000004
432
+
#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
433
+
#define SVGA_CAP2_SCREENDMA_REG 0x00000010
434
+
#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
1004
435
#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040
1005
-
#define SVGA_CAP2_CURSOR_MOB 0x00000080
1006
-
#define SVGA_CAP2_MSHINT 0x00000100
1007
-
#define SVGA_CAP2_DX3 0x00000400
1008
-
#define SVGA_CAP2_RESERVED 0x80000000
1009
-
1010
-
1011
-
/*
1012
-
* The Guest can optionally read some SVGA device capabilities through
1013
-
* the backdoor with command BDOOR_CMD_GET_SVGA_CAPABILITIES before
1014
-
* the SVGA device is initialized. The type of capability the guest
1015
-
* is requesting from the SVGABackdoorCapType enum should be placed in
1016
-
* the upper 16 bits of the backdoor command id (ECX). On success the
1017
-
* the value of EBX will be set to BDOOR_MAGIC and EAX will be set to
1018
-
* the requested capability. If the command is not supported then EBX
1019
-
* will be left unchanged and EAX will be set to -1. Because it is
1020
-
* possible that -1 is the value of the requested cap the correct way
1021
-
* to check if the command was successful is to check if EBX was changed
1022
-
* to BDOOR_MAGIC making sure to initialize the register to something
1023
-
* else first.
1024
-
*/
436
+
#define SVGA_CAP2_CURSOR_MOB 0x00000080
437
+
#define SVGA_CAP2_MSHINT 0x00000100
438
+
#define SVGA_CAP2_CB_MAX_SIZE_4MB 0x00000200
439
+
#define SVGA_CAP2_DX3 0x00000400
440
+
#define SVGA_CAP2_FRAME_TYPE 0x00000800
441
+
#define SVGA_CAP2_COTABLE_COPY 0x00001000
442
+
#define SVGA_CAP2_TRACE_FULL_FB 0x00002000
443
+
#define SVGA_CAP2_EXTRA_REGS 0x00004000
444
+
#define SVGA_CAP2_LO_STAGING 0x00008000
445
+
#define SVGA_CAP2_RESERVED 0x80000000
1025
446
1026
447
typedef enum {
1027
-
SVGABackdoorCapDeviceCaps = 0,
1028
-
SVGABackdoorCapFifoCaps = 1,
1029
-
SVGABackdoorCap3dHWVersion = 2,
1030
-
SVGABackdoorCapDeviceCaps2 = 3,
1031
-
SVGABackdoorCapDevelCaps = 4,
1032
-
SVGABackdoorDevelRenderer = 5,
1033
-
SVGABackdoorCapMax = 6,
448
+
SVGABackdoorCapDeviceCaps = 0,
449
+
SVGABackdoorCapFifoCaps = 1,
450
+
SVGABackdoorCap3dHWVersion = 2,
451
+
SVGABackdoorCapDeviceCaps2 = 3,
452
+
SVGABackdoorCapDevelCaps = 4,
453
+
SVGABackdoorDevelRenderer = 5,
454
+
SVGABackdoorDevelUsingISB = 6,
455
+
SVGABackdoorCapMax = 7,
1034
456
} SVGABackdoorCapType;
1035
457
1036
-
1037
-
/*
1038
-
* FIFO register indices.
1039
-
*
1040
-
* The FIFO is a chunk of device memory mapped into guest physmem. It
1041
-
* is always treated as 32-bit words.
1042
-
*
1043
-
* The guest driver gets to decide how to partition it between
1044
-
* - FIFO registers (there are always at least 4, specifying where the
1045
-
* following data area is and how much data it contains; there may be
1046
-
* more registers following these, depending on the FIFO protocol
1047
-
* version in use)
1048
-
* - FIFO data, written by the guest and slurped out by the VMX.
1049
-
* These indices are 32-bit word offsets into the FIFO.
1050
-
*/
1051
-
1052
458
enum {
1053
-
/*
1054
-
* Block 1 (basic registers): The originally defined FIFO registers.
1055
-
* These exist and are valid for all versions of the FIFO protocol.
1056
-
*/
1057
459
1058
-
SVGA_FIFO_MIN = 0,
1059
-
SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
1060
-
SVGA_FIFO_NEXT_CMD,
1061
-
SVGA_FIFO_STOP,
460
+
SVGA_FIFO_MIN = 0,
461
+
SVGA_FIFO_MAX,
462
+
SVGA_FIFO_NEXT_CMD,
463
+
SVGA_FIFO_STOP,
1062
464
1063
-
/*
1064
-
* Block 2 (extended registers): Mandatory registers for the extended
1065
-
* FIFO. These exist if the SVGA caps register includes
1066
-
* SVGA_CAP_EXTENDED_FIFO; some of them are valid only if their
1067
-
* associated capability bit is enabled.
1068
-
*
1069
-
* Note that when originally defined, SVGA_CAP_EXTENDED_FIFO implied
1070
-
* support only for (FIFO registers) CAPABILITIES, FLAGS, and FENCE.
1071
-
* This means that the guest has to test individually (in most cases
1072
-
* using FIFO caps) for the presence of registers after this; the VMX
1073
-
* can define "extended FIFO" to mean whatever it wants, and currently
1074
-
* won't enable it unless there's room for that set and much more.
1075
-
*/
465
+
SVGA_FIFO_CAPABILITIES = 4,
466
+
SVGA_FIFO_FLAGS,
1076
467
1077
-
SVGA_FIFO_CAPABILITIES = 4,
1078
-
SVGA_FIFO_FLAGS,
1079
-
/* Valid with SVGA_FIFO_CAP_FENCE: */
1080
-
SVGA_FIFO_FENCE,
468
+
SVGA_FIFO_FENCE,
1081
469
1082
-
/*
1083
-
* Block 3a (optional extended registers): Additional registers for the
1084
-
* extended FIFO, whose presence isn't actually implied by
1085
-
* SVGA_CAP_EXTENDED_FIFO; these exist if SVGA_FIFO_MIN is high enough to
1086
-
* leave room for them.
1087
-
*
1088
-
* These in block 3a, the VMX currently considers mandatory for the
1089
-
* extended FIFO.
1090
-
*/
470
+
SVGA_FIFO_3D_HWVERSION,
1091
471
1092
-
/* Valid if exists (i.e. if extended FIFO enabled): */
1093
-
SVGA_FIFO_3D_HWVERSION, /* See SVGA3dHardwareVersion in svga3d_reg.h */
1094
-
/* Valid with SVGA_FIFO_CAP_PITCHLOCK: */
1095
-
SVGA_FIFO_PITCHLOCK,
472
+
SVGA_FIFO_PITCHLOCK,
1096
473
1097
-
/* Valid with SVGA_FIFO_CAP_CURSOR_BYPASS_3: */
1098
-
SVGA_FIFO_CURSOR_ON, /* Cursor bypass 3 show/hide register */
1099
-
SVGA_FIFO_CURSOR_X, /* Cursor bypass 3 x register */
1100
-
SVGA_FIFO_CURSOR_Y, /* Cursor bypass 3 y register */
1101
-
SVGA_FIFO_CURSOR_COUNT, /* Incremented when any of the other 3 change */
1102
-
SVGA_FIFO_CURSOR_LAST_UPDATED,/* Last time the host updated the cursor */
474
+
SVGA_FIFO_CURSOR_ON,
475
+
SVGA_FIFO_CURSOR_X,
476
+
SVGA_FIFO_CURSOR_Y,
477
+
SVGA_FIFO_CURSOR_COUNT,
478
+
SVGA_FIFO_CURSOR_LAST_UPDATED,
1103
479
1104
-
/* Valid with SVGA_FIFO_CAP_RESERVE: */
1105
-
SVGA_FIFO_RESERVED, /* Bytes past NEXT_CMD with real contents */
480
+
SVGA_FIFO_RESERVED,
1106
481
1107
-
/*
1108
-
* Valid with SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2:
1109
-
*
1110
-
* By default this is SVGA_ID_INVALID, to indicate that the cursor
1111
-
* coordinates are specified relative to the virtual root. If this
1112
-
* is set to a specific screen ID, cursor position is reinterpreted
1113
-
* as a signed offset relative to that screen's origin.
1114
-
*/
1115
-
SVGA_FIFO_CURSOR_SCREEN_ID,
482
+
SVGA_FIFO_CURSOR_SCREEN_ID,
1116
483
1117
-
/*
1118
-
* Valid with SVGA_FIFO_CAP_DEAD
1119
-
*
1120
-
* An arbitrary value written by the host, drivers should not use it.
1121
-
*/
1122
-
SVGA_FIFO_DEAD,
484
+
SVGA_FIFO_DEAD,
1123
485
1124
-
/*
1125
-
* Valid with SVGA_FIFO_CAP_3D_HWVERSION_REVISED:
1126
-
*
1127
-
* Contains 3D HWVERSION (see SVGA3dHardwareVersion in svga3d_reg.h)
1128
-
* on platforms that can enforce graphics resource limits.
1129
-
*/
1130
-
SVGA_FIFO_3D_HWVERSION_REVISED,
486
+
SVGA_FIFO_3D_HWVERSION_REVISED,
1131
487
1132
-
/*
1133
-
* XXX: The gap here, up until SVGA_FIFO_3D_CAPS, can be used for new
1134
-
* registers, but this must be done carefully and with judicious use of
1135
-
* capability bits, since comparisons based on SVGA_FIFO_MIN aren't
1136
-
* enough to tell you whether the register exists: we've shipped drivers
1137
-
* and products that used SVGA_FIFO_3D_CAPS but didn't know about some of
1138
-
* the earlier ones. The actual order of introduction was:
1139
-
* - PITCHLOCK
1140
-
* - 3D_CAPS
1141
-
* - CURSOR_* (cursor bypass 3)
1142
-
* - RESERVED
1143
-
* So, code that wants to know whether it can use any of the
1144
-
* aforementioned registers, or anything else added after PITCHLOCK and
1145
-
* before 3D_CAPS, needs to reason about something other than
1146
-
* SVGA_FIFO_MIN.
1147
-
*/
488
+
SVGA_FIFO_3D_CAPS = 32,
489
+
SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
1148
490
1149
-
/*
1150
-
* 3D caps block space; valid with 3D hardware version >=
1151
-
* SVGA3D_HWVERSION_WS6_B1.
1152
-
*/
1153
-
SVGA_FIFO_3D_CAPS = 32,
1154
-
SVGA_FIFO_3D_CAPS_LAST = 32 + 255,
491
+
SVGA_FIFO_GUEST_3D_HWVERSION,
492
+
SVGA_FIFO_FENCE_GOAL,
493
+
SVGA_FIFO_BUSY,
1155
494
1156
-
/*
1157
-
* End of VMX's current definition of "extended-FIFO registers".
1158
-
* Registers before here are always enabled/disabled as a block; either
1159
-
* the extended FIFO is enabled and includes all preceding registers, or
1160
-
* it's disabled entirely.
1161
-
*
1162
-
* Block 3b (truly optional extended registers): Additional registers for
1163
-
* the extended FIFO, which the VMX already knows how to enable and
1164
-
* disable with correct granularity.
1165
-
*
1166
-
* Registers after here exist if and only if the guest SVGA driver
1167
-
* sets SVGA_FIFO_MIN high enough to leave room for them.
1168
-
*/
1169
-
1170
-
/* Valid if register exists: */
1171
-
SVGA_FIFO_GUEST_3D_HWVERSION, /* Guest driver's 3D version */
1172
-
SVGA_FIFO_FENCE_GOAL, /* Matching target for SVGA_IRQFLAG_FENCE_GOAL */
1173
-
SVGA_FIFO_BUSY, /* See "FIFO Synchronization Registers" */
1174
-
1175
-
/*
1176
-
* Always keep this last. This defines the maximum number of
1177
-
* registers we know about. At power-on, this value is placed in
1178
-
* the SVGA_REG_MEM_REGS register, and we expect the guest driver
1179
-
* to allocate this much space in FIFO memory for registers.
1180
-
*/
1181
-
SVGA_FIFO_NUM_REGS
495
+
SVGA_FIFO_NUM_REGS
1182
496
};
1183
497
498
+
#define SVGA_FIFO_3D_CAPS_SIZE (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1)
1184
499
1185
-
/*
1186
-
* Definition of registers included in extended FIFO support.
1187
-
*
1188
-
* The guest SVGA driver gets to allocate the FIFO between registers
1189
-
* and data. It must always allocate at least 4 registers, but old
1190
-
* drivers stopped there.
1191
-
*
1192
-
* The VMX will enable extended FIFO support if and only if the guest
1193
-
* left enough room for all registers defined as part of the mandatory
1194
-
* set for the extended FIFO.
1195
-
*
1196
-
* Note that the guest drivers typically allocate the FIFO only at
1197
-
* initialization time, not at mode switches, so it's likely that the
1198
-
* number of FIFO registers won't change without a reboot.
1199
-
*
1200
-
* All registers less than this value are guaranteed to be present if
1201
-
* svgaUser->fifo.extended is set. Any later registers must be tested
1202
-
* individually for compatibility at each use (in the VMX).
1203
-
*
1204
-
* This value is used only by the VMX, so it can change without
1205
-
* affecting driver compatibility; keep it that way?
1206
-
*/
1207
-
#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
500
+
#define SVGA3D_FIFO_CAPS_RECORD_DEVCAPS 0x100
501
+
typedef uint32 SVGA3dFifoCapsRecordType;
1208
502
503
+
typedef uint32 SVGA3dFifoCapPair[2];
1209
504
1210
-
/*
1211
-
* FIFO Synchronization Registers
1212
-
*
1213
-
* SVGA_REG_SYNC --
1214
-
*
1215
-
* The SYNC register can be used by the guest driver to signal to the
1216
-
* device that the guest driver is waiting for previously submitted
1217
-
* commands to complete.
1218
-
*
1219
-
* When the guest driver writes to the SYNC register, the device sets
1220
-
* the BUSY register to TRUE, and starts processing the submitted commands
1221
-
* (if it was not already doing so). When all previously submitted
1222
-
* commands are finished and the device is idle again, it sets the BUSY
1223
-
* register back to FALSE. (If the guest driver submits new commands
1224
-
* after writing the SYNC register, the new commands are not guaranteed
1225
-
* to have been procesesd.)
1226
-
*
1227
-
* When guest drivers are submitting commands using the FIFO, the device
1228
-
* periodically polls to check for new FIFO commands when idle, which may
1229
-
* introduce a delay in command processing. If the guest-driver wants
1230
-
* the commands to be processed quickly (which it typically does), it
1231
-
* should write SYNC after each batch of commands is committed to the
1232
-
* FIFO to immediately wake up the device. For even better performance,
1233
-
* the guest can use the SVGA_FIFO_BUSY register to avoid these extra
1234
-
* SYNC writes if the device is already active, using the technique known
1235
-
* as "Ringing the Doorbell" (described below). (Note that command
1236
-
* buffer submission implicitly wakes up the device, and so doesn't
1237
-
* suffer from this problem.)
1238
-
*
1239
-
* The SYNC register can also be used in combination with BUSY to
1240
-
* synchronously ensure that all SVGA commands are processed (with both
1241
-
* the FIFO and command-buffers). To do this, the guest driver should
1242
-
* write to SYNC, and then loop reading BUSY until BUSY returns FALSE.
1243
-
* This technique is known as a "Legacy Sync".
1244
-
*
1245
-
* SVGA_REG_BUSY --
1246
-
*
1247
-
* This register is set to TRUE when SVGA_REG_SYNC is written,
1248
-
* and is set back to FALSE when the device has finished processing
1249
-
* all commands and is idle again.
1250
-
*
1251
-
* Every read from the BUSY reigster will block for an undefined
1252
-
* amount of time (normally until the device finishes some interesting
1253
-
* work unit), or the device is idle.
1254
-
*
1255
-
* Guest drivers can also do a partial Legacy Sync to check for some
1256
-
* particular condition, for instance by stopping early when a fence
1257
-
* passes before BUSY has been set back to FALSE. This is particularly
1258
-
* useful if the guest-driver knows that it is blocked waiting on the
1259
-
* device, because it will yield CPU time back to the host.
1260
-
*
1261
-
* SVGA_FIFO_BUSY --
1262
-
*
1263
-
* The SVGA_FIFO_BUSY register is a fast way for the guest driver to check
1264
-
* whether the device is actively processing FIFO commands before writing
1265
-
* the more expensive SYNC register.
1266
-
*
1267
-
* If this register reads as TRUE, the device is actively processing
1268
-
* FIFO commands.
1269
-
*
1270
-
* If this register reads as FALSE, the device may not be actively
1271
-
* processing commands, and the guest driver should try
1272
-
* "Ringing the Doorbell".
1273
-
*
1274
-
* To Ring the Doorbell, the guest should:
1275
-
*
1276
-
* 1. Have already written their batch of commands into the FIFO.
1277
-
* 2. Check if the SVGA_FIFO_BUSY register is available by reading
1278
-
* SVGA_FIFO_MIN.
1279
-
* 3. Read SVGA_FIFO_BUSY. If it reads as TRUE, the device is actively
1280
-
* processing FIFO commands, and no further action is necessary.
1281
-
* 4. If SVGA_FIFO_BUSY was FALSE, write TRUE to SVGA_REG_SYNC.
1282
-
*
1283
-
* For maximum performance, this procedure should be followed after
1284
-
* every meaningful batch of commands has been written into the FIFO.
1285
-
* (Normally when the underlying application signals it's finished a
1286
-
* meaningful work unit by calling Flush.)
1287
-
*/
505
+
#pragma pack(push, 1)
506
+
typedef struct SVGA3dFifoCapsRecordHeader {
507
+
uint32 length;
508
+
SVGA3dFifoCapsRecordType type;
1288
509
510
+
} SVGA3dFifoCapsRecordHeader;
511
+
#pragma pack(pop)
1289
512
1290
-
/*
1291
-
* FIFO Capabilities
1292
-
*
1293
-
* Fence -- Fence register and command are supported
1294
-
* Accel Front -- Front buffer only commands are supported
1295
-
* Pitch Lock -- Pitch lock register is supported
1296
-
* Video -- SVGA Video overlay units are supported
1297
-
* Escape -- Escape command is supported
1298
-
*
1299
-
* SVGA_FIFO_CAP_SCREEN_OBJECT --
1300
-
*
1301
-
* Provides dynamic multi-screen rendering, for improved Unity and
1302
-
* multi-monitor modes. With Screen Object, the guest can
1303
-
* dynamically create and destroy 'screens', which can represent
1304
-
* Unity windows or virtual monitors. Screen Object also provides
1305
-
* strong guarantees that DMA operations happen only when
1306
-
* guest-initiated. Screen Object deprecates the BAR1 guest
1307
-
* framebuffer (GFB) and all commands that work only with the GFB.
1308
-
*
1309
-
* New registers:
1310
-
* FIFO_CURSOR_SCREEN_ID, VIDEO_DATA_GMRID, VIDEO_DST_SCREEN_ID
1311
-
*
1312
-
* New 2D commands:
1313
-
* DEFINE_SCREEN, DESTROY_SCREEN, DEFINE_GMRFB, BLIT_GMRFB_TO_SCREEN,
1314
-
* BLIT_SCREEN_TO_GMRFB, ANNOTATION_FILL, ANNOTATION_COPY
1315
-
*
1316
-
* New 3D commands:
1317
-
* BLIT_SURFACE_TO_SCREEN
1318
-
*
1319
-
* New guarantees:
1320
-
*
1321
-
* - The host will not read or write guest memory, including the GFB,
1322
-
* except when explicitly initiated by a DMA command.
1323
-
*
1324
-
* - All DMA, including legacy DMA like UPDATE and PRESENT_READBACK,
1325
-
* is guaranteed to complete before any subsequent FENCEs.
1326
-
*
1327
-
* - All legacy commands which affect a Screen (UPDATE, PRESENT,
1328
-
* PRESENT_READBACK) as well as new Screen blit commands will
1329
-
* all behave consistently as blits, and memory will be read
1330
-
* or written in FIFO order.
1331
-
*
1332
-
* For example, if you PRESENT from one SVGA3D surface to multiple
1333
-
* places on the screen, the data copied will always be from the
1334
-
* SVGA3D surface at the time the PRESENT was issued in the FIFO.
1335
-
* This was not necessarily true on devices without Screen Object.
1336
-
*
1337
-
* This means that on devices that support Screen Object, the
1338
-
* PRESENT_READBACK command should not be necessary unless you
1339
-
* actually want to read back the results of 3D rendering into
1340
-
* system memory. (And for that, the BLIT_SCREEN_TO_GMRFB
1341
-
* command provides a strict superset of functionality.)
1342
-
*
1343
-
* - When a screen is resized, either using Screen Object commands or
1344
-
* legacy multimon registers, its contents are preserved.
1345
-
*
1346
-
* SVGA_FIFO_CAP_GMR2 --
1347
-
*
1348
-
* Provides new commands to define and remap guest memory regions (GMR).
1349
-
*
1350
-
* New 2D commands:
1351
-
* DEFINE_GMR2, REMAP_GMR2.
1352
-
*
1353
-
* SVGA_FIFO_CAP_3D_HWVERSION_REVISED --
1354
-
*
1355
-
* Indicates new register SVGA_FIFO_3D_HWVERSION_REVISED exists.
1356
-
* This register may replace SVGA_FIFO_3D_HWVERSION on platforms
1357
-
* that enforce graphics resource limits. This allows the platform
1358
-
* to clear SVGA_FIFO_3D_HWVERSION and disable 3D in legacy guest
1359
-
* drivers that do not limit their resources.
1360
-
*
1361
-
* Note this is an alias to SVGA_FIFO_CAP_GMR2 because these indicators
1362
-
* are codependent (and thus we use a single capability bit).
1363
-
*
1364
-
* SVGA_FIFO_CAP_SCREEN_OBJECT_2 --
1365
-
*
1366
-
* Modifies the DEFINE_SCREEN command to include a guest provided
1367
-
* backing store in GMR memory and the bytesPerLine for the backing
1368
-
* store. This capability requires the use of a backing store when
1369
-
* creating screen objects. However if SVGA_FIFO_CAP_SCREEN_OBJECT
1370
-
* is present then backing stores are optional.
1371
-
*
1372
-
* SVGA_FIFO_CAP_DEAD --
1373
-
*
1374
-
* Drivers should not use this cap bit. This cap bit can not be
1375
-
* reused since some hosts already expose it.
1376
-
*/
513
+
#define SVGA_FIFO_EXTENDED_MANDATORY_REGS (SVGA_FIFO_3D_CAPS_LAST + 1)
1377
514
1378
-
#define SVGA_FIFO_CAP_NONE 0
1379
-
#define SVGA_FIFO_CAP_FENCE (1<<0)
1380
-
#define SVGA_FIFO_CAP_ACCELFRONT (1<<1)
1381
-
#define SVGA_FIFO_CAP_PITCHLOCK (1<<2)
1382
-
#define SVGA_FIFO_CAP_VIDEO (1<<3)
1383
-
#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1<<4)
1384
-
#define SVGA_FIFO_CAP_ESCAPE (1<<5)
1385
-
#define SVGA_FIFO_CAP_RESERVE (1<<6)
1386
-
#define SVGA_FIFO_CAP_SCREEN_OBJECT (1<<7)
1387
-
#define SVGA_FIFO_CAP_GMR2 (1<<8)
1388
-
#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
1389
-
#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1<<9)
1390
-
#define SVGA_FIFO_CAP_DEAD (1<<10)
515
+
#define SVGA_FIFO_CAP_NONE 0
516
+
#define SVGA_FIFO_CAP_FENCE (1 << 0)
517
+
#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
518
+
#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
519
+
#define SVGA_FIFO_CAP_VIDEO (1 << 3)
520
+
#define SVGA_FIFO_CAP_CURSOR_BYPASS_3 (1 << 4)
521
+
#define SVGA_FIFO_CAP_ESCAPE (1 << 5)
522
+
#define SVGA_FIFO_CAP_RESERVE (1 << 6)
523
+
#define SVGA_FIFO_CAP_SCREEN_OBJECT (1 << 7)
524
+
#define SVGA_FIFO_CAP_GMR2 (1 << 8)
525
+
#define SVGA_FIFO_CAP_3D_HWVERSION_REVISED SVGA_FIFO_CAP_GMR2
526
+
#define SVGA_FIFO_CAP_SCREEN_OBJECT_2 (1 << 9)
527
+
#define SVGA_FIFO_CAP_DEAD (1 << 10)
1391
528
529
+
#define SVGA_FIFO_FLAG_NONE 0
530
+
#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
531
+
#define SVGA_FIFO_FLAG_RESERVED (1 << 31)
1392
532
1393
-
/*
1394
-
* FIFO Flags
1395
-
*
1396
-
* Accel Front -- Driver should use front buffer only commands
1397
-
*/
533
+
#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
1398
534
1399
-
#define SVGA_FIFO_FLAG_NONE 0
1400
-
#define SVGA_FIFO_FLAG_ACCELFRONT (1<<0)
1401
-
#define SVGA_FIFO_FLAG_RESERVED (1<<31) /* Internal use only */
1402
-
1403
-
/*
1404
-
* FIFO reservation sentinel value
1405
-
*/
1406
-
1407
-
#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
1408
-
1409
-
1410
-
/*
1411
-
* ScreenDMA Register Values
1412
-
*/
1413
-
1414
-
#define SVGA_SCREENDMA_REG_UNDEFINED 0
1415
-
#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
1416
-
#define SVGA_SCREENDMA_REG_PRESENT 2
1417
-
#define SVGA_SCREENDMA_REG_MAX 3
1418
-
1419
-
/*
1420
-
* Video overlay support
1421
-
*/
535
+
#define SVGA_SCREENDMA_REG_UNDEFINED 0
536
+
#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
537
+
#define SVGA_SCREENDMA_REG_PRESENT 2
538
+
#define SVGA_SCREENDMA_REG_MAX 3
1422
539
1423
540
#define SVGA_NUM_OVERLAY_UNITS 32
1424
541
1425
-
1426
-
/*
1427
-
* Video capabilities that the guest is currently using
1428
-
*/
1429
-
1430
-
#define SVGA_VIDEO_FLAG_COLORKEY 0x0001
1431
-
1432
-
1433
-
/*
1434
-
* Offsets for the video overlay registers
1435
-
*/
542
+
#define SVGA_VIDEO_FLAG_COLORKEY 0x0001
1436
543
1437
544
enum {
1438
-
SVGA_VIDEO_ENABLED = 0,
1439
-
SVGA_VIDEO_FLAGS,
1440
-
SVGA_VIDEO_DATA_OFFSET,
1441
-
SVGA_VIDEO_FORMAT,
1442
-
SVGA_VIDEO_COLORKEY,
1443
-
SVGA_VIDEO_SIZE, /* Deprecated */
1444
-
SVGA_VIDEO_WIDTH,
1445
-
SVGA_VIDEO_HEIGHT,
1446
-
SVGA_VIDEO_SRC_X,
1447
-
SVGA_VIDEO_SRC_Y,
1448
-
SVGA_VIDEO_SRC_WIDTH,
1449
-
SVGA_VIDEO_SRC_HEIGHT,
1450
-
SVGA_VIDEO_DST_X, /* Signed int32 */
1451
-
SVGA_VIDEO_DST_Y, /* Signed int32 */
1452
-
SVGA_VIDEO_DST_WIDTH,
1453
-
SVGA_VIDEO_DST_HEIGHT,
1454
-
SVGA_VIDEO_PITCH_1,
1455
-
SVGA_VIDEO_PITCH_2,
1456
-
SVGA_VIDEO_PITCH_3,
1457
-
SVGA_VIDEO_DATA_GMRID, /* Optional, defaults to SVGA_GMR_FRAMEBUFFER */
1458
-
SVGA_VIDEO_DST_SCREEN_ID, /* Optional, defaults to virtual coords */
1459
-
/* (SVGA_ID_INVALID) */
1460
-
SVGA_VIDEO_NUM_REGS
545
+
SVGA_VIDEO_ENABLED = 0,
546
+
SVGA_VIDEO_FLAGS,
547
+
SVGA_VIDEO_DATA_OFFSET,
548
+
SVGA_VIDEO_FORMAT,
549
+
SVGA_VIDEO_COLORKEY,
550
+
SVGA_VIDEO_SIZE,
551
+
SVGA_VIDEO_WIDTH,
552
+
SVGA_VIDEO_HEIGHT,
553
+
SVGA_VIDEO_SRC_X,
554
+
SVGA_VIDEO_SRC_Y,
555
+
SVGA_VIDEO_SRC_WIDTH,
556
+
SVGA_VIDEO_SRC_HEIGHT,
557
+
SVGA_VIDEO_DST_X,
558
+
SVGA_VIDEO_DST_Y,
559
+
SVGA_VIDEO_DST_WIDTH,
560
+
SVGA_VIDEO_DST_HEIGHT,
561
+
SVGA_VIDEO_PITCH_1,
562
+
SVGA_VIDEO_PITCH_2,
563
+
SVGA_VIDEO_PITCH_3,
564
+
SVGA_VIDEO_DATA_GMRID,
565
+
SVGA_VIDEO_DST_SCREEN_ID,
566
+
SVGA_VIDEO_NUM_REGS
1461
567
};
1462
568
569
+
#pragma pack(push, 1)
570
+
typedef struct SVGAOverlayUnit {
571
+
uint32 enabled;
572
+
uint32 flags;
573
+
uint32 dataOffset;
574
+
uint32 format;
575
+
uint32 colorKey;
576
+
uint32 size;
577
+
uint32 width;
578
+
uint32 height;
579
+
uint32 srcX;
580
+
uint32 srcY;
581
+
uint32 srcWidth;
582
+
uint32 srcHeight;
583
+
int32 dstX;
584
+
int32 dstY;
585
+
uint32 dstWidth;
586
+
uint32 dstHeight;
587
+
uint32 pitches[3];
588
+
uint32 dataGMRId;
589
+
uint32 dstScreenId;
590
+
} SVGAOverlayUnit;
591
+
#pragma pack(pop)
1463
592
1464
-
/*
1465
-
* SVGA Overlay Units
1466
-
*
1467
-
* width and height relate to the entire source video frame.
1468
-
* srcX, srcY, srcWidth and srcHeight represent subset of the source
1469
-
* video frame to be displayed.
1470
-
*/
1471
-
1472
-
typedef
1473
-
#include "vmware_pack_begin.h"
1474
-
struct SVGAOverlayUnit {
1475
-
uint32 enabled;
1476
-
uint32 flags;
1477
-
uint32 dataOffset;
1478
-
uint32 format;
1479
-
uint32 colorKey;
1480
-
uint32 size;
1481
-
uint32 width;
1482
-
uint32 height;
1483
-
uint32 srcX;
1484
-
uint32 srcY;
1485
-
uint32 srcWidth;
1486
-
uint32 srcHeight;
1487
-
int32 dstX;
1488
-
int32 dstY;
1489
-
uint32 dstWidth;
1490
-
uint32 dstHeight;
1491
-
uint32 pitches[3];
1492
-
uint32 dataGMRId;
1493
-
uint32 dstScreenId;
1494
-
}
1495
-
#include "vmware_pack_end.h"
1496
-
SVGAOverlayUnit;
1497
-
1498
-
1499
-
/*
1500
-
* Guest display topology
1501
-
*
1502
-
* XXX: This structure is not part of the SVGA device's interface, and
1503
-
* doesn't really belong here.
1504
-
*/
1505
593
#define SVGA_INVALID_DISPLAY_ID ((uint32)-1)
1506
594
1507
595
typedef struct SVGADisplayTopology {
1508
-
uint16 displayId;
1509
-
uint16 isPrimary;
1510
-
uint32 width;
1511
-
uint32 height;
1512
-
uint32 positionX;
1513
-
uint32 positionY;
596
+
uint16 displayId;
597
+
uint16 isPrimary;
598
+
uint32 width;
599
+
uint32 height;
600
+
uint32 positionX;
601
+
uint32 positionY;
1514
602
} SVGADisplayTopology;
1515
603
1516
-
1517
-
/*
1518
-
* SVGAScreenObject --
1519
-
*
1520
-
* This is a new way to represent a guest's multi-monitor screen or
1521
-
* Unity window. Screen objects are only supported if the
1522
-
* SVGA_FIFO_CAP_SCREEN_OBJECT capability bit is set.
1523
-
*
1524
-
* If Screen Objects are supported, they can be used to fully
1525
-
* replace the functionality provided by the framebuffer registers
1526
-
* (SVGA_REG_WIDTH, HEIGHT, etc.) and by SVGA_CAP_DISPLAY_TOPOLOGY.
1527
-
*
1528
-
* The screen object is a struct with guaranteed binary
1529
-
* compatibility. New flags can be added, and the struct may grow,
1530
-
* but existing fields must retain their meaning.
1531
-
*
1532
-
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2 are required fields of
1533
-
* a SVGAGuestPtr that is used to back the screen contents. This
1534
-
* memory must come from the GFB. The guest is not allowed to
1535
-
* access the memory and doing so will have undefined results. The
1536
-
* backing store is required to be page aligned and the size is
1537
-
* padded to the next page boundry. The number of pages is:
1538
-
* (bytesPerLine * size.width * 4 + PAGE_SIZE - 1) / PAGE_SIZE
1539
-
*
1540
-
* The pitch in the backingStore is required to be at least large
1541
-
* enough to hold a 32bbp scanline. It is recommended that the
1542
-
* driver pad bytesPerLine for a potential performance win.
1543
-
*
1544
-
* The cloneCount field is treated as a hint from the guest that
1545
-
* the user wants this display to be cloned, countCount times. A
1546
-
* value of zero means no cloning should happen.
1547
-
*/
1548
-
1549
-
#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
1550
-
#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET /* Deprecated */
1551
-
#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
604
+
#define SVGA_SCREEN_MUST_BE_SET (1 << 0)
605
+
#define SVGA_SCREEN_HAS_ROOT SVGA_SCREEN_MUST_BE_SET
606
+
#define SVGA_SCREEN_IS_PRIMARY (1 << 1)
1552
607
#define SVGA_SCREEN_FULLSCREEN_HINT (1 << 2)
1553
608
1554
-
/*
1555
-
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When the screen is
1556
-
* deactivated the base layer is defined to lose all contents and
1557
-
* become black. When a screen is deactivated the backing store is
1558
-
* optional. When set backingPtr and bytesPerLine will be ignored.
1559
-
*/
1560
-
#define SVGA_SCREEN_DEACTIVATE (1 << 3)
609
+
#define SVGA_SCREEN_DEACTIVATE (1 << 3)
1561
610
1562
-
/*
1563
-
* Added with SVGA_FIFO_CAP_SCREEN_OBJECT_2. When this flag is set
1564
-
* the screen contents will be outputted as all black to the user
1565
-
* though the base layer contents is preserved. The screen base layer
1566
-
* can still be read and written to like normal though the no visible
1567
-
* effect will be seen by the user. When the flag is changed the
1568
-
* screen will be blanked or redrawn to the current contents as needed
1569
-
* without any extra commands from the driver. This flag only has an
1570
-
* effect when the screen is not deactivated.
1571
-
*/
1572
611
#define SVGA_SCREEN_BLANKING (1 << 4)
1573
612
1574
-
typedef
1575
-
#include "vmware_pack_begin.h"
1576
-
struct {
1577
-
uint32 structSize; /* sizeof(SVGAScreenObject) */
1578
-
uint32 id;
1579
-
uint32 flags;
1580
-
struct {
1581
-
uint32 width;
1582
-
uint32 height;
1583
-
} size;
1584
-
struct {
1585
-
int32 x;
1586
-
int32 y;
1587
-
} root;
613
+
#pragma pack(push, 1)
614
+
typedef struct {
615
+
uint32 structSize;
616
+
uint32 id;
617
+
uint32 flags;
618
+
struct {
619
+
uint32 width;
620
+
uint32 height;
621
+
} size;
622
+
struct {
623
+
int32 x;
624
+
int32 y;
625
+
} root;
1588
626
1589
-
/*
1590
-
* Added and required by SVGA_FIFO_CAP_SCREEN_OBJECT_2, optional
1591
-
* with SVGA_FIFO_CAP_SCREEN_OBJECT.
1592
-
*/
1593
-
SVGAGuestImage backingStore;
627
+
SVGAGuestImage backingStore;
1594
628
1595
-
/*
1596
-
* The cloneCount field is treated as a hint from the guest that
1597
-
* the user wants this display to be cloned, cloneCount times.
1598
-
*
1599
-
* A value of zero means no cloning should happen.
1600
-
*/
1601
-
uint32 cloneCount;
1602
-
}
1603
-
#include "vmware_pack_end.h"
1604
-
SVGAScreenObject;
1605
-
1606
-
1607
-
/*
1608
-
* Commands in the command FIFO:
1609
-
*
1610
-
* Command IDs defined below are used for the traditional 2D FIFO
1611
-
* communication (not all commands are available for all versions of the
1612
-
* SVGA FIFO protocol).
1613
-
*
1614
-
* Note the holes in the command ID numbers: These commands have been
1615
-
* deprecated, and the old IDs must not be reused.
1616
-
*
1617
-
* Command IDs from 1000 to 2999 are reserved for use by the SVGA3D
1618
-
* protocol.
1619
-
*
1620
-
* Each command's parameters are described by the comments and
1621
-
* structs below.
1622
-
*/
629
+
uint32 cloneCount;
630
+
} SVGAScreenObject;
631
+
#pragma pack(pop)
1623
632
1624
633
typedef enum {
1625
-
SVGA_CMD_INVALID_CMD = 0,
1626
-
SVGA_CMD_UPDATE = 1,
1627
-
SVGA_CMD_RECT_COPY = 3,
1628
-
SVGA_CMD_RECT_ROP_COPY = 14,
1629
-
SVGA_CMD_DEFINE_CURSOR = 19,
1630
-
SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
1631
-
SVGA_CMD_UPDATE_VERBOSE = 25,
1632
-
SVGA_CMD_FRONT_ROP_FILL = 29,
1633
-
SVGA_CMD_FENCE = 30,
1634
-
SVGA_CMD_ESCAPE = 33,
1635
-
SVGA_CMD_DEFINE_SCREEN = 34,
1636
-
SVGA_CMD_DESTROY_SCREEN = 35,
1637
-
SVGA_CMD_DEFINE_GMRFB = 36,
1638
-
SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
1639
-
SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
1640
-
SVGA_CMD_ANNOTATION_FILL = 39,
1641
-
SVGA_CMD_ANNOTATION_COPY = 40,
1642
-
SVGA_CMD_DEFINE_GMR2 = 41,
1643
-
SVGA_CMD_REMAP_GMR2 = 42,
1644
-
SVGA_CMD_DEAD = 43,
1645
-
SVGA_CMD_DEAD_2 = 44,
1646
-
SVGA_CMD_NOP = 45,
1647
-
SVGA_CMD_NOP_ERROR = 46,
1648
-
SVGA_CMD_MAX
634
+
SVGA_CMD_INVALID_CMD = 0,
635
+
SVGA_CMD_UPDATE = 1,
636
+
SVGA_CMD_RECT_COPY = 3,
637
+
SVGA_CMD_RECT_ROP_COPY = 14,
638
+
SVGA_CMD_DEFINE_CURSOR = 19,
639
+
SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
640
+
SVGA_CMD_UPDATE_VERBOSE = 25,
641
+
SVGA_CMD_FRONT_ROP_FILL = 29,
642
+
SVGA_CMD_FENCE = 30,
643
+
SVGA_CMD_ESCAPE = 33,
644
+
SVGA_CMD_DEFINE_SCREEN = 34,
645
+
SVGA_CMD_DESTROY_SCREEN = 35,
646
+
SVGA_CMD_DEFINE_GMRFB = 36,
647
+
SVGA_CMD_BLIT_GMRFB_TO_SCREEN = 37,
648
+
SVGA_CMD_BLIT_SCREEN_TO_GMRFB = 38,
649
+
SVGA_CMD_ANNOTATION_FILL = 39,
650
+
SVGA_CMD_ANNOTATION_COPY = 40,
651
+
SVGA_CMD_DEFINE_GMR2 = 41,
652
+
SVGA_CMD_REMAP_GMR2 = 42,
653
+
SVGA_CMD_DEAD = 43,
654
+
SVGA_CMD_DEAD_2 = 44,
655
+
SVGA_CMD_NOP = 45,
656
+
SVGA_CMD_NOP_ERROR = 46,
657
+
SVGA_CMD_MAX
1649
658
} SVGAFifoCmdId;
1650
659
1651
-
#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
1652
-
#define SVGA_CMD_MAX_ARGS 64
660
+
#define SVGA_CMD_MAX_DATASIZE (256 * 1024)
661
+
#define SVGA_CMD_MAX_ARGS 64
1653
662
663
+
#pragma pack(push, 1)
664
+
typedef struct {
665
+
uint32 x;
666
+
uint32 y;
667
+
uint32 width;
668
+
uint32 height;
669
+
} SVGAFifoCmdUpdate;
670
+
#pragma pack(pop)
1654
671
1655
-
/*
1656
-
* SVGA_CMD_UPDATE --
1657
-
*
1658
-
* This is a DMA transfer which copies from the Guest Framebuffer
1659
-
* (GFB) at BAR1 + SVGA_REG_FB_OFFSET to any screens which
1660
-
* intersect with the provided virtual rectangle.
1661
-
*
1662
-
* This command does not support using arbitrary guest memory as a
1663
-
* data source- it only works with the pre-defined GFB memory.
1664
-
* This command also does not support signed virtual coordinates.
1665
-
* If you have defined screens (using SVGA_CMD_DEFINE_SCREEN) with
1666
-
* negative root x/y coordinates, the negative portion of those
1667
-
* screens will not be reachable by this command.
1668
-
*
1669
-
* This command is not necessary when using framebuffer
1670
-
* traces. Traces are automatically enabled if the SVGA FIFO is
1671
-
* disabled, and you may explicitly enable/disable traces using
1672
-
* SVGA_REG_TRACES. With traces enabled, any write to the GFB will
1673
-
* automatically act as if a subsequent SVGA_CMD_UPDATE was issued.
1674
-
*
1675
-
* Traces and SVGA_CMD_UPDATE are the only supported ways to render
1676
-
* pseudocolor screen updates. The newer Screen Object commands
1677
-
* only support true color formats.
1678
-
*
1679
-
* Availability:
1680
-
* Always available.
1681
-
*/
672
+
#pragma pack(push, 1)
673
+
typedef struct {
674
+
uint32 srcX;
675
+
uint32 srcY;
676
+
uint32 destX;
677
+
uint32 destY;
678
+
uint32 width;
679
+
uint32 height;
680
+
} SVGAFifoCmdRectCopy;
681
+
#pragma pack(pop)
1682
682
1683
-
typedef
1684
-
#include "vmware_pack_begin.h"
1685
-
struct {
1686
-
uint32 x;
1687
-
uint32 y;
1688
-
uint32 width;
1689
-
uint32 height;
1690
-
}
1691
-
#include "vmware_pack_end.h"
1692
-
SVGAFifoCmdUpdate;
683
+
#pragma pack(push, 1)
684
+
typedef struct {
685
+
uint32 srcX;
686
+
uint32 srcY;
687
+
uint32 destX;
688
+
uint32 destY;
689
+
uint32 width;
690
+
uint32 height;
691
+
uint32 rop;
692
+
} SVGAFifoCmdRectRopCopy;
693
+
#pragma pack(pop)
1693
694
695
+
#pragma pack(push, 1)
696
+
typedef struct {
697
+
uint32 id;
698
+
uint32 hotspotX;
699
+
uint32 hotspotY;
700
+
uint32 width;
701
+
uint32 height;
702
+
uint32 andMaskDepth;
703
+
uint32 xorMaskDepth;
1694
704
1695
-
/*
1696
-
* SVGA_CMD_RECT_COPY --
1697
-
*
1698
-
* Perform a rectangular DMA transfer from one area of the GFB to
1699
-
* another, and copy the result to any screens which intersect it.
1700
-
*
1701
-
* Availability:
1702
-
* SVGA_CAP_RECT_COPY
1703
-
*/
705
+
} SVGAFifoCmdDefineCursor;
706
+
#pragma pack(pop)
1704
707
1705
-
typedef
1706
-
#include "vmware_pack_begin.h"
1707
-
struct {
1708
-
uint32 srcX;
1709
-
uint32 srcY;
1710
-
uint32 destX;
1711
-
uint32 destY;
1712
-
uint32 width;
1713
-
uint32 height;
1714
-
}
1715
-
#include "vmware_pack_end.h"
1716
-
SVGAFifoCmdRectCopy;
708
+
#pragma pack(push, 1)
709
+
typedef struct {
710
+
uint32 id;
711
+
uint32 hotspotX;
712
+
uint32 hotspotY;
713
+
uint32 width;
714
+
uint32 height;
1717
715
716
+
} SVGAFifoCmdDefineAlphaCursor;
717
+
#pragma pack(pop)
1718
718
1719
-
/*
1720
-
* SVGA_CMD_RECT_ROP_COPY --
1721
-
*
1722
-
* Perform a rectangular DMA transfer from one area of the GFB to
1723
-
* another, and copy the result to any screens which intersect it.
1724
-
* The value of ROP may only be SVGA_ROP_COPY, and this command is
1725
-
* only supported for backwards compatibility reasons.
1726
-
*
1727
-
* Availability:
1728
-
* SVGA_CAP_RECT_COPY
1729
-
*/
719
+
#pragma pack(push, 1)
720
+
typedef struct {
721
+
uint32 hotspotX;
722
+
uint32 hotspotY;
723
+
uint32 width;
724
+
uint32 height;
725
+
uint32 andMaskDepth;
726
+
uint32 xorMaskDepth;
1730
727
1731
-
typedef
1732
-
#include "vmware_pack_begin.h"
1733
-
struct {
1734
-
uint32 srcX;
1735
-
uint32 srcY;
1736
-
uint32 destX;
1737
-
uint32 destY;
1738
-
uint32 width;
1739
-
uint32 height;
1740
-
uint32 rop;
1741
-
}
1742
-
#include "vmware_pack_end.h"
1743
-
SVGAFifoCmdRectRopCopy;
728
+
} SVGAGBColorCursorHeader;
729
+
#pragma pack(pop)
1744
730
731
+
#pragma pack(push, 1)
732
+
typedef struct {
733
+
uint32 hotspotX;
734
+
uint32 hotspotY;
735
+
uint32 width;
736
+
uint32 height;
1745
737
1746
-
/*
1747
-
* SVGA_CMD_DEFINE_CURSOR --
1748
-
*
1749
-
* Provide a new cursor image, as an AND/XOR mask.
1750
-
*
1751
-
* The recommended way to position the cursor overlay is by using
1752
-
* the SVGA_FIFO_CURSOR_* registers, supported by the
1753
-
* SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1754
-
*
1755
-
* Availability:
1756
-
* SVGA_CAP_CURSOR
1757
-
*/
1758
-
1759
-
typedef
1760
-
#include "vmware_pack_begin.h"
1761
-
struct {
1762
-
uint32 id; /* Reserved, must be zero. */
1763
-
uint32 hotspotX;
1764
-
uint32 hotspotY;
1765
-
uint32 width;
1766
-
uint32 height;
1767
-
uint32 andMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
1768
-
uint32 xorMaskDepth; /* Value must be 1 or equal to BITS_PER_PIXEL */
1769
-
/*
1770
-
* Followed by scanline data for AND mask, then XOR mask.
1771
-
* Each scanline is padded to a 32-bit boundary.
1772
-
*/
1773
-
}
1774
-
#include "vmware_pack_end.h"
1775
-
SVGAFifoCmdDefineCursor;
1776
-
1777
-
1778
-
/*
1779
-
* SVGA_CMD_DEFINE_ALPHA_CURSOR --
1780
-
*
1781
-
* Provide a new cursor image, in 32-bit BGRA format.
1782
-
*
1783
-
* The recommended way to position the cursor overlay is by using
1784
-
* the SVGA_FIFO_CURSOR_* registers, supported by the
1785
-
* SVGA_FIFO_CAP_CURSOR_BYPASS_3 capability.
1786
-
*
1787
-
* Availability:
1788
-
* SVGA_CAP_ALPHA_CURSOR
1789
-
*/
1790
-
1791
-
typedef
1792
-
#include "vmware_pack_begin.h"
1793
-
struct {
1794
-
uint32 id; /* Reserved, must be zero. */
1795
-
uint32 hotspotX;
1796
-
uint32 hotspotY;
1797
-
uint32 width;
1798
-
uint32 height;
1799
-
/* Followed by scanline data */
1800
-
}
1801
-
#include "vmware_pack_end.h"
1802
-
SVGAFifoCmdDefineAlphaCursor;
1803
-
1804
-
1805
-
/*
1806
-
* Provide a new large cursor image, as an AND/XOR mask.
1807
-
*
1808
-
* Should only be used for CursorMob functionality
1809
-
*/
1810
-
1811
-
typedef
1812
-
#include "vmware_pack_begin.h"
1813
-
struct {
1814
-
uint32 hotspotX;
1815
-
uint32 hotspotY;
1816
-
uint32 width;
1817
-
uint32 height;
1818
-
uint32 andMaskDepth;
1819
-
uint32 xorMaskDepth;
1820
-
/*
1821
-
* Followed by scanline data for AND mask, then XOR mask.
1822
-
* Each scanline is padded to a 32-bit boundary.
1823
-
*/
1824
-
}
1825
-
#include "vmware_pack_end.h"
1826
-
SVGAGBColorCursorHeader;
1827
-
1828
-
1829
-
/*
1830
-
* Provide a new large cursor image, in 32-bit BGRA format.
1831
-
*
1832
-
* Should only be used for CursorMob functionality
1833
-
*/
1834
-
1835
-
typedef
1836
-
#include "vmware_pack_begin.h"
1837
-
struct {
1838
-
uint32 hotspotX;
1839
-
uint32 hotspotY;
1840
-
uint32 width;
1841
-
uint32 height;
1842
-
/* Followed by scanline data */
1843
-
}
1844
-
#include "vmware_pack_end.h"
1845
-
SVGAGBAlphaCursorHeader;
1846
-
1847
-
/*
1848
-
* Define the SVGA guest backed cursor types
1849
-
*/
738
+
} SVGAGBAlphaCursorHeader;
739
+
#pragma pack(pop)
1850
740
1851
741
typedef enum {
1852
-
SVGA_COLOR_CURSOR = 0,
1853
-
SVGA_ALPHA_CURSOR = 1,
742
+
SVGA_COLOR_CURSOR = 0,
743
+
SVGA_ALPHA_CURSOR = 1,
1854
744
} SVGAGBCursorType;
1855
745
1856
-
/*
1857
-
* Provide a new large cursor image.
1858
-
*
1859
-
* Should only be used for CursorMob functionality
1860
-
*/
746
+
#pragma pack(push, 1)
747
+
typedef struct {
748
+
SVGAGBCursorType type;
749
+
union {
750
+
SVGAGBColorCursorHeader colorHeader;
751
+
SVGAGBAlphaCursorHeader alphaHeader;
752
+
} header;
753
+
uint32 sizeInBytes;
1861
754
1862
-
typedef
1863
-
#include "vmware_pack_begin.h"
1864
-
struct {
1865
-
SVGAGBCursorType type;
1866
-
union {
1867
-
SVGAGBColorCursorHeader colorHeader;
1868
-
SVGAGBAlphaCursorHeader alphaHeader;
1869
-
} header;
1870
-
uint32 sizeInBytes;
1871
-
/*
1872
-
* Followed by the cursor data
1873
-
*/
1874
-
}
1875
-
#include "vmware_pack_end.h"
1876
-
SVGAGBCursorHeader;
755
+
} SVGAGBCursorHeader;
756
+
#pragma pack(pop)
1877
757
758
+
#pragma pack(push, 1)
759
+
typedef struct {
760
+
uint32 x;
761
+
uint32 y;
762
+
uint32 width;
763
+
uint32 height;
764
+
uint32 reason;
765
+
} SVGAFifoCmdUpdateVerbose;
766
+
#pragma pack(pop)
1878
767
1879
-
/*
1880
-
* SVGA_CMD_UPDATE_VERBOSE --
1881
-
*
1882
-
* Just like SVGA_CMD_UPDATE, but also provide a per-rectangle
1883
-
* 'reason' value, an opaque cookie which is used by internal
1884
-
* debugging tools. Third party drivers should not use this
1885
-
* command.
1886
-
*
1887
-
* Availability:
1888
-
* SVGA_CAP_EXTENDED_FIFO
1889
-
*/
768
+
#pragma pack(push, 1)
769
+
typedef struct {
770
+
uint32 color;
771
+
uint32 x;
772
+
uint32 y;
773
+
uint32 width;
774
+
uint32 height;
775
+
uint32 rop;
776
+
} SVGAFifoCmdFrontRopFill;
777
+
#pragma pack(pop)
1890
778
1891
-
typedef
1892
-
#include "vmware_pack_begin.h"
1893
-
struct {
1894
-
uint32 x;
1895
-
uint32 y;
1896
-
uint32 width;
1897
-
uint32 height;
1898
-
uint32 reason;
1899
-
}
1900
-
#include "vmware_pack_end.h"
1901
-
SVGAFifoCmdUpdateVerbose;
779
+
#pragma pack(push, 1)
780
+
typedef struct {
781
+
uint32 fence;
782
+
} SVGAFifoCmdFence;
783
+
#pragma pack(pop)
1902
784
785
+
#pragma pack(push, 1)
786
+
typedef struct {
787
+
uint32 nsid;
788
+
uint32 size;
1903
789
1904
-
/*
1905
-
* SVGA_CMD_FRONT_ROP_FILL --
1906
-
*
1907
-
* This is a hint which tells the SVGA device that the driver has
1908
-
* just filled a rectangular region of the GFB with a solid
1909
-
* color. Instead of reading these pixels from the GFB, the device
1910
-
* can assume that they all equal 'color'. This is primarily used
1911
-
* for remote desktop protocols.
1912
-
*
1913
-
* Availability:
1914
-
* SVGA_FIFO_CAP_ACCELFRONT
1915
-
*/
790
+
} SVGAFifoCmdEscape;
791
+
#pragma pack(pop)
1916
792
1917
-
#define SVGA_ROP_COPY 0x03
793
+
#pragma pack(push, 1)
794
+
typedef struct {
795
+
SVGAScreenObject screen;
796
+
} SVGAFifoCmdDefineScreen;
797
+
#pragma pack(pop)
1918
798
1919
-
typedef
1920
-
#include "vmware_pack_begin.h"
1921
-
struct {
1922
-
uint32 color; /* In the same format as the GFB */
1923
-
uint32 x;
1924
-
uint32 y;
1925
-
uint32 width;
1926
-
uint32 height;
1927
-
uint32 rop; /* Must be SVGA_ROP_COPY */
1928
-
}
1929
-
#include "vmware_pack_end.h"
1930
-
SVGAFifoCmdFrontRopFill;
799
+
#pragma pack(push, 1)
800
+
typedef struct {
801
+
uint32 screenId;
802
+
} SVGAFifoCmdDestroyScreen;
803
+
#pragma pack(pop)
1931
804
805
+
#pragma pack(push, 1)
806
+
typedef struct {
807
+
SVGAGuestPtr ptr;
808
+
uint32 bytesPerLine;
809
+
SVGAGMRImageFormat format;
810
+
} SVGAFifoCmdDefineGMRFB;
811
+
#pragma pack(pop)
1932
812
1933
-
/*
1934
-
* SVGA_CMD_FENCE --
1935
-
*
1936
-
* Insert a synchronization fence. When the SVGA device reaches
1937
-
* this command, it will copy the 'fence' value into the
1938
-
* SVGA_FIFO_FENCE register. It will also compare the fence against
1939
-
* SVGA_FIFO_FENCE_GOAL. If the fence matches the goal and the
1940
-
* SVGA_IRQFLAG_FENCE_GOAL interrupt is enabled, the device will
1941
-
* raise this interrupt.
1942
-
*
1943
-
* Availability:
1944
-
* SVGA_FIFO_FENCE for this command,
1945
-
* SVGA_CAP_IRQMASK for SVGA_FIFO_FENCE_GOAL.
1946
-
*/
813
+
#pragma pack(push, 1)
814
+
typedef struct {
815
+
SVGASignedPoint srcOrigin;
816
+
SVGASignedRect destRect;
817
+
uint32 destScreenId;
818
+
} SVGAFifoCmdBlitGMRFBToScreen;
819
+
#pragma pack(pop)
1947
820
1948
-
typedef
1949
-
#include "vmware_pack_begin.h"
1950
-
struct {
1951
-
uint32 fence;
1952
-
}
1953
-
#include "vmware_pack_end.h"
1954
-
SVGAFifoCmdFence;
821
+
#pragma pack(push, 1)
822
+
typedef struct {
823
+
SVGASignedPoint destOrigin;
824
+
SVGASignedRect srcRect;
825
+
uint32 srcScreenId;
826
+
} SVGAFifoCmdBlitScreenToGMRFB;
827
+
#pragma pack(pop)
1955
828
829
+
#pragma pack(push, 1)
830
+
typedef struct {
831
+
SVGAColorBGRX color;
832
+
} SVGAFifoCmdAnnotationFill;
833
+
#pragma pack(pop)
1956
834
1957
-
/*
1958
-
* SVGA_CMD_ESCAPE --
1959
-
*
1960
-
* Send an extended or vendor-specific variable length command.
1961
-
* This is used for video overlay, third party plugins, and
1962
-
* internal debugging tools. See svga_escape.h
1963
-
*
1964
-
* Availability:
1965
-
* SVGA_FIFO_CAP_ESCAPE
1966
-
*/
835
+
#pragma pack(push, 1)
836
+
typedef struct {
837
+
SVGASignedPoint srcOrigin;
838
+
uint32 srcScreenId;
839
+
} SVGAFifoCmdAnnotationCopy;
840
+
#pragma pack(pop)
1967
841
1968
-
typedef
1969
-
#include "vmware_pack_begin.h"
1970
-
struct {
1971
-
uint32 nsid;
1972
-
uint32 size;
1973
-
/* followed by 'size' bytes of data */
1974
-
}
1975
-
#include "vmware_pack_end.h"
1976
-
SVGAFifoCmdEscape;
1977
-
1978
-
1979
-
/*
1980
-
* SVGA_CMD_DEFINE_SCREEN --
1981
-
*
1982
-
* Define or redefine an SVGAScreenObject. See the description of
1983
-
* SVGAScreenObject above. The video driver is responsible for
1984
-
* generating new screen IDs. They should be small positive
1985
-
* integers. The virtual device will have an implementation
1986
-
* specific upper limit on the number of screen IDs
1987
-
* supported. Drivers are responsible for recycling IDs. The first
1988
-
* valid ID is zero.
1989
-
*
1990
-
* - Interaction with other registers:
1991
-
*
1992
-
* For backwards compatibility, when the GFB mode registers (WIDTH,
1993
-
* HEIGHT, PITCHLOCK, BITS_PER_PIXEL) are modified, the SVGA device
1994
-
* deletes all screens other than screen #0, and redefines screen
1995
-
* #0 according to the specified mode. Drivers that use
1996
-
* SVGA_CMD_DEFINE_SCREEN should destroy or redefine screen #0.
1997
-
*
1998
-
* If you use screen objects, do not use the legacy multi-mon
1999
-
* registers (SVGA_REG_NUM_GUEST_DISPLAYS, SVGA_REG_DISPLAY_*).
2000
-
*
2001
-
* Availability:
2002
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2003
-
*/
2004
-
2005
-
typedef
2006
-
#include "vmware_pack_begin.h"
2007
-
struct {
2008
-
SVGAScreenObject screen; /* Variable-length according to version */
2009
-
}
2010
-
#include "vmware_pack_end.h"
2011
-
SVGAFifoCmdDefineScreen;
2012
-
2013
-
2014
-
/*
2015
-
* SVGA_CMD_DESTROY_SCREEN --
2016
-
*
2017
-
* Destroy an SVGAScreenObject. Its ID is immediately available for
2018
-
* re-use.
2019
-
*
2020
-
* Availability:
2021
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2022
-
*/
2023
-
2024
-
typedef
2025
-
#include "vmware_pack_begin.h"
2026
-
struct {
2027
-
uint32 screenId;
2028
-
}
2029
-
#include "vmware_pack_end.h"
2030
-
SVGAFifoCmdDestroyScreen;
2031
-
2032
-
2033
-
/*
2034
-
* SVGA_CMD_DEFINE_GMRFB --
2035
-
*
2036
-
* This command sets a piece of SVGA device state called the
2037
-
* Guest Memory Region Framebuffer, or GMRFB. The GMRFB is a
2038
-
* piece of light-weight state which identifies the location and
2039
-
* format of an image in guest memory or in BAR1. The GMRFB has
2040
-
* an arbitrary size, and it doesn't need to match the geometry
2041
-
* of the GFB or any screen object.
2042
-
*
2043
-
* The GMRFB can be redefined as often as you like. You could
2044
-
* always use the same GMRFB, you could redefine it before
2045
-
* rendering from a different guest screen, or you could even
2046
-
* redefine it before every blit.
2047
-
*
2048
-
* There are multiple ways to use this command. The simplest way is
2049
-
* to use it to move the framebuffer either to elsewhere in the GFB
2050
-
* (BAR1) memory region, or to a user-defined GMR. This lets a
2051
-
* driver use a framebuffer allocated entirely out of normal system
2052
-
* memory, which we encourage.
2053
-
*
2054
-
* Another way to use this command is to set up a ring buffer of
2055
-
* updates in GFB memory. If a driver wants to ensure that no
2056
-
* frames are skipped by the SVGA device, it is important that the
2057
-
* driver not modify the source data for a blit until the device is
2058
-
* done processing the command. One efficient way to accomplish
2059
-
* this is to use a ring of small DMA buffers. Each buffer is used
2060
-
* for one blit, then we move on to the next buffer in the
2061
-
* ring. The FENCE mechanism is used to protect each buffer from
2062
-
* re-use until the device is finished with that buffer's
2063
-
* corresponding blit.
2064
-
*
2065
-
* This command does not affect the meaning of SVGA_CMD_UPDATE.
2066
-
* UPDATEs always occur from the legacy GFB memory area. This
2067
-
* command has no support for pseudocolor GMRFBs. Currently only
2068
-
* true-color 15, 16, and 24-bit depths are supported. Future
2069
-
* devices may expose capabilities for additional framebuffer
2070
-
* formats.
2071
-
*
2072
-
* The default GMRFB value is undefined. Drivers must always send
2073
-
* this command at least once before performing any blit from the
2074
-
* GMRFB.
2075
-
*
2076
-
* Availability:
2077
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2078
-
*/
2079
-
2080
-
typedef
2081
-
#include "vmware_pack_begin.h"
2082
-
struct {
2083
-
SVGAGuestPtr ptr;
2084
-
uint32 bytesPerLine;
2085
-
SVGAGMRImageFormat format;
2086
-
}
2087
-
#include "vmware_pack_end.h"
2088
-
SVGAFifoCmdDefineGMRFB;
2089
-
2090
-
2091
-
/*
2092
-
* SVGA_CMD_BLIT_GMRFB_TO_SCREEN --
2093
-
*
2094
-
* This is a guest-to-host blit. It performs a DMA operation to
2095
-
* copy a rectangular region of pixels from the current GMRFB to
2096
-
* a ScreenObject.
2097
-
*
2098
-
* The destination coordinate may be specified relative to a
2099
-
* screen's origin. The provided screen ID must be valid.
2100
-
*
2101
-
* The SVGA device is guaranteed to finish reading from the GMRFB
2102
-
* by the time any subsequent FENCE commands are reached.
2103
-
*
2104
-
* This command consumes an annotation. See the
2105
-
* SVGA_CMD_ANNOTATION_* commands for details.
2106
-
*
2107
-
* Availability:
2108
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2109
-
*/
2110
-
2111
-
typedef
2112
-
#include "vmware_pack_begin.h"
2113
-
struct {
2114
-
SVGASignedPoint srcOrigin;
2115
-
SVGASignedRect destRect;
2116
-
uint32 destScreenId;
2117
-
}
2118
-
#include "vmware_pack_end.h"
2119
-
SVGAFifoCmdBlitGMRFBToScreen;
2120
-
2121
-
2122
-
/*
2123
-
* SVGA_CMD_BLIT_SCREEN_TO_GMRFB --
2124
-
*
2125
-
* This is a host-to-guest blit. It performs a DMA operation to
2126
-
* copy a rectangular region of pixels from a single ScreenObject
2127
-
* back to the current GMRFB.
2128
-
*
2129
-
* The source coordinate is specified relative to a screen's
2130
-
* origin. The provided screen ID must be valid. If any parameters
2131
-
* are invalid, the resulting pixel values are undefined.
2132
-
*
2133
-
* The SVGA device is guaranteed to finish writing to the GMRFB by
2134
-
* the time any subsequent FENCE commands are reached.
2135
-
*
2136
-
* Availability:
2137
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2138
-
*/
2139
-
2140
-
typedef
2141
-
#include "vmware_pack_begin.h"
2142
-
struct {
2143
-
SVGASignedPoint destOrigin;
2144
-
SVGASignedRect srcRect;
2145
-
uint32 srcScreenId;
2146
-
}
2147
-
#include "vmware_pack_end.h"
2148
-
SVGAFifoCmdBlitScreenToGMRFB;
2149
-
2150
-
2151
-
/*
2152
-
* SVGA_CMD_ANNOTATION_FILL --
2153
-
*
2154
-
* The annotation commands have been deprecated, should not be used
2155
-
* by new drivers. They used to provide performance hints to the SVGA
2156
-
* device about the content of screen updates, but newer SVGA devices
2157
-
* ignore these.
2158
-
*
2159
-
* Availability:
2160
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2161
-
*/
2162
-
2163
-
typedef
2164
-
#include "vmware_pack_begin.h"
2165
-
struct {
2166
-
SVGAColorBGRX color;
2167
-
}
2168
-
#include "vmware_pack_end.h"
2169
-
SVGAFifoCmdAnnotationFill;
2170
-
2171
-
2172
-
/*
2173
-
* SVGA_CMD_ANNOTATION_COPY --
2174
-
*
2175
-
* The annotation commands have been deprecated, should not be used
2176
-
* by new drivers. They used to provide performance hints to the SVGA
2177
-
* device about the content of screen updates, but newer SVGA devices
2178
-
* ignore these.
2179
-
*
2180
-
* Availability:
2181
-
* SVGA_FIFO_CAP_SCREEN_OBJECT or SVGA_FIFO_CAP_SCREEN_OBJECT_2
2182
-
*/
2183
-
2184
-
typedef
2185
-
#include "vmware_pack_begin.h"
2186
-
struct {
2187
-
SVGASignedPoint srcOrigin;
2188
-
uint32 srcScreenId;
2189
-
}
2190
-
#include "vmware_pack_end.h"
2191
-
SVGAFifoCmdAnnotationCopy;
2192
-
2193
-
2194
-
/*
2195
-
* SVGA_CMD_DEFINE_GMR2 --
2196
-
*
2197
-
* Define guest memory region v2. See the description of GMRs above.
2198
-
*
2199
-
* Availability:
2200
-
* SVGA_CAP_GMR2
2201
-
*/
2202
-
2203
-
typedef
2204
-
#include "vmware_pack_begin.h"
2205
-
struct {
2206
-
uint32 gmrId;
2207
-
uint32 numPages;
2208
-
}
2209
-
#include "vmware_pack_end.h"
2210
-
SVGAFifoCmdDefineGMR2;
2211
-
2212
-
2213
-
/*
2214
-
* SVGA_CMD_REMAP_GMR2 --
2215
-
*
2216
-
* Remap guest memory region v2. See the description of GMRs above.
2217
-
*
2218
-
* This command allows guest to modify a portion of an existing GMR by
2219
-
* invalidating it or reassigning it to different guest physical pages.
2220
-
* The pages are identified by physical page number (PPN). The pages
2221
-
* are assumed to be pinned and valid for DMA operations.
2222
-
*
2223
-
* Description of command flags:
2224
-
*
2225
-
* SVGA_REMAP_GMR2_VIA_GMR: If enabled, references a PPN list in a GMR.
2226
-
* The PPN list must not overlap with the remap region (this can be
2227
-
* handled trivially by referencing a separate GMR). If flag is
2228
-
* disabled, PPN list is appended to SVGARemapGMR command.
2229
-
*
2230
-
* SVGA_REMAP_GMR2_PPN64: If set, PPN list is in PPN64 format, otherwise
2231
-
* it is in PPN32 format.
2232
-
*
2233
-
* SVGA_REMAP_GMR2_SINGLE_PPN: If set, PPN list contains a single entry.
2234
-
* A single PPN can be used to invalidate a portion of a GMR or
2235
-
* map it to to a single guest scratch page.
2236
-
*
2237
-
* Availability:
2238
-
* SVGA_CAP_GMR2
2239
-
*/
842
+
#pragma pack(push, 1)
843
+
typedef struct {
844
+
uint32 gmrId;
845
+
uint32 numPages;
846
+
} SVGAFifoCmdDefineGMR2;
847
+
#pragma pack(pop)
2240
848
2241
849
typedef enum {
2242
-
SVGA_REMAP_GMR2_PPN32 = 0,
2243
-
SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
2244
-
SVGA_REMAP_GMR2_PPN64 = (1 << 1),
2245
-
SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
850
+
SVGA_REMAP_GMR2_PPN32 = 0,
851
+
SVGA_REMAP_GMR2_VIA_GMR = (1 << 0),
852
+
SVGA_REMAP_GMR2_PPN64 = (1 << 1),
853
+
SVGA_REMAP_GMR2_SINGLE_PPN = (1 << 2),
2246
854
} SVGARemapGMR2Flags;
2247
855
2248
-
typedef
2249
-
#include "vmware_pack_begin.h"
2250
-
struct {
2251
-
uint32 gmrId;
2252
-
SVGARemapGMR2Flags flags;
2253
-
uint32 offsetPages; /* offset in pages to begin remap */
2254
-
uint32 numPages; /* number of pages to remap */
2255
-
/*
2256
-
* Followed by additional data depending on SVGARemapGMR2Flags.
2257
-
*
2258
-
* If flag SVGA_REMAP_GMR2_VIA_GMR is set, single SVGAGuestPtr follows.
2259
-
* Otherwise an array of page descriptors in PPN32 or PPN64 format
2260
-
* (according to flag SVGA_REMAP_GMR2_PPN64) follows. If flag
2261
-
* SVGA_REMAP_GMR2_SINGLE_PPN is set, array contains a single entry.
2262
-
*/
2263
-
}
2264
-
#include "vmware_pack_end.h"
2265
-
SVGAFifoCmdRemapGMR2;
856
+
#pragma pack(push, 1)
857
+
typedef struct {
858
+
uint32 gmrId;
859
+
SVGARemapGMR2Flags flags;
860
+
uint32 offsetPages;
861
+
uint32 numPages;
2266
862
863
+
} SVGAFifoCmdRemapGMR2;
864
+
#pragma pack(pop)
2267
865
2268
-
/*
2269
-
* Size of SVGA device memory such as frame buffer and FIFO.
2270
-
*/
2271
-
#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480) /* bytes */
2272
-
#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
2273
-
#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
2274
-
#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
2275
-
#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
2276
-
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
866
+
#define SVGA_VRAM_MIN_SIZE (4 * 640 * 480)
867
+
#define SVGA_VRAM_MIN_SIZE_3D (16 * 1024 * 1024)
868
+
#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
869
+
#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
870
+
#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
871
+
#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
2277
872
#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024)
2278
873
#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024)
2279
874
#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024)
2280
875
#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024)
2281
876
#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
2282
877
2283
-
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
878
+
#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024)
2284
879
2285
880
#if defined(VMX86_SERVER)
2286
-
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
2287
-
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
2288
-
#define SVGA_FIFO_SIZE (256 * 1024)
2289
-
#define SVGA_FIFO_SIZE_3D (516 * 1024)
2290
-
#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
2291
-
#define SVGA_AUTODETECT_DEFAULT FALSE
881
+
#define SVGA_VRAM_SIZE (4 * 1024 * 1024)
882
+
#define SVGA_VRAM_SIZE_3D (64 * 1024 * 1024)
883
+
#define SVGA_FIFO_SIZE (256 * 1024)
884
+
#define SVGA_FIFO_SIZE_3D (516 * 1024)
885
+
#define SVGA_MEMORY_SIZE_DEFAULT (160 * 1024 * 1024)
886
+
#define SVGA_AUTODETECT_DEFAULT FALSE
2292
887
#else
2293
-
#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
2294
-
#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
2295
-
#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
2296
-
#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
2297
-
#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
2298
-
#define SVGA_AUTODETECT_DEFAULT TRUE
888
+
#define SVGA_VRAM_SIZE (16 * 1024 * 1024)
889
+
#define SVGA_VRAM_SIZE_3D SVGA_VRAM_MAX_SIZE
890
+
#define SVGA_FIFO_SIZE (2 * 1024 * 1024)
891
+
#define SVGA_FIFO_SIZE_3D SVGA_FIFO_SIZE
892
+
#define SVGA_MEMORY_SIZE_DEFAULT (768 * 1024 * 1024)
893
+
#define SVGA_AUTODETECT_DEFAULT TRUE
2299
894
#endif
2300
895
2301
-
#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
2302
-
#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
2303
-
2304
-
#define SVGA_PCI_REGS_PAGES (1)
896
+
#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
897
+
#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
2305
898
2306
899
#endif
+11
-3
drivers/gpu/drm/vmwgfx/device_include/svga_types.h
drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
+11
-3
drivers/gpu/drm/vmwgfx/device_include/svga_types.h
drivers/gpu/drm/vmwgfx/device_include/vm_basic_types.h
···
1
1
/* SPDX-License-Identifier: GPL-2.0 OR MIT */
2
2
/**********************************************************
3
-
* Copyright 2015 VMware, Inc.
3
+
* Copyright 2015-2021 VMware, Inc.
4
4
*
5
5
* Permission is hereby granted, free of charge, to any person
6
6
* obtaining a copy of this software and associated documentation
···
23
23
* SOFTWARE.
24
24
*
25
25
**********************************************************/
26
-
#ifndef _SVGA_TYPES_H_
27
-
#define _SVGA_TYPES_H_
26
+
#ifndef VM_BASIC_TYPES_H
27
+
#define VM_BASIC_TYPES_H
28
+
28
29
#include <linux/kernel.h>
29
30
#include <linux/mm.h>
30
31
#include <asm/page.h>
···
50
49
#define MAX_UINT16 U16_MAX
51
50
52
51
#define CONST64U(x) x##ULL
52
+
53
+
#ifndef MBYTES_SHIFT
54
+
#define MBYTES_SHIFT 20
55
+
#endif
56
+
#ifndef MBYTES_2_BYTES
57
+
#define MBYTES_2_BYTES(_nbytes) ((uint64)(_nbytes) << MBYTES_SHIFT)
58
+
#endif
53
59
54
60
/*
55
61
* MKS Guest Stats types
-2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
-2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_begin.h
-2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
-2
drivers/gpu/drm/vmwgfx/device_include/vmware_pack_end.h
+539
drivers/gpu/drm/vmwgfx/vmw_surface_cache.h
+539
drivers/gpu/drm/vmwgfx/vmw_surface_cache.h
···
1
+
/**********************************************************
2
+
* Copyright 2021 VMware, Inc.
3
+
* SPDX-License-Identifier: GPL-2.0 OR MIT
4
+
*
5
+
* Permission is hereby granted, free of charge, to any person
6
+
* obtaining a copy of this software and associated documentation
7
+
* files (the "Software"), to deal in the Software without
8
+
* restriction, including without limitation the rights to use, copy,
9
+
* modify, merge, publish, distribute, sublicense, and/or sell copies
10
+
* of the Software, and to permit persons to whom the Software is
11
+
* furnished to do so, subject to the following conditions:
12
+
*
13
+
* The above copyright notice and this permission notice shall be
14
+
* included in all copies or substantial portions of the Software.
15
+
*
16
+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17
+
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18
+
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19
+
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
20
+
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
21
+
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
22
+
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23
+
* SOFTWARE.
24
+
*
25
+
**********************************************************/
26
+
27
+
#ifndef VMW_SURFACE_CACHE_H
28
+
#define VMW_SURFACE_CACHE_H
29
+
30
+
#include "device_include/svga3d_surfacedefs.h"
31
+
32
+
#include <drm/vmwgfx_drm.h>
33
+
34
+
static inline u32 clamped_umul32(u32 a, u32 b)
35
+
{
36
+
uint64_t tmp = (uint64_t) a*b;
37
+
return (tmp > (uint64_t) ((u32) -1)) ? (u32) -1 : tmp;
38
+
}
39
+
40
+
/**
41
+
* vmw_surface_get_desc - Look up the appropriate SVGA3dSurfaceDesc for the
42
+
* given format.
43
+
*/
44
+
static inline const SVGA3dSurfaceDesc *
45
+
vmw_surface_get_desc(SVGA3dSurfaceFormat format)
46
+
{
47
+
if (format < ARRAY_SIZE(g_SVGA3dSurfaceDescs))
48
+
return &g_SVGA3dSurfaceDescs[format];
49
+
50
+
return &g_SVGA3dSurfaceDescs[SVGA3D_FORMAT_INVALID];
51
+
}
52
+
53
+
/**
54
+
* vmw_surface_get_mip_size - Given a base level size and the mip level,
55
+
* compute the size of the mip level.
56
+
*/
57
+
static inline struct drm_vmw_size
58
+
vmw_surface_get_mip_size(struct drm_vmw_size base_level, u32 mip_level)
59
+
{
60
+
struct drm_vmw_size size = {
61
+
.width = max_t(u32, base_level.width >> mip_level, 1),
62
+
.height = max_t(u32, base_level.height >> mip_level, 1),
63
+
.depth = max_t(u32, base_level.depth >> mip_level, 1)
64
+
};
65
+
66
+
return size;
67
+
}
68
+
69
+
static inline void
70
+
vmw_surface_get_size_in_blocks(const SVGA3dSurfaceDesc *desc,
71
+
const struct drm_vmw_size *pixel_size,
72
+
SVGA3dSize *block_size)
73
+
{
74
+
block_size->width = __KERNEL_DIV_ROUND_UP(pixel_size->width,
75
+
desc->blockSize.width);
76
+
block_size->height = __KERNEL_DIV_ROUND_UP(pixel_size->height,
77
+
desc->blockSize.height);
78
+
block_size->depth = __KERNEL_DIV_ROUND_UP(pixel_size->depth,
79
+
desc->blockSize.depth);
80
+
}
81
+
82
+
static inline bool
83
+
vmw_surface_is_planar_surface(const SVGA3dSurfaceDesc *desc)
84
+
{
85
+
return (desc->blockDesc & SVGA3DBLOCKDESC_PLANAR_YUV) != 0;
86
+
}
87
+
88
+
static inline u32
89
+
vmw_surface_calculate_pitch(const SVGA3dSurfaceDesc *desc,
90
+
const struct drm_vmw_size *size)
91
+
{
92
+
u32 pitch;
93
+
SVGA3dSize blocks;
94
+
95
+
vmw_surface_get_size_in_blocks(desc, size, &blocks);
96
+
97
+
pitch = blocks.width * desc->pitchBytesPerBlock;
98
+
99
+
return pitch;
100
+
}
101
+
102
+
/**
103
+
* vmw_surface_get_image_buffer_size - Calculates image buffer size.
104
+
*
105
+
* Return the number of bytes of buffer space required to store one image of a
106
+
* surface, optionally using the specified pitch.
107
+
*
108
+
* If pitch is zero, it is assumed that rows are tightly packed.
109
+
*
110
+
* This function is overflow-safe. If the result would have overflowed, instead
111
+
* we return MAX_UINT32.
112
+
*/
113
+
static inline u32
114
+
vmw_surface_get_image_buffer_size(const SVGA3dSurfaceDesc *desc,
115
+
const struct drm_vmw_size *size,
116
+
u32 pitch)
117
+
{
118
+
SVGA3dSize image_blocks;
119
+
u32 slice_size, total_size;
120
+
121
+
vmw_surface_get_size_in_blocks(desc, size, &image_blocks);
122
+
123
+
if (vmw_surface_is_planar_surface(desc)) {
124
+
total_size = clamped_umul32(image_blocks.width,
125
+
image_blocks.height);
126
+
total_size = clamped_umul32(total_size, image_blocks.depth);
127
+
total_size = clamped_umul32(total_size, desc->bytesPerBlock);
128
+
return total_size;
129
+
}
130
+
131
+
if (pitch == 0)
132
+
pitch = vmw_surface_calculate_pitch(desc, size);
133
+
134
+
slice_size = clamped_umul32(image_blocks.height, pitch);
135
+
total_size = clamped_umul32(slice_size, image_blocks.depth);
136
+
137
+
return total_size;
138
+
}
139
+
140
+
/**
141
+
* vmw_surface_get_serialized_size - Get the serialized size for the image.
142
+
*/
143
+
static inline u32
144
+
vmw_surface_get_serialized_size(SVGA3dSurfaceFormat format,
145
+
struct drm_vmw_size base_level_size,
146
+
u32 num_mip_levels,
147
+
u32 num_layers)
148
+
{
149
+
const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
150
+
u32 total_size = 0;
151
+
u32 mip;
152
+
153
+
for (mip = 0; mip < num_mip_levels; mip++) {
154
+
struct drm_vmw_size size =
155
+
vmw_surface_get_mip_size(base_level_size, mip);
156
+
total_size += vmw_surface_get_image_buffer_size(desc,
157
+
&size, 0);
158
+
}
159
+
160
+
return total_size * num_layers;
161
+
}
162
+
163
+
/**
164
+
* vmw_surface_get_serialized_size_extended - Returns the number of bytes
165
+
* required for a surface with given parameters. Support for sample count.
166
+
*/
167
+
static inline u32
168
+
vmw_surface_get_serialized_size_extended(SVGA3dSurfaceFormat format,
169
+
struct drm_vmw_size base_level_size,
170
+
u32 num_mip_levels,
171
+
u32 num_layers,
172
+
u32 num_samples)
173
+
{
174
+
uint64_t total_size =
175
+
vmw_surface_get_serialized_size(format,
176
+
base_level_size,
177
+
num_mip_levels,
178
+
num_layers);
179
+
total_size *= max_t(u32, 1, num_samples);
180
+
181
+
return min_t(uint64_t, total_size, (uint64_t)U32_MAX);
182
+
}
183
+
184
+
/**
185
+
* vmw_surface_get_pixel_offset - Compute the offset (in bytes) to a pixel
186
+
* in an image (or volume).
187
+
*
188
+
* @width: The image width in pixels.
189
+
* @height: The image height in pixels
190
+
*/
191
+
static inline u32
192
+
vmw_surface_get_pixel_offset(SVGA3dSurfaceFormat format,
193
+
u32 width, u32 height,
194
+
u32 x, u32 y, u32 z)
195
+
{
196
+
const SVGA3dSurfaceDesc *desc = vmw_surface_get_desc(format);
197
+
const u32 bw = desc->blockSize.width, bh = desc->blockSize.height;
198
+
const u32 bd = desc->blockSize.depth;
199
+
const u32 rowstride = __KERNEL_DIV_ROUND_UP(width, bw) *
200
+
desc->bytesPerBlock;
201
+
const u32 imgstride = __KERNEL_DIV_ROUND_UP(height, bh) * rowstride;
202
+
const u32 offset = (z / bd * imgstride +
203
+
y / bh * rowstride +
204
+
x / bw * desc->bytesPerBlock);
205
+
return offset;
206
+
}
207
+
208
+
static inline u32
209
+
vmw_surface_get_image_offset(SVGA3dSurfaceFormat format,
210
+
struct drm_vmw_size baseLevelSize,
211
+
u32 numMipLevels,
212
+
u32 face,
213
+
u32 mip)
214
+
215
+
{
216
+
u32 offset;
217
+
u32 mipChainBytes;
218
+
u32 mipChainBytesToLevel;
219
+
u32 i;
220
+
const SVGA3dSurfaceDesc *desc;
221
+
struct drm_vmw_size mipSize;
222
+
u32 bytes;
223
+
224
+
desc = vmw_surface_get_desc(format);
225
+
226
+
mipChainBytes = 0;
227
+
mipChainBytesToLevel = 0;
228
+
for (i = 0; i < numMipLevels; i++) {
229
+
mipSize = vmw_surface_get_mip_size(baseLevelSize, i);
230
+
bytes = vmw_surface_get_image_buffer_size(desc, &mipSize, 0);
231
+
mipChainBytes += bytes;
232
+
if (i < mip)
233
+
mipChainBytesToLevel += bytes;
234
+
}
235
+
236
+
offset = mipChainBytes * face + mipChainBytesToLevel;
237
+
238
+
return offset;
239
+
}
240
+
241
+
242
+
/**
243
+
* vmw_surface_is_gb_screen_target_format - Is the specified format usable as
244
+
* a ScreenTarget?
245
+
* (with just the GBObjects cap-bit
246
+
* set)
247
+
* @format: format to queried
248
+
*
249
+
* RETURNS:
250
+
* true if queried format is valid for screen targets
251
+
*/
252
+
static inline bool
253
+
vmw_surface_is_gb_screen_target_format(SVGA3dSurfaceFormat format)
254
+
{
255
+
return (format == SVGA3D_X8R8G8B8 ||
256
+
format == SVGA3D_A8R8G8B8 ||
257
+
format == SVGA3D_R5G6B5 ||
258
+
format == SVGA3D_X1R5G5B5 ||
259
+
format == SVGA3D_A1R5G5B5 ||
260
+
format == SVGA3D_P8);
261
+
}
262
+
263
+
264
+
/**
265
+
* vmw_surface_is_dx_screen_target_format - Is the specified format usable as
266
+
* a ScreenTarget?
267
+
* (with DX10 enabled)
268
+
*
269
+
* @format: format to queried
270
+
*
271
+
* Results:
272
+
* true if queried format is valid for screen targets
273
+
*/
274
+
static inline bool
275
+
vmw_surface_is_dx_screen_target_format(SVGA3dSurfaceFormat format)
276
+
{
277
+
return (format == SVGA3D_R8G8B8A8_UNORM ||
278
+
format == SVGA3D_B8G8R8A8_UNORM ||
279
+
format == SVGA3D_B8G8R8X8_UNORM);
280
+
}
281
+
282
+
283
+
/**
284
+
* vmw_surface_is_screen_target_format - Is the specified format usable as a
285
+
* ScreenTarget?
286
+
* (for some combination of caps)
287
+
*
288
+
* @format: format to queried
289
+
*
290
+
* Results:
291
+
* true if queried format is valid for screen targets
292
+
*/
293
+
static inline bool
294
+
vmw_surface_is_screen_target_format(SVGA3dSurfaceFormat format)
295
+
{
296
+
if (vmw_surface_is_gb_screen_target_format(format)) {
297
+
return true;
298
+
}
299
+
return vmw_surface_is_dx_screen_target_format(format);
300
+
}
301
+
302
+
/**
303
+
* struct vmw_surface_mip - Mimpmap level information
304
+
* @bytes: Bytes required in the backing store of this mipmap level.
305
+
* @img_stride: Byte stride per image.
306
+
* @row_stride: Byte stride per block row.
307
+
* @size: The size of the mipmap.
308
+
*/
309
+
struct vmw_surface_mip {
310
+
size_t bytes;
311
+
size_t img_stride;
312
+
size_t row_stride;
313
+
struct drm_vmw_size size;
314
+
315
+
};
316
+
317
+
/**
318
+
* struct vmw_surface_cache - Cached surface information
319
+
* @desc: Pointer to the surface descriptor
320
+
* @mip: Array of mipmap level information. Valid size is @num_mip_levels.
321
+
* @mip_chain_bytes: Bytes required in the backing store for the whole chain
322
+
* of mip levels.
323
+
* @sheet_bytes: Bytes required in the backing store for a sheet
324
+
* representing a single sample.
325
+
* @num_mip_levels: Valid size of the @mip array. Number of mipmap levels in
326
+
* a chain.
327
+
* @num_layers: Number of slices in an array texture or number of faces in
328
+
* a cubemap texture.
329
+
*/
330
+
struct vmw_surface_cache {
331
+
const SVGA3dSurfaceDesc *desc;
332
+
struct vmw_surface_mip mip[DRM_VMW_MAX_MIP_LEVELS];
333
+
size_t mip_chain_bytes;
334
+
size_t sheet_bytes;
335
+
u32 num_mip_levels;
336
+
u32 num_layers;
337
+
};
338
+
339
+
/**
340
+
* struct vmw_surface_loc - Surface location
341
+
* @sheet: The multisample sheet.
342
+
* @sub_resource: Surface subresource. Defined as layer * num_mip_levels +
343
+
* mip_level.
344
+
* @x: X coordinate.
345
+
* @y: Y coordinate.
346
+
* @z: Z coordinate.
347
+
*/
348
+
struct vmw_surface_loc {
349
+
u32 sheet;
350
+
u32 sub_resource;
351
+
u32 x, y, z;
352
+
};
353
+
354
+
/**
355
+
* vmw_surface_subres - Compute the subresource from layer and mipmap.
356
+
* @cache: Surface layout data.
357
+
* @mip_level: The mipmap level.
358
+
* @layer: The surface layer (face or array slice).
359
+
*
360
+
* Return: The subresource.
361
+
*/
362
+
static inline u32 vmw_surface_subres(const struct vmw_surface_cache *cache,
363
+
u32 mip_level, u32 layer)
364
+
{
365
+
return cache->num_mip_levels * layer + mip_level;
366
+
}
367
+
368
+
/**
369
+
* vmw_surface_setup_cache - Build a surface cache entry
370
+
* @size: The surface base level dimensions.
371
+
* @format: The surface format.
372
+
* @num_mip_levels: Number of mipmap levels.
373
+
* @num_layers: Number of layers.
374
+
* @cache: Pointer to a struct vmw_surface_cach object to be filled in.
375
+
*
376
+
* Return: Zero on success, -EINVAL on invalid surface layout.
377
+
*/
378
+
static inline int vmw_surface_setup_cache(const struct drm_vmw_size *size,
379
+
SVGA3dSurfaceFormat format,
380
+
u32 num_mip_levels,
381
+
u32 num_layers,
382
+
u32 num_samples,
383
+
struct vmw_surface_cache *cache)
384
+
{
385
+
const SVGA3dSurfaceDesc *desc;
386
+
u32 i;
387
+
388
+
memset(cache, 0, sizeof(*cache));
389
+
cache->desc = desc = vmw_surface_get_desc(format);
390
+
cache->num_mip_levels = num_mip_levels;
391
+
cache->num_layers = num_layers;
392
+
for (i = 0; i < cache->num_mip_levels; i++) {
393
+
struct vmw_surface_mip *mip = &cache->mip[i];
394
+
395
+
mip->size = vmw_surface_get_mip_size(*size, i);
396
+
mip->bytes = vmw_surface_get_image_buffer_size
397
+
(desc, &mip->size, 0);
398
+
mip->row_stride =
399
+
__KERNEL_DIV_ROUND_UP(mip->size.width,
400
+
desc->blockSize.width) *
401
+
desc->bytesPerBlock * num_samples;
402
+
if (!mip->row_stride)
403
+
goto invalid_dim;
404
+
405
+
mip->img_stride =
406
+
__KERNEL_DIV_ROUND_UP(mip->size.height,
407
+
desc->blockSize.height) *
408
+
mip->row_stride;
409
+
if (!mip->img_stride)
410
+
goto invalid_dim;
411
+
412
+
cache->mip_chain_bytes += mip->bytes;
413
+
}
414
+
cache->sheet_bytes = cache->mip_chain_bytes * num_layers;
415
+
if (!cache->sheet_bytes)
416
+
goto invalid_dim;
417
+
418
+
return 0;
419
+
420
+
invalid_dim:
421
+
VMW_DEBUG_USER("Invalid surface layout for dirty tracking.\n");
422
+
return -EINVAL;
423
+
}
424
+
425
+
/**
426
+
* vmw_surface_get_loc - Get a surface location from an offset into the
427
+
* backing store
428
+
* @cache: Surface layout data.
429
+
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
430
+
* @offset: Offset into the surface backing store.
431
+
*/
432
+
static inline void
433
+
vmw_surface_get_loc(const struct vmw_surface_cache *cache,
434
+
struct vmw_surface_loc *loc,
435
+
size_t offset)
436
+
{
437
+
const struct vmw_surface_mip *mip = &cache->mip[0];
438
+
const SVGA3dSurfaceDesc *desc = cache->desc;
439
+
u32 layer;
440
+
int i;
441
+
442
+
loc->sheet = offset / cache->sheet_bytes;
443
+
offset -= loc->sheet * cache->sheet_bytes;
444
+
445
+
layer = offset / cache->mip_chain_bytes;
446
+
offset -= layer * cache->mip_chain_bytes;
447
+
for (i = 0; i < cache->num_mip_levels; ++i, ++mip) {
448
+
if (mip->bytes > offset)
449
+
break;
450
+
offset -= mip->bytes;
451
+
}
452
+
453
+
loc->sub_resource = vmw_surface_subres(cache, i, layer);
454
+
loc->z = offset / mip->img_stride;
455
+
offset -= loc->z * mip->img_stride;
456
+
loc->z *= desc->blockSize.depth;
457
+
loc->y = offset / mip->row_stride;
458
+
offset -= loc->y * mip->row_stride;
459
+
loc->y *= desc->blockSize.height;
460
+
loc->x = offset / desc->bytesPerBlock;
461
+
loc->x *= desc->blockSize.width;
462
+
}
463
+
464
+
/**
465
+
* vmw_surface_inc_loc - Clamp increment a surface location with one block
466
+
* size
467
+
* in each dimension.
468
+
* @loc: Pointer to a struct vmw_surface_loc to be incremented.
469
+
*
470
+
* When computing the size of a range as size = end - start, the range does not
471
+
* include the end element. However a location representing the last byte
472
+
* of a touched region in the backing store *is* included in the range.
473
+
* This function modifies such a location to match the end definition
474
+
* given as start + size which is the one used in a SVGA3dBox.
475
+
*/
476
+
static inline void
477
+
vmw_surface_inc_loc(const struct vmw_surface_cache *cache,
478
+
struct vmw_surface_loc *loc)
479
+
{
480
+
const SVGA3dSurfaceDesc *desc = cache->desc;
481
+
u32 mip = loc->sub_resource % cache->num_mip_levels;
482
+
const struct drm_vmw_size *size = &cache->mip[mip].size;
483
+
484
+
loc->sub_resource++;
485
+
loc->x += desc->blockSize.width;
486
+
if (loc->x > size->width)
487
+
loc->x = size->width;
488
+
loc->y += desc->blockSize.height;
489
+
if (loc->y > size->height)
490
+
loc->y = size->height;
491
+
loc->z += desc->blockSize.depth;
492
+
if (loc->z > size->depth)
493
+
loc->z = size->depth;
494
+
}
495
+
496
+
/**
497
+
* vmw_surface_min_loc - The start location in a subresource
498
+
* @cache: Surface layout data.
499
+
* @sub_resource: The subresource.
500
+
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
501
+
*/
502
+
static inline void
503
+
vmw_surface_min_loc(const struct vmw_surface_cache *cache,
504
+
u32 sub_resource,
505
+
struct vmw_surface_loc *loc)
506
+
{
507
+
loc->sheet = 0;
508
+
loc->sub_resource = sub_resource;
509
+
loc->x = loc->y = loc->z = 0;
510
+
}
511
+
512
+
/**
513
+
* vmw_surface_min_loc - The end location in a subresource
514
+
* @cache: Surface layout data.
515
+
* @sub_resource: The subresource.
516
+
* @loc: Pointer to a struct vmw_surface_loc to be filled in.
517
+
*
518
+
* Following the end definition given in vmw_surface_inc_loc(),
519
+
* Compute the end location of a surface subresource.
520
+
*/
521
+
static inline void
522
+
vmw_surface_max_loc(const struct vmw_surface_cache *cache,
523
+
u32 sub_resource,
524
+
struct vmw_surface_loc *loc)
525
+
{
526
+
const struct drm_vmw_size *size;
527
+
u32 mip;
528
+
529
+
loc->sheet = 0;
530
+
loc->sub_resource = sub_resource + 1;
531
+
mip = sub_resource % cache->num_mip_levels;
532
+
size = &cache->mip[mip].size;
533
+
loc->x = size->width;
534
+
loc->y = size->height;
535
+
loc->z = size->depth;
536
+
}
537
+
538
+
539
+
#endif /* VMW_SURFACE_CACHE_H */
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_binding.c
···
844
844
size_t cmd_size, view_id_size;
845
845
const struct vmw_resource *ctx = vmw_cbs_context(cbs);
846
846
847
-
vmw_collect_view_ids(cbs, loc, SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS);
847
+
vmw_collect_view_ids(cbs, loc, SVGA3D_DX_MAX_RENDER_TARGETS);
848
848
view_id_size = cbs->bind_cmd_count*sizeof(uint32);
849
849
cmd_size = sizeof(*cmd) + view_id_size;
850
850
cmd = VMW_CMD_CTX_RESERVE(ctx->dev_priv, cmd_size, ctx->id);
···
1440
1440
static void vmw_binding_build_asserts(void)
1441
1441
{
1442
1442
BUILD_BUG_ON(SVGA3D_NUM_SHADERTYPE_DX10 != 3);
1443
-
BUILD_BUG_ON(SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS > SVGA3D_RT_MAX);
1443
+
BUILD_BUG_ON(SVGA3D_DX_MAX_RENDER_TARGETS > SVGA3D_RT_MAX);
1444
1444
BUILD_BUG_ON(sizeof(uint32) != sizeof(u32));
1445
1445
1446
1446
/*
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_context.c
+2
-2
drivers/gpu/drm/vmwgfx/vmwgfx_context.c
···
185
185
container_of(res, struct vmw_user_context, res);
186
186
187
187
res->backup_size = (dx ? sizeof(SVGADXContextMobFormat) :
188
-
SVGA3D_CONTEXT_DATA_SIZE);
188
+
sizeof(SVGAGBContextData));
189
189
ret = vmw_resource_init(dev_priv, res, true,
190
190
res_free,
191
191
dx ? &vmw_dx_context_func :
···
259
259
goto out_early;
260
260
}
261
261
262
-
if (unlikely(res->id >= SVGA3D_MAX_CONTEXT_IDS)) {
262
+
if (unlikely(res->id >= SVGA3D_HB_MAX_CONTEXT_IDS)) {
263
263
DRM_ERROR("Out of hw context ids.\n");
264
264
vmw_resource_unreference(&res);
265
265
return -ENOMEM;
+5
-5
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
+5
-5
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.c
···
31
31
32
32
33
33
struct svga_3d_compat_cap {
34
-
SVGA3dCapsRecordHeader header;
35
-
SVGA3dCapPair pairs[SVGA3D_DEVCAP_MAX];
34
+
SVGA3dFifoCapsRecordHeader header;
35
+
SVGA3dFifoCapPair pairs[SVGA3D_DEVCAP_MAX];
36
36
};
37
37
38
38
···
64
64
if (size < pair_offset)
65
65
return -EINVAL;
66
66
67
-
max_size = (size - pair_offset) / sizeof(SVGA3dCapPair);
67
+
max_size = (size - pair_offset) / sizeof(SVGA3dFifoCapPair);
68
68
69
69
if (max_size > SVGA3D_DEVCAP_MAX)
70
70
max_size = SVGA3D_DEVCAP_MAX;
71
71
72
72
compat_cap->header.length =
73
-
(pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);
74
-
compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
73
+
(pair_offset + max_size * sizeof(SVGA3dFifoCapPair)) / sizeof(u32);
74
+
compat_cap->header.type = SVGA3D_FIFO_CAPS_RECORD_DEVCAPS;
75
75
76
76
for (i = 0; i < max_size; ++i) {
77
77
compat_cap->pairs[i][0] = i;
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_devcaps.h
+4
-5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+4
-5
drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
···
891
891
mem_size *= 3;
892
892
893
893
dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
894
-
dev_priv->prim_bb_mem =
895
-
vmw_read(dev_priv,
896
-
SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM);
894
+
dev_priv->max_primary_mem =
895
+
vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
897
896
dev_priv->max_mob_size =
898
897
vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE);
899
898
dev_priv->stdu_max_width =
···
911
912
} else {
912
913
dev_priv->texture_max_width = 8192;
913
914
dev_priv->texture_max_height = 8192;
914
-
dev_priv->prim_bb_mem = dev_priv->vram_size;
915
+
dev_priv->max_primary_mem = dev_priv->vram_size;
915
916
}
916
917
917
918
vmw_print_capabilities(dev_priv->capabilities);
···
935
936
(unsigned)dev_priv->memory_size / 1024);
936
937
}
937
938
DRM_INFO("Maximum display memory size is %llu kiB\n",
938
-
(uint64_t)dev_priv->prim_bb_mem / 1024);
939
+
(uint64_t)dev_priv->max_primary_mem / 1024);
939
940
940
941
/* Need mmio memory to check for fifo pitchlock cap. */
941
942
if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) &&
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_drv.h
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c
···
2365
2365
sizeof(SVGA3dRenderTargetViewId);
2366
2366
int ret;
2367
2367
2368
-
if (num_rt_view > SVGA3D_MAX_SIMULTANEOUS_RENDER_TARGETS) {
2368
+
if (num_rt_view > SVGA3D_DX_MAX_RENDER_TARGETS) {
2369
2369
VMW_DEBUG_USER("Invalid DX Rendertarget binding.\n");
2370
2370
return -EINVAL;
2371
2371
}
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+3
-3
drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
···
1487
1487
* SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM is not present vram size is
1488
1488
* limit on primary bounding box
1489
1489
*/
1490
-
if (pixel_mem > dev_priv->prim_bb_mem) {
1490
+
if (pixel_mem > dev_priv->max_primary_mem) {
1491
1491
VMW_DEBUG_KMS("Combined output size too large.\n");
1492
1492
return -EINVAL;
1493
1493
}
···
1497
1497
!(dev_priv->capabilities & SVGA_CAP_NO_BB_RESTRICTION)) {
1498
1498
bb_mem = (u64) bounding_box.x2 * bounding_box.y2 * 4;
1499
1499
1500
-
if (bb_mem > dev_priv->prim_bb_mem) {
1500
+
if (bb_mem > dev_priv->max_primary_mem) {
1501
1501
VMW_DEBUG_KMS("Topology is beyond supported limits.\n");
1502
1502
return -EINVAL;
1503
1503
}
···
1897
1897
{
1898
1898
return ((u64) pitch * (u64) height) < (u64)
1899
1899
((dev_priv->active_display_unit == vmw_du_screen_target) ?
1900
-
dev_priv->prim_bb_mem : dev_priv->vram_size);
1900
+
dev_priv->max_primary_mem : dev_priv->vram_size);
1901
1901
}
1902
1902
1903
1903
+18
-18
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
+18
-18
drivers/gpu/drm/vmwgfx/vmwgfx_mob.c
···
37
37
38
38
#ifdef CONFIG_64BIT
39
39
#define VMW_PPN_SIZE 8
40
-
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH64_0
41
-
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH64_1
42
-
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH64_2
40
+
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT64_0
41
+
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT64_1
42
+
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT64_2
43
43
#else
44
44
#define VMW_PPN_SIZE 4
45
-
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PTDEPTH_0
46
-
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PTDEPTH_1
47
-
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PTDEPTH_2
45
+
#define VMW_MOBFMT_PTDEPTH_0 SVGA3D_MOBFMT_PT_0
46
+
#define VMW_MOBFMT_PTDEPTH_1 SVGA3D_MOBFMT_PT_1
47
+
#define VMW_MOBFMT_PTDEPTH_2 SVGA3D_MOBFMT_PT_2
48
48
#endif
49
49
50
50
/*
···
70
70
* @page_table: Pointer to a struct vmw_mob holding the page table.
71
71
*/
72
72
static const struct vmw_otable pre_dx_tables[] = {
73
-
{VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
74
-
{VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
75
-
{VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
76
-
{VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
77
-
{VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
73
+
{VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
74
+
{VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
75
+
{VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
76
+
{VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
77
+
{VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
78
78
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE}
79
79
};
80
80
81
81
static const struct vmw_otable dx_tables[] = {
82
-
{VMWGFX_NUM_MOB * SVGA3D_OTABLE_MOB_ENTRY_SIZE, NULL, true},
83
-
{VMWGFX_NUM_GB_SURFACE * SVGA3D_OTABLE_SURFACE_ENTRY_SIZE, NULL, true},
84
-
{VMWGFX_NUM_GB_CONTEXT * SVGA3D_OTABLE_CONTEXT_ENTRY_SIZE, NULL, true},
85
-
{VMWGFX_NUM_GB_SHADER * SVGA3D_OTABLE_SHADER_ENTRY_SIZE, NULL, true},
86
-
{VMWGFX_NUM_GB_SCREEN_TARGET * SVGA3D_OTABLE_SCREEN_TARGET_ENTRY_SIZE,
82
+
{VMWGFX_NUM_MOB * sizeof(SVGAOTableMobEntry), NULL, true},
83
+
{VMWGFX_NUM_GB_SURFACE * sizeof(SVGAOTableSurfaceEntry), NULL, true},
84
+
{VMWGFX_NUM_GB_CONTEXT * sizeof(SVGAOTableContextEntry), NULL, true},
85
+
{VMWGFX_NUM_GB_SHADER * sizeof(SVGAOTableShaderEntry), NULL, true},
86
+
{VMWGFX_NUM_GB_SCREEN_TARGET * sizeof(SVGAOTableScreenTargetEntry),
87
87
NULL, VMWGFX_ENABLE_SCREEN_TARGET_OTABLE},
88
88
{VMWGFX_NUM_DXCONTEXT * sizeof(SVGAOTableDXContextEntry), NULL, true},
89
89
};
···
155
155
goto out_no_populate;
156
156
157
157
vmw_mob_pt_setup(mob, iter, otable->size >> PAGE_SHIFT);
158
-
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
158
+
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
159
159
}
160
160
161
161
cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
···
636
636
637
637
vmw_mob_pt_setup(mob, data_iter, num_data_pages);
638
638
pt_set_up = true;
639
-
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PTDEPTH_1;
639
+
mob->pt_level += VMW_MOBFMT_PTDEPTH_1 - SVGA3D_MOBFMT_PT_1;
640
640
}
641
641
642
642
vmw_fifo_resource_inc(dev_priv);
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+1
-1
drivers/gpu/drm/vmwgfx/vmwgfx_stdu.c
+38
-37
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
+38
-37
drivers/gpu/drm/vmwgfx/vmwgfx_surface.c
···
31
31
#include "vmwgfx_resource_priv.h"
32
32
#include "vmwgfx_so.h"
33
33
#include "vmwgfx_binding.h"
34
+
#include "vmw_surface_cache.h"
34
35
#include "device_include/svga3d_surfacedefs.h"
35
36
36
37
#define SVGA3D_FLAGS_64(upper32, lower32) (((uint64_t)upper32 << 32) | lower32)
···
79
78
* @boxes: Array of SVGA3dBoxes indicating dirty regions. One per subresource.
80
79
*/
81
80
struct vmw_surface_dirty {
82
-
struct svga3dsurface_cache cache;
81
+
struct vmw_surface_cache cache;
83
82
size_t size;
84
83
u32 num_subres;
85
84
SVGA3dBox boxes[];
···
308
307
{
309
308
uint32_t i;
310
309
struct vmw_surface_dma *cmd = (struct vmw_surface_dma *)cmd_space;
311
-
const struct svga3d_surface_desc *desc =
312
-
svga3dsurface_get_desc(srf->metadata.format);
310
+
const struct SVGA3dSurfaceDesc *desc =
311
+
vmw_surface_get_desc(srf->metadata.format);
313
312
314
313
for (i = 0; i < srf->metadata.num_sizes; ++i) {
315
314
SVGA3dCmdHeader *header = &cmd->header;
···
324
323
325
324
body->guest.ptr = *ptr;
326
325
body->guest.ptr.offset += cur_offset->bo_offset;
327
-
body->guest.pitch = svga3dsurface_calculate_pitch(desc,
328
-
cur_size);
326
+
body->guest.pitch = vmw_surface_calculate_pitch(desc, cur_size);
329
327
body->host.sid = srf->res.id;
330
328
body->host.face = cur_offset->face;
331
329
body->host.mipmap = cur_offset->mip;
···
342
342
343
343
suffix->suffixSize = sizeof(*suffix);
344
344
suffix->maximumOffset =
345
-
svga3dsurface_get_image_buffer_size(desc, cur_size,
345
+
vmw_surface_get_image_buffer_size(desc, cur_size,
346
346
body->guest.pitch);
347
347
suffix->flags.discard = 0;
348
348
suffix->flags.unsynchronized = 0;
···
432
432
goto out_no_id;
433
433
}
434
434
435
-
if (unlikely(res->id >= SVGA3D_MAX_SURFACE_IDS)) {
435
+
if (unlikely(res->id >= SVGA3D_HB_MAX_SURFACE_IDS)) {
436
436
ret = -EBUSY;
437
437
goto out_no_fifo;
438
438
}
···
751
751
struct vmw_surface_offset *cur_offset;
752
752
uint32_t num_sizes;
753
753
uint32_t size;
754
-
const struct svga3d_surface_desc *desc;
754
+
const SVGA3dSurfaceDesc *desc;
755
755
756
756
if (unlikely(vmw_user_surface_size == 0))
757
757
vmw_user_surface_size = ttm_round_pot(sizeof(*user_srf)) +
···
772
772
ttm_round_pot(num_sizes * sizeof(struct drm_vmw_size)) +
773
773
ttm_round_pot(num_sizes * sizeof(struct vmw_surface_offset));
774
774
775
-
desc = svga3dsurface_get_desc(req->format);
776
-
if (unlikely(desc->block_desc == SVGA3DBLOCKDESC_NONE)) {
775
+
desc = vmw_surface_get_desc(req->format);
776
+
if (unlikely(desc->blockDesc == SVGA3DBLOCKDESC_NONE)) {
777
777
VMW_DEBUG_USER("Invalid format %d for surface creation.\n",
778
778
req->format);
779
779
return -EINVAL;
···
833
833
834
834
for (i = 0; i < DRM_VMW_MAX_SURFACE_FACES; ++i) {
835
835
for (j = 0; j < metadata->mip_levels[i]; ++j) {
836
-
uint32_t stride = svga3dsurface_calculate_pitch
837
-
(desc, cur_size);
836
+
uint32_t stride = vmw_surface_calculate_pitch(
837
+
desc, cur_size);
838
838
839
839
cur_offset->face = i;
840
840
cur_offset->mip = j;
841
841
cur_offset->bo_offset = cur_bo_offset;
842
-
cur_bo_offset += svga3dsurface_get_image_buffer_size
842
+
cur_bo_offset += vmw_surface_get_image_buffer_size
843
843
(desc, cur_size, stride);
844
844
++cur_offset;
845
845
++cur_size;
···
1711
1711
* than partial z slices are dirtied.
1712
1712
*/
1713
1713
static void vmw_subres_dirty_add(struct vmw_surface_dirty *dirty,
1714
-
const struct svga3dsurface_loc *loc_start,
1715
-
const struct svga3dsurface_loc *loc_end)
1714
+
const struct vmw_surface_loc *loc_start,
1715
+
const struct vmw_surface_loc *loc_end)
1716
1716
{
1717
-
const struct svga3dsurface_cache *cache = &dirty->cache;
1717
+
const struct vmw_surface_cache *cache = &dirty->cache;
1718
1718
SVGA3dBox *box = &dirty->boxes[loc_start->sub_resource];
1719
1719
u32 mip = loc_start->sub_resource % cache->num_mip_levels;
1720
1720
const struct drm_vmw_size *size = &cache->mip[mip].size;
···
1760
1760
*/
1761
1761
static void vmw_subres_dirty_full(struct vmw_surface_dirty *dirty, u32 subres)
1762
1762
{
1763
-
const struct svga3dsurface_cache *cache = &dirty->cache;
1763
+
const struct vmw_surface_cache *cache = &dirty->cache;
1764
1764
u32 mip = subres % cache->num_mip_levels;
1765
1765
const struct drm_vmw_size *size = &cache->mip[mip].size;
1766
1766
SVGA3dBox *box = &dirty->boxes[subres];
···
1783
1783
struct vmw_surface_dirty *dirty =
1784
1784
(struct vmw_surface_dirty *) res->dirty;
1785
1785
size_t backup_end = res->backup_offset + res->backup_size;
1786
-
struct svga3dsurface_loc loc1, loc2;
1787
-
const struct svga3dsurface_cache *cache;
1786
+
struct vmw_surface_loc loc1, loc2;
1787
+
const struct vmw_surface_cache *cache;
1788
1788
1789
1789
start = max_t(size_t, start, res->backup_offset) - res->backup_offset;
1790
1790
end = min(end, backup_end) - res->backup_offset;
1791
1791
cache = &dirty->cache;
1792
-
svga3dsurface_get_loc(cache, &loc1, start);
1793
-
svga3dsurface_get_loc(cache, &loc2, end - 1);
1794
-
svga3dsurface_inc_loc(cache, &loc2);
1792
+
vmw_surface_get_loc(cache, &loc1, start);
1793
+
vmw_surface_get_loc(cache, &loc2, end - 1);
1794
+
vmw_surface_inc_loc(cache, &loc2);
1795
1795
1796
1796
if (loc1.sheet != loc2.sheet) {
1797
1797
u32 sub_res;
···
1811
1811
vmw_subres_dirty_add(dirty, &loc1, &loc2);
1812
1812
} else {
1813
1813
/* Dirty range covers multiple sub-resources */
1814
-
struct svga3dsurface_loc loc_min, loc_max;
1814
+
struct vmw_surface_loc loc_min, loc_max;
1815
1815
u32 sub_res;
1816
1816
1817
-
svga3dsurface_max_loc(cache, loc1.sub_resource, &loc_max);
1817
+
vmw_surface_max_loc(cache, loc1.sub_resource, &loc_max);
1818
1818
vmw_subres_dirty_add(dirty, &loc1, &loc_max);
1819
-
svga3dsurface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
1819
+
vmw_surface_min_loc(cache, loc2.sub_resource - 1, &loc_min);
1820
1820
vmw_subres_dirty_add(dirty, &loc_min, &loc2);
1821
1821
for (sub_res = loc1.sub_resource + 1;
1822
1822
sub_res < loc2.sub_resource - 1; ++sub_res)
···
1833
1833
{
1834
1834
struct vmw_surface_dirty *dirty =
1835
1835
(struct vmw_surface_dirty *) res->dirty;
1836
-
const struct svga3dsurface_cache *cache = &dirty->cache;
1836
+
const struct vmw_surface_cache *cache = &dirty->cache;
1837
1837
size_t backup_end = res->backup_offset + cache->mip_chain_bytes;
1838
1838
SVGA3dBox *box = &dirty->boxes[0];
1839
1839
u32 box_c2;
···
1876
1876
struct vmw_surface_dirty *dirty =
1877
1877
(struct vmw_surface_dirty *) res->dirty;
1878
1878
size_t alloc_size;
1879
-
const struct svga3dsurface_cache *cache = &dirty->cache;
1879
+
const struct vmw_surface_cache *cache = &dirty->cache;
1880
1880
struct {
1881
1881
SVGA3dCmdHeader header;
1882
1882
SVGA3dCmdDXUpdateSubResource body;
···
1989
1989
}
1990
1990
1991
1991
num_samples = max_t(u32, 1, metadata->multisample_count);
1992
-
ret = svga3dsurface_setup_cache(&metadata->base_size, metadata->format,
1992
+
ret = vmw_surface_setup_cache(&metadata->base_size, metadata->format,
1993
1993
num_mip, num_layers, num_samples,
1994
1994
&dirty->cache);
1995
1995
if (ret)
···
2080
2080
*srf_out = NULL;
2081
2081
2082
2082
if (req->scanout) {
2083
-
if (!svga3dsurface_is_screen_target_format(req->format)) {
2083
+
if (!vmw_surface_is_screen_target_format(req->format)) {
2084
2084
VMW_DEBUG_USER("Invalid Screen Target surface format.");
2085
2085
return -EINVAL;
2086
2086
}
···
2095
2095
return -EINVAL;
2096
2096
}
2097
2097
} else {
2098
-
const struct svga3d_surface_desc *desc =
2099
-
svga3dsurface_get_desc(req->format);
2098
+
const SVGA3dSurfaceDesc *desc =
2099
+
vmw_surface_get_desc(req->format);
2100
2100
2101
-
if (desc->block_desc == SVGA3DBLOCKDESC_NONE) {
2101
+
if (desc->blockDesc == SVGA3DBLOCKDESC_NONE) {
2102
2102
VMW_DEBUG_USER("Invalid surface format.\n");
2103
2103
return -EINVAL;
2104
2104
}
···
2147
2147
sample_count = metadata->multisample_count;
2148
2148
2149
2149
srf->res.backup_size =
2150
-
svga3dsurface_get_serialized_size_extended(metadata->format,
2151
-
metadata->base_size,
2152
-
metadata->mip_levels[0],
2153
-
num_layers,
2154
-
sample_count);
2150
+
vmw_surface_get_serialized_size_extended(
2151
+
metadata->format,
2152
+
metadata->base_size,
2153
+
metadata->mip_levels[0],
2154
+
num_layers,
2155
+
sample_count);
2155
2156
2156
2157
if (metadata->flags & SVGA3D_SURFACE_BIND_STREAM_OUTPUT)
2157
2158
srf->res.backup_size += sizeof(SVGA3dDXSOState);