Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Increase cp0 compare clockevent min_delta_ns from 0x30 to 0x300.
[MIPS] Cache: Provide more information on cache policy on bootup.
[MIPS] Fix aliasing bug in copy_user_highpage, take 2.
[MIPS] VPE loader: convert from struct class_ device to struct device
[MIPS] MIPSsim: Fix booting from NFS root
[MIPS] Alchemy: Get rid of au1xxx_irq_map_t.
[MIPS] Alchemy: Get rid of au_ffz().
[MIPS] Alchemy: Get rid of au_ffs().
[MIPS] Alchemy: cleanup interrupt code.
[MIPS] Lasat: Fix build by conversion to irq_cpu.c.
[MIPS] Lasat: Add #ifndef ... #endif include warpper to lasatint.h.
[MIPS] IP22: Enable -Werror.
[MIPS] IP22: Fix warning.
[MIPS] IP22: Complain if requesting the front panel irq failed.
[MIPS] vmlinux.lds.S: Handle KPROBES_TEXT.
[MIPS] vmlinux.lds.S: Fix handling of .notes in final link.
[MIPS] vmlinux.lds.S: Remove duplicate comment.
[MIPS] MSP71XX: Add workarounds file.
[MIPS] IP32: Fix build by conversion to irq_cpu.c.

arch/mips/Kconfig

···
 	select DMA_NONCOHERENT
 	select SYS_HAS_EARLY_PRINTK
 	select HW_HAS_PCI
+	select IRQ_CPU
 	select PCI_GT64XXX_PCI0
 	select MIPS_NILE4
 	select R5000_CPU_SCACHE
···
 	select BOOT_ELF32
 	select DMA_NONCOHERENT
 	select HW_HAS_PCI
+	select IRQ_CPU
 	select R5000_CPU_SCACHE
 	select RM7000_CPU_SCACHE
 	select SYS_HAS_CPU_R5000

arch/mips/au1000/common/au1xxx_irqmap.c

···
  * Careful if you change match 2 request!
  * The interrupt handler is called directly from the low level dispatch code.
  */
-au1xxx_irq_map_t __initdata au1xxx_ic0_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
 
 #if defined(CONFIG_SOC_AU1000)
 	{ AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},

arch/mips/au1000/common/dbdma.c

···
 
 	intstat = dbdma_gptr->ddma_intstat;
 	au_sync();
-	chan_index = au_ffs(intstat) - 1;
+	chan_index = ffs(intstat);
 
 	ctp = chan_tab_ptr[chan_index];
 	cp = ctp->chan_ptr;

arch/mips/au1000/common/irq.c

···
  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  *  675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/delay.h>
 #include <linux/bitops.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
 
-#include <asm/bootinfo.h>
-#include <asm/io.h>
 #include <asm/mipsregs.h>
-#include <asm/system.h>
 #include <asm/mach-au1x00/au1000.h>
 #ifdef CONFIG_MIPS_PB1000
 #include <asm/mach-pb1x00/pb1000.h>
-#endif
-
-#undef DEBUG_IRQ
-#ifdef DEBUG_IRQ
-/* note: prints function name for you */
-#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
-#else
-#define DPRINTK(fmt, args...)
 #endif
 
 #define EXT_INTC0_REQ0 2 /* IP 2 */
···
 
 static DEFINE_SPINLOCK(irq_lock);
 
-
-inline void local_enable_irq(unsigned int irq_nr)
-{
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		au_writel(1<<(irq_nr-32), IC1_MASKSET);
-		au_writel(1<<(irq_nr-32), IC1_WAKESET);
-	}
-	else {
-		au_writel(1<<irq_nr, IC0_MASKSET);
-		au_writel(1<<irq_nr, IC0_WAKESET);
-	}
-	au_sync();
-}
-
-
-inline void local_disable_irq(unsigned int irq_nr)
-{
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
-		au_writel(1<<(irq_nr-32), IC1_WAKECLR);
-	}
-	else {
-		au_writel(1<<irq_nr, IC0_MASKCLR);
-		au_writel(1<<irq_nr, IC0_WAKECLR);
-	}
-	au_sync();
-}
-
-
-static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
-{
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
-		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
-	}
-	else {
-		au_writel(1<<irq_nr, IC0_RISINGCLR);
-		au_writel(1<<irq_nr, IC0_MASKCLR);
-	}
-	au_sync();
-}
-
-
-static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
-{
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
-		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
-	}
-	else {
-		au_writel(1<<irq_nr, IC0_FALLINGCLR);
-		au_writel(1<<irq_nr, IC0_MASKCLR);
-	}
-	au_sync();
-}
-
-
-static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
-{
-	/* This may assume that we don't get interrupts from
-	 * both edges at once, or if we do, that we don't care.
-	 */
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
-		au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
-		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
-	}
-	else {
-		au_writel(1<<irq_nr, IC0_FALLINGCLR);
-		au_writel(1<<irq_nr, IC0_RISINGCLR);
-		au_writel(1<<irq_nr, IC0_MASKCLR);
-	}
-	au_sync();
-}
-
-
-static inline void mask_and_ack_level_irq(unsigned int irq_nr)
-{
-
-	local_disable_irq(irq_nr);
-	au_sync();
-#if defined(CONFIG_MIPS_PB1000)
-	if (irq_nr == AU1000_GPIO_15) {
-		au_writel(0x8000, PB1000_MDR); /* ack int */
-		au_sync();
-	}
-#endif
-	return;
-}
-
-
-static void end_irq(unsigned int irq_nr)
-{
-	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
-		local_enable_irq(irq_nr);
-	}
-#if defined(CONFIG_MIPS_PB1000)
-	if (irq_nr == AU1000_GPIO_15) {
-		au_writel(0x4000, PB1000_MDR); /* enable int */
-		au_sync();
-	}
-#endif
-}
-
-unsigned long save_local_and_disable(int controller)
-{
-	int i;
-	unsigned long flags, mask;
-
-	spin_lock_irqsave(&irq_lock, flags);
-	if (controller) {
-		mask = au_readl(IC1_MASKSET);
-		for (i=32; i<64; i++) {
-			local_disable_irq(i);
-		}
-	}
-	else {
-		mask = au_readl(IC0_MASKSET);
-		for (i=0; i<32; i++) {
-			local_disable_irq(i);
-		}
-	}
-	spin_unlock_irqrestore(&irq_lock, flags);
-
-	return mask;
-}
-
-void restore_local_and_enable(int controller, unsigned long mask)
-{
-	int i;
-	unsigned long flags, new_mask;
-
-	spin_lock_irqsave(&irq_lock, flags);
-	for (i=0; i<32; i++) {
-		if (mask & (1<<i)) {
-			if (controller)
-				local_enable_irq(i+32);
-			else
-				local_enable_irq(i);
-		}
-	}
-	if (controller)
-		new_mask = au_readl(IC1_MASKSET);
-	else
-		new_mask = au_readl(IC0_MASKSET);
-
-	spin_unlock_irqrestore(&irq_lock, flags);
-}
-
-
-static struct irq_chip rise_edge_irq_type = {
-	.name = "Au1000 Rise Edge",
-	.ack = mask_and_ack_rise_edge_irq,
-	.mask = local_disable_irq,
-	.mask_ack = mask_and_ack_rise_edge_irq,
-	.unmask = local_enable_irq,
-	.end = end_irq,
-};
-
-static struct irq_chip fall_edge_irq_type = {
-	.name = "Au1000 Fall Edge",
-	.ack = mask_and_ack_fall_edge_irq,
-	.mask = local_disable_irq,
-	.mask_ack = mask_and_ack_fall_edge_irq,
-	.unmask = local_enable_irq,
-	.end = end_irq,
-};
-
-static struct irq_chip either_edge_irq_type = {
-	.name = "Au1000 Rise or Fall Edge",
-	.ack = mask_and_ack_either_edge_irq,
-	.mask = local_disable_irq,
-	.mask_ack = mask_and_ack_either_edge_irq,
-	.unmask = local_enable_irq,
-	.end = end_irq,
-};
-
-static struct irq_chip level_irq_type = {
-	.name = "Au1000 Level",
-	.ack = mask_and_ack_level_irq,
-	.mask = local_disable_irq,
-	.mask_ack = mask_and_ack_level_irq,
-	.unmask = local_enable_irq,
-	.end = end_irq,
-};
-
-#ifdef CONFIG_PM
-void startup_match20_interrupt(irq_handler_t handler)
-{
-	struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
-
-	static struct irqaction action;
-	memset(&action, 0, sizeof(struct irqaction));
-
-	/* This is a big problem.... since we didn't use request_irq
-	 * when kernel/irq.c calls probe_irq_xxx this interrupt will
-	 * be probed for usage. This will end up disabling the device :(
-	 * Give it a bogus "action" pointer -- this will keep it from
-	 * getting auto-probed!
-	 *
-	 * By setting the status to match that of request_irq() we
-	 * can avoid it.  --cgray
-	*/
-	action.dev_id = handler;
-	action.flags = IRQF_DISABLED;
-	cpus_clear(action.mask);
-	action.name = "Au1xxx TOY";
-	action.handler = handler;
-	action.next = NULL;
-
-	desc->action = &action;
-	desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
-
-	local_enable_irq(AU1000_TOY_MATCH2_INT);
-}
-#endif
-
-static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
-{
-	if (irq_nr > AU1000_MAX_INTR) return;
-	/* Config2[n], Config1[n], Config0[n] */
-	if (irq_nr > AU1000_LAST_INTC0_INT) {
-		switch (type) {
-			case INTC_INT_RISE_EDGE: /* 0:0:1 */
-				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-				set_irq_chip(irq_nr, &rise_edge_irq_type);
-				break;
-			case INTC_INT_FALL_EDGE: /* 0:1:0 */
-				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG1SET);
-				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-				set_irq_chip(irq_nr, &fall_edge_irq_type);
-				break;
-			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
-				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG1SET);
-				au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-				set_irq_chip(irq_nr, &either_edge_irq_type);
-				break;
-			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
-				au_writel(1<<(irq_nr-32), IC1_CFG2SET);
-				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG0SET);
-				set_irq_chip(irq_nr, &level_irq_type);
-				break;
-			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
-				au_writel(1<<(irq_nr-32), IC1_CFG2SET);
-				au_writel(1<<(irq_nr-32), IC1_CFG1SET);
-				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-				set_irq_chip(irq_nr, &level_irq_type);
-				break;
-			case INTC_INT_DISABLED: /* 0:0:0 */
-				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
-				break;
-			default: /* disable the interrupt */
-				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
-				au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
-				au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
-				return;
-		}
-		if (int_req) /* assign to interrupt request 1 */
-			au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
-		else	     /* assign to interrupt request 0 */
-			au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
-		au_writel(1<<(irq_nr-32), IC1_SRCSET);
-		au_writel(1<<(irq_nr-32), IC1_MASKCLR);
-		au_writel(1<<(irq_nr-32), IC1_WAKECLR);
-	}
-	else {
-		switch (type) {
-			case INTC_INT_RISE_EDGE: /* 0:0:1 */
-				au_writel(1<<irq_nr, IC0_CFG2CLR);
-				au_writel(1<<irq_nr, IC0_CFG1CLR);
-				au_writel(1<<irq_nr, IC0_CFG0SET);
-				set_irq_chip(irq_nr, &rise_edge_irq_type);
-				break;
-			case INTC_INT_FALL_EDGE: /* 0:1:0 */
-				au_writel(1<<irq_nr, IC0_CFG2CLR);
-				au_writel(1<<irq_nr, IC0_CFG1SET);
-				au_writel(1<<irq_nr, IC0_CFG0CLR);
-				set_irq_chip(irq_nr, &fall_edge_irq_type);
-				break;
-			case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
-				au_writel(1<<irq_nr, IC0_CFG2CLR);
-				au_writel(1<<irq_nr, IC0_CFG1SET);
-				au_writel(1<<irq_nr, IC0_CFG0SET);
-				set_irq_chip(irq_nr, &either_edge_irq_type);
-				break;
-			case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
-				au_writel(1<<irq_nr, IC0_CFG2SET);
-				au_writel(1<<irq_nr, IC0_CFG1CLR);
-				au_writel(1<<irq_nr, IC0_CFG0SET);
-				set_irq_chip(irq_nr, &level_irq_type);
-				break;
-			case INTC_INT_LOW_LEVEL: /* 1:1:0 */
-				au_writel(1<<irq_nr, IC0_CFG2SET);
-				au_writel(1<<irq_nr, IC0_CFG1SET);
-				au_writel(1<<irq_nr, IC0_CFG0CLR);
-				set_irq_chip(irq_nr, &level_irq_type);
-				break;
-			case INTC_INT_DISABLED: /* 0:0:0 */
-				au_writel(1<<irq_nr, IC0_CFG0CLR);
-				au_writel(1<<irq_nr, IC0_CFG1CLR);
-				au_writel(1<<irq_nr, IC0_CFG2CLR);
-				break;
-			default: /* disable the interrupt */
-				printk("unexpected int type %d (irq %d)\n", type, irq_nr);
-				au_writel(1<<irq_nr, IC0_CFG0CLR);
-				au_writel(1<<irq_nr, IC0_CFG1CLR);
-				au_writel(1<<irq_nr, IC0_CFG2CLR);
-				return;
-		}
-		if (int_req) /* assign to interrupt request 1 */
-			au_writel(1<<irq_nr, IC0_ASSIGNCLR);
-		else	     /* assign to interrupt request 0 */
-			au_writel(1<<irq_nr, IC0_ASSIGNSET);
-		au_writel(1<<irq_nr, IC0_SRCSET);
-		au_writel(1<<irq_nr, IC0_MASKCLR);
-		au_writel(1<<irq_nr, IC0_WAKECLR);
-	}
-	au_sync();
-}
-
-
-void __init arch_init_irq(void)
-{
-	int i;
-	unsigned long cp0_status;
-	au1xxx_irq_map_t *imp;
-	extern au1xxx_irq_map_t au1xxx_irq_map[];
-	extern au1xxx_irq_map_t au1xxx_ic0_map[];
-	extern int au1xxx_nr_irqs;
-	extern int au1xxx_ic0_nr_irqs;
-
-	cp0_status = read_c0_status();
-
-	/* Initialize interrupt controllers to a safe state.
-	*/
-	au_writel(0xffffffff, IC0_CFG0CLR);
-	au_writel(0xffffffff, IC0_CFG1CLR);
-	au_writel(0xffffffff, IC0_CFG2CLR);
-	au_writel(0xffffffff, IC0_MASKCLR);
-	au_writel(0xffffffff, IC0_ASSIGNSET);
-	au_writel(0xffffffff, IC0_WAKECLR);
-	au_writel(0xffffffff, IC0_SRCSET);
-	au_writel(0xffffffff, IC0_FALLINGCLR);
-	au_writel(0xffffffff, IC0_RISINGCLR);
-	au_writel(0x00000000, IC0_TESTBIT);
-
-	au_writel(0xffffffff, IC1_CFG0CLR);
-	au_writel(0xffffffff, IC1_CFG1CLR);
-	au_writel(0xffffffff, IC1_CFG2CLR);
-	au_writel(0xffffffff, IC1_MASKCLR);
-	au_writel(0xffffffff, IC1_ASSIGNSET);
-	au_writel(0xffffffff, IC1_WAKECLR);
-	au_writel(0xffffffff, IC1_SRCSET);
-	au_writel(0xffffffff, IC1_FALLINGCLR);
-	au_writel(0xffffffff, IC1_RISINGCLR);
-	au_writel(0x00000000, IC1_TESTBIT);
-
-	/* Initialize IC0, which is fixed per processor.
-	*/
-	imp = au1xxx_ic0_map;
-	for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
-		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
-		imp++;
-	}
-
-	/* Now set up the irq mapping for the board.
-	*/
-	imp = au1xxx_irq_map;
-	for (i=0; i<au1xxx_nr_irqs; i++) {
-		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
-		imp++;
-	}
-
-	set_c0_status(ALLINTS);
-
-	/* Board specific IRQ initialization.
-	*/
-	if (board_init_irq)
-		(*board_init_irq)();
-}
-
-
-/*
- * Interrupts are nested. Even if an interrupt handler is registered
- * as "fast", we might get another interrupt before we return from
- * intcX_reqX_irqdispatch().
- */
-
-static void intc0_req0_irqdispatch(void)
-{
-	int irq = 0;
-	static unsigned long intc0_req0 = 0;
-
-	intc0_req0 |= au_readl(IC0_REQ0INT);
-
-	if (!intc0_req0)
-		return;
-#ifdef AU1000_USB_DEV_REQ_INT
-	/*
-	 * Because of the tight timing of SETUP token to reply
-	 * transactions, the USB devices-side packet complete
-	 * interrupt needs the highest priority.
-	 */
-	if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
-		intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
-		do_IRQ(AU1000_USB_DEV_REQ_INT);
-		return;
-	}
-#endif
-	irq = au_ffs(intc0_req0) - 1;
-	intc0_req0 &= ~(1<<irq);
-	do_IRQ(irq);
-}
-
-
-static void intc0_req1_irqdispatch(void)
-{
-	int irq = 0;
-	static unsigned long intc0_req1 = 0;
-
-	intc0_req1 |= au_readl(IC0_REQ1INT);
-
-	if (!intc0_req1)
-		return;
-
-	irq = au_ffs(intc0_req1) - 1;
-	intc0_req1 &= ~(1<<irq);
-	do_IRQ(irq);
-}
-
-
-/*
- * Interrupt Controller 1:
- * interrupts 32 - 63
- */
-static void intc1_req0_irqdispatch(void)
-{
-	int irq = 0;
-	static unsigned long intc1_req0 = 0;
-
-	intc1_req0 |= au_readl(IC1_REQ0INT);
-
-	if (!intc1_req0)
-		return;
-
-	irq = au_ffs(intc1_req0) - 1;
-	intc1_req0 &= ~(1<<irq);
-	irq += 32;
-	do_IRQ(irq);
-}
-
-
-static void intc1_req1_irqdispatch(void)
-{
-	int irq = 0;
-	static unsigned long intc1_req1 = 0;
-
-	intc1_req1 |= au_readl(IC1_REQ1INT);
-
-	if (!intc1_req1)
-		return;
-
-	irq = au_ffs(intc1_req1) - 1;
-	intc1_req1 &= ~(1<<irq);
-	irq += 32;
-	do_IRQ(irq);
-}
-
 #ifdef CONFIG_PM
 
-/* Save/restore the interrupt controller state.
+/*
+ * Save/restore the interrupt controller state.
  * Called from the save/restore core registers as part of the
  * au_sleep function in power.c.....maybe I should just pm_register()
  * them instead?
···
 static unsigned int	sleep_intctl_wake[2];
 static unsigned int	sleep_intctl_mask[2];
 
-void
-save_au1xxx_intctl(void)
+void save_au1xxx_intctl(void)
 {
 	sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 	sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
···
 	sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 }
 
-/* For most restore operations, we clear the entire register and
+/*
+ * For most restore operations, we clear the entire register and
  * then set the bits we found during the save.
  */
-void
-restore_au1xxx_intctl(void)
+void restore_au1xxx_intctl(void)
 {
 	au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 
···
 }
 #endif /* CONFIG_PM */
 
+
+inline void local_enable_irq(unsigned int irq_nr)
+{
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		au_writel(1 << (irq_nr - 32), IC1_MASKSET);
+		au_writel(1 << (irq_nr - 32), IC1_WAKESET);
+	} else {
+		au_writel(1 << irq_nr, IC0_MASKSET);
+		au_writel(1 << irq_nr, IC0_WAKESET);
+	}
+	au_sync();
+}
+
+
+inline void local_disable_irq(unsigned int irq_nr)
+{
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
+		au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
+	} else {
+		au_writel(1 << irq_nr, IC0_MASKCLR);
+		au_writel(1 << irq_nr, IC0_WAKECLR);
+	}
+	au_sync();
+}
+
+
+static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
+{
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
+		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
+	} else {
+		au_writel(1 << irq_nr, IC0_RISINGCLR);
+		au_writel(1 << irq_nr, IC0_MASKCLR);
+	}
+	au_sync();
+}
+
+
+static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
+{
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
+		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
+	} else {
+		au_writel(1 << irq_nr, IC0_FALLINGCLR);
+		au_writel(1 << irq_nr, IC0_MASKCLR);
+	}
+	au_sync();
+}
+
+
+static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
+{
+	/* This may assume that we don't get interrupts from
+	 * both edges at once, or if we do, that we don't care.
+	 */
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
+		au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
+		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
+	} else {
+		au_writel(1 << irq_nr, IC0_FALLINGCLR);
+		au_writel(1 << irq_nr, IC0_RISINGCLR);
+		au_writel(1 << irq_nr, IC0_MASKCLR);
+	}
+	au_sync();
+}
+
+
+static inline void mask_and_ack_level_irq(unsigned int irq_nr)
+{
+
+	local_disable_irq(irq_nr);
+	au_sync();
+#if defined(CONFIG_MIPS_PB1000)
+	if (irq_nr == AU1000_GPIO_15) {
+		au_writel(0x8000, PB1000_MDR); /* ack int */
+		au_sync();
+	}
+#endif
+	return;
+}
+
+
+static void end_irq(unsigned int irq_nr)
+{
+	if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
+		local_enable_irq(irq_nr);
+
+#if defined(CONFIG_MIPS_PB1000)
+	if (irq_nr == AU1000_GPIO_15) {
+		au_writel(0x4000, PB1000_MDR); /* enable int */
+		au_sync();
+	}
+#endif
+}
+
+unsigned long save_local_and_disable(int controller)
+{
+	int i;
+	unsigned long flags, mask;
+
+	spin_lock_irqsave(&irq_lock, flags);
+	if (controller) {
+		mask = au_readl(IC1_MASKSET);
+		for (i = 32; i < 64; i++)
+			local_disable_irq(i);
+	} else {
+		mask = au_readl(IC0_MASKSET);
+		for (i = 0; i < 32; i++)
+			local_disable_irq(i);
+	}
+	spin_unlock_irqrestore(&irq_lock, flags);
+
+	return mask;
+}
+
+void restore_local_and_enable(int controller, unsigned long mask)
+{
+	int i;
+	unsigned long flags, new_mask;
+
+	spin_lock_irqsave(&irq_lock, flags);
+	for (i = 0; i < 32; i++) {
+		if (mask & (1 << i)) {
+			if (controller)
+				local_enable_irq(i + 32);
+			else
+				local_enable_irq(i);
+		}
+	}
+	if (controller)
+		new_mask = au_readl(IC1_MASKSET);
+	else
+		new_mask = au_readl(IC0_MASKSET);
+
+	spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+
+static struct irq_chip rise_edge_irq_type = {
+	.name		= "Au1000 Rise Edge",
+	.ack		= mask_and_ack_rise_edge_irq,
+	.mask		= local_disable_irq,
+	.mask_ack	= mask_and_ack_rise_edge_irq,
+	.unmask		= local_enable_irq,
+	.end		= end_irq,
+};
+
+static struct irq_chip fall_edge_irq_type = {
+	.name		= "Au1000 Fall Edge",
+	.ack		= mask_and_ack_fall_edge_irq,
+	.mask		= local_disable_irq,
+	.mask_ack	= mask_and_ack_fall_edge_irq,
+	.unmask		= local_enable_irq,
+	.end		= end_irq,
+};
+
+static struct irq_chip either_edge_irq_type = {
+	.name		= "Au1000 Rise or Fall Edge",
+	.ack		= mask_and_ack_either_edge_irq,
+	.mask		= local_disable_irq,
+	.mask_ack	= mask_and_ack_either_edge_irq,
+	.unmask		= local_enable_irq,
+	.end		= end_irq,
+};
+
+static struct irq_chip level_irq_type = {
+	.name		= "Au1000 Level",
+	.ack		= mask_and_ack_level_irq,
+	.mask		= local_disable_irq,
+	.mask_ack	= mask_and_ack_level_irq,
+	.unmask		= local_enable_irq,
+	.end		= end_irq,
+};
+
+#ifdef CONFIG_PM
+void startup_match20_interrupt(irq_handler_t handler)
+{
+	struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
+
+	static struct irqaction action;
+	memset(&action, 0, sizeof(struct irqaction));
+
+	/*
+	 * This is a big problem.... since we didn't use request_irq
+	 * when kernel/irq.c calls probe_irq_xxx this interrupt will
+	 * be probed for usage. This will end up disabling the device :(
+	 * Give it a bogus "action" pointer -- this will keep it from
+	 * getting auto-probed!
+	 *
+	 * By setting the status to match that of request_irq() we
+	 * can avoid it.  --cgray
+	*/
+	action.dev_id = handler;
+	action.flags = IRQF_DISABLED;
+	cpus_clear(action.mask);
+	action.name = "Au1xxx TOY";
+	action.handler = handler;
+	action.next = NULL;
+
+	desc->action = &action;
+	desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
+
+	local_enable_irq(AU1000_TOY_MATCH2_INT);
+}
+#endif
+
+static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
+{
+	if (irq_nr > AU1000_MAX_INTR) return;
+	/* Config2[n], Config1[n], Config0[n] */
+	if (irq_nr > AU1000_LAST_INTC0_INT) {
+		switch (type) {
+		case INTC_INT_RISE_EDGE: /* 0:0:1 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
+			set_irq_chip(irq_nr, &rise_edge_irq_type);
+			break;
+		case INTC_INT_FALL_EDGE: /* 0:1:0 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
+			set_irq_chip(irq_nr, &fall_edge_irq_type);
+			break;
+		case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
+			set_irq_chip(irq_nr, &either_edge_irq_type);
+			break;
+		case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
+			set_irq_chip(irq_nr, &level_irq_type);
+			break;
+		case INTC_INT_LOW_LEVEL: /* 1:1:0 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
+			set_irq_chip(irq_nr, &level_irq_type);
+			break;
+		case INTC_INT_DISABLED: /* 0:0:0 */
+			au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
+			break;
+		default: /* disable the interrupt */
+			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
+			       type, irq_nr);
+			au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
+			au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
+			return;
+		}
+		if (int_req) /* assign to interrupt request 1 */
+			au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR);
+		else	     /* assign to interrupt request 0 */
+			au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET);
+		au_writel(1 << (irq_nr - 32), IC1_SRCSET);
+		au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
+		au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
+	} else {
+		switch (type) {
+		case INTC_INT_RISE_EDGE: /* 0:0:1 */
+			au_writel(1 << irq_nr, IC0_CFG2CLR);
+			au_writel(1 << irq_nr, IC0_CFG1CLR);
+			au_writel(1 << irq_nr, IC0_CFG0SET);
+			set_irq_chip(irq_nr, &rise_edge_irq_type);
+			break;
+		case INTC_INT_FALL_EDGE: /* 0:1:0 */
+			au_writel(1 << irq_nr, IC0_CFG2CLR);
+			au_writel(1 << irq_nr, IC0_CFG1SET);
+			au_writel(1 << irq_nr, IC0_CFG0CLR);
+			set_irq_chip(irq_nr, &fall_edge_irq_type);
+			break;
+		case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
+			au_writel(1 << irq_nr, IC0_CFG2CLR);
+			au_writel(1 << irq_nr, IC0_CFG1SET);
+			au_writel(1 << irq_nr, IC0_CFG0SET);
+			set_irq_chip(irq_nr, &either_edge_irq_type);
+			break;
+		case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
+			au_writel(1 << irq_nr, IC0_CFG2SET);
+			au_writel(1 << irq_nr, IC0_CFG1CLR);
+			au_writel(1 << irq_nr, IC0_CFG0SET);
+			set_irq_chip(irq_nr, &level_irq_type);
+			break;
+		case INTC_INT_LOW_LEVEL: /* 1:1:0 */
+			au_writel(1 << irq_nr, IC0_CFG2SET);
+			au_writel(1 << irq_nr, IC0_CFG1SET);
+			au_writel(1 << irq_nr, IC0_CFG0CLR);
+			set_irq_chip(irq_nr, &level_irq_type);
+			break;
+		case INTC_INT_DISABLED: /* 0:0:0 */
+			au_writel(1 << irq_nr, IC0_CFG0CLR);
+			au_writel(1 << irq_nr, IC0_CFG1CLR);
+			au_writel(1 << irq_nr, IC0_CFG2CLR);
+			break;
+		default: /* disable the interrupt */
+			printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
+			       type, irq_nr);
+			au_writel(1 << irq_nr, IC0_CFG0CLR);
+			au_writel(1 << irq_nr, IC0_CFG1CLR);
+			au_writel(1 << irq_nr, IC0_CFG2CLR);
+			return;
+		}
+		if (int_req) /* assign to interrupt request 1 */
+			au_writel(1 << irq_nr, IC0_ASSIGNCLR);
+		else	     /* assign to interrupt request 0 */
+			au_writel(1 << irq_nr, IC0_ASSIGNSET);
+		au_writel(1 << irq_nr, IC0_SRCSET);
+		au_writel(1 << irq_nr, IC0_MASKCLR);
+		au_writel(1 << irq_nr, IC0_WAKECLR);
+	}
+	au_sync();
+}
+
+/*
+ * Interrupts are nested. Even if an interrupt handler is registered
+ * as "fast", we might get another interrupt before we return from
+ * intcX_reqX_irqdispatch().
+ */
+
+static void intc0_req0_irqdispatch(void)
+{
+	int irq = 0;
+	static unsigned long intc0_req0;
+
+	intc0_req0 |= au_readl(IC0_REQ0INT);
+
+	if (!intc0_req0)
+		return;
+
+#ifdef AU1000_USB_DEV_REQ_INT
+	/*
+	 * Because of the tight timing of SETUP token to reply
+	 * transactions, the USB devices-side packet complete
+	 * interrupt needs the highest priority.
+	 */
+	if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) {
+		intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT);
+		do_IRQ(AU1000_USB_DEV_REQ_INT);
+		return;
+	}
+#endif
+	irq = ffs(intc0_req0);
+	intc0_req0 &= ~(1 << irq);
+	do_IRQ(irq);
+}
+
+
+static void intc0_req1_irqdispatch(void)
+{
+	int irq = 0;
+	static unsigned long intc0_req1;
+
+	intc0_req1 |= au_readl(IC0_REQ1INT);
+
+	if (!intc0_req1)
+		return;
+
+	irq = ffs(intc0_req1);
+	intc0_req1 &= ~(1 << irq);
+	do_IRQ(irq);
+}
+
+
+/*
+ * Interrupt Controller 1:
+ * interrupts 32 - 63
+ */
+static void intc1_req0_irqdispatch(void)
+{
+	int irq = 0;
+	static unsigned long intc1_req0;
+
+	intc1_req0 |= au_readl(IC1_REQ0INT);
+
+	if (!intc1_req0)
+		return;
+
+	irq = ffs(intc1_req0);
+	intc1_req0 &= ~(1 << irq);
+	irq += 32;
+	do_IRQ(irq);
+}
+
+
+static void intc1_req1_irqdispatch(void)
+{
+	int irq = 0;
+	static unsigned long intc1_req1;
+
+	intc1_req1 |= au_readl(IC1_REQ1INT);
+
+	if (!intc1_req1)
+		return;
+
+	irq = ffs(intc1_req1);
+	intc1_req1 &= ~(1 << irq);
+	irq += 32;
+	do_IRQ(irq);
+}
+
 asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
···
 		intc1_req1_irqdispatch();
 	else
 		spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+	int i;
+	unsigned long cp0_status;
+	struct au1xxx_irqmap *imp;
+	extern struct au1xxx_irqmap au1xxx_irq_map[];
+	extern struct au1xxx_irqmap au1xxx_ic0_map[];
+	extern int au1xxx_nr_irqs;
+	extern int au1xxx_ic0_nr_irqs;
+
+	cp0_status = read_c0_status();
+
+	/* Initialize interrupt controllers to a safe state.
+	*/
+	au_writel(0xffffffff, IC0_CFG0CLR);
+	au_writel(0xffffffff, IC0_CFG1CLR);
+	au_writel(0xffffffff, IC0_CFG2CLR);
+	au_writel(0xffffffff, IC0_MASKCLR);
+	au_writel(0xffffffff, IC0_ASSIGNSET);
+	au_writel(0xffffffff, IC0_WAKECLR);
+	au_writel(0xffffffff, IC0_SRCSET);
+	au_writel(0xffffffff, IC0_FALLINGCLR);
+	au_writel(0xffffffff, IC0_RISINGCLR);
+	au_writel(0x00000000, IC0_TESTBIT);
+
+	au_writel(0xffffffff, IC1_CFG0CLR);
+	au_writel(0xffffffff, IC1_CFG1CLR);
+	au_writel(0xffffffff, IC1_CFG2CLR);
+	au_writel(0xffffffff, IC1_MASKCLR);
+	au_writel(0xffffffff, IC1_ASSIGNSET);
+	au_writel(0xffffffff, IC1_WAKECLR);
+	au_writel(0xffffffff, IC1_SRCSET);
+	au_writel(0xffffffff, IC1_FALLINGCLR);
+	au_writel(0xffffffff, IC1_RISINGCLR);
+	au_writel(0x00000000, IC1_TESTBIT);
+
+	/* Initialize IC0, which is fixed per processor.
+	*/
+	imp = au1xxx_ic0_map;
+	for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
+		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
+		imp++;
+	}
+
+	/* Now set up the irq mapping for the board.
+	*/
+	imp = au1xxx_irq_map;
+	for (i = 0; i < au1xxx_nr_irqs; i++) {
+		setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
+		imp++;
+	}
+
+	set_c0_status(ALLINTS);
+
+	/* Board specific IRQ initialization.
+	*/
+	if (board_init_irq)
+		(*board_init_irq)();
 }

arch/mips/au1000/db1x00/irqmap.c

···
 #endif
 
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 
 #ifndef CONFIG_MIPS_MIRAGE
 #ifdef CONFIG_MIPS_DB1550

arch/mips/au1000/mtx-1/irqmap.c

···
  [7] = { -1, INTD, INTC, INTX, INTX},   /* IDSEL 07 - AdapterD-Slot1 (bottom) */
 };
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
        { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
        { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
        { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },

arch/mips/au1000/pb1000/irqmap.c

···
 #include <asm/system.h>
 #include <asm/mach-au1x00/au1000.h>
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
 };
 

arch/mips/au1000/pb1100/irqmap.c

···
 #include <asm/system.h>
 #include <asm/mach-au1x00/au1000.h>
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted#
 	{ AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG#
 	{ AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ#

arch/mips/au1000/pb1200/irqmap.c

···
 #define PB1200_INT_END DB1200_INT_END
 #endif
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
 };
 
···
 	bcsr->int_status = bisr;
 	for( ; bisr; bisr &= (bisr-1) )
 	{
-		extirq_nr = (PB1200_INT_BEGIN-1) + au_ffs(bisr);
+		extirq_nr = PB1200_INT_BEGIN + au_ffs(bisr);
 		/* Ack and dispatch IRQ */
 		do_IRQ(extirq_nr);
 	}

arch/mips/au1000/pb1500/irqmap.c

···
  [13] = { -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot */
 };
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },

arch/mips/au1000/pb1550/irqmap.c

···
  [13] =	{ -1, INTA, INTB, INTC, INTD},   /* IDSEL 13 - PCI slot 1 (right) */
 };
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
 	{ AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
 };

arch/mips/au1000/xxs1500/irqmap.c

···
 #include <asm/system.h>
 #include <asm/au1000.h>
 
-au1xxx_irq_map_t __initdata au1xxx_irq_map[] = {
+struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
 	{ AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0},
 	{ AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
 	{ AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },

arch/mips/kernel/time.c

···
 	cd->mult	= div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
 	cd->shift		= 32;
 	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
-	cd->min_delta_ns	= clockevent_delta2ns(0x30, cd);
+	cd->min_delta_ns	= clockevent_delta2ns(0x300, cd);
 
 	cd->rating		= 300;
 	cd->irq			= irq;

arch/mips/kernel/traps.c

···
 __setup("raw_show_trace", set_raw_show_trace);
 #endif
 
-static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
+static void show_backtrace(struct task_struct *task, const struct pt_regs *regs)
 {
 	unsigned long sp = regs->regs[29];
 	unsigned long ra = regs->regs[31];
···
  * This routine abuses get_user()/put_user() to reference pointers
  * with at least a bit of error checking ...
  */
-static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
+static void show_stacktrace(struct task_struct *task,
+	const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
 	long stackdata;
···
 	}
 }
 
-void show_regs(struct pt_regs *regs)
+static void __show_regs(const struct pt_regs *regs)
 {
 	const int field = 2 * sizeof(unsigned long);
 	unsigned int cause = regs->cp0_cause;
···
 	       cpu_name_string());
 }
 
-void show_registers(struct pt_regs *regs)
+/*
+ * FIXME: really the generic show_regs should take a const pointer argument.
+ */
+void show_regs(struct pt_regs *regs)
 {
-	show_regs(regs);
+	__show_regs((struct pt_regs *)regs);
+}
+
+void show_registers(const struct pt_regs *regs)
+{
+	__show_regs(regs);
 	print_modules();
 	printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
 	        current->comm, current->pid, current_thread_info(), current);
···
 
 static DEFINE_SPINLOCK(die_lock);
 
-void __noreturn die(const char * str, struct pt_regs * regs)
+void __noreturn die(const char * str, const struct pt_regs * regs)
 {
 	static int die_counter;
 #ifdef CONFIG_MIPS_MT_SMTC

arch/mips/kernel/vmlinux.lds.S

···
 #define mips mips
 OUTPUT_ARCH(mips)
 ENTRY(kernel_entry)
+PHDRS {
+	text PT_LOAD FLAGS(7);	/* RWX */
+	note PT_NOTE FLAGS(4);	/* R__ */
+}
 jiffies = JIFFIES;
 
 SECTIONS
···
 	 */
 
 	/* . = 0xa800000000300000; */
-	/* . = 0xa800000000300000; */
 	. = 0xffffffff80300000;
 #endif
 	. = LOADADDR;
···
 		TEXT_TEXT
 		SCHED_TEXT
 		LOCK_TEXT
+		KPROBES_TEXT
 		*(.fixup)
 		*(.gnu.warning)
-	} =0
+	} :text = 0
 	_etext = .;	/* End of text section */
 
 	/* Exception table */
···
 		*(__dbe_table)
 		__stop___dbe_table = .;
 	}
+
+	NOTES :text :note
+	.dummy : { *(.dummy) } :text
+
 	RODATA
 
 	/* writeable */
···
 	.gptab.sbss : {
 		*(.gptab.bss)
 		*(.gptab.sbss)
-	}
-	.note : {
-		*(.note)
 	}
 }

arch/mips/kernel/vpe.c

···
 }
 #endif
 
-static ssize_t store_kill(struct class_device *dev, const char *buf, size_t len)
+static ssize_t store_kill(struct device *dev, struct device_attribute *attr,
+			  const char *buf, size_t len)
 {
 	struct vpe *vpe = get_vpe(tclimit);
 	struct vpe_notifications *not;
···
 	return len;
 }
 
-static ssize_t show_ntcs(struct class_device *cd, char *buf)
+static ssize_t show_ntcs(struct device *cd, struct device_attribute *attr,
+			 char *buf)
 {
 	struct vpe *vpe = get_vpe(tclimit);
 
 	return sprintf(buf, "%d\n", vpe->ntcs);
 }
 
-static ssize_t store_ntcs(struct class_device *dev, const char *buf, size_t len)
+static ssize_t store_ntcs(struct device *dev, struct device_attribute *attr,
+			  const char *buf, size_t len)
 {
 	struct vpe *vpe = get_vpe(tclimit);
 	unsigned long new;
···
 	return -EINVAL;;
 }
 
-static struct class_device_attribute vpe_class_attributes[] = {
+static struct device_attribute vpe_class_attributes[] = {
 	__ATTR(kill, S_IWUSR, NULL, store_kill),
 	__ATTR(ntcs, S_IRUGO | S_IWUSR, show_ntcs, store_ntcs),
 	{}
 };
 
-static void vpe_class_device_release(struct class_device *cd)
+static void vpe_device_release(struct device *cd)
 {
 	kfree(cd);
 }
···
 struct class vpe_class = {
 	.name = "vpe",
 	.owner = THIS_MODULE,
-	.release = vpe_class_device_release,
-	.class_dev_attrs = vpe_class_attributes,
+	.dev_release = vpe_device_release,
+	.dev_attrs = vpe_class_attributes,
 };
 
-struct class_device vpe_device;
+struct device vpe_device;
 
 static int __init vpe_module_init(void)
 {
···
 		goto out_chrdev;
 	}
 
-	class_device_initialize(&vpe_device);
+	device_initialize(&vpe_device);
 	vpe_device.class	= &vpe_class,
 	vpe_device.parent	= NULL,
-	strlcpy(vpe_device.class_id, "vpe1", BUS_ID_SIZE);
+	strlcpy(vpe_device.bus_id, "vpe1", BUS_ID_SIZE);
 	vpe_device.devt = MKDEV(major, minor);
-	err = class_device_add(&vpe_device);
+	err = device_add(&vpe_device);
 	if (err) {
 		printk(KERN_ERR "Adding vpe_device failed\n");
 		goto out_class;
···
 		}
 	}
 
-	class_device_del(&vpe_device);
+	device_del(&vpe_device);
 	unregister_chrdev(major, module_name);
 }
 

arch/mips/lasat/interrupt.c

···
 #include <linux/kernel_stat.h>
 
 #include <asm/bootinfo.h>
+#include <asm/irq_cpu.h>
 #include <asm/lasat/lasatint.h>
 #include <asm/time.h>
 #include <asm/gdb-stub.h>
···
 	int irq;
 
 	if (cause & CAUSEF_IP7) {	/* R4000 count / compare IRQ */
-		ll_timer_interrupt(7);
+		do_IRQ(7);
 		return;
 	}
 
···
 
 	/* if int_status == 0, then the interrupt has already been cleared */
 	if (int_status) {
-		irq = ls1bit32(int_status);
+		irq = LASATINT_BASE + ls1bit32(int_status);
 
 		do_IRQ(irq);
 	}
···
 		panic("arch_init_irq: mips_machtype incorrect");
 	}
 
-	for (i = 0; i <= LASATINT_END; i++)
+	mips_cpu_irq_init();
+	for (i = LASATINT_BASE; i <= LASATINT_END; i++)
 		set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
 }

arch/mips/mipssim/sim_cmdline.c

···
 
 void  __init prom_init_cmdline(void)
 {
-	char *cp;
-	cp = arcs_cmdline;
-	/* Get boot line from environment? */
-	*cp = '\0';
+	/* XXX: Get boot line from environment? */
 }

arch/mips/mm/c-r4k.c

···
 
 	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
 	       icache_size >> 10,
-	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+	       cpu_has_vtag_icache ? "VIVT" : "VIPT",
 	       way_string[c->icache.ways], c->icache.linesz);
 
-	printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
-	       dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+	printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
+	       dcache_size >> 10, way_string[c->dcache.ways],
+	       (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
+	       (c->dcache.flags & MIPS_CACHE_ALIASES) ?
+			"cache aliases" : "no aliases",
+	       c->dcache.linesz);
 }
 
 /*

arch/mips/mm/init.c

···
 	void *vfrom, *vto;
 
 	vto = kmap_atomic(to, KM_USER1);
-	if (cpu_has_dc_aliases && !Page_dcache_dirty(from)) {
+	if (cpu_has_dc_aliases && page_mapped(from)) {
 		vfrom = kmap_coherent(from, vaddr);
 		copy_page(vto, vfrom);
 		kunmap_coherent();
···
 	struct page *page, unsigned long vaddr, void *dst, const void *src,
 	unsigned long len)
 {
-	if (cpu_has_dc_aliases) {
+	if (cpu_has_dc_aliases && page_mapped(page)) {
 		void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
 		memcpy(vto, src, len);
 		kunmap_coherent();
-	} else
+	} else {
 		memcpy(dst, src, len);
+		if (cpu_has_dc_aliases)
+			SetPageDcacheDirty(page);
+	}
 	if ((vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc)
 		flush_cache_page(vma, vaddr, page_to_pfn(page));
 }
···
 	struct page *page, unsigned long vaddr, void *dst, const void *src,
 	unsigned long len)
 {
-	if (cpu_has_dc_aliases) {
-		void *vfrom =
-			kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
+	if (cpu_has_dc_aliases && page_mapped(page)) {
+		void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
 		memcpy(dst, vfrom, len);
 		kunmap_coherent();
-	} else
+	} else {
 		memcpy(dst, src, len);
+		if (cpu_has_dc_aliases)
+			SetPageDcacheDirty(page);
+	}
 }
 
 EXPORT_SYMBOL(copy_from_user_page);

arch/mips/pci/pci-lasat.c

···
 #include <linux/pci.h>
 #include <linux/types.h>
 #include <asm/bootinfo.h>
+#include <asm/lasat/lasatint.h>
 
 extern struct pci_ops nile4_pci_ops;
 extern struct pci_ops gt64xxx_pci0_ops;
···
 
 arch_initcall(lasat_pci_setup);
 
-#define LASATINT_ETH1   0
-#define LASATINT_ETH0   1
-#define LASATINT_HDC    2
-#define LASATINT_COMP   3
-#define LASATINT_HDLC   4
-#define LASATINT_PCIA   5
-#define LASATINT_PCIB   6
-#define LASATINT_PCIC   7
-#define LASATINT_PCID   8
+#define LASATINT_ETH1   (LASATINT_BASE + 0)
+#define LASATINT_ETH0   (LASATINT_BASE + 1)
+#define LASATINT_HDC    (LASATINT_BASE + 2)
+#define LASATINT_COMP   (LASATINT_BASE + 3)
+#define LASATINT_HDLC   (LASATINT_BASE + 4)
+#define LASATINT_PCIA   (LASATINT_BASE + 5)
+#define LASATINT_PCIB   (LASATINT_BASE + 6)
+#define LASATINT_PCIC   (LASATINT_BASE + 7)
+#define LASATINT_PCID   (LASATINT_BASE + 8)
 
 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 {

arch/mips/sgi-ip22/Makefile

···
 	   ip22-time.o ip22-nvram.o ip22-platform.o ip22-reset.o ip22-setup.o
 
 obj-$(CONFIG_EISA)	+= ip22-eisa.o
+
+EXTRA_CFLAGS += -Werror

arch/mips/sgi-ip22/ip22-reset.c

···
 
 static int __init reboot_setup(void)
 {
+	int res;
+
 	_machine_restart = sgi_machine_restart;
 	_machine_halt = sgi_machine_halt;
 	pm_power_off = sgi_machine_power_off;
 
-	request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL);
+	res = request_irq(SGI_PANEL_IRQ, panel_int, 0, "Front Panel", NULL);
+	if (res) {
+		printk(KERN_ERR "Allocation of front panel IRQ failed\n");
+		return res;
+	}
+
 	init_timer(&blink_timer);
 	blink_timer.function = blink_timeout;
 	atomic_notifier_chain_register(&panic_notifier_list, &panic_block);

arch/mips/sgi-ip32/ip32-irq.c

···
 #include <linux/random.h>
 #include <linux/sched.h>
 
+#include <asm/irq_cpu.h>
 #include <asm/mipsregs.h>
 #include <asm/signal.h>
 #include <asm/system.h>
···
 #define DBG(x...)
 #endif
 
-/* O2 irq map
+/*
+ * O2 irq map
  *
  * IP0 -> software (ignored)
  * IP1 -> software (ignored)
···
  * IP4 -> (irq2) X unknown
  * IP5 -> (irq3) X unknown
  * IP6 -> (irq4) X unknown
- * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
+ * IP7 -> (irq5) 7 CPU count/compare timer (system timer)
  *
  * crime: (C)
  *
  * CRIME_INT_STAT 31:0:
  *
- * 0  -> 1  Video in 1
- * 1  -> 2  Video in 2
- * 2  -> 3  Video out
- * 3  -> 4  Mace ethernet
+ * 0  ->  8  Video in 1
+ * 1  ->  9 Video in 2
+ * 2  -> 10  Video out
+ * 3  -> 11  Mace ethernet
  * 4  -> S  SuperIO sub-interrupt
  * 5  -> M  Miscellaneous sub-interrupt
  * 6  -> A  Audio sub-interrupt
- * 7  -> 8  PCI bridge errors
- * 8  -> 9  PCI SCSI aic7xxx 0
- * 9  -> 10 PCI SCSI aic7xxx 1
- * 10 -> 11 PCI slot 0
- * 11 -> 12 unused (PCI slot 1)
- * 12 -> 13 unused (PCI slot 2)
- * 13 -> 14 unused (PCI shared 0)
- * 14 -> 15 unused (PCI shared 1)
- * 15 -> 16 unused (PCI shared 2)
- * 16 -> 17 GBE0 (E)
- * 17 -> 18 GBE1 (E)
- * 18 -> 19 GBE2 (E)
- * 19 -> 20 GBE3 (E)
- * 20 -> 21 CPU errors
- * 21 -> 22 Memory errors
- * 22 -> 23 RE empty edge (E)
- * 23 -> 24 RE full edge (E)
- * 24 -> 25 RE idle edge (E)
- * 25 -> 26 RE empty level
- * 26 -> 27 RE full level
- * 27 -> 28 RE idle level
- * 28 -> 29 unused (software 0) (E)
- * 29 -> 30 unused (software 1) (E)
- * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
- * 31 -> 32 VICE
+ * 7  -> 15  PCI bridge errors
+ * 8  -> 16  PCI SCSI aic7xxx 0
+ * 9  -> 17 PCI SCSI aic7xxx 1
+ * 10 -> 18 PCI slot 0
+ * 11 -> 19 unused (PCI slot 1)
+ * 12 -> 20 unused (PCI slot 2)
+ * 13 -> 21 unused (PCI shared 0)
+ * 14 -> 22 unused (PCI shared 1)
+ * 15 -> 23 unused (PCI shared 2)
+ * 16 -> 24 GBE0 (E)
+ * 17 -> 25 GBE1 (E)
+ * 18 -> 26 GBE2 (E)
+ * 19 -> 27 GBE3 (E)
+ * 20 -> 28 CPU errors
+ * 21 -> 29 Memory errors
+ * 22 -> 30 RE empty edge (E)
+ * 23 -> 31 RE full edge (E)
+ * 24 -> 32 RE idle edge (E)
+ * 25 -> 33 RE empty level
+ * 26 -> 34 RE full level
+ * 27 -> 35 RE idle level
+ * 28 -> 36 unused (software 0) (E)
+ * 29 -> 37 unused (software 1) (E)
+ * 30 -> 38 unused (software 2) - crime 1.5 CPU SysCorError (E)
+ * 31 -> 39 VICE
  *
  * S, M, A: Use the MACE ISA interrupt register
  * MACE_ISA_INT_STAT 31:0
  *
- * 0-7 -> 33-40 Audio
- * 8 -> 41 RTC
- * 9 -> 42 Keyboard
+ * 0-7 -> 40-47 Audio
+ * 8 -> 48 RTC
+ * 9 -> 49 Keyboard
  * 10 -> X Keyboard polled
- * 11 -> 44 Mouse
+ * 11 -> 51 Mouse
  * 12 -> X Mouse polled
- * 13-15 -> 46-48 Count/compare timers
- * 16-19 -> 49-52 Parallel (16 E)
- * 20-25 -> 53-58 Serial 1 (22 E)
- * 26-31 -> 59-64 Serial 2 (28 E)
+ * 13-15 -> 53-55 Count/compare timers
+ * 16-19 -> 56-59 Parallel (16 E)
+ * 20-25 -> 60-62 Serial 1 (22 E)
+ * 26-31 -> 66-71 Serial 2 (28 E)
  *
- * Note that this means IRQs 5-7, 43, and 45 do not exist.  This is a
+ * Note that this means IRQs 12-14, 50, and 52 do not exist.  This is a
  * different IRQ map than IRIX uses, but that's OK as Linux irq handling
  * is quite different anyway.
  */
···
 	.flags = IRQF_DISABLED,
 	.mask = CPU_MASK_NONE,
 	.name = "CRIME CPU error",
-};
-
-/*
- * For interrupts wired from a single device to the CPU.  Only the clock
- * uses this it seems, which is IRQ 0 and IP7.
- */
-
-static void enable_cpu_irq(unsigned int irq)
-{
-	set_c0_status(STATUSF_IP7);
-}
-
-static void disable_cpu_irq(unsigned int irq)
-{
-	clear_c0_status(STATUSF_IP7);
-}
-
-static void end_cpu_irq(unsigned int irq)
-{
-	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
-		enable_cpu_irq(irq);
-}
-
-static struct irq_chip ip32_cpu_interrupt = {
-	.name = "IP32 CPU",
-	.ack = disable_cpu_irq,
-	.mask = disable_cpu_irq,
-	.mask_ack = disable_cpu_irq,
-	.unmask = enable_cpu_irq,
-	.end = end_cpu_irq,
 };
 
 /*
···
 	uint64_t crime_int;
 	int irq = 0;
 
+	/*
+	 * Sanity check interrupt numbering enum.
+	 * MACE got 32 interrupts and there are 32 MACE ISA interrupts daisy
+	 * chained.
+	 */
+	BUILD_BUG_ON(CRIME_VICE_IRQ - MACE_VID_IN1_IRQ != 31);
+	BUILD_BUG_ON(MACEISA_SERIAL2_RDMAOR_IRQ - MACEISA_AUDIO_SW_IRQ != 31);
+
 	crime_int = crime->istat & crime_mask;
-	irq = __ffs(crime_int);
+	irq = MACE_VID_IN1_IRQ + __ffs(crime_int);
 	crime_int = 1 << irq;
 
 	if (crime_int & CRIME_MACEISA_INT_MASK) {
 		unsigned long mace_int = mace->perif.ctrl.istat;
-		irq = __ffs(mace_int & maceisa_mask) + 32;
+		irq = __ffs(mace_int & maceisa_mask) + MACEISA_AUDIO_SW_IRQ;
 	}
-	irq++;
+
 	DBG("*irq %u*\n", irq);
 	do_IRQ(irq);
 }
···
 
 static void ip32_irq5(void)
 {
-	do_IRQ(IP32_R4K_TIMER_IRQ);
+	do_IRQ(MIPS_CPU_IRQ_BASE + 7);
 }
 
 asmlinkage void plat_irq_dispatch(void)
···
 	mace->perif.ctrl.istat = 0;
 	mace->perif.ctrl.imask = 0;
 
-	for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
-		struct irq_chip *controller;
+	mips_cpu_irq_init();
+	for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) {
+		struct irq_chip *chip;
 
-		if (irq == IP32_R4K_TIMER_IRQ)
-			controller = &ip32_cpu_interrupt;
-		else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
-			controller = &ip32_mace_interrupt;
-		else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
-			controller = &ip32_macepci_interrupt;
-		else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
-			controller = &ip32_crime_interrupt;
-		else
-			controller = &ip32_maceisa_interrupt;
+		switch (irq) {
+		case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
+			chip = &ip32_mace_interrupt;
+			break;
+		case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
+			chip = &ip32_macepci_interrupt;
+			break;
+		case CRIME_GBE0_IRQ ... CRIME_VICE_IRQ:
+			chip = &ip32_crime_interrupt;
+			break;
+		default:
+			chip = &ip32_maceisa_interrupt;
+		}
 
-		set_irq_chip(irq, controller);
+		set_irq_chip(irq, chip);
 	}
 	setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
 	setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);

arch/mips/sgi-ip32/ip32-setup.c

···
 void __init plat_timer_setup(struct irqaction *irq)
 {
 	irq->handler = no_action;
-	setup_irq(IP32_R4K_TIMER_IRQ, irq);
+	setup_irq(MIPS_CPU_IRQ_BASE + 7, irq);
 }
 
 void __init plat_mem_setup(void)

include/asm-mips/ip32/ip32_ints.h

···
 #ifndef __ASM_IP32_INTS_H
 #define __ASM_IP32_INTS_H
 
+#include <asm/irq.h>
+
 /*
  * This list reflects the assignment of interrupt numbers to
  * interrupting events.  Order is fairly irrelevant to handling
  * priority.  This differs from irix.
  */
 
-/* CPU */
-#define IP32_R4K_TIMER_IRQ		0
+enum ip32_irq_no {
+	/*
+	 * CPU interrupts are 0 ... 7
+	 */
 
-/* MACE */
-#define MACE_VID_IN1_IRQ		1
-#define MACE_VID_IN2_IRQ		2
-#define MACE_VID_OUT_IRQ		3
-#define MACE_ETHERNET_IRQ		4
-/* SUPERIO, MISC, and AUDIO are MACEISA */
-#define MACE_PCI_BRIDGE_IRQ		8
+	/*
+	 * MACE
+	 */
+	MACE_VID_IN1_IRQ		= MIPS_CPU_IRQ_BASE + 8,
+	MACE_VID_IN2_IRQ,
+	MACE_VID_OUT_IRQ,
+	MACE_ETHERNET_IRQ,
+	/* SUPERIO, MISC, and AUDIO are MACEISA */
+	__MACE_SUPERIO,
+	__MACE_MISC,
+	__MACE_AUDIO,
+	MACE_PCI_BRIDGE_IRQ,
 
-/* MACEPCI */
-#define MACEPCI_SCSI0_IRQ		9
-#define MACEPCI_SCSI1_IRQ		10
-#define MACEPCI_SLOT0_IRQ		11
-#define MACEPCI_SLOT1_IRQ		12
-#define MACEPCI_SLOT2_IRQ		13
-#define MACEPCI_SHARED0_IRQ		14
-#define MACEPCI_SHARED1_IRQ		15
-#define MACEPCI_SHARED2_IRQ		16
+	/*
+	 * MACEPCI
+	 */
+	MACEPCI_SCSI0_IRQ,
+	MACEPCI_SCSI1_IRQ,
+	MACEPCI_SLOT0_IRQ,
+	MACEPCI_SLOT1_IRQ,
+	MACEPCI_SLOT2_IRQ,
+	MACEPCI_SHARED0_IRQ,
+	MACEPCI_SHARED1_IRQ,
+	MACEPCI_SHARED2_IRQ,
 
-/* CRIME */
-#define CRIME_GBE0_IRQ			17
-#define CRIME_GBE1_IRQ			18
-#define CRIME_GBE2_IRQ			19
-#define CRIME_GBE3_IRQ			20
-#define CRIME_CPUERR_IRQ		21
-#define CRIME_MEMERR_IRQ		22
-#define CRIME_RE_EMPTY_E_IRQ		23
-#define CRIME_RE_FULL_E_IRQ		24
-#define CRIME_RE_IDLE_E_IRQ		25
-#define CRIME_RE_EMPTY_L_IRQ		26
-#define CRIME_RE_FULL_L_IRQ		27
-#define CRIME_RE_IDLE_L_IRQ		28
-#define CRIME_SOFT0_IRQ			29
-#define CRIME_SOFT1_IRQ			30
-#define CRIME_SOFT2_IRQ			31
-#define CRIME_SYSCORERR_IRQ		CRIME_SOFT2_IRQ
-#define CRIME_VICE_IRQ			32
+	/*
+	 * CRIME
+	 */
+	CRIME_GBE0_IRQ,
+	CRIME_GBE1_IRQ,
+	CRIME_GBE2_IRQ,
+	CRIME_GBE3_IRQ,
+	CRIME_CPUERR_IRQ,
+	CRIME_MEMERR_IRQ,
+	CRIME_RE_EMPTY_E_IRQ,
+	CRIME_RE_FULL_E_IRQ,
+	CRIME_RE_IDLE_E_IRQ,
+	CRIME_RE_EMPTY_L_IRQ,
+	CRIME_RE_FULL_L_IRQ,
+	CRIME_RE_IDLE_L_IRQ,
+	CRIME_SOFT0_IRQ,
+	CRIME_SOFT1_IRQ,
+	CRIME_SOFT2_IRQ,
+	CRIME_SYSCORERR_IRQ		= CRIME_SOFT2_IRQ,
+	CRIME_VICE_IRQ,
 
-/* MACEISA */
-#define MACEISA_AUDIO_SW_IRQ		33
-#define MACEISA_AUDIO_SC_IRQ		34
-#define MACEISA_AUDIO1_DMAT_IRQ		35
-#define MACEISA_AUDIO1_OF_IRQ		36
-#define MACEISA_AUDIO2_DMAT_IRQ		37
-#define MACEISA_AUDIO2_MERR_IRQ		38
-#define MACEISA_AUDIO3_DMAT_IRQ		39
-#define MACEISA_AUDIO3_MERR_IRQ		40
-#define MACEISA_RTC_IRQ			41
-#define MACEISA_KEYB_IRQ		42
-/* MACEISA_KEYB_POLL is not an IRQ */
-#define MACEISA_MOUSE_IRQ		44
-/* MACEISA_MOUSE_POLL is not an IRQ */
-#define MACEISA_TIMER0_IRQ		46
-#define MACEISA_TIMER1_IRQ		47
-#define MACEISA_TIMER2_IRQ		48
-#define MACEISA_PARALLEL_IRQ		49
-#define MACEISA_PAR_CTXA_IRQ		50
-#define MACEISA_PAR_CTXB_IRQ		51
-#define MACEISA_PAR_MERR_IRQ		52
-#define MACEISA_SERIAL1_IRQ		53
-#define MACEISA_SERIAL1_TDMAT_IRQ	54
-#define MACEISA_SERIAL1_TDMAPR_IRQ	55
-#define MACEISA_SERIAL1_TDMAME_IRQ	56
-#define MACEISA_SERIAL1_RDMAT_IRQ	57
-#define MACEISA_SERIAL1_RDMAOR_IRQ	58
-#define MACEISA_SERIAL2_IRQ		59
-#define MACEISA_SERIAL2_TDMAT_IRQ	60
-#define MACEISA_SERIAL2_TDMAPR_IRQ	61
-#define MACEISA_SERIAL2_TDMAME_IRQ	62
-#define MACEISA_SERIAL2_RDMAT_IRQ	63
-#define MACEISA_SERIAL2_RDMAOR_IRQ	64
+	/*
+	 * MACEISA
+	 */
+	MACEISA_AUDIO_SW_IRQ,
+	MACEISA_AUDIO_SC_IRQ,
+	MACEISA_AUDIO1_DMAT_IRQ,
+	MACEISA_AUDIO1_OF_IRQ,
+	MACEISA_AUDIO2_DMAT_IRQ,
+	MACEISA_AUDIO2_MERR_IRQ,
+	MACEISA_AUDIO3_DMAT_IRQ,
+	MACEISA_AUDIO3_MERR_IRQ,
+	MACEISA_RTC_IRQ,
+	MACEISA_KEYB_IRQ,
+	/* MACEISA_KEYB_POLL is not an IRQ */
+	__MACEISA_KEYB_POLL,
+	MACEISA_MOUSE_IRQ,
+	/* MACEISA_MOUSE_POLL is not an IRQ */
+	__MACEISA_MOUSE_POLL,
+	MACEISA_TIMER0_IRQ,
+	MACEISA_TIMER1_IRQ,
+	MACEISA_TIMER2_IRQ,
+	MACEISA_PARALLEL_IRQ,
+	MACEISA_PAR_CTXA_IRQ,
+	MACEISA_PAR_CTXB_IRQ,
+	MACEISA_PAR_MERR_IRQ,
+	MACEISA_SERIAL1_IRQ,
+	MACEISA_SERIAL1_TDMAT_IRQ,
+	MACEISA_SERIAL1_TDMAPR_IRQ,
+	MACEISA_SERIAL1_TDMAME_IRQ,
+	MACEISA_SERIAL1_RDMAT_IRQ,
+	MACEISA_SERIAL1_RDMAOR_IRQ,
+	MACEISA_SERIAL2_IRQ,
+	MACEISA_SERIAL2_TDMAT_IRQ,
+	MACEISA_SERIAL2_TDMAPR_IRQ,
+	MACEISA_SERIAL2_TDMAME_IRQ,
+	MACEISA_SERIAL2_RDMAT_IRQ,
+	MACEISA_SERIAL2_RDMAOR_IRQ,
 
-#define IP32_IRQ_MAX			MACEISA_SERIAL2_RDMAOR_IRQ
+	IP32_IRQ_MAX			= MACEISA_SERIAL2_RDMAOR_IRQ
+};
 
 #endif /* __ASM_IP32_INTS_H */

include/asm-mips/lasat/lasatint.h

···
-#define LASATINT_END 16
+#ifndef __ASM_LASAT_LASATINT_H
+#define __ASM_LASAT_LASATINT_H
+
+#include <linux/irq.h>
+
+#define LASATINT_BASE	MIPS_CPU_IRQ_BASE
+#define LASATINT_END	(LASATINT_BASE + 16)
 
 /* lasat 100 */
 #define LASAT_INT_STATUS_REG_100	(KSEG1ADDR(0x1c880000))
···
 #define LASAT_INT_MASK_REG_200		(KSEG1ADDR(0x1104003c))
 #define LASATINT_MASK_SHIFT_200		16
 
+#endif /* __ASM_LASAT_LASATINT_H */

include/asm-mips/mach-au1x00/au1000.h

···
 }
 
 
-static __inline__ int au_ffz(unsigned int x)
-{
-	if ((x = ~x) == 0)
-		return 32;
-	return __ilog2(x & -x);
-}
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static __inline__ int au_ffs(int x)
-{
-	return __ilog2(x & -x) + 1;
-}
-
 /* arch/mips/au1000/common/clocks.c */
 extern void set_au1x00_speed(unsigned int new_freq);
 extern unsigned int get_au1x00_speed(void);
···
 /*
  * Every board describes its IRQ mapping with this table.
  */
-typedef struct au1xxx_irqmap {
+struct au1xxx_irqmap {
 	int	im_irq;
 	int	im_type;
 	int	im_request;
-} au1xxx_irq_map_t;
+};
 
 /*
  * init_IRQ looks for a table with this name.
  */
-extern au1xxx_irq_map_t au1xxx_irq_map[];
+extern struct au1xxx_irqmap au1xxx_irq_map[];
 
 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
 

include/asm-mips/pmc-sierra/msp71xx/war.h

···
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <[e-mail]>
+ */
+#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
+#define __ASM_MIPS_PMC_SIERRA_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
+	defined(CONFIG_PMC_MSP7120_FPGA)
+#define MIPS34K_MISSED_ITLB_WAR         1
+#endif
+
+#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */

include/asm-mips/ptrace.h

···
 
 extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
 
-extern NORET_TYPE void die(const char *, struct pt_regs *) ATTRIB_NORET;
+extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
 
-static inline void die_if_kernel(const char *str, struct pt_regs *regs)
+static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
 {
 	if (unlikely(!user_mode(regs)))
 		die(str, regs);