Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

drm/amd/display: Clean up dcn10_optc.c kdoc

Fixes the following W=1 kernel build warning:

display/dc/dcn10/dcn10_optc.c:45: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* apply_front_porch_workaround TODO FPGA still need?
display/dc/dcn10/dcn10_optc.c:136: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* program_timing_generator used by mode timing set
display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'optc' not described in 'optc1_set_timing_double_buffer'
display/dc/dcn10/dcn10_optc.c:391: warning: Function parameter or member 'enable' not described in 'optc1_set_timing_double_buffer'
display/dc/dcn10/dcn10_optc.c:404: warning: Function parameter or member 'optc' not described in 'optc1_unblank_crtc'
display/dc/dcn10/dcn10_optc.c:404: warning: expecting prototype for unblank_crtc(). Prototype was for optc1_unblank_crtc() instead
display/dc/dcn10/dcn10_optc.c:427: warning: Function parameter or member 'optc' not described in 'optc1_blank_crtc'
display/dc/dcn10/dcn10_optc.c:427: warning: expecting prototype for blank_crtc(). Prototype was for optc1_blank_crtc() instead
display/dc/dcn10/dcn10_optc.c:496: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
* Enable CRTC
display/dc/dcn10/dcn10_optc.c:895: warning: Cannot understand *****************************************************************************
on line 895 - I thought it was a doc line

Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Srinivasan Shanmugam and committed by
Alex Deucher
ebbb0b10 2e1e62c8

+36 -21
+36 -21
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
··· 42 42 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100 43 43 44 44 /** 45 - * apply_front_porch_workaround TODO FPGA still need? 46 - * 47 - * This is a workaround for a bug that has existed since R5xx and has not been 48 - * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive. 49 - */ 45 + * apply_front_porch_workaround() - This is a workaround for a bug that has 46 + * existed since R5xx and has not been fixed 47 + * keep Front porch at minimum 2 for Interlaced 48 + * mode or 1 for progressive. 49 + * 50 + * @timing: Timing parameters used to configure DCN blocks. 51 + */ 50 52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing) 51 53 { 52 54 if (timing->flags.INTERLACE == 1) { ··· 135 133 } 136 134 137 135 /** 138 - * program_timing_generator used by mode timing set 139 - * Program CRTC Timing Registers - OTG_H_*, OTG_V_*, Pixel repetition. 140 - * Including SYNC. Call BIOS command table to program Timings. 136 + * optc1_program_timing() - used by mode timing set Program 137 + * CRTC Timing Registers - OTG_H_*, 138 + * OTG_V_*, Pixel repetition. 139 + * Including SYNC. Call BIOS command table to program Timings. 140 + * 141 + * @optc: timing_generator instance. 142 + * @dc_crtc_timing: Timing parameters used to configure DCN blocks. 143 + * @vready_offset: Vready's starting position. 144 + * @vstartup_start: Vstartup period. 145 + * @vupdate_offset: Vupdate starting position. 146 + * @vupdate_width: Vupdate duration. 147 + * @signal: DC signal types. 148 + * @use_vbios: to program timings from BIOS command table. 149 + * 141 150 */ 142 151 void optc1_program_timing( 143 152 struct timing_generator *optc, ··· 398 385 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 399 386 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 400 387 * 388 + * @optc: timing_generator instance. 389 + * @enable: Enable DRR double buffering control if true, disable otherwise. 390 + * 401 391 * Options: any time, start of frame, dp start of frame (range timing) 402 392 */ 403 393 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable) ··· 413 397 } 414 398 415 399 /** 416 - * unblank_crtc 417 - * Call ASIC Control Object to UnBlank CRTC. 400 + * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC. 401 + * 402 + * @optc: timing_generator instance. 418 403 */ 419 404 static void optc1_unblank_crtc(struct timing_generator *optc) 420 405 { ··· 436 419 } 437 420 438 421 /** 439 - * blank_crtc 440 - * Call ASIC Control Object to Blank CRTC. 422 + * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC. 423 + * 424 + * @optc: timing_generator instance. 441 425 */ 442 426 443 427 static void optc1_blank_crtc(struct timing_generator *optc) ··· 511 493 } 512 494 513 495 /** 514 - * Enable CRTC 515 - * Enable CRTC - call ASIC Control Object to enable Timing generator. 496 + * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator. 497 + * 498 + * @optc: timing_generator instance. 516 499 */ 517 500 static bool optc1_enable_crtc(struct timing_generator *optc) 518 501 { ··· 909 890 MANUAL_FLOW_CONTROL, 0); 910 891 } 911 892 912 - 913 893 /** 914 - ***************************************************************************** 915 - * Function: set_drr 894 + * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 916 895 * 917 - * @brief 918 - * Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*. 919 - * 920 - ***************************************************************************** 896 + * @optc: timing_generator instance. 897 + * @params: parameters used for Dynamic Refresh Rate. 921 898 */ 922 899 void optc1_set_drr( 923 900 struct timing_generator *optc,