drm/rockchip: vop: add a series of vop support

+9

drivers/gpu/drm/rockchip/rockchip_drm_vop.h

··· 15 15 #ifndef _ROCKCHIP_DRM_VOP_H 16 16 #define _ROCKCHIP_DRM_VOP_H 17 17 18 + /* 19 + * major: IP major version, used for IP structure 20 + * minor: big feature change under same structure 21 + */ 22 + #define VOP_VERSION(major, minor) ((major) << 8 | (minor)) 23 + #define VOP_MAJOR(version) ((version) >> 8) 24 + #define VOP_MINOR(version) ((version) & 0xff) 25 + 18 26 enum vop_data_format { 19 27 VOP_FMT_ARGB8888 = 0, 20 28 VOP_FMT_RGB888, ··· 150 142 }; 151 143 152 144 struct vop_data { 145 + uint32_t version; 153 146 const struct vop_intr *intr; 154 147 const struct vop_common *common; 155 148 const struct vop_misc *misc;

+187 -31

drivers/gpu/drm/rockchip/rockchip_vop_reg.c

··· 277 277 }; 278 278 279 279 static const struct vop_data rk3288_vop = { 280 + .version = VOP_VERSION(3, 1), 280 281 .feature = VOP_FEATURE_OUTPUT_RGB10, 281 282 .intr = &rk3288_vop_intr, 282 283 .common = &rk3288_common, ··· 287 286 .win_size = ARRAY_SIZE(rk3288_vop_win_data), 288 287 }; 289 288 290 - static const int rk3399_vop_intrs[] = { 289 + static const int rk3368_vop_intrs[] = { 291 290 FS_INTR, 292 291 0, 0, 293 292 LINE_FLAG_INTR, ··· 297 296 DSP_HOLD_VALID_INTR, 298 297 }; 299 298 300 - static const struct vop_intr rk3399_vop_intr = { 301 - .intrs = rk3399_vop_intrs, 302 - .nintrs = ARRAY_SIZE(rk3399_vop_intrs), 303 - .line_flag_num[0] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 0), 304 - .line_flag_num[1] = VOP_REG(RK3399_LINE_FLAG, 0xffff, 16), 305 - .status = VOP_REG_MASK_SYNC(RK3399_INTR_STATUS0, 0xffff, 0), 306 - .enable = VOP_REG_MASK_SYNC(RK3399_INTR_EN0, 0xffff, 0), 307 - .clear = VOP_REG_MASK_SYNC(RK3399_INTR_CLEAR0, 0xffff, 0), 299 + static const struct vop_intr rk3368_vop_intr = { 300 + .intrs = rk3368_vop_intrs, 301 + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 302 + .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0), 303 + .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16), 304 + .status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0), 305 + .enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0), 306 + .clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0), 307 + }; 308 + 309 + static const struct vop_win_phy rk3368_win23_data = { 310 + .data_formats = formats_win_lite, 311 + .nformats = ARRAY_SIZE(formats_win_lite), 312 + .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0), 313 + .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4), 314 + .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5), 315 + .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20), 316 + .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0), 317 + .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0), 318 + .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0), 319 + .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0), 320 + .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0), 321 + .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0), 322 + }; 323 + 324 + static const struct vop_win_data rk3368_vop_win_data[] = { 325 + { .base = 0x00, .phy = &rk3288_win01_data, 326 + .type = DRM_PLANE_TYPE_PRIMARY }, 327 + { .base = 0x40, .phy = &rk3288_win01_data, 328 + .type = DRM_PLANE_TYPE_OVERLAY }, 329 + { .base = 0x00, .phy = &rk3368_win23_data, 330 + .type = DRM_PLANE_TYPE_OVERLAY }, 331 + { .base = 0x50, .phy = &rk3368_win23_data, 332 + .type = DRM_PLANE_TYPE_CURSOR }, 333 + }; 334 + 335 + static const struct vop_output rk3368_output = { 336 + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 337 + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 338 + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 339 + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 340 + .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 341 + .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), 342 + .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14), 343 + .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 344 + }; 345 + 346 + static const struct vop_misc rk3368_misc = { 347 + .global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11), 348 + }; 349 + 350 + static const struct vop_data rk3368_vop = { 351 + .version = VOP_VERSION(3, 2), 352 + .intr = &rk3368_vop_intr, 353 + .common = &rk3288_common, 354 + .modeset = &rk3288_modeset, 355 + .output = &rk3368_output, 356 + .misc = &rk3368_misc, 357 + .win = rk3368_vop_win_data, 358 + .win_size = ARRAY_SIZE(rk3368_vop_win_data), 359 + }; 360 + 361 + static const struct vop_intr rk3366_vop_intr = { 362 + .intrs = rk3368_vop_intrs, 363 + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 364 + .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0), 365 + .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16), 366 + .status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0), 367 + .enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0), 368 + .clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0), 369 + }; 370 + 371 + static const struct vop_data rk3366_vop = { 372 + .version = VOP_VERSION(3, 4), 373 + .intr = &rk3366_vop_intr, 374 + .common = &rk3288_common, 375 + .modeset = &rk3288_modeset, 376 + .output = &rk3368_output, 377 + .misc = &rk3368_misc, 378 + .win = rk3368_vop_win_data, 379 + .win_size = ARRAY_SIZE(rk3368_vop_win_data), 308 380 }; 309 381 310 382 static const struct vop_output rk3399_output = { 311 383 .dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 312 - .rgb_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 16), 313 - .hdmi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 20), 314 - .edp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 24), 315 - .mipi_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0xf, 28), 384 + .rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 16), 385 + .hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 20), 386 + .edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 24), 387 + .mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0xf, 28), 316 388 .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 317 389 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12), 318 390 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13), ··· 393 319 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15), 394 320 }; 395 321 396 - static const struct vop_misc rk3399_misc = { 397 - .global_regdone_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11), 398 - }; 399 - 400 322 static const struct vop_data rk3399_vop_big = { 323 + .version = VOP_VERSION(3, 5), 401 324 .feature = VOP_FEATURE_OUTPUT_RGB10, 402 - .intr = &rk3399_vop_intr, 325 + .intr = &rk3366_vop_intr, 403 326 .common = &rk3288_common, 404 327 .modeset = &rk3288_modeset, 405 328 .output = &rk3399_output, 406 - .misc = &rk3399_misc, 407 - /* 408 - * rk3399 vop big windows register layout is same as rk3288. 409 - */ 410 - .win = rk3288_vop_win_data, 411 - .win_size = ARRAY_SIZE(rk3288_vop_win_data), 329 + .misc = &rk3368_misc, 330 + .win = rk3368_vop_win_data, 331 + .win_size = ARRAY_SIZE(rk3368_vop_win_data), 412 332 }; 413 333 414 334 static const struct vop_win_data rk3399_vop_lit_win_data[] = { 415 335 { .base = 0x00, .phy = &rk3288_win01_data, 416 336 .type = DRM_PLANE_TYPE_PRIMARY }, 417 - { .base = 0x00, .phy = &rk3288_win23_data, 337 + { .base = 0x00, .phy = &rk3368_win23_data, 418 338 .type = DRM_PLANE_TYPE_CURSOR}, 419 339 }; 420 340 421 341 static const struct vop_data rk3399_vop_lit = { 422 - .intr = &rk3399_vop_intr, 342 + .version = VOP_VERSION(3, 6), 343 + .intr = &rk3366_vop_intr, 423 344 .common = &rk3288_common, 424 345 .modeset = &rk3288_modeset, 425 346 .output = &rk3399_output, 426 - .misc = &rk3399_misc, 427 - /* 428 - * rk3399 vop lit windows register layout is same as rk3288, 429 - * but cut off the win1 and win3 windows. 430 - */ 347 + .misc = &rk3368_misc, 431 348 .win = rk3399_vop_lit_win_data, 432 349 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data), 350 + }; 351 + 352 + static const struct vop_win_data rk3228_vop_win_data[] = { 353 + { .base = 0x00, .phy = &rk3288_win01_data, 354 + .type = DRM_PLANE_TYPE_PRIMARY }, 355 + { .base = 0x40, .phy = &rk3288_win01_data, 356 + .type = DRM_PLANE_TYPE_CURSOR }, 357 + }; 358 + 359 + static const struct vop_data rk3228_vop = { 360 + .version = VOP_VERSION(3, 7), 361 + .feature = VOP_FEATURE_OUTPUT_RGB10, 362 + .intr = &rk3366_vop_intr, 363 + .common = &rk3288_common, 364 + .modeset = &rk3288_modeset, 365 + .output = &rk3399_output, 366 + .misc = &rk3368_misc, 367 + .win = rk3228_vop_win_data, 368 + .win_size = ARRAY_SIZE(rk3228_vop_win_data), 369 + }; 370 + 371 + static const struct vop_modeset rk3328_modeset = { 372 + .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), 373 + .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0), 374 + .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), 375 + .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0), 376 + .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0), 377 + .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0), 378 + }; 379 + 380 + static const struct vop_output rk3328_output = { 381 + .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12), 382 + .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13), 383 + .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14), 384 + .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15), 385 + .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16), 386 + .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20), 387 + .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24), 388 + .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28), 389 + }; 390 + 391 + static const struct vop_misc rk3328_misc = { 392 + .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11), 393 + }; 394 + 395 + static const struct vop_common rk3328_common = { 396 + .standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22), 397 + .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1), 398 + .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6), 399 + .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18), 400 + .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0), 401 + .cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0), 402 + }; 403 + 404 + static const struct vop_intr rk3328_vop_intr = { 405 + .intrs = rk3368_vop_intrs, 406 + .nintrs = ARRAY_SIZE(rk3368_vop_intrs), 407 + .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0), 408 + .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16), 409 + .status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0), 410 + .enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0), 411 + .clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0), 412 + }; 413 + 414 + static const struct vop_win_data rk3328_vop_win_data[] = { 415 + { .base = 0xd0, .phy = &rk3288_win01_data, 416 + .type = DRM_PLANE_TYPE_PRIMARY }, 417 + { .base = 0x1d0, .phy = &rk3288_win01_data, 418 + .type = DRM_PLANE_TYPE_OVERLAY }, 419 + { .base = 0x2d0, .phy = &rk3288_win01_data, 420 + .type = DRM_PLANE_TYPE_CURSOR }, 421 + }; 422 + 423 + static const struct vop_data rk3328_vop = { 424 + .version = VOP_VERSION(3, 8), 425 + .feature = VOP_FEATURE_OUTPUT_RGB10, 426 + .intr = &rk3328_vop_intr, 427 + .common = &rk3328_common, 428 + .modeset = &rk3328_modeset, 429 + .output = &rk3328_output, 430 + .misc = &rk3328_misc, 431 + .win = rk3328_vop_win_data, 432 + .win_size = ARRAY_SIZE(rk3328_vop_win_data), 433 433 }; 434 434 435 435 static const struct of_device_id vop_driver_dt_match[] = { ··· 511 363 .data = &rk3036_vop }, 512 364 { .compatible = "rockchip,rk3288-vop", 513 365 .data = &rk3288_vop }, 366 + { .compatible = "rockchip,rk3368-vop", 367 + .data = &rk3368_vop }, 368 + { .compatible = "rockchip,rk3366-vop", 369 + .data = &rk3366_vop }, 514 370 { .compatible = "rockchip,rk3399-vop-big", 515 371 .data = &rk3399_vop_big }, 516 372 { .compatible = "rockchip,rk3399-vop-lit", 517 373 .data = &rk3399_vop_lit }, 374 + { .compatible = "rockchip,rk3228-vop", 375 + .data = &rk3228_vop }, 376 + { .compatible = "rockchip,rk3328-vop", 377 + .data = &rk3328_vop }, 518 378 {}, 519 379 }; 520 380 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);

+712 -193

drivers/gpu/drm/rockchip/rockchip_vop_reg.h

··· 41 41 #define RK3288_WIN0_SRC_ALPHA_CTRL 0x0060 42 42 #define RK3288_WIN0_DST_ALPHA_CTRL 0x0064 43 43 #define RK3288_WIN0_FADING_CTRL 0x0068 44 + #define RK3288_WIN0_CTRL2 0x006c 44 45 45 46 /* win1 register */ 46 47 #define RK3288_WIN1_CTRL0 0x0070 ··· 123 122 #define RK3288_DSP_VACT_ST_END_F1 0x019c 124 123 /* register definition end */ 125 124 125 + /* rk3368 register definition */ 126 + #define RK3368_REG_CFG_DONE 0x0000 127 + #define RK3368_VERSION_INFO 0x0004 128 + #define RK3368_SYS_CTRL 0x0008 129 + #define RK3368_SYS_CTRL1 0x000c 130 + #define RK3368_DSP_CTRL0 0x0010 131 + #define RK3368_DSP_CTRL1 0x0014 132 + #define RK3368_DSP_BG 0x0018 133 + #define RK3368_MCU_CTRL 0x001c 134 + #define RK3368_LINE_FLAG 0x0020 135 + #define RK3368_INTR_EN 0x0024 136 + #define RK3368_INTR_CLEAR 0x0028 137 + #define RK3368_INTR_STATUS 0x002c 138 + #define RK3368_WIN0_CTRL0 0x0030 139 + #define RK3368_WIN0_CTRL1 0x0034 140 + #define RK3368_WIN0_COLOR_KEY 0x0038 141 + #define RK3368_WIN0_VIR 0x003c 142 + #define RK3368_WIN0_YRGB_MST 0x0040 143 + #define RK3368_WIN0_CBR_MST 0x0044 144 + #define RK3368_WIN0_ACT_INFO 0x0048 145 + #define RK3368_WIN0_DSP_INFO 0x004c 146 + #define RK3368_WIN0_DSP_ST 0x0050 147 + #define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054 148 + #define RK3368_WIN0_SCL_FACTOR_CBR 0x0058 149 + #define RK3368_WIN0_SCL_OFFSET 0x005c 150 + #define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060 151 + #define RK3368_WIN0_DST_ALPHA_CTRL 0x0064 152 + #define RK3368_WIN0_FADING_CTRL 0x0068 153 + #define RK3368_WIN0_CTRL2 0x006c 154 + #define RK3368_WIN1_CTRL0 0x0070 155 + #define RK3368_WIN1_CTRL1 0x0074 156 + #define RK3368_WIN1_COLOR_KEY 0x0078 157 + #define RK3368_WIN1_VIR 0x007c 158 + #define RK3368_WIN1_YRGB_MST 0x0080 159 + #define RK3368_WIN1_CBR_MST 0x0084 160 + #define RK3368_WIN1_ACT_INFO 0x0088 161 + #define RK3368_WIN1_DSP_INFO 0x008c 162 + #define RK3368_WIN1_DSP_ST 0x0090 163 + #define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094 164 + #define RK3368_WIN1_SCL_FACTOR_CBR 0x0098 165 + #define RK3368_WIN1_SCL_OFFSET 0x009c 166 + #define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0 167 + #define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4 168 + #define RK3368_WIN1_FADING_CTRL 0x00a8 169 + #define RK3368_WIN1_CTRL2 0x00ac 170 + #define RK3368_WIN2_CTRL0 0x00b0 171 + #define RK3368_WIN2_CTRL1 0x00b4 172 + #define RK3368_WIN2_VIR0_1 0x00b8 173 + #define RK3368_WIN2_VIR2_3 0x00bc 174 + #define RK3368_WIN2_MST0 0x00c0 175 + #define RK3368_WIN2_DSP_INFO0 0x00c4 176 + #define RK3368_WIN2_DSP_ST0 0x00c8 177 + #define RK3368_WIN2_COLOR_KEY 0x00cc 178 + #define RK3368_WIN2_MST1 0x00d0 179 + #define RK3368_WIN2_DSP_INFO1 0x00d4 180 + #define RK3368_WIN2_DSP_ST1 0x00d8 181 + #define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc 182 + #define RK3368_WIN2_MST2 0x00e0 183 + #define RK3368_WIN2_DSP_INFO2 0x00e4 184 + #define RK3368_WIN2_DSP_ST2 0x00e8 185 + #define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec 186 + #define RK3368_WIN2_MST3 0x00f0 187 + #define RK3368_WIN2_DSP_INFO3 0x00f4 188 + #define RK3368_WIN2_DSP_ST3 0x00f8 189 + #define RK3368_WIN2_FADING_CTRL 0x00fc 190 + #define RK3368_WIN3_CTRL0 0x0100 191 + #define RK3368_WIN3_CTRL1 0x0104 192 + #define RK3368_WIN3_VIR0_1 0x0108 193 + #define RK3368_WIN3_VIR2_3 0x010c 194 + #define RK3368_WIN3_MST0 0x0110 195 + #define RK3368_WIN3_DSP_INFO0 0x0114 196 + #define RK3368_WIN3_DSP_ST0 0x0118 197 + #define RK3368_WIN3_COLOR_KEY 0x011c 198 + #define RK3368_WIN3_MST1 0x0120 199 + #define RK3368_WIN3_DSP_INFO1 0x0124 200 + #define RK3368_WIN3_DSP_ST1 0x0128 201 + #define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c 202 + #define RK3368_WIN3_MST2 0x0130 203 + #define RK3368_WIN3_DSP_INFO2 0x0134 204 + #define RK3368_WIN3_DSP_ST2 0x0138 205 + #define RK3368_WIN3_DST_ALPHA_CTRL 0x013c 206 + #define RK3368_WIN3_MST3 0x0140 207 + #define RK3368_WIN3_DSP_INFO3 0x0144 208 + #define RK3368_WIN3_DSP_ST3 0x0148 209 + #define RK3368_WIN3_FADING_CTRL 0x014c 210 + #define RK3368_HWC_CTRL0 0x0150 211 + #define RK3368_HWC_CTRL1 0x0154 212 + #define RK3368_HWC_MST 0x0158 213 + #define RK3368_HWC_DSP_ST 0x015c 214 + #define RK3368_HWC_SRC_ALPHA_CTRL 0x0160 215 + #define RK3368_HWC_DST_ALPHA_CTRL 0x0164 216 + #define RK3368_HWC_FADING_CTRL 0x0168 217 + #define RK3368_HWC_RESERVED1 0x016c 218 + #define RK3368_POST_DSP_HACT_INFO 0x0170 219 + #define RK3368_POST_DSP_VACT_INFO 0x0174 220 + #define RK3368_POST_SCL_FACTOR_YRGB 0x0178 221 + #define RK3368_POST_RESERVED 0x017c 222 + #define RK3368_POST_SCL_CTRL 0x0180 223 + #define RK3368_POST_DSP_VACT_INFO_F1 0x0184 224 + #define RK3368_DSP_HTOTAL_HS_END 0x0188 225 + #define RK3368_DSP_HACT_ST_END 0x018c 226 + #define RK3368_DSP_VTOTAL_VS_END 0x0190 227 + #define RK3368_DSP_VACT_ST_END 0x0194 228 + #define RK3368_DSP_VS_ST_END_F1 0x0198 229 + #define RK3368_DSP_VACT_ST_END_F1 0x019c 230 + #define RK3368_PWM_CTRL 0x01a0 231 + #define RK3368_PWM_PERIOD_HPR 0x01a4 232 + #define RK3368_PWM_DUTY_LPR 0x01a8 233 + #define RK3368_PWM_CNT 0x01ac 234 + #define RK3368_BCSH_COLOR_BAR 0x01b0 235 + #define RK3368_BCSH_BCS 0x01b4 236 + #define RK3368_BCSH_H 0x01b8 237 + #define RK3368_BCSH_CTRL 0x01bc 238 + #define RK3368_CABC_CTRL0 0x01c0 239 + #define RK3368_CABC_CTRL1 0x01c4 240 + #define RK3368_CABC_CTRL2 0x01c8 241 + #define RK3368_CABC_CTRL3 0x01cc 242 + #define RK3368_CABC_GAUSS_LINE0_0 0x01d0 243 + #define RK3368_CABC_GAUSS_LINE0_1 0x01d4 244 + #define RK3368_CABC_GAUSS_LINE1_0 0x01d8 245 + #define RK3368_CABC_GAUSS_LINE1_1 0x01dc 246 + #define RK3368_CABC_GAUSS_LINE2_0 0x01e0 247 + #define RK3368_CABC_GAUSS_LINE2_1 0x01e4 248 + #define RK3368_FRC_LOWER01_0 0x01e8 249 + #define RK3368_FRC_LOWER01_1 0x01ec 250 + #define RK3368_FRC_LOWER10_0 0x01f0 251 + #define RK3368_FRC_LOWER10_1 0x01f4 252 + #define RK3368_FRC_LOWER11_0 0x01f8 253 + #define RK3368_FRC_LOWER11_1 0x01fc 254 + #define RK3368_IFBDC_CTRL 0x0200 255 + #define RK3368_IFBDC_TILES_NUM 0x0204 256 + #define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208 257 + #define RK3368_IFBDC_BASE_ADDR 0x020c 258 + #define RK3368_IFBDC_MB_SIZE 0x0210 259 + #define RK3368_IFBDC_CMP_INDEX_INIT 0x0214 260 + #define RK3368_IFBDC_VIR 0x0220 261 + #define RK3368_IFBDC_DEBUG0 0x0230 262 + #define RK3368_IFBDC_DEBUG1 0x0234 263 + #define RK3368_LATENCY_CTRL0 0x0250 264 + #define RK3368_RD_MAX_LATENCY_NUM0 0x0254 265 + #define RK3368_RD_LATENCY_THR_NUM0 0x0258 266 + #define RK3368_RD_LATENCY_SAMP_NUM0 0x025c 267 + #define RK3368_WIN0_DSP_BG 0x0260 268 + #define RK3368_WIN1_DSP_BG 0x0264 269 + #define RK3368_WIN2_DSP_BG 0x0268 270 + #define RK3368_WIN3_DSP_BG 0x026c 271 + #define RK3368_SCAN_LINE_NUM 0x0270 272 + #define RK3368_CABC_DEBUG0 0x0274 273 + #define RK3368_CABC_DEBUG1 0x0278 274 + #define RK3368_CABC_DEBUG2 0x027c 275 + #define RK3368_DBG_REG_000 0x0280 276 + #define RK3368_DBG_REG_001 0x0284 277 + #define RK3368_DBG_REG_002 0x0288 278 + #define RK3368_DBG_REG_003 0x028c 279 + #define RK3368_DBG_REG_004 0x0290 280 + #define RK3368_DBG_REG_005 0x0294 281 + #define RK3368_DBG_REG_006 0x0298 282 + #define RK3368_DBG_REG_007 0x029c 283 + #define RK3368_DBG_REG_008 0x02a0 284 + #define RK3368_DBG_REG_016 0x02c0 285 + #define RK3368_DBG_REG_017 0x02c4 286 + #define RK3368_DBG_REG_018 0x02c8 287 + #define RK3368_DBG_REG_019 0x02cc 288 + #define RK3368_DBG_REG_020 0x02d0 289 + #define RK3368_DBG_REG_021 0x02d4 290 + #define RK3368_DBG_REG_022 0x02d8 291 + #define RK3368_DBG_REG_023 0x02dc 292 + #define RK3368_DBG_REG_028 0x02f0 293 + #define RK3368_MMU_DTE_ADDR 0x0300 294 + #define RK3368_MMU_STATUS 0x0304 295 + #define RK3368_MMU_COMMAND 0x0308 296 + #define RK3368_MMU_PAGE_FAULT_ADDR 0x030c 297 + #define RK3368_MMU_ZAP_ONE_LINE 0x0310 298 + #define RK3368_MMU_INT_RAWSTAT 0x0314 299 + #define RK3368_MMU_INT_CLEAR 0x0318 300 + #define RK3368_MMU_INT_MASK 0x031c 301 + #define RK3368_MMU_INT_STATUS 0x0320 302 + #define RK3368_MMU_AUTO_GATING 0x0324 303 + #define RK3368_WIN2_LUT_ADDR 0x0400 304 + #define RK3368_WIN3_LUT_ADDR 0x0800 305 + #define RK3368_HWC_LUT_ADDR 0x0c00 306 + #define RK3368_GAMMA_LUT_ADDR 0x1000 307 + #define RK3368_CABC_GAMMA_LUT_ADDR 0x1800 308 + #define RK3368_MCU_BYPASS_WPORT 0x2200 309 + #define RK3368_MCU_BYPASS_RPORT 0x2300 310 + /* rk3368 register definition end */ 311 + 312 + #define RK3366_REG_CFG_DONE 0x0000 313 + #define RK3366_VERSION_INFO 0x0004 314 + #define RK3366_SYS_CTRL 0x0008 315 + #define RK3366_SYS_CTRL1 0x000c 316 + #define RK3366_DSP_CTRL0 0x0010 317 + #define RK3366_DSP_CTRL1 0x0014 318 + #define RK3366_DSP_BG 0x0018 319 + #define RK3366_MCU_CTRL 0x001c 320 + #define RK3366_WB_CTRL0 0x0020 321 + #define RK3366_WB_CTRL1 0x0024 322 + #define RK3366_WB_YRGB_MST 0x0028 323 + #define RK3366_WB_CBR_MST 0x002c 324 + #define RK3366_WIN0_CTRL0 0x0030 325 + #define RK3366_WIN0_CTRL1 0x0034 326 + #define RK3366_WIN0_COLOR_KEY 0x0038 327 + #define RK3366_WIN0_VIR 0x003c 328 + #define RK3366_WIN0_YRGB_MST 0x0040 329 + #define RK3366_WIN0_CBR_MST 0x0044 330 + #define RK3366_WIN0_ACT_INFO 0x0048 331 + #define RK3366_WIN0_DSP_INFO 0x004c 332 + #define RK3366_WIN0_DSP_ST 0x0050 333 + #define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054 334 + #define RK3366_WIN0_SCL_FACTOR_CBR 0x0058 335 + #define RK3366_WIN0_SCL_OFFSET 0x005c 336 + #define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060 337 + #define RK3366_WIN0_DST_ALPHA_CTRL 0x0064 338 + #define RK3366_WIN0_FADING_CTRL 0x0068 339 + #define RK3366_WIN0_CTRL2 0x006c 340 + #define RK3366_WIN1_CTRL0 0x0070 341 + #define RK3366_WIN1_CTRL1 0x0074 342 + #define RK3366_WIN1_COLOR_KEY 0x0078 343 + #define RK3366_WIN1_VIR 0x007c 344 + #define RK3366_WIN1_YRGB_MST 0x0080 345 + #define RK3366_WIN1_CBR_MST 0x0084 346 + #define RK3366_WIN1_ACT_INFO 0x0088 347 + #define RK3366_WIN1_DSP_INFO 0x008c 348 + #define RK3366_WIN1_DSP_ST 0x0090 349 + #define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094 350 + #define RK3366_WIN1_SCL_FACTOR_CBR 0x0098 351 + #define RK3366_WIN1_SCL_OFFSET 0x009c 352 + #define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0 353 + #define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4 354 + #define RK3366_WIN1_FADING_CTRL 0x00a8 355 + #define RK3366_WIN1_CTRL2 0x00ac 356 + #define RK3366_WIN2_CTRL0 0x00b0 357 + #define RK3366_WIN2_CTRL1 0x00b4 358 + #define RK3366_WIN2_VIR0_1 0x00b8 359 + #define RK3366_WIN2_VIR2_3 0x00bc 360 + #define RK3366_WIN2_MST0 0x00c0 361 + #define RK3366_WIN2_DSP_INFO0 0x00c4 362 + #define RK3366_WIN2_DSP_ST0 0x00c8 363 + #define RK3366_WIN2_COLOR_KEY 0x00cc 364 + #define RK3366_WIN2_MST1 0x00d0 365 + #define RK3366_WIN2_DSP_INFO1 0x00d4 366 + #define RK3366_WIN2_DSP_ST1 0x00d8 367 + #define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc 368 + #define RK3366_WIN2_MST2 0x00e0 369 + #define RK3366_WIN2_DSP_INFO2 0x00e4 370 + #define RK3366_WIN2_DSP_ST2 0x00e8 371 + #define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec 372 + #define RK3366_WIN2_MST3 0x00f0 373 + #define RK3366_WIN2_DSP_INFO3 0x00f4 374 + #define RK3366_WIN2_DSP_ST3 0x00f8 375 + #define RK3366_WIN2_FADING_CTRL 0x00fc 376 + #define RK3366_WIN3_CTRL0 0x0100 377 + #define RK3366_WIN3_CTRL1 0x0104 378 + #define RK3366_WIN3_VIR0_1 0x0108 379 + #define RK3366_WIN3_VIR2_3 0x010c 380 + #define RK3366_WIN3_MST0 0x0110 381 + #define RK3366_WIN3_DSP_INFO0 0x0114 382 + #define RK3366_WIN3_DSP_ST0 0x0118 383 + #define RK3366_WIN3_COLOR_KEY 0x011c 384 + #define RK3366_WIN3_MST1 0x0120 385 + #define RK3366_WIN3_DSP_INFO1 0x0124 386 + #define RK3366_WIN3_DSP_ST1 0x0128 387 + #define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c 388 + #define RK3366_WIN3_MST2 0x0130 389 + #define RK3366_WIN3_DSP_INFO2 0x0134 390 + #define RK3366_WIN3_DSP_ST2 0x0138 391 + #define RK3366_WIN3_DST_ALPHA_CTRL 0x013c 392 + #define RK3366_WIN3_MST3 0x0140 393 + #define RK3366_WIN3_DSP_INFO3 0x0144 394 + #define RK3366_WIN3_DSP_ST3 0x0148 395 + #define RK3366_WIN3_FADING_CTRL 0x014c 396 + #define RK3366_HWC_CTRL0 0x0150 397 + #define RK3366_HWC_CTRL1 0x0154 398 + #define RK3366_HWC_MST 0x0158 399 + #define RK3366_HWC_DSP_ST 0x015c 400 + #define RK3366_HWC_SRC_ALPHA_CTRL 0x0160 401 + #define RK3366_HWC_DST_ALPHA_CTRL 0x0164 402 + #define RK3366_HWC_FADING_CTRL 0x0168 403 + #define RK3366_HWC_RESERVED1 0x016c 404 + #define RK3366_POST_DSP_HACT_INFO 0x0170 405 + #define RK3366_POST_DSP_VACT_INFO 0x0174 406 + #define RK3366_POST_SCL_FACTOR_YRGB 0x0178 407 + #define RK3366_POST_RESERVED 0x017c 408 + #define RK3366_POST_SCL_CTRL 0x0180 409 + #define RK3366_POST_DSP_VACT_INFO_F1 0x0184 410 + #define RK3366_DSP_HTOTAL_HS_END 0x0188 411 + #define RK3366_DSP_HACT_ST_END 0x018c 412 + #define RK3366_DSP_VTOTAL_VS_END 0x0190 413 + #define RK3366_DSP_VACT_ST_END 0x0194 414 + #define RK3366_DSP_VS_ST_END_F1 0x0198 415 + #define RK3366_DSP_VACT_ST_END_F1 0x019c 416 + #define RK3366_PWM_CTRL 0x01a0 417 + #define RK3366_PWM_PERIOD_HPR 0x01a4 418 + #define RK3366_PWM_DUTY_LPR 0x01a8 419 + #define RK3366_PWM_CNT 0x01ac 420 + #define RK3366_BCSH_COLOR_BAR 0x01b0 421 + #define RK3366_BCSH_BCS 0x01b4 422 + #define RK3366_BCSH_H 0x01b8 423 + #define RK3366_BCSH_CTRL 0x01bc 424 + #define RK3366_CABC_CTRL0 0x01c0 425 + #define RK3366_CABC_CTRL1 0x01c4 426 + #define RK3366_CABC_CTRL2 0x01c8 427 + #define RK3366_CABC_CTRL3 0x01cc 428 + #define RK3366_CABC_GAUSS_LINE0_0 0x01d0 429 + #define RK3366_CABC_GAUSS_LINE0_1 0x01d4 430 + #define RK3366_CABC_GAUSS_LINE1_0 0x01d8 431 + #define RK3366_CABC_GAUSS_LINE1_1 0x01dc 432 + #define RK3366_CABC_GAUSS_LINE2_0 0x01e0 433 + #define RK3366_CABC_GAUSS_LINE2_1 0x01e4 434 + #define RK3366_FRC_LOWER01_0 0x01e8 435 + #define RK3366_FRC_LOWER01_1 0x01ec 436 + #define RK3366_FRC_LOWER10_0 0x01f0 437 + #define RK3366_FRC_LOWER10_1 0x01f4 438 + #define RK3366_FRC_LOWER11_0 0x01f8 439 + #define RK3366_FRC_LOWER11_1 0x01fc 440 + #define RK3366_INTR_EN0 0x0280 441 + #define RK3366_INTR_CLEAR0 0x0284 442 + #define RK3366_INTR_STATUS0 0x0288 443 + #define RK3366_INTR_RAW_STATUS0 0x028c 444 + #define RK3366_INTR_EN1 0x0290 445 + #define RK3366_INTR_CLEAR1 0x0294 446 + #define RK3366_INTR_STATUS1 0x0298 447 + #define RK3366_INTR_RAW_STATUS1 0x029c 448 + #define RK3366_LINE_FLAG 0x02a0 449 + #define RK3366_VOP_STATUS 0x02a4 450 + #define RK3366_BLANKING_VALUE 0x02a8 451 + #define RK3366_WIN0_DSP_BG 0x02b0 452 + #define RK3366_WIN1_DSP_BG 0x02b4 453 + #define RK3366_WIN2_DSP_BG 0x02b8 454 + #define RK3366_WIN3_DSP_BG 0x02bc 455 + #define RK3366_WIN2_LUT_ADDR 0x0400 456 + #define RK3366_WIN3_LUT_ADDR 0x0800 457 + #define RK3366_HWC_LUT_ADDR 0x0c00 458 + #define RK3366_GAMMA0_LUT_ADDR 0x1000 459 + #define RK3366_GAMMA1_LUT_ADDR 0x1400 460 + #define RK3366_CABC_GAMMA_LUT_ADDR 0x1800 461 + #define RK3366_MCU_BYPASS_WPORT 0x2200 462 + #define RK3366_MCU_BYPASS_RPORT 0x2300 463 + #define RK3366_MMU_DTE_ADDR 0x2400 464 + #define RK3366_MMU_STATUS 0x2404 465 + #define RK3366_MMU_COMMAND 0x2408 466 + #define RK3366_MMU_PAGE_FAULT_ADDR 0x240c 467 + #define RK3366_MMU_ZAP_ONE_LINE 0x2410 468 + #define RK3366_MMU_INT_RAWSTAT 0x2414 469 + #define RK3366_MMU_INT_CLEAR 0x2418 470 + #define RK3366_MMU_INT_MASK 0x241c 471 + #define RK3366_MMU_INT_STATUS 0x2420 472 + #define RK3366_MMU_AUTO_GATING 0x2424 473 + 474 + /* rk3399 register definition */ 475 + #define RK3399_REG_CFG_DONE 0x0000 476 + #define RK3399_VERSION_INFO 0x0004 477 + #define RK3399_SYS_CTRL 0x0008 478 + #define RK3399_SYS_CTRL1 0x000c 479 + #define RK3399_DSP_CTRL0 0x0010 480 + #define RK3399_DSP_CTRL1 0x0014 481 + #define RK3399_DSP_BG 0x0018 482 + #define RK3399_MCU_CTRL 0x001c 483 + #define RK3399_WB_CTRL0 0x0020 484 + #define RK3399_WB_CTRL1 0x0024 485 + #define RK3399_WB_YRGB_MST 0x0028 486 + #define RK3399_WB_CBR_MST 0x002c 487 + #define RK3399_WIN0_CTRL0 0x0030 488 + #define RK3399_WIN0_CTRL1 0x0034 489 + #define RK3399_WIN0_COLOR_KEY 0x0038 490 + #define RK3399_WIN0_VIR 0x003c 491 + #define RK3399_WIN0_YRGB_MST 0x0040 492 + #define RK3399_WIN0_CBR_MST 0x0044 493 + #define RK3399_WIN0_ACT_INFO 0x0048 494 + #define RK3399_WIN0_DSP_INFO 0x004c 495 + #define RK3399_WIN0_DSP_ST 0x0050 496 + #define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054 497 + #define RK3399_WIN0_SCL_FACTOR_CBR 0x0058 498 + #define RK3399_WIN0_SCL_OFFSET 0x005c 499 + #define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060 500 + #define RK3399_WIN0_DST_ALPHA_CTRL 0x0064 501 + #define RK3399_WIN0_FADING_CTRL 0x0068 502 + #define RK3399_WIN0_CTRL2 0x006c 503 + #define RK3399_WIN1_CTRL0 0x0070 504 + #define RK3399_WIN1_CTRL1 0x0074 505 + #define RK3399_WIN1_COLOR_KEY 0x0078 506 + #define RK3399_WIN1_VIR 0x007c 507 + #define RK3399_WIN1_YRGB_MST 0x0080 508 + #define RK3399_WIN1_CBR_MST 0x0084 509 + #define RK3399_WIN1_ACT_INFO 0x0088 510 + #define RK3399_WIN1_DSP_INFO 0x008c 511 + #define RK3399_WIN1_DSP_ST 0x0090 512 + #define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094 513 + #define RK3399_WIN1_SCL_FACTOR_CBR 0x0098 514 + #define RK3399_WIN1_SCL_OFFSET 0x009c 515 + #define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0 516 + #define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4 517 + #define RK3399_WIN1_FADING_CTRL 0x00a8 518 + #define RK3399_WIN1_CTRL2 0x00ac 519 + #define RK3399_WIN2_CTRL0 0x00b0 520 + #define RK3399_WIN2_CTRL1 0x00b4 521 + #define RK3399_WIN2_VIR0_1 0x00b8 522 + #define RK3399_WIN2_VIR2_3 0x00bc 523 + #define RK3399_WIN2_MST0 0x00c0 524 + #define RK3399_WIN2_DSP_INFO0 0x00c4 525 + #define RK3399_WIN2_DSP_ST0 0x00c8 526 + #define RK3399_WIN2_COLOR_KEY 0x00cc 527 + #define RK3399_WIN2_MST1 0x00d0 528 + #define RK3399_WIN2_DSP_INFO1 0x00d4 529 + #define RK3399_WIN2_DSP_ST1 0x00d8 530 + #define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc 531 + #define RK3399_WIN2_MST2 0x00e0 532 + #define RK3399_WIN2_DSP_INFO2 0x00e4 533 + #define RK3399_WIN2_DSP_ST2 0x00e8 534 + #define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec 535 + #define RK3399_WIN2_MST3 0x00f0 536 + #define RK3399_WIN2_DSP_INFO3 0x00f4 537 + #define RK3399_WIN2_DSP_ST3 0x00f8 538 + #define RK3399_WIN2_FADING_CTRL 0x00fc 539 + #define RK3399_WIN3_CTRL0 0x0100 540 + #define RK3399_WIN3_CTRL1 0x0104 541 + #define RK3399_WIN3_VIR0_1 0x0108 542 + #define RK3399_WIN3_VIR2_3 0x010c 543 + #define RK3399_WIN3_MST0 0x0110 544 + #define RK3399_WIN3_DSP_INFO0 0x0114 545 + #define RK3399_WIN3_DSP_ST0 0x0118 546 + #define RK3399_WIN3_COLOR_KEY 0x011c 547 + #define RK3399_WIN3_MST1 0x0120 548 + #define RK3399_WIN3_DSP_INFO1 0x0124 549 + #define RK3399_WIN3_DSP_ST1 0x0128 550 + #define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c 551 + #define RK3399_WIN3_MST2 0x0130 552 + #define RK3399_WIN3_DSP_INFO2 0x0134 553 + #define RK3399_WIN3_DSP_ST2 0x0138 554 + #define RK3399_WIN3_DST_ALPHA_CTRL 0x013c 555 + #define RK3399_WIN3_MST3 0x0140 556 + #define RK3399_WIN3_DSP_INFO3 0x0144 557 + #define RK3399_WIN3_DSP_ST3 0x0148 558 + #define RK3399_WIN3_FADING_CTRL 0x014c 559 + #define RK3399_HWC_CTRL0 0x0150 560 + #define RK3399_HWC_CTRL1 0x0154 561 + #define RK3399_HWC_MST 0x0158 562 + #define RK3399_HWC_DSP_ST 0x015c 563 + #define RK3399_HWC_SRC_ALPHA_CTRL 0x0160 564 + #define RK3399_HWC_DST_ALPHA_CTRL 0x0164 565 + #define RK3399_HWC_FADING_CTRL 0x0168 566 + #define RK3399_HWC_RESERVED1 0x016c 567 + #define RK3399_POST_DSP_HACT_INFO 0x0170 568 + #define RK3399_POST_DSP_VACT_INFO 0x0174 569 + #define RK3399_POST_SCL_FACTOR_YRGB 0x0178 570 + #define RK3399_POST_RESERVED 0x017c 571 + #define RK3399_POST_SCL_CTRL 0x0180 572 + #define RK3399_POST_DSP_VACT_INFO_F1 0x0184 573 + #define RK3399_DSP_HTOTAL_HS_END 0x0188 574 + #define RK3399_DSP_HACT_ST_END 0x018c 575 + #define RK3399_DSP_VTOTAL_VS_END 0x0190 576 + #define RK3399_DSP_VACT_ST_END 0x0194 577 + #define RK3399_DSP_VS_ST_END_F1 0x0198 578 + #define RK3399_DSP_VACT_ST_END_F1 0x019c 579 + #define RK3399_PWM_CTRL 0x01a0 580 + #define RK3399_PWM_PERIOD_HPR 0x01a4 581 + #define RK3399_PWM_DUTY_LPR 0x01a8 582 + #define RK3399_PWM_CNT 0x01ac 583 + #define RK3399_BCSH_COLOR_BAR 0x01b0 584 + #define RK3399_BCSH_BCS 0x01b4 585 + #define RK3399_BCSH_H 0x01b8 586 + #define RK3399_BCSH_CTRL 0x01bc 587 + #define RK3399_CABC_CTRL0 0x01c0 588 + #define RK3399_CABC_CTRL1 0x01c4 589 + #define RK3399_CABC_CTRL2 0x01c8 590 + #define RK3399_CABC_CTRL3 0x01cc 591 + #define RK3399_CABC_GAUSS_LINE0_0 0x01d0 592 + #define RK3399_CABC_GAUSS_LINE0_1 0x01d4 593 + #define RK3399_CABC_GAUSS_LINE1_0 0x01d8 594 + #define RK3399_CABC_GAUSS_LINE1_1 0x01dc 595 + #define RK3399_CABC_GAUSS_LINE2_0 0x01e0 596 + #define RK3399_CABC_GAUSS_LINE2_1 0x01e4 597 + #define RK3399_FRC_LOWER01_0 0x01e8 598 + #define RK3399_FRC_LOWER01_1 0x01ec 599 + #define RK3399_FRC_LOWER10_0 0x01f0 600 + #define RK3399_FRC_LOWER10_1 0x01f4 601 + #define RK3399_FRC_LOWER11_0 0x01f8 602 + #define RK3399_FRC_LOWER11_1 0x01fc 603 + #define RK3399_AFBCD0_CTRL 0x0200 604 + #define RK3399_AFBCD0_HDR_PTR 0x0204 605 + #define RK3399_AFBCD0_PIC_SIZE 0x0208 606 + #define RK3399_AFBCD0_STATUS 0x020c 607 + #define RK3399_AFBCD1_CTRL 0x0220 608 + #define RK3399_AFBCD1_HDR_PTR 0x0224 609 + #define RK3399_AFBCD1_PIC_SIZE 0x0228 610 + #define RK3399_AFBCD1_STATUS 0x022c 611 + #define RK3399_AFBCD2_CTRL 0x0240 612 + #define RK3399_AFBCD2_HDR_PTR 0x0244 613 + #define RK3399_AFBCD2_PIC_SIZE 0x0248 614 + #define RK3399_AFBCD2_STATUS 0x024c 615 + #define RK3399_AFBCD3_CTRL 0x0260 616 + #define RK3399_AFBCD3_HDR_PTR 0x0264 617 + #define RK3399_AFBCD3_PIC_SIZE 0x0268 618 + #define RK3399_AFBCD3_STATUS 0x026c 619 + #define RK3399_INTR_EN0 0x0280 620 + #define RK3399_INTR_CLEAR0 0x0284 621 + #define RK3399_INTR_STATUS0 0x0288 622 + #define RK3399_INTR_RAW_STATUS0 0x028c 623 + #define RK3399_INTR_EN1 0x0290 624 + #define RK3399_INTR_CLEAR1 0x0294 625 + #define RK3399_INTR_STATUS1 0x0298 626 + #define RK3399_INTR_RAW_STATUS1 0x029c 627 + #define RK3399_LINE_FLAG 0x02a0 628 + #define RK3399_VOP_STATUS 0x02a4 629 + #define RK3399_BLANKING_VALUE 0x02a8 630 + #define RK3399_MCU_BYPASS_PORT 0x02ac 631 + #define RK3399_WIN0_DSP_BG 0x02b0 632 + #define RK3399_WIN1_DSP_BG 0x02b4 633 + #define RK3399_WIN2_DSP_BG 0x02b8 634 + #define RK3399_WIN3_DSP_BG 0x02bc 635 + #define RK3399_YUV2YUV_WIN 0x02c0 636 + #define RK3399_YUV2YUV_POST 0x02c4 637 + #define RK3399_AUTO_GATING_EN 0x02cc 638 + #define RK3399_WIN0_CSC_COE 0x03a0 639 + #define RK3399_WIN1_CSC_COE 0x03c0 640 + #define RK3399_WIN2_CSC_COE 0x03e0 641 + #define RK3399_WIN3_CSC_COE 0x0400 642 + #define RK3399_HWC_CSC_COE 0x0420 643 + #define RK3399_BCSH_R2Y_CSC_COE 0x0440 644 + #define RK3399_BCSH_Y2R_CSC_COE 0x0460 645 + #define RK3399_POST_YUV2YUV_Y2R_COE 0x0480 646 + #define RK3399_POST_YUV2YUV_3X3_COE 0x04a0 647 + #define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0 648 + #define RK3399_WIN0_YUV2YUV_Y2R 0x04e0 649 + #define RK3399_WIN0_YUV2YUV_3X3 0x0500 650 + #define RK3399_WIN0_YUV2YUV_R2Y 0x0520 651 + #define RK3399_WIN1_YUV2YUV_Y2R 0x0540 652 + #define RK3399_WIN1_YUV2YUV_3X3 0x0560 653 + #define RK3399_WIN1_YUV2YUV_R2Y 0x0580 654 + #define RK3399_WIN2_YUV2YUV_Y2R 0x05a0 655 + #define RK3399_WIN2_YUV2YUV_3X3 0x05c0 656 + #define RK3399_WIN2_YUV2YUV_R2Y 0x05e0 657 + #define RK3399_WIN3_YUV2YUV_Y2R 0x0600 658 + #define RK3399_WIN3_YUV2YUV_3X3 0x0620 659 + #define RK3399_WIN3_YUV2YUV_R2Y 0x0640 660 + #define RK3399_WIN2_LUT_ADDR 0x1000 661 + #define RK3399_WIN3_LUT_ADDR 0x1400 662 + #define RK3399_HWC_LUT_ADDR 0x1800 663 + #define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00 664 + #define RK3399_GAMMA_LUT_ADDR 0x2000 665 + /* rk3399 register definition end */ 666 + 667 + /* rk3328 register definition end */ 668 + #define RK3328_REG_CFG_DONE 0x00000000 669 + #define RK3328_VERSION_INFO 0x00000004 670 + #define RK3328_SYS_CTRL 0x00000008 671 + #define RK3328_SYS_CTRL1 0x0000000c 672 + #define RK3328_DSP_CTRL0 0x00000010 673 + #define RK3328_DSP_CTRL1 0x00000014 674 + #define RK3328_DSP_BG 0x00000018 675 + #define RK3328_AUTO_GATING_EN 0x0000003c 676 + #define RK3328_LINE_FLAG 0x00000040 677 + #define RK3328_VOP_STATUS 0x00000044 678 + #define RK3328_BLANKING_VALUE 0x00000048 679 + #define RK3328_WIN0_DSP_BG 0x00000050 680 + #define RK3328_WIN1_DSP_BG 0x00000054 681 + #define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0 682 + #define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4 683 + #define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8 684 + #define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc 685 + #define RK3328_INTR_EN0 0x000000e0 686 + #define RK3328_INTR_CLEAR0 0x000000e4 687 + #define RK3328_INTR_STATUS0 0x000000e8 688 + #define RK3328_INTR_RAW_STATUS0 0x000000ec 689 + #define RK3328_INTR_EN1 0x000000f0 690 + #define RK3328_INTR_CLEAR1 0x000000f4 691 + #define RK3328_INTR_STATUS1 0x000000f8 692 + #define RK3328_INTR_RAW_STATUS1 0x000000fc 693 + #define RK3328_WIN0_CTRL0 0x00000100 694 + #define RK3328_WIN0_CTRL1 0x00000104 695 + #define RK3328_WIN0_COLOR_KEY 0x00000108 696 + #define RK3328_WIN0_VIR 0x0000010c 697 + #define RK3328_WIN0_YRGB_MST 0x00000110 698 + #define RK3328_WIN0_CBR_MST 0x00000114 699 + #define RK3328_WIN0_ACT_INFO 0x00000118 700 + #define RK3328_WIN0_DSP_INFO 0x0000011c 701 + #define RK3328_WIN0_DSP_ST 0x00000120 702 + #define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124 703 + #define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128 704 + #define RK3328_WIN0_SCL_OFFSET 0x0000012c 705 + #define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130 706 + #define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134 707 + #define RK3328_WIN0_FADING_CTRL 0x00000138 708 + #define RK3328_WIN0_CTRL2 0x0000013c 709 + #define RK3328_DBG_WIN0_REG0 0x000001f0 710 + #define RK3328_DBG_WIN0_REG1 0x000001f4 711 + #define RK3328_DBG_WIN0_REG2 0x000001f8 712 + #define RK3328_DBG_WIN0_RESERVED 0x000001fc 713 + #define RK3328_WIN1_CTRL0 0x00000200 714 + #define RK3328_WIN1_CTRL1 0x00000204 715 + #define RK3328_WIN1_COLOR_KEY 0x00000208 716 + #define RK3328_WIN1_VIR 0x0000020c 717 + #define RK3328_WIN1_YRGB_MST 0x00000210 718 + #define RK3328_WIN1_CBR_MST 0x00000214 719 + #define RK3328_WIN1_ACT_INFO 0x00000218 720 + #define RK3328_WIN1_DSP_INFO 0x0000021c 721 + #define RK3328_WIN1_DSP_ST 0x00000220 722 + #define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224 723 + #define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228 724 + #define RK3328_WIN1_SCL_OFFSET 0x0000022c 725 + #define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230 726 + #define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234 727 + #define RK3328_WIN1_FADING_CTRL 0x00000238 728 + #define RK3328_WIN1_CTRL2 0x0000023c 729 + #define RK3328_DBG_WIN1_REG0 0x000002f0 730 + #define RK3328_DBG_WIN1_REG1 0x000002f4 731 + #define RK3328_DBG_WIN1_REG2 0x000002f8 732 + #define RK3328_DBG_WIN1_RESERVED 0x000002fc 733 + #define RK3328_WIN2_CTRL0 0x00000300 734 + #define RK3328_WIN2_CTRL1 0x00000304 735 + #define RK3328_WIN2_COLOR_KEY 0x00000308 736 + #define RK3328_WIN2_VIR 0x0000030c 737 + #define RK3328_WIN2_YRGB_MST 0x00000310 738 + #define RK3328_WIN2_CBR_MST 0x00000314 739 + #define RK3328_WIN2_ACT_INFO 0x00000318 740 + #define RK3328_WIN2_DSP_INFO 0x0000031c 741 + #define RK3328_WIN2_DSP_ST 0x00000320 742 + #define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324 743 + #define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328 744 + #define RK3328_WIN2_SCL_OFFSET 0x0000032c 745 + #define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330 746 + #define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334 747 + #define RK3328_WIN2_FADING_CTRL 0x00000338 748 + #define RK3328_WIN2_CTRL2 0x0000033c 749 + #define RK3328_DBG_WIN2_REG0 0x000003f0 750 + #define RK3328_DBG_WIN2_REG1 0x000003f4 751 + #define RK3328_DBG_WIN2_REG2 0x000003f8 752 + #define RK3328_DBG_WIN2_RESERVED 0x000003fc 753 + #define RK3328_WIN3_CTRL0 0x00000400 754 + #define RK3328_WIN3_CTRL1 0x00000404 755 + #define RK3328_WIN3_COLOR_KEY 0x00000408 756 + #define RK3328_WIN3_VIR 0x0000040c 757 + #define RK3328_WIN3_YRGB_MST 0x00000410 758 + #define RK3328_WIN3_CBR_MST 0x00000414 759 + #define RK3328_WIN3_ACT_INFO 0x00000418 760 + #define RK3328_WIN3_DSP_INFO 0x0000041c 761 + #define RK3328_WIN3_DSP_ST 0x00000420 762 + #define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424 763 + #define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428 764 + #define RK3328_WIN3_SCL_OFFSET 0x0000042c 765 + #define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430 766 + #define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434 767 + #define RK3328_WIN3_FADING_CTRL 0x00000438 768 + #define RK3328_WIN3_CTRL2 0x0000043c 769 + #define RK3328_DBG_WIN3_REG0 0x000004f0 770 + #define RK3328_DBG_WIN3_REG1 0x000004f4 771 + #define RK3328_DBG_WIN3_REG2 0x000004f8 772 + #define RK3328_DBG_WIN3_RESERVED 0x000004fc 773 + 774 + #define RK3328_HWC_CTRL0 0x00000500 775 + #define RK3328_HWC_CTRL1 0x00000504 776 + #define RK3328_HWC_MST 0x00000508 777 + #define RK3328_HWC_DSP_ST 0x0000050c 778 + #define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510 779 + #define RK3328_HWC_DST_ALPHA_CTRL 0x00000514 780 + #define RK3328_HWC_FADING_CTRL 0x00000518 781 + #define RK3328_HWC_RESERVED1 0x0000051c 782 + #define RK3328_POST_DSP_HACT_INFO 0x00000600 783 + #define RK3328_POST_DSP_VACT_INFO 0x00000604 784 + #define RK3328_POST_SCL_FACTOR_YRGB 0x00000608 785 + #define RK3328_POST_RESERVED 0x0000060c 786 + #define RK3328_POST_SCL_CTRL 0x00000610 787 + #define RK3328_POST_DSP_VACT_INFO_F1 0x00000614 788 + #define RK3328_DSP_HTOTAL_HS_END 0x00000618 789 + #define RK3328_DSP_HACT_ST_END 0x0000061c 790 + #define RK3328_DSP_VTOTAL_VS_END 0x00000620 791 + #define RK3328_DSP_VACT_ST_END 0x00000624 792 + #define RK3328_DSP_VS_ST_END_F1 0x00000628 793 + #define RK3328_DSP_VACT_ST_END_F1 0x0000062c 794 + #define RK3328_BCSH_COLOR_BAR 0x00000640 795 + #define RK3328_BCSH_BCS 0x00000644 796 + #define RK3328_BCSH_H 0x00000648 797 + #define RK3328_BCSH_CTRL 0x0000064c 798 + #define RK3328_FRC_LOWER01_0 0x00000678 799 + #define RK3328_FRC_LOWER01_1 0x0000067c 800 + #define RK3328_FRC_LOWER10_0 0x00000680 801 + #define RK3328_FRC_LOWER10_1 0x00000684 802 + #define RK3328_FRC_LOWER11_0 0x00000688 803 + #define RK3328_FRC_LOWER11_1 0x0000068c 804 + #define RK3328_DBG_POST_REG0 0x000006e8 805 + #define RK3328_DBG_POST_RESERVED 0x000006ec 806 + #define RK3328_DBG_DATAO 0x000006f0 807 + #define RK3328_DBG_DATAO_2 0x000006f4 808 + 809 + /* sdr to hdr */ 810 + #define RK3328_SDR2HDR_CTRL 0x00000700 811 + #define RK3328_EOTF_OETF_Y0 0x00000704 812 + #define RK3328_RESERVED0001 0x00000708 813 + #define RK3328_RESERVED0002 0x0000070c 814 + #define RK3328_EOTF_OETF_Y1 0x00000710 815 + #define RK3328_EOTF_OETF_Y64 0x0000080c 816 + #define RK3328_OETF_DX_DXPOW1 0x00000810 817 + #define RK3328_OETF_DX_DXPOW64 0x0000090c 818 + #define RK3328_OETF_XN1 0x00000910 819 + #define RK3328_OETF_XN63 0x00000a08 820 + 821 + /* hdr to sdr */ 822 + #define RK3328_HDR2SDR_CTRL 0x00000a10 823 + #define RK3328_HDR2SDR_SRC_RANGE 0x00000a14 824 + #define RK3328_HDR2SDR_NORMFACEETF 0x00000a18 825 + #define RK3328_RESERVED0003 0x00000a1c 826 + #define RK3328_HDR2SDR_DST_RANGE 0x00000a20 827 + #define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24 828 + #define RK3328_EETF_OETF_Y0 0x00000a28 829 + #define RK3328_SAT_Y0 0x00000a2c 830 + #define RK3328_EETF_OETF_Y1 0x00000a30 831 + #define RK3328_SAT_Y1 0x00000ab0 832 + #define RK3328_SAT_Y8 0x00000acc 833 + 834 + #define RK3328_HWC_LUT_ADDR 0x00000c00 835 + 126 836 /* rk3036 register definition */ 127 837 #define RK3036_SYS_CTRL 0x00 128 838 #define RK3036_DSP_CTRL0 0x04 ··· 877 165 #define RK3036_WIN1_LUT_ADDR 0x400 878 166 #define RK3036_HWC_LUT_ADDR 0x800 879 167 /* rk3036 register definition end */ 880 - 881 - /* rk3399 register definition */ 882 - #define RK3399_REG_CFG_DONE 0x00000 883 - #define RK3399_VERSION_INFO 0x00004 884 - #define RK3399_SYS_CTRL 0x00008 885 - #define RK3399_SYS_CTRL1 0x0000c 886 - #define RK3399_DSP_CTRL0 0x00010 887 - #define RK3399_DSP_CTRL1 0x00014 888 - #define RK3399_DSP_BG 0x00018 889 - #define RK3399_MCU_CTRL 0x0001c 890 - #define RK3399_WB_CTRL0 0x00020 891 - #define RK3399_WB_CTRL1 0x00024 892 - #define RK3399_WB_YRGB_MST 0x00028 893 - #define RK3399_WB_CBR_MST 0x0002c 894 - #define RK3399_WIN0_CTRL0 0x00030 895 - #define RK3399_WIN0_CTRL1 0x00034 896 - #define RK3399_WIN0_COLOR_KEY 0x00038 897 - #define RK3399_WIN0_VIR 0x0003c 898 - #define RK3399_WIN0_YRGB_MST 0x00040 899 - #define RK3399_WIN0_CBR_MST 0x00044 900 - #define RK3399_WIN0_ACT_INFO 0x00048 901 - #define RK3399_WIN0_DSP_INFO 0x0004c 902 - #define RK3399_WIN0_DSP_ST 0x00050 903 - #define RK3399_WIN0_SCL_FACTOR_YRGB 0x00054 904 - #define RK3399_WIN0_SCL_FACTOR_CBR 0x00058 905 - #define RK3399_WIN0_SCL_OFFSET 0x0005c 906 - #define RK3399_WIN0_SRC_ALPHA_CTRL 0x00060 907 - #define RK3399_WIN0_DST_ALPHA_CTRL 0x00064 908 - #define RK3399_WIN0_FADING_CTRL 0x00068 909 - #define RK3399_WIN0_CTRL2 0x0006c 910 - #define RK3399_WIN1_CTRL0 0x00070 911 - #define RK3399_WIN1_CTRL1 0x00074 912 - #define RK3399_WIN1_COLOR_KEY 0x00078 913 - #define RK3399_WIN1_VIR 0x0007c 914 - #define RK3399_WIN1_YRGB_MST 0x00080 915 - #define RK3399_WIN1_CBR_MST 0x00084 916 - #define RK3399_WIN1_ACT_INFO 0x00088 917 - #define RK3399_WIN1_DSP_INFO 0x0008c 918 - #define RK3399_WIN1_DSP_ST 0x00090 919 - #define RK3399_WIN1_SCL_FACTOR_YRGB 0x00094 920 - #define RK3399_WIN1_SCL_FACTOR_CBR 0x00098 921 - #define RK3399_WIN1_SCL_OFFSET 0x0009c 922 - #define RK3399_WIN1_SRC_ALPHA_CTRL 0x000a0 923 - #define RK3399_WIN1_DST_ALPHA_CTRL 0x000a4 924 - #define RK3399_WIN1_FADING_CTRL 0x000a8 925 - #define RK3399_WIN1_CTRL2 0x000ac 926 - #define RK3399_WIN2_CTRL0 0x000b0 927 - #define RK3399_WIN2_CTRL1 0x000b4 928 - #define RK3399_WIN2_VIR0_1 0x000b8 929 - #define RK3399_WIN2_VIR2_3 0x000bc 930 - #define RK3399_WIN2_MST0 0x000c0 931 - #define RK3399_WIN2_DSP_INFO0 0x000c4 932 - #define RK3399_WIN2_DSP_ST0 0x000c8 933 - #define RK3399_WIN2_COLOR_KEY 0x000cc 934 - #define RK3399_WIN2_MST1 0x000d0 935 - #define RK3399_WIN2_DSP_INFO1 0x000d4 936 - #define RK3399_WIN2_DSP_ST1 0x000d8 937 - #define RK3399_WIN2_SRC_ALPHA_CTRL 0x000dc 938 - #define RK3399_WIN2_MST2 0x000e0 939 - #define RK3399_WIN2_DSP_INFO2 0x000e4 940 - #define RK3399_WIN2_DSP_ST2 0x000e8 941 - #define RK3399_WIN2_DST_ALPHA_CTRL 0x000ec 942 - #define RK3399_WIN2_MST3 0x000f0 943 - #define RK3399_WIN2_DSP_INFO3 0x000f4 944 - #define RK3399_WIN2_DSP_ST3 0x000f8 945 - #define RK3399_WIN2_FADING_CTRL 0x000fc 946 - #define RK3399_WIN3_CTRL0 0x00100 947 - #define RK3399_WIN3_CTRL1 0x00104 948 - #define RK3399_WIN3_VIR0_1 0x00108 949 - #define RK3399_WIN3_VIR2_3 0x0010c 950 - #define RK3399_WIN3_MST0 0x00110 951 - #define RK3399_WIN3_DSP_INFO0 0x00114 952 - #define RK3399_WIN3_DSP_ST0 0x00118 953 - #define RK3399_WIN3_COLOR_KEY 0x0011c 954 - #define RK3399_WIN3_MST1 0x00120 955 - #define RK3399_WIN3_DSP_INFO1 0x00124 956 - #define RK3399_WIN3_DSP_ST1 0x00128 957 - #define RK3399_WIN3_SRC_ALPHA_CTRL 0x0012c 958 - #define RK3399_WIN3_MST2 0x00130 959 - #define RK3399_WIN3_DSP_INFO2 0x00134 960 - #define RK3399_WIN3_DSP_ST2 0x00138 961 - #define RK3399_WIN3_DST_ALPHA_CTRL 0x0013c 962 - #define RK3399_WIN3_MST3 0x00140 963 - #define RK3399_WIN3_DSP_INFO3 0x00144 964 - #define RK3399_WIN3_DSP_ST3 0x00148 965 - #define RK3399_WIN3_FADING_CTRL 0x0014c 966 - #define RK3399_HWC_CTRL0 0x00150 967 - #define RK3399_HWC_CTRL1 0x00154 968 - #define RK3399_HWC_MST 0x00158 969 - #define RK3399_HWC_DSP_ST 0x0015c 970 - #define RK3399_HWC_SRC_ALPHA_CTRL 0x00160 971 - #define RK3399_HWC_DST_ALPHA_CTRL 0x00164 972 - #define RK3399_HWC_FADING_CTRL 0x00168 973 - #define RK3399_HWC_RESERVED1 0x0016c 974 - #define RK3399_POST_DSP_HACT_INFO 0x00170 975 - #define RK3399_POST_DSP_VACT_INFO 0x00174 976 - #define RK3399_POST_SCL_FACTOR_YRGB 0x00178 977 - #define RK3399_POST_RESERVED 0x0017c 978 - #define RK3399_POST_SCL_CTRL 0x00180 979 - #define RK3399_POST_DSP_VACT_INFO_F1 0x00184 980 - #define RK3399_DSP_HTOTAL_HS_END 0x00188 981 - #define RK3399_DSP_HACT_ST_END 0x0018c 982 - #define RK3399_DSP_VTOTAL_VS_END 0x00190 983 - #define RK3399_DSP_VACT_ST_END 0x00194 984 - #define RK3399_DSP_VS_ST_END_F1 0x00198 985 - #define RK3399_DSP_VACT_ST_END_F1 0x0019c 986 - #define RK3399_PWM_CTRL 0x001a0 987 - #define RK3399_PWM_PERIOD_HPR 0x001a4 988 - #define RK3399_PWM_DUTY_LPR 0x001a8 989 - #define RK3399_PWM_CNT 0x001ac 990 - #define RK3399_BCSH_COLOR_BAR 0x001b0 991 - #define RK3399_BCSH_BCS 0x001b4 992 - #define RK3399_BCSH_H 0x001b8 993 - #define RK3399_BCSH_CTRL 0x001bc 994 - #define RK3399_CABC_CTRL0 0x001c0 995 - #define RK3399_CABC_CTRL1 0x001c4 996 - #define RK3399_CABC_CTRL2 0x001c8 997 - #define RK3399_CABC_CTRL3 0x001cc 998 - #define RK3399_CABC_GAUSS_LINE0_0 0x001d0 999 - #define RK3399_CABC_GAUSS_LINE0_1 0x001d4 1000 - #define RK3399_CABC_GAUSS_LINE1_0 0x001d8 1001 - #define RK3399_CABC_GAUSS_LINE1_1 0x001dc 1002 - #define RK3399_CABC_GAUSS_LINE2_0 0x001e0 1003 - #define RK3399_CABC_GAUSS_LINE2_1 0x001e4 1004 - #define RK3399_FRC_LOWER01_0 0x001e8 1005 - #define RK3399_FRC_LOWER01_1 0x001ec 1006 - #define RK3399_FRC_LOWER10_0 0x001f0 1007 - #define RK3399_FRC_LOWER10_1 0x001f4 1008 - #define RK3399_FRC_LOWER11_0 0x001f8 1009 - #define RK3399_FRC_LOWER11_1 0x001fc 1010 - #define RK3399_AFBCD0_CTRL 0x00200 1011 - #define RK3399_AFBCD0_HDR_PTR 0x00204 1012 - #define RK3399_AFBCD0_PIC_SIZE 0x00208 1013 - #define RK3399_AFBCD0_STATUS 0x0020c 1014 - #define RK3399_AFBCD1_CTRL 0x00220 1015 - #define RK3399_AFBCD1_HDR_PTR 0x00224 1016 - #define RK3399_AFBCD1_PIC_SIZE 0x00228 1017 - #define RK3399_AFBCD1_STATUS 0x0022c 1018 - #define RK3399_AFBCD2_CTRL 0x00240 1019 - #define RK3399_AFBCD2_HDR_PTR 0x00244 1020 - #define RK3399_AFBCD2_PIC_SIZE 0x00248 1021 - #define RK3399_AFBCD2_STATUS 0x0024c 1022 - #define RK3399_AFBCD3_CTRL 0x00260 1023 - #define RK3399_AFBCD3_HDR_PTR 0x00264 1024 - #define RK3399_AFBCD3_PIC_SIZE 0x00268 1025 - #define RK3399_AFBCD3_STATUS 0x0026c 1026 - #define RK3399_INTR_EN0 0x00280 1027 - #define RK3399_INTR_CLEAR0 0x00284 1028 - #define RK3399_INTR_STATUS0 0x00288 1029 - #define RK3399_INTR_RAW_STATUS0 0x0028c 1030 - #define RK3399_INTR_EN1 0x00290 1031 - #define RK3399_INTR_CLEAR1 0x00294 1032 - #define RK3399_INTR_STATUS1 0x00298 1033 - #define RK3399_INTR_RAW_STATUS1 0x0029c 1034 - #define RK3399_LINE_FLAG 0x002a0 1035 - #define RK3399_VOP_STATUS 0x002a4 1036 - #define RK3399_BLANKING_VALUE 0x002a8 1037 - #define RK3399_MCU_BYPASS_PORT 0x002ac 1038 - #define RK3399_WIN0_DSP_BG 0x002b0 1039 - #define RK3399_WIN1_DSP_BG 0x002b4 1040 - #define RK3399_WIN2_DSP_BG 0x002b8 1041 - #define RK3399_WIN3_DSP_BG 0x002bc 1042 - #define RK3399_YUV2YUV_WIN 0x002c0 1043 - #define RK3399_YUV2YUV_POST 0x002c4 1044 - #define RK3399_AUTO_GATING_EN 0x002cc 1045 - #define RK3399_WIN0_CSC_COE 0x003a0 1046 - #define RK3399_WIN1_CSC_COE 0x003c0 1047 - #define RK3399_WIN2_CSC_COE 0x003e0 1048 - #define RK3399_WIN3_CSC_COE 0x00400 1049 - #define RK3399_HWC_CSC_COE 0x00420 1050 - #define RK3399_BCSH_R2Y_CSC_COE 0x00440 1051 - #define RK3399_BCSH_Y2R_CSC_COE 0x00460 1052 - #define RK3399_POST_YUV2YUV_Y2R_COE 0x00480 1053 - #define RK3399_POST_YUV2YUV_3X3_COE 0x004a0 1054 - #define RK3399_POST_YUV2YUV_R2Y_COE 0x004c0 1055 - #define RK3399_WIN0_YUV2YUV_Y2R 0x004e0 1056 - #define RK3399_WIN0_YUV2YUV_3X3 0x00500 1057 - #define RK3399_WIN0_YUV2YUV_R2Y 0x00520 1058 - #define RK3399_WIN1_YUV2YUV_Y2R 0x00540 1059 - #define RK3399_WIN1_YUV2YUV_3X3 0x00560 1060 - #define RK3399_WIN1_YUV2YUV_R2Y 0x00580 1061 - #define RK3399_WIN2_YUV2YUV_Y2R 0x005a0 1062 - #define RK3399_WIN2_YUV2YUV_3X3 0x005c0 1063 - #define RK3399_WIN2_YUV2YUV_R2Y 0x005e0 1064 - #define RK3399_WIN3_YUV2YUV_Y2R 0x00600 1065 - #define RK3399_WIN3_YUV2YUV_3X3 0x00620 1066 - #define RK3399_WIN3_YUV2YUV_R2Y 0x00640 1067 - #define RK3399_WIN2_LUT_ADDR 0x01000 1068 - #define RK3399_WIN3_LUT_ADDR 0x01400 1069 - #define RK3399_HWC_LUT_ADDR 0x01800 1070 - #define RK3399_CABC_GAMMA_LUT_ADDR 0x01c00 1071 - #define RK3399_GAMMA_LUT_ADDR 0x02000 1072 - /* rk3399 register definition end */ 1073 168 1074 169 #endif /* _ROCKCHIP_VOP_REG_H */