Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

staging: pi433: Remove unused driver

Marcus started a project in 2016 to bring the pi433 alive. One project
was funded successfully but the second not. So only a few pi433 got sold
to early adaptors during this time that ended late 2017. There is a
simple user space program available for a demo with the pi433 but that
does not use this driver.

The driver is unused since 2018. No description or user space application
to use it can be found. To bring it alive the device tree needs to be
adjusted manually.

The last patch reviewed by Marcus was in June 2018, last patch tested
was in July 2017.

No response since 27. March 2024 regarding the removal of the driver.
Remove unused driver because of the above named reasons.

Link: https://lore.kernel.org/linux-staging/c4c5ab38-8c67-4c21-86bc-f4f3c06be358@gmail.com/
Link: https://www.kickstarter.com/projects/1292669042/pi433-a-radio-module-funkmodul-for-raspberry-pi
Link: https://www.kickstarter.com/projects/1292669042/smarthome-pi/comments
Link: https://www.pi433.de/en.html
Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Cc: Marcus Wolf <marcus.wolf@wolf-entwicklungen.de>
Link: https://lore.kernel.org/r/20240421195717.GA10943@matrix-ESPRIMO-P710
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

authored by

Philipp Hortmann and committed by
Greg Kroah-Hartman
eb563dc7 cf707f77

-3503
-2
drivers/staging/Kconfig
··· 60 60 61 61 source "drivers/staging/vc04_services/Kconfig" 62 62 63 - source "drivers/staging/pi433/Kconfig" 64 - 65 63 source "drivers/staging/axis-fifo/Kconfig" 66 64 67 65 source "drivers/staging/fieldbus/Kconfig"
-1
drivers/staging/Makefile
··· 20 20 obj-$(CONFIG_KS7010) += ks7010/ 21 21 obj-$(CONFIG_GREYBUS) += greybus/ 22 22 obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/ 23 - obj-$(CONFIG_PI433) += pi433/ 24 23 obj-$(CONFIG_XIL_AXIS_FIFO) += axis-fifo/ 25 24 obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/
-48
drivers/staging/pi433/Documentation/devicetree/pi433-overlay.dtso
··· 1 - // Definitions for Pi433 2 - /dts-v1/; 3 - /plugin/; 4 - 5 - / { 6 - compatible = "brcm,bcm2835", "brcm,bcm2708", "brcm,bcm2709"; 7 - }; 8 - 9 - &spi0 { 10 - #address-cells = <1>; 11 - #size-cells = <0>; 12 - status = "okay"; 13 - 14 - spidev@0{ 15 - reg = <0>; 16 - status = "disabled"; 17 - }; 18 - 19 - spidev@1{ 20 - reg = <1>; 21 - status = "disabled"; 22 - }; 23 - }; 24 - 25 - &gpio { 26 - pi433_pins: pi433_pins { 27 - brcm,pins = <7 25 24>; 28 - brcm,function = <0 0 0>; // in in in 29 - }; 30 - }; 31 - 32 - &spi0 { 33 - #address-cells = <1>; 34 - #size-cells = <0>; 35 - status = "okay"; 36 - 37 - pi433: pi433@0 { 38 - compatible = "Smarthome-Wolf,pi433"; 39 - reg = <0>; 40 - spi-max-frequency = <10000000>; 41 - status = "okay"; 42 - 43 - pinctrl-0 = <&pi433_pins>; 44 - DIO0-gpio = <&gpio 24 0>; 45 - DIO1-gpio = <&gpio 25 0>; 46 - DIO2-gpio = <&gpio 7 0>; 47 - }; 48 - };
-62
drivers/staging/pi433/Documentation/devicetree/pi433.txt
··· 1 - * Smarthome-Wolf Pi433 - a 433MHz radio module/shield for Raspberry Pi (see www.pi433.de) 2 - 3 - Required properties: 4 - - compatible: must be "Smarthome-Wolf,pi433" 5 - - reg: chip select of SPI Interface 6 - - DIOx-gpio must be dedicated to the GPIO, connected with DIOx of the RFM69 module 7 - 8 - 9 - Example: 10 - 11 - With the following lines in gpio-section, the gpio pins, connected with pi433 are 12 - reserved/declared. 13 - 14 - &gpio{ 15 - [...] 16 - 17 - pi433_pins: pi433_pins { 18 - brcm,pins = <7 25 24>; 19 - brcm,function = <0 0 0>; // in in in 20 - }; 21 - 22 - [...] 23 - } 24 - 25 - With the following lines in spi section, the device pi433 is declared. 26 - It consists of the three gpio pins and an spi interface (here chip select 0) 27 - 28 - &spi0{ 29 - [...] 30 - 31 - pi433: pi433@0 { 32 - compatible = "Smarthome-Wolf,pi433"; 33 - reg = <0>; /* CE 0 */ 34 - #address-cells = <1>; 35 - #size-cells = <0>; 36 - spi-max-frequency = <10000000>; 37 - 38 - pinctrl-0 = <&pi433_pins>; 39 - DIO0-gpio = <&gpio 24 0>; 40 - DIO1-gpio = <&gpio 25 0>; 41 - DIO2-gpio = <&gpio 7 0>; 42 - }; 43 - } 44 - 45 - 46 - 47 - For Raspbian users only 48 - ======================= 49 - Since Raspbian supports device tree overlays, you may use an overlay instead 50 - of editing your boards device tree. 51 - To use the overlay, you need to compile the file pi433-overlay.dtso which can 52 - be found alongside this documentation. 53 - The file needs to be compiled - either manually or by integration in your kernel 54 - source tree. For a manual compile, you may use a command line like the following: 55 - 'linux/scripts/dtc/dtc -@ -I dts -O dtb -o pi433.dtbo pi433-overlay.dtso' 56 - 57 - For compiling inside of the kernel tree, you need to copy pi433-overlay.dtso to 58 - arch/arm/boot/dts/overlays and you need to add the file to the list of files 59 - in the Makefile over there. Execute 'make dtbs' in kernel tree root to make the 60 - kernel make files compile the device tree overlay for you. 61 - 62 -
-274
drivers/staging/pi433/Documentation/pi433.txt
··· 1 - ===== 2 - Pi433 3 - ===== 4 - 5 - 6 - Introduction 7 - ============ 8 - This driver is for controlling pi433, a radio module for the Raspberry Pi 9 - (www.pi433.de). It supports transmission and reception. It can be opened 10 - by multiple applications for transmission and reception. While transmit 11 - jobs are queued and processed automatically in the background, the first 12 - application asking for reception will block out all other applications 13 - until something gets received terminates the read request. 14 - The driver supports on the fly reloading of the hardware fifo of the rf 15 - chip, thus enabling for much longer telegrams than the hardware fifo size. 16 - 17 - Description of driver operation 18 - =============================== 19 - 20 - a) transmission 21 - 22 - Each transmission can take place with a different configuration of the rf 23 - module. Therefore each application can set its own set of parameters. The driver 24 - takes care, that each transmission takes place with the parameterset of the 25 - application, that requests the transmission. To allow the transmission to take 26 - place in the background, a tx thread is introduced. 27 - The transfer of data from the main thread to the tx thread is realised by a 28 - kfifo. With each write request of an application, the passed in data and the 29 - corresponding parameter set gets written to the kfifo. 30 - On the other "side" of the kfifo, the tx thread continuously checks, whether the 31 - kfifo is empty. If not, it gets one set of config and data from the kfifo. If 32 - there is no receive request or the receiver is still waiting for something in 33 - the air, the rf module is set to standby, the parameters for transmission gets 34 - set, the hardware fifo of the rf chip gets preloaded and the transmission gets 35 - started. Upon hardware fifo threshold interrupt it gets reloaded, thus enabling 36 - much longer telegrams than the hardware fifo size. If the telegram is sent and there 37 - is more data available in the kfifo, the procedure is repeated. If not the 38 - transmission cycle ends. 39 - 40 - b) reception 41 - 42 - Since there is only one application allowed to receive data at a time, for 43 - reception there is only one configuration set. 44 - As soon as an application sets a request for receiving a telegram, the reception 45 - configuration set is written to the rf module and it gets set into receiving mode. 46 - Now the driver is waiting, that a predefined RSSI level (signal strength at the 47 - receiver) is reached. Until this hasn't happened, the reception can be 48 - interrupted by the transmission thread at any time to insert a transmission cycle. 49 - As soon as the predefined RSSI level is met, a receiving cycle starts. Similar 50 - as described for the transmission cycle the read out of the hardware fifo is done 51 - dynamically. Upon each hardware fifo threshold interrupt, a portion of data gets 52 - read. So also for reception it is possible to receive more data than the hardware 53 - fifo can hold. 54 - 55 - 56 - Driver API 57 - ========== 58 - 59 - The driver is currently implemented as a character device. Therefore it supports 60 - the calls open, ioctl, read, write and close. 61 - 62 - 63 - params for ioctl 64 - ---------------- 65 - 66 - There are four options: 67 - PI433_IOC_RD_TX_CFG - get the transmission parameters from the driver 68 - PI433_IOC_WR_TX_CFG - set the transmission parameters 69 - PI433_IOC_RD_RX_CFG - get the receiving parameters from the driver 70 - PI433_IOC_WR_RX_CFG - set the receiving parameters 71 - 72 - The tx configuration is transferred via struct pi433_tx_cfg, the parameterset for transmission. 73 - It is divided into two sections: rf parameters and packet format. 74 - 75 - rf params: 76 - frequency 77 - frequency used for transmission. 78 - Allowed values: 433050000...434790000 79 - bit_rate 80 - bit rate used for transmission. 81 - Allowed values: ##### 82 - dev_frequency 83 - frequency deviation in case of FSK. 84 - Allowed values: 600...500000 85 - modulation 86 - FSK - frequency shift key 87 - OOK - On-Off-key 88 - modShaping 89 - shapingOff - no shaping 90 - shaping1_0 - gauss filter with BT 1 (FSK only) 91 - shaping0_5 - gauss filter with BT 0.5 (FSK only) 92 - shaping0_3 - gauss filter with BT 0.3 (FSK only) 93 - shapingBR - filter cut off at BR (OOK only) 94 - shaping2BR - filter cut off at 2*BR (OOK only) 95 - pa_ramp (FSK only) 96 - ramp3400 - amp ramps up in 3.4ms 97 - ramp2000 - amp ramps up in 2.0ms 98 - ramp1000 - amp ramps up in 1ms 99 - ramp500 - amp ramps up in 500us 100 - ramp250 - amp ramps up in 250us 101 - ramp125 - amp ramps up in 125us 102 - ramp100 - amp ramps up in 100us 103 - ramp62 - amp ramps up in 62us 104 - ramp50 - amp ramps up in 50us 105 - ramp40 - amp ramps up in 40us 106 - ramp31 - amp ramps up in 31us 107 - ramp25 - amp ramps up in 25us 108 - ramp20 - amp ramps up in 20us 109 - ramp15 - amp ramps up in 15us 110 - ramp12 - amp ramps up in 12us 111 - ramp10 - amp ramps up in 10us 112 - tx_start_condition 113 - fifo_level - transmission starts, if fifo is filled to 114 - threshold level 115 - fifo_not_empty - transmission starts, as soon as there is one 116 - byte in internal fifo 117 - repetitions 118 - This gives the option, to send a telegram multiple times. Default: 1 119 - 120 - packet format: 121 - enable_preamble 122 - optionOn - a preamble will be automatically generated 123 - optionOff - no preamble will be generated 124 - enable_sync 125 - optionOn - a sync word will be automatically added to 126 - the telegram after the preamble 127 - optionOff - no sync word will be added 128 - Attention: While possible to generate sync without preamble, the 129 - receiver won't be able to detect the sync without preamble. 130 - enable_length_byte 131 - optionOn - the length of the telegram will be automatically 132 - added to the telegram. It's part of the payload 133 - optionOff - no length information will be automatically added 134 - to the telegram. 135 - Attention: For telegram length over 255 bytes, this option can't be used 136 - Attention: should be used in combination with sync, only 137 - enable_address_byte 138 - optionOn - the address byte will be automatically added to the 139 - telegram. It's part of the payload 140 - optionOff - the address byte will not be added to the telegram. 141 - The address byte can be used for address filtering, so the receiver 142 - will only receive telegrams with a given address byte. 143 - Attention: should be used in combination with sync, only 144 - enable_crc 145 - optionOn - an crc will be automatically calculated over the 146 - payload of the telegram and added to the telegram 147 - after payload. 148 - optionOff - no crc will be calculated 149 - preamble_length 150 - length of the preamble. Allowed values: 0...65536 151 - sync_length 152 - length of the sync word. Allowed values: 0...8 153 - fixed_message_length 154 - length of the payload of the telegram. Will override the length 155 - given by the buffer, passed in with the write command. Will be 156 - ignored if set to zero. 157 - sync_pattern[8] 158 - contains up to eight values, that are used as the sync pattern 159 - on sync option 160 - address_byte 161 - one byte, used as address byte on address byte option. 162 - 163 - 164 - The rx configuration is transferred via struct pi433_rx_cfg, the parameterset for receiving. It is divided into two sections: rf parameters and packet format. 165 - 166 - rf params: 167 - frequency 168 - frequency used for transmission. 169 - Allowed values: 433050000...434790000 170 - bit_rate 171 - bit rate used for transmission. 172 - Allowed values: ##### 173 - dev_frequency 174 - frequency deviation in case of FSK. 175 - Allowed values: 600...500000 176 - modulation 177 - FSK - frequency shift key 178 - OOK - on off key 179 - rssi_threshold 180 - threshold value for the signal strength on the receiver input. 181 - If this value is exceeded, a reception cycle starts 182 - Allowed values: 0...255 183 - threshold_decrement 184 - in order to adapt to different levels of singnal strength, over 185 - time the receiver gets more and more sensitive. This value 186 - determs, how fast the sensitivity increases. 187 - step_0_5db - increase in 0,5dB steps 188 - step_1_0db - increase in 1 db steps 189 - step_1_5db - increase in 1,5dB steps 190 - step_2_0db - increase in 2 db steps 191 - step_3_0db - increase in 3 db steps 192 - step_4_0db - increase in 4 db steps 193 - step_5_0db - increase in 5 db steps 194 - step_6_0db - increase in 6 db steps 195 - antenna_impedance 196 - sets the electrical adoption of the antenna 197 - fifty_ohm - for antennas with an impedance of 50Ohm 198 - two_hundred_ohm - for antennas with an impedance of 200Ohm 199 - lna_gain 200 - sets the gain of the low noise amp 201 - automatic - lna gain is determined by an agc 202 - max - lna gain is set to maximum 203 - max_minus_6 - lna gain is set to 6db below max 204 - max_minus_12 - lna gain is set to 12db below max 205 - max_minus_24 - lna gain is set to 24db below max 206 - max_minus_36 - lna gain is set to 36db below max 207 - max_minus_48 - lna gain is set to 48db below max 208 - bw_mantisse 209 - sets the bandwidth of the channel filter - part one: mantisse. 210 - mantisse16 - mantisse is set to 16 211 - mantisse20 - mantisse is set to 20 212 - mantisse24 - mantisse is set to 24 213 - bw_exponent 214 - sets the bandwidth of the channel filter - part two: exponent. 215 - Allowd values: 0...7 216 - dagc; 217 - operation mode of the digital automatic gain control 218 - normal_mode 219 - improve 220 - improve_for_low_modulation_index 221 - 222 - packet format: 223 - enable_sync 224 - optionOn - sync detection is enabled. If configured sync pattern 225 - isn't found, telegram will be internally discarded 226 - optionOff - sync detection is disabled. 227 - enable_length_byte 228 - optionOn - First byte of payload will be used as a length byte, 229 - regardless of the amount of bytes that were requested 230 - by the read request. 231 - optionOff - Number of bytes to be read will be set according to 232 - amount of bytes that were requested by the read request. 233 - Attention: should be used in combination with sync, only 234 - enable_address_filtering; 235 - filtering_off - no address filtering will take place 236 - node_address - all telegrams, not matching the node 237 - address will be internally discarded 238 - node_or_broadcast_address - all telegrams, neither matching the 239 - node, nor the broadcast address will 240 - be internally discarded 241 - Attention: Sync option must be enabled in order to use this feature 242 - enable_crc 243 - optionOn - a crc will be calculated over the payload of 244 - the telegram, that was received. If the 245 - calculated crc doesn't match to two bytes, 246 - that follow the payload, the telegram will be 247 - internally discarded. 248 - Attention: This option is only operational if sync on and fixed length 249 - or length byte is used 250 - sync_length 251 - Gives the length of the payload. 252 - Attention: This setting must meet the setting of the transmitter, 253 - if sync option is used. 254 - fixed_message_length 255 - Overrides the telegram length either given by the first byte of 256 - payload or by the read request. 257 - bytes_to_drop 258 - gives the number of bytes, that will be dropped before transferring 259 - data to the read buffer 260 - This option is only useful if all packet helper are switched 261 - off and the rf chip is used in raw receiving mode. This may be 262 - needed, if a telegram of a third party device should be received, 263 - using a protocol not compatible with the packet engine of the rf69 chip. 264 - sync_pattern[8] 265 - contains up to eight values, that are used as the sync pattern 266 - on sync option. 267 - This setting must meet the configuration of the transmitting device, 268 - if sync option is enabled. 269 - node_address 270 - one byte, used as node address byte on address byte option. 271 - broadcast_address 272 - one byte, used as broadcast address byte on address byte option. 273 - 274 -
-17
drivers/staging/pi433/Kconfig
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - config PI433 3 - tristate "Pi433 - a 433MHz radio module for Raspberry Pi" 4 - depends on SPI 5 - help 6 - This option allows you to enable support for the radio module Pi433. 7 - 8 - Pi433 is a shield that fits onto the GPIO header of a Raspberry Pi 9 - or compatible. It extends the Raspberry Pi with the option, to 10 - send and receive data in the 433MHz ISM band - for example to 11 - communicate between two systems without using ethernet or bluetooth 12 - or for control or read sockets, actors, sensors, widely available 13 - for low price. 14 - 15 - For details or the option to buy, please visit https://pi433.de/en.html 16 - 17 - If in doubt, say N here, but saying yes most probably won't hurt
-4
drivers/staging/pi433/Makefile
··· 1 - # SPDX-License-Identifier: GPL-2.0 2 - obj-$(CONFIG_PI433) += pi433.o 3 - 4 - pi433-objs := pi433_if.o rf69.o
-8
drivers/staging/pi433/TODO
··· 1 - * currently the code introduces new IOCTLs. I'm afraid this is a bad idea. 2 - -> Replace this with another interface, hints are welcome! 3 - * Some missing data (marked with ###) needs to be added in the documentation 4 - * Change (struct pi433_tx_cfg)->bit_rate to be a u32 so that we can support 5 - bit rates up to 300kbps per the spec. 6 - -> This configuration needs to be moved to sysfs instead of being done through 7 - IOCTL. Going forward, we need to port userspace tools to use sysfs instead 8 - of IOCTL and then we would delete IOCTL.
-1437
drivers/staging/pi433/pi433_if.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * userspace interface for pi433 radio module 4 - * 5 - * Pi433 is a 433MHz radio module for the Raspberry Pi. 6 - * It is based on the HopeRf Module RFM69CW. Therefore inside of this 7 - * driver, you'll find an abstraction of the rf69 chip. 8 - * 9 - * If needed, this driver could be extended, to also support other 10 - * devices, basing on HopeRfs rf69. 11 - * 12 - * The driver can also be extended, to support other modules of 13 - * HopeRf with a similar interface - e. g. RFM69HCW, RFM12, RFM95, ... 14 - * 15 - * Copyright (C) 2016 Wolf-Entwicklungen 16 - * Marcus Wolf <linux@wolf-entwicklungen.de> 17 - */ 18 - 19 - #undef DEBUG 20 - 21 - #include <linux/init.h> 22 - #include <linux/module.h> 23 - #include <linux/idr.h> 24 - #include <linux/ioctl.h> 25 - #include <linux/uaccess.h> 26 - #include <linux/fs.h> 27 - #include <linux/device.h> 28 - #include <linux/cdev.h> 29 - #include <linux/err.h> 30 - #include <linux/kfifo.h> 31 - #include <linux/errno.h> 32 - #include <linux/mutex.h> 33 - #include <linux/of.h> 34 - #include <linux/interrupt.h> 35 - #include <linux/irq.h> 36 - #include <linux/gpio/consumer.h> 37 - #include <linux/kthread.h> 38 - #include <linux/wait.h> 39 - #include <linux/spi/spi.h> 40 - #ifdef CONFIG_COMPAT 41 - #include <linux/compat.h> 42 - #endif 43 - #include <linux/debugfs.h> 44 - #include <linux/seq_file.h> 45 - 46 - #include "pi433_if.h" 47 - #include "rf69.h" 48 - 49 - #define N_PI433_MINORS BIT(MINORBITS) /*32*/ /* ... up to 256 */ 50 - #define MAX_MSG_SIZE 900 /* min: FIFO_SIZE! */ 51 - #define MSG_FIFO_SIZE 65536 /* 65536 = 2^16 */ 52 - #define FIFO_THRESHOLD 15 /* bytes */ 53 - #define NUM_DIO 2 54 - 55 - static dev_t pi433_devt; 56 - static DEFINE_IDR(pi433_idr); 57 - static DEFINE_MUTEX(minor_lock); /* Protect idr accesses */ 58 - static struct dentry *root_dir; /* debugfs root directory for the driver */ 59 - 60 - /* mainly for udev to create /dev/pi433 */ 61 - static const struct class pi433_class = { 62 - .name = "pi433", 63 - }; 64 - 65 - /* 66 - * tx config is instance specific 67 - * so with each open a new tx config struct is needed 68 - */ 69 - /* 70 - * rx config is device specific 71 - * so we have just one rx config, embedded in device struct 72 - */ 73 - struct pi433_device { 74 - /* device handling related values */ 75 - dev_t devt; 76 - int minor; 77 - struct device *dev; 78 - struct cdev *cdev; 79 - struct spi_device *spi; 80 - 81 - /* irq related values */ 82 - struct gpio_desc *gpiod[NUM_DIO]; 83 - int irq_num[NUM_DIO]; 84 - u8 irq_state[NUM_DIO]; 85 - 86 - /* tx related values */ 87 - STRUCT_KFIFO_REC_1(MSG_FIFO_SIZE) tx_fifo; 88 - struct mutex tx_fifo_lock; /* serialize userspace writers */ 89 - struct task_struct *tx_task_struct; 90 - wait_queue_head_t tx_wait_queue; 91 - u8 free_in_fifo; 92 - char tx_buffer[MAX_MSG_SIZE]; 93 - 94 - /* rx related values */ 95 - struct pi433_rx_cfg rx_cfg; 96 - u8 *rx_buffer; 97 - unsigned int rx_buffer_size; 98 - u32 rx_bytes_to_drop; 99 - u32 rx_bytes_dropped; 100 - unsigned int rx_position; 101 - struct mutex rx_lock; /* protects rx_* variable accesses */ 102 - wait_queue_head_t rx_wait_queue; 103 - 104 - /* fifo wait queue */ 105 - struct task_struct *fifo_task_struct; 106 - wait_queue_head_t fifo_wait_queue; 107 - 108 - /* flags */ 109 - bool rx_active; 110 - bool tx_active; 111 - bool interrupt_rx_allowed; 112 - }; 113 - 114 - struct pi433_instance { 115 - struct pi433_device *pi433; 116 - struct pi433_tx_cfg tx_cfg; 117 - 118 - /* control flags */ 119 - bool tx_cfg_initialized; 120 - }; 121 - 122 - /*-------------------------------------------------------------------------*/ 123 - 124 - /* GPIO interrupt handlers */ 125 - static irqreturn_t DIO0_irq_handler(int irq, void *dev_id) 126 - { 127 - struct pi433_device *pi433 = dev_id; 128 - 129 - if (pi433->irq_state[DIO0] == DIO_PACKET_SENT) { 130 - pi433->free_in_fifo = FIFO_SIZE; 131 - dev_dbg(pi433->dev, "DIO0 irq: Packet sent\n"); 132 - wake_up_interruptible(&pi433->fifo_wait_queue); 133 - } else if (pi433->irq_state[DIO0] == DIO_RSSI_DIO0) { 134 - dev_dbg(pi433->dev, "DIO0 irq: RSSI level over threshold\n"); 135 - wake_up_interruptible(&pi433->rx_wait_queue); 136 - } else if (pi433->irq_state[DIO0] == DIO_PAYLOAD_READY) { 137 - dev_dbg(pi433->dev, "DIO0 irq: Payload ready\n"); 138 - pi433->free_in_fifo = 0; 139 - wake_up_interruptible(&pi433->fifo_wait_queue); 140 - } 141 - 142 - return IRQ_HANDLED; 143 - } 144 - 145 - static irqreturn_t DIO1_irq_handler(int irq, void *dev_id) 146 - { 147 - struct pi433_device *pi433 = dev_id; 148 - 149 - if (pi433->irq_state[DIO1] == DIO_FIFO_NOT_EMPTY_DIO1) { 150 - pi433->free_in_fifo = FIFO_SIZE; 151 - } else if (pi433->irq_state[DIO1] == DIO_FIFO_LEVEL) { 152 - if (pi433->rx_active) 153 - pi433->free_in_fifo = FIFO_THRESHOLD - 1; 154 - else 155 - pi433->free_in_fifo = FIFO_SIZE - FIFO_THRESHOLD - 1; 156 - } 157 - dev_dbg(pi433->dev, 158 - "DIO1 irq: %d bytes free in fifo\n", pi433->free_in_fifo); 159 - wake_up_interruptible(&pi433->fifo_wait_queue); 160 - 161 - return IRQ_HANDLED; 162 - } 163 - 164 - /*-------------------------------------------------------------------------*/ 165 - 166 - static int 167 - rf69_set_rx_cfg(struct pi433_device *pi433, struct pi433_rx_cfg *rx_cfg) 168 - { 169 - int ret; 170 - int payload_length; 171 - 172 - /* receiver config */ 173 - ret = rf69_set_frequency(pi433->spi, rx_cfg->frequency); 174 - if (ret < 0) 175 - return ret; 176 - ret = rf69_set_modulation(pi433->spi, rx_cfg->modulation); 177 - if (ret < 0) 178 - return ret; 179 - ret = rf69_set_bit_rate(pi433->spi, rx_cfg->bit_rate); 180 - if (ret < 0) 181 - return ret; 182 - ret = rf69_set_antenna_impedance(pi433->spi, rx_cfg->antenna_impedance); 183 - if (ret < 0) 184 - return ret; 185 - ret = rf69_set_rssi_threshold(pi433->spi, rx_cfg->rssi_threshold); 186 - if (ret < 0) 187 - return ret; 188 - ret = rf69_set_ook_threshold_dec(pi433->spi, rx_cfg->threshold_decrement); 189 - if (ret < 0) 190 - return ret; 191 - ret = rf69_set_bandwidth(pi433->spi, rx_cfg->bw_mantisse, 192 - rx_cfg->bw_exponent); 193 - if (ret < 0) 194 - return ret; 195 - ret = rf69_set_bandwidth_during_afc(pi433->spi, rx_cfg->bw_mantisse, 196 - rx_cfg->bw_exponent); 197 - if (ret < 0) 198 - return ret; 199 - ret = rf69_set_dagc(pi433->spi, rx_cfg->dagc); 200 - if (ret < 0) 201 - return ret; 202 - 203 - pi433->rx_bytes_to_drop = rx_cfg->bytes_to_drop; 204 - 205 - /* packet config */ 206 - /* enable */ 207 - if (rx_cfg->enable_sync == OPTION_ON) { 208 - ret = rf69_enable_sync(pi433->spi); 209 - if (ret < 0) 210 - return ret; 211 - 212 - ret = rf69_set_fifo_fill_condition(pi433->spi, 213 - after_sync_interrupt); 214 - if (ret < 0) 215 - return ret; 216 - } else { 217 - ret = rf69_disable_sync(pi433->spi); 218 - if (ret < 0) 219 - return ret; 220 - 221 - ret = rf69_set_fifo_fill_condition(pi433->spi, always); 222 - if (ret < 0) 223 - return ret; 224 - } 225 - if (rx_cfg->enable_length_byte == OPTION_ON) { 226 - ret = rf69_set_packet_format(pi433->spi, packet_length_var); 227 - if (ret < 0) 228 - return ret; 229 - } else { 230 - ret = rf69_set_packet_format(pi433->spi, packet_length_fix); 231 - if (ret < 0) 232 - return ret; 233 - } 234 - ret = rf69_set_address_filtering(pi433->spi, 235 - rx_cfg->enable_address_filtering); 236 - if (ret < 0) 237 - return ret; 238 - 239 - if (rx_cfg->enable_crc == OPTION_ON) { 240 - ret = rf69_enable_crc(pi433->spi); 241 - if (ret < 0) 242 - return ret; 243 - } else { 244 - ret = rf69_disable_crc(pi433->spi); 245 - if (ret < 0) 246 - return ret; 247 - } 248 - 249 - /* lengths */ 250 - ret = rf69_set_sync_size(pi433->spi, rx_cfg->sync_length); 251 - if (ret < 0) 252 - return ret; 253 - if (rx_cfg->enable_length_byte == OPTION_ON) { 254 - ret = rf69_set_payload_length(pi433->spi, 0xff); 255 - if (ret < 0) 256 - return ret; 257 - } else if (rx_cfg->fixed_message_length != 0) { 258 - payload_length = rx_cfg->fixed_message_length; 259 - if (rx_cfg->enable_length_byte == OPTION_ON) 260 - payload_length++; 261 - if (rx_cfg->enable_address_filtering != filtering_off) 262 - payload_length++; 263 - ret = rf69_set_payload_length(pi433->spi, payload_length); 264 - if (ret < 0) 265 - return ret; 266 - } else { 267 - ret = rf69_set_payload_length(pi433->spi, 0); 268 - if (ret < 0) 269 - return ret; 270 - } 271 - 272 - /* values */ 273 - if (rx_cfg->enable_sync == OPTION_ON) { 274 - ret = rf69_set_sync_values(pi433->spi, rx_cfg->sync_pattern); 275 - if (ret < 0) 276 - return ret; 277 - } 278 - if (rx_cfg->enable_address_filtering != filtering_off) { 279 - ret = rf69_set_node_address(pi433->spi, rx_cfg->node_address); 280 - if (ret < 0) 281 - return ret; 282 - ret = rf69_set_broadcast_address(pi433->spi, 283 - rx_cfg->broadcast_address); 284 - if (ret < 0) 285 - return ret; 286 - } 287 - 288 - return 0; 289 - } 290 - 291 - static int 292 - rf69_set_tx_cfg(struct pi433_device *pi433, struct pi433_tx_cfg *tx_cfg) 293 - { 294 - int ret; 295 - 296 - ret = rf69_set_frequency(pi433->spi, tx_cfg->frequency); 297 - if (ret < 0) 298 - return ret; 299 - ret = rf69_set_modulation(pi433->spi, tx_cfg->modulation); 300 - if (ret < 0) 301 - return ret; 302 - ret = rf69_set_bit_rate(pi433->spi, tx_cfg->bit_rate); 303 - if (ret < 0) 304 - return ret; 305 - ret = rf69_set_deviation(pi433->spi, tx_cfg->dev_frequency); 306 - if (ret < 0) 307 - return ret; 308 - ret = rf69_set_pa_ramp(pi433->spi, tx_cfg->pa_ramp); 309 - if (ret < 0) 310 - return ret; 311 - ret = rf69_set_modulation_shaping(pi433->spi, tx_cfg->mod_shaping); 312 - if (ret < 0) 313 - return ret; 314 - ret = rf69_set_tx_start_condition(pi433->spi, tx_cfg->tx_start_condition); 315 - if (ret < 0) 316 - return ret; 317 - 318 - /* packet format enable */ 319 - if (tx_cfg->enable_preamble == OPTION_ON) { 320 - ret = rf69_set_preamble_length(pi433->spi, 321 - tx_cfg->preamble_length); 322 - if (ret < 0) 323 - return ret; 324 - } else { 325 - ret = rf69_set_preamble_length(pi433->spi, 0); 326 - if (ret < 0) 327 - return ret; 328 - } 329 - 330 - if (tx_cfg->enable_sync == OPTION_ON) { 331 - ret = rf69_set_sync_size(pi433->spi, tx_cfg->sync_length); 332 - if (ret < 0) 333 - return ret; 334 - ret = rf69_set_sync_values(pi433->spi, tx_cfg->sync_pattern); 335 - if (ret < 0) 336 - return ret; 337 - ret = rf69_enable_sync(pi433->spi); 338 - if (ret < 0) 339 - return ret; 340 - } else { 341 - ret = rf69_disable_sync(pi433->spi); 342 - if (ret < 0) 343 - return ret; 344 - } 345 - 346 - if (tx_cfg->enable_length_byte == OPTION_ON) { 347 - ret = rf69_set_packet_format(pi433->spi, packet_length_var); 348 - if (ret < 0) 349 - return ret; 350 - } else { 351 - ret = rf69_set_packet_format(pi433->spi, packet_length_fix); 352 - if (ret < 0) 353 - return ret; 354 - } 355 - 356 - if (tx_cfg->enable_crc == OPTION_ON) { 357 - ret = rf69_enable_crc(pi433->spi); 358 - if (ret < 0) 359 - return ret; 360 - } else { 361 - ret = rf69_disable_crc(pi433->spi); 362 - if (ret < 0) 363 - return ret; 364 - } 365 - 366 - return 0; 367 - } 368 - 369 - /*-------------------------------------------------------------------------*/ 370 - 371 - static int pi433_start_rx(struct pi433_device *pi433) 372 - { 373 - int retval; 374 - 375 - /* return without action, if no pending read request */ 376 - if (!pi433->rx_active) 377 - return 0; 378 - 379 - /* setup for receiving */ 380 - retval = rf69_set_rx_cfg(pi433, &pi433->rx_cfg); 381 - if (retval) 382 - return retval; 383 - 384 - /* setup rssi irq */ 385 - retval = rf69_set_dio_mapping(pi433->spi, DIO0, DIO_RSSI_DIO0); 386 - if (retval < 0) 387 - return retval; 388 - pi433->irq_state[DIO0] = DIO_RSSI_DIO0; 389 - irq_set_irq_type(pi433->irq_num[DIO0], IRQ_TYPE_EDGE_RISING); 390 - 391 - /* setup fifo level interrupt */ 392 - retval = rf69_set_fifo_threshold(pi433->spi, FIFO_SIZE - FIFO_THRESHOLD); 393 - if (retval < 0) 394 - return retval; 395 - retval = rf69_set_dio_mapping(pi433->spi, DIO1, DIO_FIFO_LEVEL); 396 - if (retval < 0) 397 - return retval; 398 - pi433->irq_state[DIO1] = DIO_FIFO_LEVEL; 399 - irq_set_irq_type(pi433->irq_num[DIO1], IRQ_TYPE_EDGE_RISING); 400 - 401 - /* set module to receiving mode */ 402 - retval = rf69_set_mode(pi433->spi, receive); 403 - if (retval < 0) 404 - return retval; 405 - 406 - return 0; 407 - } 408 - 409 - /*-------------------------------------------------------------------------*/ 410 - 411 - static int pi433_receive(struct pi433_device *pi433) 412 - { 413 - struct spi_device *spi = pi433->spi; 414 - int bytes_to_read, bytes_total; 415 - int retval; 416 - 417 - pi433->interrupt_rx_allowed = false; 418 - 419 - /* wait for any tx to finish */ 420 - dev_dbg(pi433->dev, "rx: going to wait for any tx to finish\n"); 421 - retval = wait_event_interruptible(pi433->rx_wait_queue, !pi433->tx_active); 422 - if (retval) { 423 - /* wait was interrupted */ 424 - pi433->interrupt_rx_allowed = true; 425 - wake_up_interruptible(&pi433->tx_wait_queue); 426 - return retval; 427 - } 428 - 429 - /* prepare status vars */ 430 - pi433->free_in_fifo = FIFO_SIZE; 431 - pi433->rx_position = 0; 432 - pi433->rx_bytes_dropped = 0; 433 - 434 - /* setup radio module to listen for something "in the air" */ 435 - retval = pi433_start_rx(pi433); 436 - if (retval) 437 - return retval; 438 - 439 - /* now check RSSI, if low wait for getting high (RSSI interrupt) */ 440 - while (!(rf69_read_reg(spi, REG_IRQFLAGS1) & MASK_IRQFLAGS1_RSSI)) { 441 - /* allow tx to interrupt us while waiting for high RSSI */ 442 - pi433->interrupt_rx_allowed = true; 443 - wake_up_interruptible(&pi433->tx_wait_queue); 444 - 445 - /* wait for RSSI level to become high */ 446 - dev_dbg(pi433->dev, "rx: going to wait for high RSSI level\n"); 447 - retval = wait_event_interruptible(pi433->rx_wait_queue, 448 - rf69_read_reg(spi, REG_IRQFLAGS1) & 449 - MASK_IRQFLAGS1_RSSI); 450 - if (retval) /* wait was interrupted */ 451 - goto abort; 452 - pi433->interrupt_rx_allowed = false; 453 - 454 - /* cross check for ongoing tx */ 455 - if (!pi433->tx_active) 456 - break; 457 - } 458 - 459 - /* configure payload ready irq */ 460 - retval = rf69_set_dio_mapping(spi, DIO0, DIO_PAYLOAD_READY); 461 - if (retval < 0) 462 - goto abort; 463 - pi433->irq_state[DIO0] = DIO_PAYLOAD_READY; 464 - irq_set_irq_type(pi433->irq_num[DIO0], IRQ_TYPE_EDGE_RISING); 465 - 466 - /* fixed or unlimited length? */ 467 - if (pi433->rx_cfg.fixed_message_length != 0) { 468 - if (pi433->rx_cfg.fixed_message_length > pi433->rx_buffer_size) { 469 - retval = -1; 470 - goto abort; 471 - } 472 - bytes_total = pi433->rx_cfg.fixed_message_length; 473 - dev_dbg(pi433->dev, "rx: msg len set to %d by fixed length\n", 474 - bytes_total); 475 - } else { 476 - bytes_total = pi433->rx_buffer_size; 477 - dev_dbg(pi433->dev, "rx: msg len set to %d as requested by read\n", 478 - bytes_total); 479 - } 480 - 481 - /* length byte enabled? */ 482 - if (pi433->rx_cfg.enable_length_byte == OPTION_ON) { 483 - retval = wait_event_interruptible(pi433->fifo_wait_queue, 484 - pi433->free_in_fifo < FIFO_SIZE); 485 - if (retval) /* wait was interrupted */ 486 - goto abort; 487 - 488 - rf69_read_fifo(spi, (u8 *)&bytes_total, 1); 489 - if (bytes_total > pi433->rx_buffer_size) { 490 - retval = -1; 491 - goto abort; 492 - } 493 - pi433->free_in_fifo++; 494 - dev_dbg(pi433->dev, "rx: msg len reset to %d due to length byte\n", 495 - bytes_total); 496 - } 497 - 498 - /* address byte enabled? */ 499 - if (pi433->rx_cfg.enable_address_filtering != filtering_off) { 500 - u8 dummy; 501 - 502 - bytes_total--; 503 - 504 - retval = wait_event_interruptible(pi433->fifo_wait_queue, 505 - pi433->free_in_fifo < FIFO_SIZE); 506 - if (retval) /* wait was interrupted */ 507 - goto abort; 508 - 509 - rf69_read_fifo(spi, &dummy, 1); 510 - pi433->free_in_fifo++; 511 - dev_dbg(pi433->dev, "rx: address byte stripped off\n"); 512 - } 513 - 514 - /* get payload */ 515 - while (pi433->rx_position < bytes_total) { 516 - if (!(rf69_read_reg(spi, REG_IRQFLAGS2) & MASK_IRQFLAGS2_PAYLOAD_READY)) { 517 - retval = wait_event_interruptible(pi433->fifo_wait_queue, 518 - pi433->free_in_fifo < FIFO_SIZE); 519 - if (retval) /* wait was interrupted */ 520 - goto abort; 521 - } 522 - 523 - /* need to drop bytes or acquire? */ 524 - if (pi433->rx_bytes_to_drop > pi433->rx_bytes_dropped) 525 - bytes_to_read = pi433->rx_bytes_to_drop - 526 - pi433->rx_bytes_dropped; 527 - else 528 - bytes_to_read = bytes_total - pi433->rx_position; 529 - 530 - /* access the fifo */ 531 - if (bytes_to_read > FIFO_SIZE - pi433->free_in_fifo) 532 - bytes_to_read = FIFO_SIZE - pi433->free_in_fifo; 533 - retval = rf69_read_fifo(spi, 534 - &pi433->rx_buffer[pi433->rx_position], 535 - bytes_to_read); 536 - if (retval) /* read failed */ 537 - goto abort; 538 - 539 - pi433->free_in_fifo += bytes_to_read; 540 - 541 - /* adjust status vars */ 542 - if (pi433->rx_bytes_to_drop > pi433->rx_bytes_dropped) 543 - pi433->rx_bytes_dropped += bytes_to_read; 544 - else 545 - pi433->rx_position += bytes_to_read; 546 - } 547 - 548 - /* rx done, wait was interrupted or error occurred */ 549 - abort: 550 - pi433->interrupt_rx_allowed = true; 551 - if (rf69_set_mode(pi433->spi, standby)) 552 - pr_err("rf69_set_mode(): radio module failed to go standby\n"); 553 - wake_up_interruptible(&pi433->tx_wait_queue); 554 - 555 - if (retval) 556 - return retval; 557 - else 558 - return bytes_total; 559 - } 560 - 561 - static int pi433_tx_thread(void *data) 562 - { 563 - struct pi433_device *pi433 = data; 564 - struct spi_device *spi = pi433->spi; 565 - struct pi433_tx_cfg tx_cfg; 566 - size_t size; 567 - bool rx_interrupted = false; 568 - int position, repetitions; 569 - int retval; 570 - 571 - while (1) { 572 - /* wait for fifo to be populated or for request to terminate*/ 573 - dev_dbg(pi433->dev, "thread: going to wait for new messages\n"); 574 - wait_event_interruptible(pi433->tx_wait_queue, 575 - (!kfifo_is_empty(&pi433->tx_fifo) || 576 - kthread_should_stop())); 577 - if (kthread_should_stop()) 578 - return 0; 579 - 580 - /* 581 - * get data from fifo in the following order: 582 - * - tx_cfg 583 - * - size of message 584 - * - message 585 - */ 586 - retval = kfifo_out(&pi433->tx_fifo, &tx_cfg, sizeof(tx_cfg)); 587 - if (retval != sizeof(tx_cfg)) { 588 - dev_dbg(pi433->dev, 589 - "reading tx_cfg from fifo failed: got %d byte(s), expected %d\n", 590 - retval, (unsigned int)sizeof(tx_cfg)); 591 - continue; 592 - } 593 - 594 - retval = kfifo_out(&pi433->tx_fifo, &size, sizeof(size_t)); 595 - if (retval != sizeof(size_t)) { 596 - dev_dbg(pi433->dev, 597 - "reading msg size from fifo failed: got %d, expected %d\n", 598 - retval, (unsigned int)sizeof(size_t)); 599 - continue; 600 - } 601 - 602 - /* use fixed message length, if requested */ 603 - if (tx_cfg.fixed_message_length != 0) 604 - size = tx_cfg.fixed_message_length; 605 - 606 - /* increase size, if len byte is requested */ 607 - if (tx_cfg.enable_length_byte == OPTION_ON) 608 - size++; 609 - 610 - /* increase size, if adr byte is requested */ 611 - if (tx_cfg.enable_address_byte == OPTION_ON) 612 - size++; 613 - 614 - /* prime tx_buffer */ 615 - memset(pi433->tx_buffer, 0, size); 616 - position = 0; 617 - 618 - /* add length byte, if requested */ 619 - if (tx_cfg.enable_length_byte == OPTION_ON) 620 - /* 621 - * according to spec, length byte itself must be 622 - * excluded from the length calculation 623 - */ 624 - pi433->tx_buffer[position++] = size - 1; 625 - 626 - /* add adr byte, if requested */ 627 - if (tx_cfg.enable_address_byte == OPTION_ON) 628 - pi433->tx_buffer[position++] = tx_cfg.address_byte; 629 - 630 - /* finally get message data from fifo */ 631 - retval = kfifo_out(&pi433->tx_fifo, &pi433->tx_buffer[position], 632 - sizeof(pi433->tx_buffer) - position); 633 - dev_dbg(pi433->dev, 634 - "read %d message byte(s) from fifo queue.\n", retval); 635 - 636 - /* 637 - * if rx is active, we need to interrupt the waiting for 638 - * incoming telegrams, to be able to send something. 639 - * We are only allowed, if currently no reception takes 640 - * place otherwise we need to wait for the incoming telegram 641 - * to finish 642 - */ 643 - wait_event_interruptible(pi433->tx_wait_queue, 644 - !pi433->rx_active || 645 - pi433->interrupt_rx_allowed); 646 - 647 - /* 648 - * prevent race conditions 649 - * irq will be re-enabled after tx config is set 650 - */ 651 - disable_irq(pi433->irq_num[DIO0]); 652 - pi433->tx_active = true; 653 - 654 - /* clear fifo, set fifo threshold, set payload length */ 655 - retval = rf69_set_mode(spi, standby); /* this clears the fifo */ 656 - if (retval < 0) 657 - goto abort; 658 - 659 - if (pi433->rx_active && !rx_interrupted) { 660 - /* 661 - * rx is currently waiting for a telegram; 662 - * we need to set the radio module to standby 663 - */ 664 - rx_interrupted = true; 665 - } 666 - 667 - retval = rf69_set_fifo_threshold(spi, FIFO_THRESHOLD); 668 - if (retval < 0) 669 - goto abort; 670 - if (tx_cfg.enable_length_byte == OPTION_ON) { 671 - retval = rf69_set_payload_length(spi, size * tx_cfg.repetitions); 672 - if (retval < 0) 673 - goto abort; 674 - } else { 675 - retval = rf69_set_payload_length(spi, 0); 676 - if (retval < 0) 677 - goto abort; 678 - } 679 - 680 - /* configure the rf chip */ 681 - retval = rf69_set_tx_cfg(pi433, &tx_cfg); 682 - if (retval < 0) 683 - goto abort; 684 - 685 - /* enable fifo level interrupt */ 686 - retval = rf69_set_dio_mapping(spi, DIO1, DIO_FIFO_LEVEL); 687 - if (retval < 0) 688 - goto abort; 689 - pi433->irq_state[DIO1] = DIO_FIFO_LEVEL; 690 - irq_set_irq_type(pi433->irq_num[DIO1], IRQ_TYPE_EDGE_FALLING); 691 - 692 - /* enable packet sent interrupt */ 693 - retval = rf69_set_dio_mapping(spi, DIO0, DIO_PACKET_SENT); 694 - if (retval < 0) 695 - goto abort; 696 - pi433->irq_state[DIO0] = DIO_PACKET_SENT; 697 - irq_set_irq_type(pi433->irq_num[DIO0], IRQ_TYPE_EDGE_RISING); 698 - enable_irq(pi433->irq_num[DIO0]); /* was disabled by rx active check */ 699 - 700 - /* enable transmission */ 701 - retval = rf69_set_mode(spi, transmit); 702 - if (retval < 0) 703 - goto abort; 704 - 705 - /* transfer this msg (and repetitions) to chip fifo */ 706 - pi433->free_in_fifo = FIFO_SIZE; 707 - position = 0; 708 - repetitions = tx_cfg.repetitions; 709 - while ((repetitions > 0) && (size > position)) { 710 - if ((size - position) > pi433->free_in_fifo) { 711 - /* msg to big for fifo - take a part */ 712 - int write_size = pi433->free_in_fifo; 713 - 714 - pi433->free_in_fifo = 0; 715 - rf69_write_fifo(spi, 716 - &pi433->tx_buffer[position], 717 - write_size); 718 - position += write_size; 719 - } else { 720 - /* msg fits into fifo - take all */ 721 - pi433->free_in_fifo -= size; 722 - repetitions--; 723 - rf69_write_fifo(spi, 724 - &pi433->tx_buffer[position], 725 - (size - position)); 726 - position = 0; /* reset for next repetition */ 727 - } 728 - 729 - retval = wait_event_interruptible(pi433->fifo_wait_queue, 730 - pi433->free_in_fifo > 0); 731 - if (retval) { 732 - dev_dbg(pi433->dev, "ABORT\n"); 733 - goto abort; 734 - } 735 - } 736 - 737 - /* we are done. Wait for packet to get sent */ 738 - dev_dbg(pi433->dev, 739 - "thread: wait for packet to get sent/fifo to be empty\n"); 740 - wait_event_interruptible(pi433->fifo_wait_queue, 741 - pi433->free_in_fifo == FIFO_SIZE || 742 - kthread_should_stop()); 743 - if (kthread_should_stop()) 744 - return 0; 745 - 746 - /* STOP_TRANSMISSION */ 747 - dev_dbg(pi433->dev, "thread: Packet sent. Set mode to stby.\n"); 748 - retval = rf69_set_mode(spi, standby); 749 - if (retval < 0) 750 - goto abort; 751 - 752 - /* everything sent? */ 753 - if (kfifo_is_empty(&pi433->tx_fifo)) { 754 - abort: 755 - if (rx_interrupted) { 756 - rx_interrupted = false; 757 - pi433_start_rx(pi433); 758 - } 759 - pi433->tx_active = false; 760 - wake_up_interruptible(&pi433->rx_wait_queue); 761 - } 762 - } 763 - } 764 - 765 - /*-------------------------------------------------------------------------*/ 766 - 767 - static ssize_t 768 - pi433_read(struct file *filp, char __user *buf, size_t size, loff_t *f_pos) 769 - { 770 - struct pi433_instance *instance; 771 - struct pi433_device *pi433; 772 - int bytes_received; 773 - ssize_t retval; 774 - 775 - /* check, whether internal buffer is big enough for requested size */ 776 - if (size > MAX_MSG_SIZE) 777 - return -EMSGSIZE; 778 - 779 - instance = filp->private_data; 780 - pi433 = instance->pi433; 781 - 782 - /* just one read request at a time */ 783 - mutex_lock(&pi433->rx_lock); 784 - if (pi433->rx_active) { 785 - mutex_unlock(&pi433->rx_lock); 786 - return -EAGAIN; 787 - } 788 - 789 - pi433->rx_active = true; 790 - mutex_unlock(&pi433->rx_lock); 791 - 792 - /* start receiving */ 793 - /* will block until something was received*/ 794 - pi433->rx_buffer_size = size; 795 - bytes_received = pi433_receive(pi433); 796 - 797 - /* release rx */ 798 - mutex_lock(&pi433->rx_lock); 799 - pi433->rx_active = false; 800 - mutex_unlock(&pi433->rx_lock); 801 - 802 - /* if read was successful copy to user space*/ 803 - if (bytes_received > 0) { 804 - retval = copy_to_user(buf, pi433->rx_buffer, bytes_received); 805 - if (retval) 806 - return -EFAULT; 807 - } 808 - 809 - return bytes_received; 810 - } 811 - 812 - static ssize_t 813 - pi433_write(struct file *filp, const char __user *buf, 814 - size_t count, loff_t *f_pos) 815 - { 816 - struct pi433_instance *instance; 817 - struct pi433_device *pi433; 818 - int retval; 819 - unsigned int required, available, copied; 820 - 821 - instance = filp->private_data; 822 - pi433 = instance->pi433; 823 - 824 - /* 825 - * check, whether internal buffer (tx thread) is big enough 826 - * for requested size 827 - */ 828 - if (count > MAX_MSG_SIZE) 829 - return -EMSGSIZE; 830 - 831 - /* 832 - * check if tx_cfg has been initialized otherwise we won't be able to 833 - * config the RF trasmitter correctly due to invalid settings 834 - */ 835 - if (!instance->tx_cfg_initialized) { 836 - dev_notice_once(pi433->dev, 837 - "write: failed due to unconfigured tx_cfg (see PI433_IOC_WR_TX_CFG)\n"); 838 - return -EINVAL; 839 - } 840 - 841 - /* 842 - * write the following sequence into fifo: 843 - * - tx_cfg 844 - * - size of message 845 - * - message 846 - */ 847 - mutex_lock(&pi433->tx_fifo_lock); 848 - 849 - required = sizeof(instance->tx_cfg) + sizeof(size_t) + count; 850 - available = kfifo_avail(&pi433->tx_fifo); 851 - if (required > available) { 852 - dev_dbg(pi433->dev, "write to fifo failed: %d bytes required but %d available\n", 853 - required, available); 854 - mutex_unlock(&pi433->tx_fifo_lock); 855 - return -EAGAIN; 856 - } 857 - 858 - retval = kfifo_in(&pi433->tx_fifo, &instance->tx_cfg, 859 - sizeof(instance->tx_cfg)); 860 - if (retval != sizeof(instance->tx_cfg)) 861 - goto abort; 862 - 863 - retval = kfifo_in(&pi433->tx_fifo, &count, sizeof(size_t)); 864 - if (retval != sizeof(size_t)) 865 - goto abort; 866 - 867 - retval = kfifo_from_user(&pi433->tx_fifo, buf, count, &copied); 868 - if (retval || copied != count) 869 - goto abort; 870 - 871 - mutex_unlock(&pi433->tx_fifo_lock); 872 - 873 - /* start transfer */ 874 - wake_up_interruptible(&pi433->tx_wait_queue); 875 - dev_dbg(pi433->dev, "write: generated new msg with %d bytes.\n", copied); 876 - 877 - return copied; 878 - 879 - abort: 880 - dev_warn(pi433->dev, 881 - "write to fifo failed, non recoverable: 0x%x\n", retval); 882 - mutex_unlock(&pi433->tx_fifo_lock); 883 - return -EAGAIN; 884 - } 885 - 886 - static long pi433_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) 887 - { 888 - struct pi433_instance *instance; 889 - struct pi433_device *pi433; 890 - struct pi433_tx_cfg tx_cfg; 891 - void __user *argp = (void __user *)arg; 892 - 893 - /* Check type and command number */ 894 - if (_IOC_TYPE(cmd) != PI433_IOC_MAGIC) 895 - return -ENOTTY; 896 - 897 - instance = filp->private_data; 898 - pi433 = instance->pi433; 899 - 900 - if (!pi433) 901 - return -ESHUTDOWN; 902 - 903 - switch (cmd) { 904 - case PI433_IOC_RD_TX_CFG: 905 - if (copy_to_user(argp, &instance->tx_cfg, 906 - sizeof(struct pi433_tx_cfg))) 907 - return -EFAULT; 908 - break; 909 - case PI433_IOC_WR_TX_CFG: 910 - if (copy_from_user(&tx_cfg, argp, sizeof(struct pi433_tx_cfg))) 911 - return -EFAULT; 912 - mutex_lock(&pi433->tx_fifo_lock); 913 - memcpy(&instance->tx_cfg, &tx_cfg, sizeof(struct pi433_tx_cfg)); 914 - instance->tx_cfg_initialized = true; 915 - mutex_unlock(&pi433->tx_fifo_lock); 916 - break; 917 - case PI433_IOC_RD_RX_CFG: 918 - if (copy_to_user(argp, &pi433->rx_cfg, 919 - sizeof(struct pi433_rx_cfg))) 920 - return -EFAULT; 921 - break; 922 - case PI433_IOC_WR_RX_CFG: 923 - mutex_lock(&pi433->rx_lock); 924 - 925 - /* during pending read request, change of config not allowed */ 926 - if (pi433->rx_active) { 927 - mutex_unlock(&pi433->rx_lock); 928 - return -EAGAIN; 929 - } 930 - 931 - if (copy_from_user(&pi433->rx_cfg, argp, 932 - sizeof(struct pi433_rx_cfg))) { 933 - mutex_unlock(&pi433->rx_lock); 934 - return -EFAULT; 935 - } 936 - 937 - mutex_unlock(&pi433->rx_lock); 938 - break; 939 - default: 940 - return -EINVAL; 941 - } 942 - 943 - return 0; 944 - } 945 - 946 - /*-------------------------------------------------------------------------*/ 947 - 948 - static int pi433_open(struct inode *inode, struct file *filp) 949 - { 950 - struct pi433_device *pi433; 951 - struct pi433_instance *instance; 952 - 953 - mutex_lock(&minor_lock); 954 - pi433 = idr_find(&pi433_idr, iminor(inode)); 955 - mutex_unlock(&minor_lock); 956 - if (!pi433) { 957 - pr_debug("device: minor %d unknown.\n", iminor(inode)); 958 - return -ENODEV; 959 - } 960 - 961 - instance = kzalloc(sizeof(*instance), GFP_KERNEL); 962 - if (!instance) 963 - return -ENOMEM; 964 - 965 - /* setup instance data*/ 966 - instance->pi433 = pi433; 967 - 968 - /* instance data as context */ 969 - filp->private_data = instance; 970 - stream_open(inode, filp); 971 - 972 - return 0; 973 - } 974 - 975 - static int pi433_release(struct inode *inode, struct file *filp) 976 - { 977 - struct pi433_instance *instance; 978 - 979 - instance = filp->private_data; 980 - kfree(instance); 981 - filp->private_data = NULL; 982 - 983 - return 0; 984 - } 985 - 986 - /*-------------------------------------------------------------------------*/ 987 - 988 - static int setup_gpio(struct pi433_device *pi433) 989 - { 990 - char name[5]; 991 - int retval; 992 - int i; 993 - const irq_handler_t DIO_irq_handler[NUM_DIO] = { 994 - DIO0_irq_handler, 995 - DIO1_irq_handler 996 - }; 997 - 998 - for (i = 0; i < NUM_DIO; i++) { 999 - /* "construct" name and get the gpio descriptor */ 1000 - snprintf(name, sizeof(name), "DIO%d", i); 1001 - pi433->gpiod[i] = gpiod_get(&pi433->spi->dev, name, 1002 - 0 /*GPIOD_IN*/); 1003 - 1004 - if (pi433->gpiod[i] == ERR_PTR(-ENOENT)) { 1005 - dev_dbg(&pi433->spi->dev, 1006 - "Could not find entry for %s. Ignoring.\n", name); 1007 - continue; 1008 - } 1009 - 1010 - if (pi433->gpiod[i] == ERR_PTR(-EBUSY)) 1011 - dev_dbg(&pi433->spi->dev, "%s is busy.\n", name); 1012 - 1013 - if (IS_ERR(pi433->gpiod[i])) { 1014 - retval = PTR_ERR(pi433->gpiod[i]); 1015 - /* release already allocated gpios */ 1016 - for (i--; i >= 0; i--) { 1017 - free_irq(pi433->irq_num[i], pi433); 1018 - gpiod_put(pi433->gpiod[i]); 1019 - } 1020 - return retval; 1021 - } 1022 - 1023 - /* configure the pin */ 1024 - retval = gpiod_direction_input(pi433->gpiod[i]); 1025 - if (retval) 1026 - return retval; 1027 - 1028 - /* configure irq */ 1029 - pi433->irq_num[i] = gpiod_to_irq(pi433->gpiod[i]); 1030 - if (pi433->irq_num[i] < 0) { 1031 - pi433->gpiod[i] = ERR_PTR(-EINVAL); 1032 - return pi433->irq_num[i]; 1033 - } 1034 - retval = request_irq(pi433->irq_num[i], 1035 - DIO_irq_handler[i], 1036 - 0, /* flags */ 1037 - name, 1038 - pi433); 1039 - 1040 - if (retval) 1041 - return retval; 1042 - 1043 - dev_dbg(&pi433->spi->dev, "%s successfully configured\n", name); 1044 - } 1045 - 1046 - return 0; 1047 - } 1048 - 1049 - static void free_gpio(struct pi433_device *pi433) 1050 - { 1051 - int i; 1052 - 1053 - for (i = 0; i < NUM_DIO; i++) { 1054 - /* check if gpiod is valid */ 1055 - if (IS_ERR(pi433->gpiod[i])) 1056 - continue; 1057 - 1058 - free_irq(pi433->irq_num[i], pi433); 1059 - gpiod_put(pi433->gpiod[i]); 1060 - } 1061 - } 1062 - 1063 - static int pi433_get_minor(struct pi433_device *pi433) 1064 - { 1065 - int retval = -ENOMEM; 1066 - 1067 - mutex_lock(&minor_lock); 1068 - retval = idr_alloc(&pi433_idr, pi433, 0, N_PI433_MINORS, GFP_KERNEL); 1069 - if (retval >= 0) { 1070 - pi433->minor = retval; 1071 - retval = 0; 1072 - } else if (retval == -ENOSPC) { 1073 - dev_err(&pi433->spi->dev, "too many pi433 devices\n"); 1074 - retval = -EINVAL; 1075 - } 1076 - mutex_unlock(&minor_lock); 1077 - return retval; 1078 - } 1079 - 1080 - static void pi433_free_minor(struct pi433_device *pi433) 1081 - { 1082 - mutex_lock(&minor_lock); 1083 - idr_remove(&pi433_idr, pi433->minor); 1084 - mutex_unlock(&minor_lock); 1085 - } 1086 - 1087 - /*-------------------------------------------------------------------------*/ 1088 - 1089 - static const struct file_operations pi433_fops = { 1090 - .owner = THIS_MODULE, 1091 - /* 1092 - * REVISIT switch to aio primitives, so that userspace 1093 - * gets more complete API coverage. It'll simplify things 1094 - * too, except for the locking. 1095 - */ 1096 - .write = pi433_write, 1097 - .read = pi433_read, 1098 - .unlocked_ioctl = pi433_ioctl, 1099 - .compat_ioctl = compat_ptr_ioctl, 1100 - .open = pi433_open, 1101 - .release = pi433_release, 1102 - .llseek = no_llseek, 1103 - }; 1104 - 1105 - static int pi433_debugfs_regs_show(struct seq_file *m, void *p) 1106 - { 1107 - struct pi433_device *pi433; 1108 - u8 reg_data[114]; 1109 - int i; 1110 - char *fmt = "0x%02x, 0x%02x\n"; 1111 - int ret; 1112 - 1113 - pi433 = m->private; 1114 - 1115 - mutex_lock(&pi433->tx_fifo_lock); 1116 - mutex_lock(&pi433->rx_lock); 1117 - 1118 - // wait for on-going operations to finish 1119 - ret = wait_event_interruptible(pi433->rx_wait_queue, !pi433->tx_active); 1120 - if (ret) 1121 - goto out_unlock; 1122 - 1123 - ret = wait_event_interruptible(pi433->tx_wait_queue, !pi433->rx_active); 1124 - if (ret) 1125 - goto out_unlock; 1126 - 1127 - // skip FIFO register (0x0) otherwise this can affect some of uC ops 1128 - for (i = 1; i < 0x50; i++) 1129 - reg_data[i] = rf69_read_reg(pi433->spi, i); 1130 - 1131 - reg_data[REG_TESTLNA] = rf69_read_reg(pi433->spi, REG_TESTLNA); 1132 - reg_data[REG_TESTPA1] = rf69_read_reg(pi433->spi, REG_TESTPA1); 1133 - reg_data[REG_TESTPA2] = rf69_read_reg(pi433->spi, REG_TESTPA2); 1134 - reg_data[REG_TESTDAGC] = rf69_read_reg(pi433->spi, REG_TESTDAGC); 1135 - reg_data[REG_TESTAFC] = rf69_read_reg(pi433->spi, REG_TESTAFC); 1136 - 1137 - seq_puts(m, "# reg, val\n"); 1138 - 1139 - for (i = 1; i < 0x50; i++) 1140 - seq_printf(m, fmt, i, reg_data[i]); 1141 - 1142 - seq_printf(m, fmt, REG_TESTLNA, reg_data[REG_TESTLNA]); 1143 - seq_printf(m, fmt, REG_TESTPA1, reg_data[REG_TESTPA1]); 1144 - seq_printf(m, fmt, REG_TESTPA2, reg_data[REG_TESTPA2]); 1145 - seq_printf(m, fmt, REG_TESTDAGC, reg_data[REG_TESTDAGC]); 1146 - seq_printf(m, fmt, REG_TESTAFC, reg_data[REG_TESTAFC]); 1147 - 1148 - out_unlock: 1149 - mutex_unlock(&pi433->rx_lock); 1150 - mutex_unlock(&pi433->tx_fifo_lock); 1151 - 1152 - return ret; 1153 - } 1154 - DEFINE_SHOW_ATTRIBUTE(pi433_debugfs_regs); 1155 - 1156 - /*-------------------------------------------------------------------------*/ 1157 - 1158 - static int pi433_probe(struct spi_device *spi) 1159 - { 1160 - struct pi433_device *pi433; 1161 - int retval; 1162 - struct dentry *entry; 1163 - 1164 - /* setup spi parameters */ 1165 - spi->mode = 0x00; 1166 - spi->bits_per_word = 8; 1167 - /* 1168 - * spi->max_speed_hz = 10000000; 1169 - * 1MHz already set by device tree overlay 1170 - */ 1171 - 1172 - retval = spi_setup(spi); 1173 - if (retval) { 1174 - dev_dbg(&spi->dev, "configuration of SPI interface failed!\n"); 1175 - return retval; 1176 - } 1177 - 1178 - dev_dbg(&spi->dev, 1179 - "spi interface setup: mode 0x%2x, %d bits per word, %dhz max speed\n", 1180 - spi->mode, spi->bits_per_word, spi->max_speed_hz); 1181 - 1182 - /* read chip version */ 1183 - retval = rf69_get_version(spi); 1184 - if (retval < 0) 1185 - return retval; 1186 - 1187 - switch (retval) { 1188 - case 0x24: 1189 - dev_dbg(&spi->dev, "found pi433 (ver. 0x%x)\n", retval); 1190 - break; 1191 - default: 1192 - dev_dbg(&spi->dev, "unknown chip version: 0x%x\n", retval); 1193 - return -ENODEV; 1194 - } 1195 - 1196 - /* Allocate driver data */ 1197 - pi433 = kzalloc(sizeof(*pi433), GFP_KERNEL); 1198 - if (!pi433) 1199 - return -ENOMEM; 1200 - 1201 - /* Initialize the driver data */ 1202 - pi433->spi = spi; 1203 - pi433->rx_active = false; 1204 - pi433->tx_active = false; 1205 - pi433->interrupt_rx_allowed = false; 1206 - 1207 - /* init rx buffer */ 1208 - pi433->rx_buffer = kmalloc(MAX_MSG_SIZE, GFP_KERNEL); 1209 - if (!pi433->rx_buffer) { 1210 - retval = -ENOMEM; 1211 - goto RX_failed; 1212 - } 1213 - 1214 - /* init wait queues */ 1215 - init_waitqueue_head(&pi433->tx_wait_queue); 1216 - init_waitqueue_head(&pi433->rx_wait_queue); 1217 - init_waitqueue_head(&pi433->fifo_wait_queue); 1218 - 1219 - /* init fifo */ 1220 - INIT_KFIFO(pi433->tx_fifo); 1221 - 1222 - /* init mutexes and locks */ 1223 - mutex_init(&pi433->tx_fifo_lock); 1224 - mutex_init(&pi433->rx_lock); 1225 - 1226 - /* setup GPIO (including irq_handler) for the different DIOs */ 1227 - retval = setup_gpio(pi433); 1228 - if (retval) { 1229 - dev_dbg(&spi->dev, "setup of GPIOs failed\n"); 1230 - goto GPIO_failed; 1231 - } 1232 - 1233 - /* setup the radio module */ 1234 - retval = rf69_set_mode(spi, standby); 1235 - if (retval < 0) 1236 - goto minor_failed; 1237 - retval = rf69_set_data_mode(spi, DATAMODUL_MODE_PACKET); 1238 - if (retval < 0) 1239 - goto minor_failed; 1240 - retval = rf69_enable_amplifier(spi, MASK_PALEVEL_PA0); 1241 - if (retval < 0) 1242 - goto minor_failed; 1243 - retval = rf69_disable_amplifier(spi, MASK_PALEVEL_PA1); 1244 - if (retval < 0) 1245 - goto minor_failed; 1246 - retval = rf69_disable_amplifier(spi, MASK_PALEVEL_PA2); 1247 - if (retval < 0) 1248 - goto minor_failed; 1249 - retval = rf69_set_output_power_level(spi, 13); 1250 - if (retval < 0) 1251 - goto minor_failed; 1252 - retval = rf69_set_antenna_impedance(spi, fifty_ohm); 1253 - if (retval < 0) 1254 - goto minor_failed; 1255 - 1256 - /* determ minor number */ 1257 - retval = pi433_get_minor(pi433); 1258 - if (retval) { 1259 - dev_dbg(&spi->dev, "get of minor number failed\n"); 1260 - goto minor_failed; 1261 - } 1262 - 1263 - /* create device */ 1264 - pi433->devt = MKDEV(MAJOR(pi433_devt), pi433->minor); 1265 - pi433->dev = device_create(&pi433_class, 1266 - &spi->dev, 1267 - pi433->devt, 1268 - pi433, 1269 - "pi433.%d", 1270 - pi433->minor); 1271 - if (IS_ERR(pi433->dev)) { 1272 - pr_err("pi433: device register failed\n"); 1273 - retval = PTR_ERR(pi433->dev); 1274 - goto device_create_failed; 1275 - } else { 1276 - dev_dbg(pi433->dev, 1277 - "created device for major %d, minor %d\n", 1278 - MAJOR(pi433_devt), 1279 - pi433->minor); 1280 - } 1281 - 1282 - /* start tx thread */ 1283 - pi433->tx_task_struct = kthread_run(pi433_tx_thread, 1284 - pi433, 1285 - "pi433.%d_tx_task", 1286 - pi433->minor); 1287 - if (IS_ERR(pi433->tx_task_struct)) { 1288 - dev_dbg(pi433->dev, "start of send thread failed\n"); 1289 - retval = PTR_ERR(pi433->tx_task_struct); 1290 - goto send_thread_failed; 1291 - } 1292 - 1293 - /* create cdev */ 1294 - pi433->cdev = cdev_alloc(); 1295 - if (!pi433->cdev) { 1296 - dev_dbg(pi433->dev, "allocation of cdev failed\n"); 1297 - retval = -ENOMEM; 1298 - goto cdev_failed; 1299 - } 1300 - pi433->cdev->owner = THIS_MODULE; 1301 - cdev_init(pi433->cdev, &pi433_fops); 1302 - retval = cdev_add(pi433->cdev, pi433->devt, 1); 1303 - if (retval) { 1304 - dev_dbg(pi433->dev, "register of cdev failed\n"); 1305 - goto del_cdev; 1306 - } 1307 - 1308 - /* spi setup */ 1309 - spi_set_drvdata(spi, pi433); 1310 - 1311 - entry = debugfs_create_dir(dev_name(pi433->dev), root_dir); 1312 - debugfs_create_file("regs", 0400, entry, pi433, &pi433_debugfs_regs_fops); 1313 - 1314 - return 0; 1315 - 1316 - del_cdev: 1317 - cdev_del(pi433->cdev); 1318 - cdev_failed: 1319 - kthread_stop(pi433->tx_task_struct); 1320 - send_thread_failed: 1321 - device_destroy(&pi433_class, pi433->devt); 1322 - device_create_failed: 1323 - pi433_free_minor(pi433); 1324 - minor_failed: 1325 - free_gpio(pi433); 1326 - GPIO_failed: 1327 - kfree(pi433->rx_buffer); 1328 - RX_failed: 1329 - kfree(pi433); 1330 - 1331 - return retval; 1332 - } 1333 - 1334 - static void pi433_remove(struct spi_device *spi) 1335 - { 1336 - struct pi433_device *pi433 = spi_get_drvdata(spi); 1337 - 1338 - debugfs_lookup_and_remove(dev_name(pi433->dev), root_dir); 1339 - 1340 - /* free GPIOs */ 1341 - free_gpio(pi433); 1342 - 1343 - /* make sure ops on existing fds can abort cleanly */ 1344 - pi433->spi = NULL; 1345 - 1346 - kthread_stop(pi433->tx_task_struct); 1347 - 1348 - device_destroy(&pi433_class, pi433->devt); 1349 - 1350 - cdev_del(pi433->cdev); 1351 - 1352 - pi433_free_minor(pi433); 1353 - 1354 - kfree(pi433->rx_buffer); 1355 - kfree(pi433); 1356 - } 1357 - 1358 - static const struct of_device_id pi433_dt_ids[] = { 1359 - { .compatible = "Smarthome-Wolf,pi433" }, 1360 - {}, 1361 - }; 1362 - 1363 - MODULE_DEVICE_TABLE(of, pi433_dt_ids); 1364 - 1365 - static struct spi_driver pi433_spi_driver = { 1366 - .driver = { 1367 - .name = "pi433", 1368 - .of_match_table = of_match_ptr(pi433_dt_ids), 1369 - }, 1370 - .probe = pi433_probe, 1371 - .remove = pi433_remove, 1372 - 1373 - /* 1374 - * NOTE: suspend/resume methods are not necessary here. 1375 - * We don't do anything except pass the requests to/from 1376 - * the underlying controller. The refrigerator handles 1377 - * most issues; the controller driver handles the rest. 1378 - */ 1379 - }; 1380 - 1381 - /*-------------------------------------------------------------------------*/ 1382 - 1383 - static int __init pi433_init(void) 1384 - { 1385 - int status; 1386 - 1387 - /* 1388 - * If MAX_MSG_SIZE is smaller then FIFO_SIZE, the driver won't 1389 - * work stable - risk of buffer overflow 1390 - */ 1391 - if (MAX_MSG_SIZE < FIFO_SIZE) 1392 - return -EINVAL; 1393 - 1394 - /* 1395 - * Claim device numbers. Then register a class 1396 - * that will key udev/mdev to add/remove /dev nodes. 1397 - * Last, register the driver which manages those device numbers. 1398 - */ 1399 - status = alloc_chrdev_region(&pi433_devt, 0, N_PI433_MINORS, "pi433"); 1400 - if (status < 0) 1401 - return status; 1402 - 1403 - status = class_register(&pi433_class); 1404 - if (status) 1405 - goto unreg_chrdev; 1406 - 1407 - root_dir = debugfs_create_dir(KBUILD_MODNAME, NULL); 1408 - 1409 - status = spi_register_driver(&pi433_spi_driver); 1410 - if (status < 0) 1411 - goto unreg_class_and_remove_dbfs; 1412 - 1413 - return 0; 1414 - 1415 - unreg_class_and_remove_dbfs: 1416 - debugfs_remove(root_dir); 1417 - class_unregister(&pi433_class); 1418 - unreg_chrdev: 1419 - unregister_chrdev(MAJOR(pi433_devt), pi433_spi_driver.driver.name); 1420 - return status; 1421 - } 1422 - 1423 - module_init(pi433_init); 1424 - 1425 - static void __exit pi433_exit(void) 1426 - { 1427 - spi_unregister_driver(&pi433_spi_driver); 1428 - debugfs_remove(root_dir); 1429 - class_unregister(&pi433_class); 1430 - unregister_chrdev(MAJOR(pi433_devt), pi433_spi_driver.driver.name); 1431 - } 1432 - module_exit(pi433_exit); 1433 - 1434 - MODULE_AUTHOR("Marcus Wolf, <linux@wolf-entwicklungen.de>"); 1435 - MODULE_DESCRIPTION("Driver for Pi433"); 1436 - MODULE_LICENSE("GPL"); 1437 - MODULE_ALIAS("spi:pi433");
-148
drivers/staging/pi433/pi433_if.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * userspace interface for pi433 radio module 4 - * 5 - * Pi433 is a 433MHz radio module for the Raspberry Pi. 6 - * It is based on the HopeRf Module RFM69CW. Therefore, inside of this 7 - * driver you'll find an abstraction of the rf69 chip. 8 - * 9 - * If needed this driver could also be extended to support other 10 - * devices based on HopeRf rf69 as well as HopeRf modules with a similar 11 - * interface such as RFM69HCW, RFM12, RFM95 and so on. 12 - * 13 - * Copyright (C) 2016 Wolf-Entwicklungen 14 - * Marcus Wolf <linux@wolf-entwicklungen.de> 15 - */ 16 - 17 - #ifndef PI433_H 18 - #define PI433_H 19 - 20 - #include <linux/types.h> 21 - #include "rf69_enum.h" 22 - 23 - /*---------------------------------------------------------------------------*/ 24 - 25 - enum option_on_off { 26 - OPTION_OFF, 27 - OPTION_ON 28 - }; 29 - 30 - /* IOCTL structs and commands */ 31 - 32 - /** 33 - * struct pi433_tx_cfg 34 - * describes the configuration of the radio module for sending data 35 - * @frequency: 36 - * @bit_rate: 37 - * @modulation: 38 - * @data_mode: 39 - * @preamble_length: 40 - * @sync_pattern: 41 - * @tx_start_condition: 42 - * @payload_length: 43 - * @repetitions: 44 - * 45 - * ATTENTION: 46 - * If the contents of 'pi433_tx_cfg' ever change 47 - * incompatibly, then the ioctl number (see define below) must change. 48 - * 49 - * NOTE: struct layout is the same in 64bit and 32bit userspace. 50 - */ 51 - #define PI433_TX_CFG_IOCTL_NR 0 52 - struct pi433_tx_cfg { 53 - __u32 frequency; 54 - __u16 bit_rate; 55 - __u32 dev_frequency; 56 - enum modulation modulation; 57 - enum mod_shaping mod_shaping; 58 - 59 - enum pa_ramp pa_ramp; 60 - 61 - enum tx_start_condition tx_start_condition; 62 - 63 - __u16 repetitions; 64 - 65 - /* packet format */ 66 - enum option_on_off enable_preamble; 67 - enum option_on_off enable_sync; 68 - enum option_on_off enable_length_byte; 69 - enum option_on_off enable_address_byte; 70 - enum option_on_off enable_crc; 71 - 72 - __u16 preamble_length; 73 - __u8 sync_length; 74 - __u8 fixed_message_length; 75 - 76 - __u8 sync_pattern[8]; 77 - __u8 address_byte; 78 - }; 79 - 80 - /** 81 - * struct pi433_rx_cfg 82 - * describes the configuration of the radio module for receiving data 83 - * @frequency: 84 - * @bit_rate: 85 - * @modulation: 86 - * @data_mode: 87 - * @preamble_length: 88 - * @sync_pattern: 89 - * @tx_start_condition: 90 - * @payload_length: 91 - * @repetitions: 92 - * 93 - * ATTENTION: 94 - * If the contents of 'pi433_rx_cfg' ever change 95 - * incompatibly, then the ioctl number (see define below) must change 96 - * 97 - * NOTE: struct layout is the same in 64bit and 32bit userspace. 98 - */ 99 - #define PI433_RX_CFG_IOCTL_NR 1 100 - struct pi433_rx_cfg { 101 - __u32 frequency; 102 - __u16 bit_rate; 103 - __u32 dev_frequency; 104 - 105 - enum modulation modulation; 106 - 107 - __u8 rssi_threshold; 108 - enum threshold_decrement threshold_decrement; 109 - enum antenna_impedance antenna_impedance; 110 - enum lna_gain lna_gain; 111 - enum mantisse bw_mantisse; /* normal: 0x50 */ 112 - __u8 bw_exponent; /* during AFC: 0x8b */ 113 - enum dagc dagc; 114 - 115 - /* packet format */ 116 - enum option_on_off enable_sync; 117 - 118 - /* should be used in combination with sync, only */ 119 - enum option_on_off enable_length_byte; 120 - 121 - /* operational with sync, only */ 122 - enum address_filtering enable_address_filtering; 123 - 124 - /* only operational, if sync on and fixed length or length byte is used */ 125 - enum option_on_off enable_crc; 126 - 127 - __u8 sync_length; 128 - __u8 fixed_message_length; 129 - __u32 bytes_to_drop; 130 - 131 - __u8 sync_pattern[8]; 132 - __u8 node_address; 133 - __u8 broadcast_address; 134 - }; 135 - 136 - #define PI433_IOC_MAGIC 'r' 137 - 138 - #define PI433_IOC_RD_TX_CFG \ 139 - _IOR(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, char[sizeof(struct pi433_tx_cfg)]) 140 - #define PI433_IOC_WR_TX_CFG \ 141 - _IOW(PI433_IOC_MAGIC, PI433_TX_CFG_IOCTL_NR, char[sizeof(struct pi433_tx_cfg)]) 142 - 143 - #define PI433_IOC_RD_RX_CFG \ 144 - _IOR(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, char[sizeof(struct pi433_rx_cfg)]) 145 - #define PI433_IOC_WR_RX_CFG \ 146 - _IOW(PI433_IOC_MAGIC, PI433_RX_CFG_IOCTL_NR, char[sizeof(struct pi433_rx_cfg)]) 147 - 148 - #endif /* PI433_H */
-832
drivers/staging/pi433/rf69.c
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 2 - /* 3 - * abstraction of the spi interface of HopeRf rf69 radio module 4 - * 5 - * Copyright (C) 2016 Wolf-Entwicklungen 6 - * Marcus Wolf <linux@wolf-entwicklungen.de> 7 - */ 8 - 9 - #include <linux/types.h> 10 - #include <linux/spi/spi.h> 11 - #include <linux/units.h> 12 - 13 - #include "rf69.h" 14 - #include "rf69_registers.h" 15 - 16 - #define F_OSC (32 * HZ_PER_MHZ) 17 - 18 - /*-------------------------------------------------------------------------*/ 19 - 20 - u8 rf69_read_reg(struct spi_device *spi, u8 addr) 21 - { 22 - return spi_w8r8(spi, addr); 23 - } 24 - 25 - static int rf69_write_reg(struct spi_device *spi, u8 addr, u8 value) 26 - { 27 - char buffer[2]; 28 - 29 - buffer[0] = addr | WRITE_BIT; 30 - buffer[1] = value; 31 - 32 - return spi_write(spi, &buffer, ARRAY_SIZE(buffer)); 33 - } 34 - 35 - /*-------------------------------------------------------------------------*/ 36 - 37 - static int rf69_set_bit(struct spi_device *spi, u8 reg, u8 mask) 38 - { 39 - u8 tmp; 40 - 41 - tmp = rf69_read_reg(spi, reg); 42 - tmp = tmp | mask; 43 - return rf69_write_reg(spi, reg, tmp); 44 - } 45 - 46 - static int rf69_clear_bit(struct spi_device *spi, u8 reg, u8 mask) 47 - { 48 - u8 tmp; 49 - 50 - tmp = rf69_read_reg(spi, reg); 51 - tmp = tmp & ~mask; 52 - return rf69_write_reg(spi, reg, tmp); 53 - } 54 - 55 - static inline int rf69_read_mod_write(struct spi_device *spi, u8 reg, 56 - u8 mask, u8 value) 57 - { 58 - u8 tmp; 59 - 60 - tmp = rf69_read_reg(spi, reg); 61 - tmp = (tmp & ~mask) | value; 62 - return rf69_write_reg(spi, reg, tmp); 63 - } 64 - 65 - /*-------------------------------------------------------------------------*/ 66 - 67 - int rf69_get_version(struct spi_device *spi) 68 - { 69 - return rf69_read_reg(spi, REG_VERSION); 70 - } 71 - 72 - int rf69_set_mode(struct spi_device *spi, enum mode mode) 73 - { 74 - static const u8 mode_map[] = { 75 - [transmit] = OPMODE_MODE_TRANSMIT, 76 - [receive] = OPMODE_MODE_RECEIVE, 77 - [synthesizer] = OPMODE_MODE_SYNTHESIZER, 78 - [standby] = OPMODE_MODE_STANDBY, 79 - [mode_sleep] = OPMODE_MODE_SLEEP, 80 - }; 81 - 82 - if (unlikely(mode >= ARRAY_SIZE(mode_map))) { 83 - dev_dbg(&spi->dev, "set: illegal mode %u\n", mode); 84 - return -EINVAL; 85 - } 86 - 87 - return rf69_read_mod_write(spi, REG_OPMODE, MASK_OPMODE_MODE, 88 - mode_map[mode]); 89 - 90 - /* 91 - * we are using packet mode, so this check is not really needed 92 - * but waiting for mode ready is necessary when going from sleep 93 - * because the FIFO may not be immediately available from previous mode 94 - * while (_mode == RF69_MODE_SLEEP && (READ_REG(REG_IRQFLAGS1) & 95 - RF_IRQFLAGS1_MODEREADY) == 0x00); // Wait for ModeReady 96 - */ 97 - } 98 - 99 - int rf69_set_data_mode(struct spi_device *spi, u8 data_mode) 100 - { 101 - return rf69_read_mod_write(spi, REG_DATAMODUL, MASK_DATAMODUL_MODE, 102 - data_mode); 103 - } 104 - 105 - int rf69_set_modulation(struct spi_device *spi, enum modulation modulation) 106 - { 107 - static const u8 modulation_map[] = { 108 - [OOK] = DATAMODUL_MODULATION_TYPE_OOK, 109 - [FSK] = DATAMODUL_MODULATION_TYPE_FSK, 110 - }; 111 - 112 - if (unlikely(modulation >= ARRAY_SIZE(modulation_map))) { 113 - dev_dbg(&spi->dev, "set: illegal modulation %u\n", modulation); 114 - return -EINVAL; 115 - } 116 - 117 - return rf69_read_mod_write(spi, REG_DATAMODUL, 118 - MASK_DATAMODUL_MODULATION_TYPE, 119 - modulation_map[modulation]); 120 - } 121 - 122 - static enum modulation rf69_get_modulation(struct spi_device *spi) 123 - { 124 - u8 modulation_reg; 125 - 126 - modulation_reg = rf69_read_reg(spi, REG_DATAMODUL); 127 - 128 - switch (modulation_reg & MASK_DATAMODUL_MODULATION_TYPE) { 129 - case DATAMODUL_MODULATION_TYPE_OOK: 130 - return OOK; 131 - case DATAMODUL_MODULATION_TYPE_FSK: 132 - return FSK; 133 - default: 134 - return UNDEF; 135 - } 136 - } 137 - 138 - int rf69_set_modulation_shaping(struct spi_device *spi, 139 - enum mod_shaping mod_shaping) 140 - { 141 - switch (rf69_get_modulation(spi)) { 142 - case FSK: 143 - switch (mod_shaping) { 144 - case SHAPING_OFF: 145 - return rf69_read_mod_write(spi, REG_DATAMODUL, 146 - MASK_DATAMODUL_MODULATION_SHAPE, 147 - DATAMODUL_MODULATION_SHAPE_NONE); 148 - case SHAPING_1_0: 149 - return rf69_read_mod_write(spi, REG_DATAMODUL, 150 - MASK_DATAMODUL_MODULATION_SHAPE, 151 - DATAMODUL_MODULATION_SHAPE_1_0); 152 - case SHAPING_0_5: 153 - return rf69_read_mod_write(spi, REG_DATAMODUL, 154 - MASK_DATAMODUL_MODULATION_SHAPE, 155 - DATAMODUL_MODULATION_SHAPE_0_5); 156 - case SHAPING_0_3: 157 - return rf69_read_mod_write(spi, REG_DATAMODUL, 158 - MASK_DATAMODUL_MODULATION_SHAPE, 159 - DATAMODUL_MODULATION_SHAPE_0_3); 160 - default: 161 - dev_dbg(&spi->dev, "set: illegal mod shaping for FSK %u\n", mod_shaping); 162 - return -EINVAL; 163 - } 164 - case OOK: 165 - switch (mod_shaping) { 166 - case SHAPING_OFF: 167 - return rf69_read_mod_write(spi, REG_DATAMODUL, 168 - MASK_DATAMODUL_MODULATION_SHAPE, 169 - DATAMODUL_MODULATION_SHAPE_NONE); 170 - case SHAPING_BR: 171 - return rf69_read_mod_write(spi, REG_DATAMODUL, 172 - MASK_DATAMODUL_MODULATION_SHAPE, 173 - DATAMODUL_MODULATION_SHAPE_BR); 174 - case SHAPING_2BR: 175 - return rf69_read_mod_write(spi, REG_DATAMODUL, 176 - MASK_DATAMODUL_MODULATION_SHAPE, 177 - DATAMODUL_MODULATION_SHAPE_2BR); 178 - default: 179 - dev_dbg(&spi->dev, "set: illegal mod shaping for OOK %u\n", mod_shaping); 180 - return -EINVAL; 181 - } 182 - default: 183 - dev_dbg(&spi->dev, "set: modulation undefined\n"); 184 - return -EINVAL; 185 - } 186 - } 187 - 188 - int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate) 189 - { 190 - int retval; 191 - u32 bit_rate_reg; 192 - u8 msb; 193 - u8 lsb; 194 - enum modulation mod; 195 - 196 - // check if modulation is configured 197 - mod = rf69_get_modulation(spi); 198 - if (mod == UNDEF) { 199 - dev_dbg(&spi->dev, "setBitRate: modulation is undefined\n"); 200 - return -EINVAL; 201 - } 202 - 203 - // check input value 204 - if (bit_rate < 1200 || (mod == OOK && bit_rate > 32768)) { 205 - dev_dbg(&spi->dev, "setBitRate: illegal input param\n"); 206 - return -EINVAL; 207 - } 208 - 209 - // calculate reg settings 210 - bit_rate_reg = (F_OSC / bit_rate); 211 - 212 - msb = (bit_rate_reg & 0xff00) >> 8; 213 - lsb = (bit_rate_reg & 0xff); 214 - 215 - // transmit to RF 69 216 - retval = rf69_write_reg(spi, REG_BITRATE_MSB, msb); 217 - if (retval) 218 - return retval; 219 - retval = rf69_write_reg(spi, REG_BITRATE_LSB, lsb); 220 - if (retval) 221 - return retval; 222 - 223 - return 0; 224 - } 225 - 226 - int rf69_set_deviation(struct spi_device *spi, u32 deviation) 227 - { 228 - int retval; 229 - u64 f_reg; 230 - u64 f_step; 231 - u32 bit_rate_reg; 232 - u32 bit_rate; 233 - u8 msb; 234 - u8 lsb; 235 - u64 factor = 1000000; // to improve precision of calculation 236 - 237 - // calculate bit rate 238 - bit_rate_reg = rf69_read_reg(spi, REG_BITRATE_MSB) << 8; 239 - bit_rate_reg |= rf69_read_reg(spi, REG_BITRATE_LSB); 240 - bit_rate = F_OSC / bit_rate_reg; 241 - 242 - /* 243 - * frequency deviation must exceed 600 Hz but not exceed 244 - * 500kHz when taking bitrate dependency into consideration 245 - * to ensure proper modulation 246 - */ 247 - if (deviation < 600 || (deviation + (bit_rate / 2)) > 500000) { 248 - dev_dbg(&spi->dev, 249 - "set_deviation: illegal input param: %u\n", deviation); 250 - return -EINVAL; 251 - } 252 - 253 - // calculat f step 254 - f_step = F_OSC * factor; 255 - do_div(f_step, 524288); // 524288 = 2^19 256 - 257 - // calculate register settings 258 - f_reg = deviation * factor; 259 - do_div(f_reg, f_step); 260 - 261 - msb = (f_reg & 0xff00) >> 8; 262 - lsb = (f_reg & 0xff); 263 - 264 - // check msb 265 - if (msb & ~FDEVMASB_MASK) { 266 - dev_dbg(&spi->dev, "set_deviation: err in calc of msb\n"); 267 - return -EINVAL; 268 - } 269 - 270 - // write to chip 271 - retval = rf69_write_reg(spi, REG_FDEV_MSB, msb); 272 - if (retval) 273 - return retval; 274 - retval = rf69_write_reg(spi, REG_FDEV_LSB, lsb); 275 - if (retval) 276 - return retval; 277 - 278 - return 0; 279 - } 280 - 281 - int rf69_set_frequency(struct spi_device *spi, u32 frequency) 282 - { 283 - int retval; 284 - u32 f_max; 285 - u64 f_reg; 286 - u64 f_step; 287 - u8 msb; 288 - u8 mid; 289 - u8 lsb; 290 - u64 factor = 1000000; // to improve precision of calculation 291 - 292 - // calculat f step 293 - f_step = F_OSC * factor; 294 - do_div(f_step, 524288); // 524288 = 2^19 295 - 296 - // check input value 297 - f_max = div_u64(f_step * 8388608, factor); 298 - if (frequency > f_max) { 299 - dev_dbg(&spi->dev, "setFrequency: illegal input param\n"); 300 - return -EINVAL; 301 - } 302 - 303 - // calculate reg settings 304 - f_reg = frequency * factor; 305 - do_div(f_reg, f_step); 306 - 307 - msb = (f_reg & 0xff0000) >> 16; 308 - mid = (f_reg & 0xff00) >> 8; 309 - lsb = (f_reg & 0xff); 310 - 311 - // write to chip 312 - retval = rf69_write_reg(spi, REG_FRF_MSB, msb); 313 - if (retval) 314 - return retval; 315 - retval = rf69_write_reg(spi, REG_FRF_MID, mid); 316 - if (retval) 317 - return retval; 318 - retval = rf69_write_reg(spi, REG_FRF_LSB, lsb); 319 - if (retval) 320 - return retval; 321 - 322 - return 0; 323 - } 324 - 325 - int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask) 326 - { 327 - return rf69_set_bit(spi, REG_PALEVEL, amplifier_mask); 328 - } 329 - 330 - int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask) 331 - { 332 - return rf69_clear_bit(spi, REG_PALEVEL, amplifier_mask); 333 - } 334 - 335 - int rf69_set_output_power_level(struct spi_device *spi, u8 power_level) 336 - { 337 - u8 pa_level, ocp, test_pa1, test_pa2; 338 - bool pa0, pa1, pa2, high_power; 339 - u8 min_power_level; 340 - 341 - // check register pa_level 342 - pa_level = rf69_read_reg(spi, REG_PALEVEL); 343 - pa0 = pa_level & MASK_PALEVEL_PA0; 344 - pa1 = pa_level & MASK_PALEVEL_PA1; 345 - pa2 = pa_level & MASK_PALEVEL_PA2; 346 - 347 - // check high power mode 348 - ocp = rf69_read_reg(spi, REG_OCP); 349 - test_pa1 = rf69_read_reg(spi, REG_TESTPA1); 350 - test_pa2 = rf69_read_reg(spi, REG_TESTPA2); 351 - high_power = (ocp == 0x0f) && (test_pa1 == 0x5d) && (test_pa2 == 0x7c); 352 - 353 - if (pa0 && !pa1 && !pa2) { 354 - power_level += 18; 355 - min_power_level = 0; 356 - } else if (!pa0 && pa1 && !pa2) { 357 - power_level += 18; 358 - min_power_level = 16; 359 - } else if (!pa0 && pa1 && pa2) { 360 - if (high_power) 361 - power_level += 11; 362 - else 363 - power_level += 14; 364 - min_power_level = 16; 365 - } else { 366 - goto failed; 367 - } 368 - 369 - // check input value 370 - if (power_level > 0x1f) 371 - goto failed; 372 - 373 - if (power_level < min_power_level) 374 - goto failed; 375 - 376 - // write value 377 - return rf69_read_mod_write(spi, REG_PALEVEL, MASK_PALEVEL_OUTPUT_POWER, 378 - power_level); 379 - failed: 380 - dev_dbg(&spi->dev, "set: illegal power level %u\n", power_level); 381 - return -EINVAL; 382 - } 383 - 384 - int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp) 385 - { 386 - static const u8 pa_ramp_map[] = { 387 - [ramp3400] = PARAMP_3400, 388 - [ramp2000] = PARAMP_2000, 389 - [ramp1000] = PARAMP_1000, 390 - [ramp500] = PARAMP_500, 391 - [ramp250] = PARAMP_250, 392 - [ramp125] = PARAMP_125, 393 - [ramp100] = PARAMP_100, 394 - [ramp62] = PARAMP_62, 395 - [ramp50] = PARAMP_50, 396 - [ramp40] = PARAMP_40, 397 - [ramp31] = PARAMP_31, 398 - [ramp25] = PARAMP_25, 399 - [ramp20] = PARAMP_20, 400 - [ramp15] = PARAMP_15, 401 - [ramp10] = PARAMP_10, 402 - }; 403 - 404 - if (unlikely(pa_ramp >= ARRAY_SIZE(pa_ramp_map))) { 405 - dev_dbg(&spi->dev, "set: illegal pa_ramp %u\n", pa_ramp); 406 - return -EINVAL; 407 - } 408 - 409 - return rf69_write_reg(spi, REG_PARAMP, pa_ramp_map[pa_ramp]); 410 - } 411 - 412 - int rf69_set_antenna_impedance(struct spi_device *spi, 413 - enum antenna_impedance antenna_impedance) 414 - { 415 - switch (antenna_impedance) { 416 - case fifty_ohm: 417 - return rf69_clear_bit(spi, REG_LNA, MASK_LNA_ZIN); 418 - case two_hundred_ohm: 419 - return rf69_set_bit(spi, REG_LNA, MASK_LNA_ZIN); 420 - default: 421 - dev_dbg(&spi->dev, "set: illegal antenna impedance %u\n", antenna_impedance); 422 - return -EINVAL; 423 - } 424 - } 425 - 426 - int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain) 427 - { 428 - static const u8 lna_gain_map[] = { 429 - [automatic] = LNA_GAIN_AUTO, 430 - [max] = LNA_GAIN_MAX, 431 - [max_minus_6] = LNA_GAIN_MAX_MINUS_6, 432 - [max_minus_12] = LNA_GAIN_MAX_MINUS_12, 433 - [max_minus_24] = LNA_GAIN_MAX_MINUS_24, 434 - [max_minus_36] = LNA_GAIN_MAX_MINUS_36, 435 - [max_minus_48] = LNA_GAIN_MAX_MINUS_48, 436 - }; 437 - 438 - if (unlikely(lna_gain >= ARRAY_SIZE(lna_gain_map))) { 439 - dev_dbg(&spi->dev, "set: illegal lna gain %u\n", lna_gain); 440 - return -EINVAL; 441 - } 442 - 443 - return rf69_read_mod_write(spi, REG_LNA, MASK_LNA_GAIN, 444 - lna_gain_map[lna_gain]); 445 - } 446 - 447 - static int rf69_set_bandwidth_intern(struct spi_device *spi, u8 reg, 448 - enum mantisse mantisse, u8 exponent) 449 - { 450 - u8 bandwidth; 451 - 452 - // check value for mantisse and exponent 453 - if (exponent > 7) { 454 - dev_dbg(&spi->dev, "set: illegal bandwidth exponent %u\n", exponent); 455 - return -EINVAL; 456 - } 457 - 458 - if (mantisse != mantisse16 && 459 - mantisse != mantisse20 && 460 - mantisse != mantisse24) { 461 - dev_dbg(&spi->dev, "set: illegal bandwidth mantisse %u\n", mantisse); 462 - return -EINVAL; 463 - } 464 - 465 - // read old value 466 - bandwidth = rf69_read_reg(spi, reg); 467 - 468 - // "delete" mantisse and exponent = just keep the DCC setting 469 - bandwidth = bandwidth & MASK_BW_DCC_FREQ; 470 - 471 - // add new mantisse 472 - switch (mantisse) { 473 - case mantisse16: 474 - bandwidth = bandwidth | BW_MANT_16; 475 - break; 476 - case mantisse20: 477 - bandwidth = bandwidth | BW_MANT_20; 478 - break; 479 - case mantisse24: 480 - bandwidth = bandwidth | BW_MANT_24; 481 - break; 482 - } 483 - 484 - // add new exponent 485 - bandwidth = bandwidth | exponent; 486 - 487 - // write back 488 - return rf69_write_reg(spi, reg, bandwidth); 489 - } 490 - 491 - int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, 492 - u8 exponent) 493 - { 494 - return rf69_set_bandwidth_intern(spi, REG_RXBW, mantisse, exponent); 495 - } 496 - 497 - int rf69_set_bandwidth_during_afc(struct spi_device *spi, 498 - enum mantisse mantisse, 499 - u8 exponent) 500 - { 501 - return rf69_set_bandwidth_intern(spi, REG_AFCBW, mantisse, exponent); 502 - } 503 - 504 - int rf69_set_ook_threshold_dec(struct spi_device *spi, 505 - enum threshold_decrement threshold_decrement) 506 - { 507 - static const u8 td_map[] = { 508 - [dec_every8th] = OOKPEAK_THRESHDEC_EVERY_8TH, 509 - [dec_every4th] = OOKPEAK_THRESHDEC_EVERY_4TH, 510 - [dec_every2nd] = OOKPEAK_THRESHDEC_EVERY_2ND, 511 - [dec_once] = OOKPEAK_THRESHDEC_ONCE, 512 - [dec_twice] = OOKPEAK_THRESHDEC_TWICE, 513 - [dec_4times] = OOKPEAK_THRESHDEC_4_TIMES, 514 - [dec_8times] = OOKPEAK_THRESHDEC_8_TIMES, 515 - [dec_16times] = OOKPEAK_THRESHDEC_16_TIMES, 516 - }; 517 - 518 - if (unlikely(threshold_decrement >= ARRAY_SIZE(td_map))) { 519 - dev_dbg(&spi->dev, "set: illegal OOK threshold decrement %u\n", 520 - threshold_decrement); 521 - return -EINVAL; 522 - } 523 - 524 - return rf69_read_mod_write(spi, REG_OOKPEAK, MASK_OOKPEAK_THRESDEC, 525 - td_map[threshold_decrement]); 526 - } 527 - 528 - int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value) 529 - { 530 - u8 mask; 531 - u8 shift; 532 - u8 dio_addr; 533 - u8 dio_value; 534 - 535 - switch (dio_number) { 536 - case 0: 537 - mask = MASK_DIO0; 538 - shift = SHIFT_DIO0; 539 - dio_addr = REG_DIOMAPPING1; 540 - break; 541 - case 1: 542 - mask = MASK_DIO1; 543 - shift = SHIFT_DIO1; 544 - dio_addr = REG_DIOMAPPING1; 545 - break; 546 - case 2: 547 - mask = MASK_DIO2; 548 - shift = SHIFT_DIO2; 549 - dio_addr = REG_DIOMAPPING1; 550 - break; 551 - case 3: 552 - mask = MASK_DIO3; 553 - shift = SHIFT_DIO3; 554 - dio_addr = REG_DIOMAPPING1; 555 - break; 556 - case 4: 557 - mask = MASK_DIO4; 558 - shift = SHIFT_DIO4; 559 - dio_addr = REG_DIOMAPPING2; 560 - break; 561 - case 5: 562 - mask = MASK_DIO5; 563 - shift = SHIFT_DIO5; 564 - dio_addr = REG_DIOMAPPING2; 565 - break; 566 - default: 567 - dev_dbg(&spi->dev, "set: illegal dio number %u\n", dio_number); 568 - return -EINVAL; 569 - } 570 - 571 - // read reg 572 - dio_value = rf69_read_reg(spi, dio_addr); 573 - // delete old value 574 - dio_value = dio_value & ~mask; 575 - // add new value 576 - dio_value = dio_value | value << shift; 577 - // write back 578 - return rf69_write_reg(spi, dio_addr, dio_value); 579 - } 580 - 581 - int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold) 582 - { 583 - /* no value check needed - u8 exactly matches register size */ 584 - 585 - return rf69_write_reg(spi, REG_RSSITHRESH, threshold); 586 - } 587 - 588 - int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length) 589 - { 590 - int retval; 591 - u8 msb, lsb; 592 - 593 - /* no value check needed - u16 exactly matches register size */ 594 - 595 - /* calculate reg settings */ 596 - msb = (preamble_length & 0xff00) >> 8; 597 - lsb = (preamble_length & 0xff); 598 - 599 - /* transmit to chip */ 600 - retval = rf69_write_reg(spi, REG_PREAMBLE_MSB, msb); 601 - if (retval) 602 - return retval; 603 - return rf69_write_reg(spi, REG_PREAMBLE_LSB, lsb); 604 - } 605 - 606 - int rf69_enable_sync(struct spi_device *spi) 607 - { 608 - return rf69_set_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 609 - } 610 - 611 - int rf69_disable_sync(struct spi_device *spi) 612 - { 613 - return rf69_clear_bit(spi, REG_SYNC_CONFIG, MASK_SYNC_CONFIG_SYNC_ON); 614 - } 615 - 616 - int rf69_set_fifo_fill_condition(struct spi_device *spi, 617 - enum fifo_fill_condition fifo_fill_condition) 618 - { 619 - switch (fifo_fill_condition) { 620 - case always: 621 - return rf69_set_bit(spi, REG_SYNC_CONFIG, 622 - MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 623 - case after_sync_interrupt: 624 - return rf69_clear_bit(spi, REG_SYNC_CONFIG, 625 - MASK_SYNC_CONFIG_FIFO_FILL_CONDITION); 626 - default: 627 - dev_dbg(&spi->dev, "set: illegal fifo fill condition %u\n", fifo_fill_condition); 628 - return -EINVAL; 629 - } 630 - } 631 - 632 - int rf69_set_sync_size(struct spi_device *spi, u8 sync_size) 633 - { 634 - // check input value 635 - if (sync_size > 0x07) { 636 - dev_dbg(&spi->dev, "set: illegal sync size %u\n", sync_size); 637 - return -EINVAL; 638 - } 639 - 640 - // write value 641 - return rf69_read_mod_write(spi, REG_SYNC_CONFIG, 642 - MASK_SYNC_CONFIG_SYNC_SIZE, 643 - (sync_size << 3)); 644 - } 645 - 646 - int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8]) 647 - { 648 - int retval = 0; 649 - 650 - retval += rf69_write_reg(spi, REG_SYNCVALUE1, sync_values[0]); 651 - retval += rf69_write_reg(spi, REG_SYNCVALUE2, sync_values[1]); 652 - retval += rf69_write_reg(spi, REG_SYNCVALUE3, sync_values[2]); 653 - retval += rf69_write_reg(spi, REG_SYNCVALUE4, sync_values[3]); 654 - retval += rf69_write_reg(spi, REG_SYNCVALUE5, sync_values[4]); 655 - retval += rf69_write_reg(spi, REG_SYNCVALUE6, sync_values[5]); 656 - retval += rf69_write_reg(spi, REG_SYNCVALUE7, sync_values[6]); 657 - retval += rf69_write_reg(spi, REG_SYNCVALUE8, sync_values[7]); 658 - 659 - return retval; 660 - } 661 - 662 - int rf69_set_packet_format(struct spi_device *spi, 663 - enum packet_format packet_format) 664 - { 665 - switch (packet_format) { 666 - case packet_length_var: 667 - return rf69_set_bit(spi, REG_PACKETCONFIG1, 668 - MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE); 669 - case packet_length_fix: 670 - return rf69_clear_bit(spi, REG_PACKETCONFIG1, 671 - MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE); 672 - default: 673 - dev_dbg(&spi->dev, "set: illegal packet format %u\n", packet_format); 674 - return -EINVAL; 675 - } 676 - } 677 - 678 - int rf69_enable_crc(struct spi_device *spi) 679 - { 680 - return rf69_set_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 681 - } 682 - 683 - int rf69_disable_crc(struct spi_device *spi) 684 - { 685 - return rf69_clear_bit(spi, REG_PACKETCONFIG1, MASK_PACKETCONFIG1_CRC_ON); 686 - } 687 - 688 - int rf69_set_address_filtering(struct spi_device *spi, 689 - enum address_filtering address_filtering) 690 - { 691 - static const u8 af_map[] = { 692 - [filtering_off] = PACKETCONFIG1_ADDRESSFILTERING_OFF, 693 - [node_address] = PACKETCONFIG1_ADDRESSFILTERING_NODE, 694 - [node_or_broadcast_address] = 695 - PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST, 696 - }; 697 - 698 - if (unlikely(address_filtering >= ARRAY_SIZE(af_map))) { 699 - dev_dbg(&spi->dev, "set: illegal address filtering %u\n", address_filtering); 700 - return -EINVAL; 701 - } 702 - 703 - return rf69_read_mod_write(spi, REG_PACKETCONFIG1, 704 - MASK_PACKETCONFIG1_ADDRESSFILTERING, 705 - af_map[address_filtering]); 706 - } 707 - 708 - int rf69_set_payload_length(struct spi_device *spi, u8 payload_length) 709 - { 710 - return rf69_write_reg(spi, REG_PAYLOAD_LENGTH, payload_length); 711 - } 712 - 713 - int rf69_set_node_address(struct spi_device *spi, u8 node_address) 714 - { 715 - return rf69_write_reg(spi, REG_NODEADRS, node_address); 716 - } 717 - 718 - int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address) 719 - { 720 - return rf69_write_reg(spi, REG_BROADCASTADRS, broadcast_address); 721 - } 722 - 723 - int rf69_set_tx_start_condition(struct spi_device *spi, 724 - enum tx_start_condition tx_start_condition) 725 - { 726 - switch (tx_start_condition) { 727 - case fifo_level: 728 - return rf69_clear_bit(spi, REG_FIFO_THRESH, 729 - MASK_FIFO_THRESH_TXSTART); 730 - case fifo_not_empty: 731 - return rf69_set_bit(spi, REG_FIFO_THRESH, 732 - MASK_FIFO_THRESH_TXSTART); 733 - default: 734 - dev_dbg(&spi->dev, "set: illegal tx start condition %u\n", tx_start_condition); 735 - return -EINVAL; 736 - } 737 - } 738 - 739 - int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold) 740 - { 741 - int retval; 742 - 743 - /* check input value */ 744 - if (threshold & ~MASK_FIFO_THRESH_VALUE) { 745 - dev_dbg(&spi->dev, "set: illegal fifo threshold %u\n", threshold); 746 - return -EINVAL; 747 - } 748 - 749 - /* write value */ 750 - retval = rf69_read_mod_write(spi, REG_FIFO_THRESH, 751 - MASK_FIFO_THRESH_VALUE, 752 - threshold); 753 - if (retval) 754 - return retval; 755 - 756 - /* 757 - * access the fifo to activate new threshold 758 - * retval (mis-) used as buffer here 759 - */ 760 - return rf69_read_fifo(spi, (u8 *)&retval, 1); 761 - } 762 - 763 - int rf69_set_dagc(struct spi_device *spi, enum dagc dagc) 764 - { 765 - static const u8 dagc_map[] = { 766 - [normal_mode] = DAGC_NORMAL, 767 - [improve] = DAGC_IMPROVED_LOWBETA0, 768 - [improve_for_low_modulation_index] = DAGC_IMPROVED_LOWBETA1, 769 - }; 770 - 771 - if (unlikely(dagc >= ARRAY_SIZE(dagc_map))) { 772 - dev_dbg(&spi->dev, "set: illegal dagc %u\n", dagc); 773 - return -EINVAL; 774 - } 775 - 776 - return rf69_write_reg(spi, REG_TESTDAGC, dagc_map[dagc]); 777 - } 778 - 779 - /*-------------------------------------------------------------------------*/ 780 - 781 - int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 782 - { 783 - int i; 784 - struct spi_transfer transfer; 785 - u8 local_buffer[FIFO_SIZE + 1] = {}; 786 - int retval; 787 - 788 - if (size > FIFO_SIZE) { 789 - dev_dbg(&spi->dev, 790 - "read fifo: passed in buffer bigger then internal buffer\n"); 791 - return -EMSGSIZE; 792 - } 793 - 794 - /* prepare a bidirectional transfer */ 795 - local_buffer[0] = REG_FIFO; 796 - memset(&transfer, 0, sizeof(transfer)); 797 - transfer.tx_buf = local_buffer; 798 - transfer.rx_buf = local_buffer; 799 - transfer.len = size + 1; 800 - 801 - retval = spi_sync_transfer(spi, &transfer, 1); 802 - 803 - /* print content read from fifo for debugging purposes */ 804 - for (i = 0; i < size; i++) 805 - dev_dbg(&spi->dev, "%d - 0x%x\n", i, local_buffer[i + 1]); 806 - 807 - memcpy(buffer, &local_buffer[1], size); 808 - 809 - return retval; 810 - } 811 - 812 - int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size) 813 - { 814 - int i; 815 - u8 local_buffer[FIFO_SIZE + 1]; 816 - 817 - if (size > FIFO_SIZE) { 818 - dev_dbg(&spi->dev, 819 - "write fifo: passed in buffer bigger then internal buffer\n"); 820 - return -EMSGSIZE; 821 - } 822 - 823 - local_buffer[0] = REG_FIFO | WRITE_BIT; 824 - memcpy(&local_buffer[1], buffer, size); 825 - 826 - /* print content written from fifo for debugging purposes */ 827 - for (i = 0; i < size; i++) 828 - dev_dbg(&spi->dev, "%d - 0x%x\n", i, buffer[i]); 829 - 830 - return spi_write(spi, local_buffer, size + 1); 831 - } 832 -
-66
drivers/staging/pi433/rf69.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * hardware abstraction/register access for HopeRf rf69 radio module 4 - * 5 - * Copyright (C) 2016 Wolf-Entwicklungen 6 - * Marcus Wolf <linux@wolf-entwicklungen.de> 7 - */ 8 - #ifndef RF69_H 9 - #define RF69_H 10 - 11 - #include "rf69_enum.h" 12 - #include "rf69_registers.h" 13 - 14 - #define FIFO_SIZE 66 /* bytes */ 15 - 16 - u8 rf69_read_reg(struct spi_device *spi, u8 addr); 17 - int rf69_get_version(struct spi_device *spi); 18 - int rf69_set_mode(struct spi_device *spi, enum mode mode); 19 - int rf69_set_data_mode(struct spi_device *spi, u8 data_mode); 20 - int rf69_set_modulation(struct spi_device *spi, enum modulation modulation); 21 - int rf69_set_modulation_shaping(struct spi_device *spi, 22 - enum mod_shaping mod_shaping); 23 - int rf69_set_bit_rate(struct spi_device *spi, u16 bit_rate); 24 - int rf69_set_deviation(struct spi_device *spi, u32 deviation); 25 - int rf69_set_frequency(struct spi_device *spi, u32 frequency); 26 - int rf69_enable_amplifier(struct spi_device *spi, u8 amplifier_mask); 27 - int rf69_disable_amplifier(struct spi_device *spi, u8 amplifier_mask); 28 - int rf69_set_output_power_level(struct spi_device *spi, u8 power_level); 29 - int rf69_set_pa_ramp(struct spi_device *spi, enum pa_ramp pa_ramp); 30 - int rf69_set_antenna_impedance(struct spi_device *spi, 31 - enum antenna_impedance antenna_impedance); 32 - int rf69_set_lna_gain(struct spi_device *spi, enum lna_gain lna_gain); 33 - int rf69_set_bandwidth(struct spi_device *spi, enum mantisse mantisse, 34 - u8 exponent); 35 - int rf69_set_bandwidth_during_afc(struct spi_device *spi, 36 - enum mantisse mantisse, 37 - u8 exponent); 38 - int rf69_set_ook_threshold_dec(struct spi_device *spi, 39 - enum threshold_decrement threshold_decrement); 40 - int rf69_set_dio_mapping(struct spi_device *spi, u8 dio_number, u8 value); 41 - int rf69_set_rssi_threshold(struct spi_device *spi, u8 threshold); 42 - int rf69_set_preamble_length(struct spi_device *spi, u16 preamble_length); 43 - int rf69_enable_sync(struct spi_device *spi); 44 - int rf69_disable_sync(struct spi_device *spi); 45 - int rf69_set_fifo_fill_condition(struct spi_device *spi, 46 - enum fifo_fill_condition fifo_fill_condition); 47 - int rf69_set_sync_size(struct spi_device *spi, u8 sync_size); 48 - int rf69_set_sync_values(struct spi_device *spi, u8 sync_values[8]); 49 - int rf69_set_packet_format(struct spi_device *spi, 50 - enum packet_format packet_format); 51 - int rf69_enable_crc(struct spi_device *spi); 52 - int rf69_disable_crc(struct spi_device *spi); 53 - int rf69_set_address_filtering(struct spi_device *spi, 54 - enum address_filtering address_filtering); 55 - int rf69_set_payload_length(struct spi_device *spi, u8 payload_length); 56 - int rf69_set_node_address(struct spi_device *spi, u8 node_address); 57 - int rf69_set_broadcast_address(struct spi_device *spi, u8 broadcast_address); 58 - int rf69_set_tx_start_condition(struct spi_device *spi, 59 - enum tx_start_condition tx_start_condition); 60 - int rf69_set_fifo_threshold(struct spi_device *spi, u8 threshold); 61 - int rf69_set_dagc(struct spi_device *spi, enum dagc dagc); 62 - 63 - int rf69_read_fifo(struct spi_device *spi, u8 *buffer, unsigned int size); 64 - int rf69_write_fifo(struct spi_device *spi, u8 *buffer, unsigned int size); 65 - 66 - #endif
-126
drivers/staging/pi433/rf69_enum.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * enumerations for HopeRf rf69 radio module 4 - * 5 - * Copyright (C) 2016 Wolf-Entwicklungen 6 - * Marcus Wolf <linux@wolf-entwicklungen.de> 7 - */ 8 - 9 - #ifndef RF69_ENUM_H 10 - #define RF69_ENUM_H 11 - 12 - enum mode { 13 - mode_sleep, 14 - standby, 15 - synthesizer, 16 - transmit, 17 - receive 18 - }; 19 - 20 - enum modulation { 21 - OOK, 22 - FSK, 23 - UNDEF 24 - }; 25 - 26 - enum mod_shaping { 27 - SHAPING_OFF, 28 - SHAPING_1_0, 29 - SHAPING_0_5, 30 - SHAPING_0_3, 31 - SHAPING_BR, 32 - SHAPING_2BR 33 - }; 34 - 35 - enum pa_ramp { 36 - ramp3400, 37 - ramp2000, 38 - ramp1000, 39 - ramp500, 40 - ramp250, 41 - ramp125, 42 - ramp100, 43 - ramp62, 44 - ramp50, 45 - ramp40, 46 - ramp31, 47 - ramp25, 48 - ramp20, 49 - ramp15, 50 - ramp12, 51 - ramp10 52 - }; 53 - 54 - enum antenna_impedance { 55 - fifty_ohm, 56 - two_hundred_ohm 57 - }; 58 - 59 - enum lna_gain { 60 - automatic, 61 - max, 62 - max_minus_6, 63 - max_minus_12, 64 - max_minus_24, 65 - max_minus_36, 66 - max_minus_48, 67 - undefined 68 - }; 69 - 70 - enum mantisse { 71 - mantisse16, 72 - mantisse20, 73 - mantisse24 74 - }; 75 - 76 - enum threshold_decrement { 77 - dec_every8th, 78 - dec_every4th, 79 - dec_every2nd, 80 - dec_once, 81 - dec_twice, 82 - dec_4times, 83 - dec_8times, 84 - dec_16times 85 - }; 86 - 87 - enum fifo_fill_condition { 88 - after_sync_interrupt, 89 - always 90 - }; 91 - 92 - enum packet_format { 93 - /* 94 - * Used when the size of payload is fixed in advance. This mode of 95 - * operation may be of interest to minimize RF overhead by 1 byte as 96 - * no length byte field is required 97 - */ 98 - packet_length_fix, 99 - /* 100 - * Used when the size of payload isn't known in advance. It requires the 101 - * transmitter to send the length byte in each packet so the receiver 102 - * would know how to operate properly 103 - */ 104 - packet_length_var 105 - }; 106 - 107 - enum tx_start_condition { 108 - /* the number of bytes in the FIFO exceeds FIFO_THRESHOLD */ 109 - fifo_level, 110 - /* at least one byte in the FIFO */ 111 - fifo_not_empty 112 - }; 113 - 114 - enum address_filtering { 115 - filtering_off, 116 - node_address, 117 - node_or_broadcast_address 118 - }; 119 - 120 - enum dagc { 121 - normal_mode, 122 - improve, 123 - improve_for_low_modulation_index 124 - }; 125 - 126 - #endif
-478
drivers/staging/pi433/rf69_registers.h
··· 1 - /* SPDX-License-Identifier: GPL-2.0+ */ 2 - /* 3 - * register description for HopeRf rf69 radio module 4 - * 5 - * Copyright (C) 2016 Wolf-Entwicklungen 6 - * Marcus Wolf <linux@wolf-entwicklungen.de> 7 - */ 8 - 9 - /*******************************************/ 10 - /* RF69 register addresses */ 11 - /*******************************************/ 12 - #define REG_FIFO 0x00 13 - #define REG_OPMODE 0x01 14 - #define REG_DATAMODUL 0x02 15 - #define REG_BITRATE_MSB 0x03 16 - #define REG_BITRATE_LSB 0x04 17 - #define REG_FDEV_MSB 0x05 18 - #define REG_FDEV_LSB 0x06 19 - #define REG_FRF_MSB 0x07 20 - #define REG_FRF_MID 0x08 21 - #define REG_FRF_LSB 0x09 22 - #define REG_OSC1 0x0A 23 - #define REG_AFCCTRL 0x0B 24 - #define REG_LOWBAT 0x0C 25 - #define REG_LISTEN1 0x0D 26 - #define REG_LISTEN2 0x0E 27 - #define REG_LISTEN3 0x0F 28 - #define REG_VERSION 0x10 29 - #define REG_PALEVEL 0x11 30 - #define REG_PARAMP 0x12 31 - #define REG_OCP 0x13 32 - #define REG_AGCREF 0x14 /* not available on RF69 */ 33 - #define REG_AGCTHRESH1 0x15 /* not available on RF69 */ 34 - #define REG_AGCTHRESH2 0x16 /* not available on RF69 */ 35 - #define REG_AGCTHRESH3 0x17 /* not available on RF69 */ 36 - #define REG_LNA 0x18 37 - #define REG_RXBW 0x19 38 - #define REG_AFCBW 0x1A 39 - #define REG_OOKPEAK 0x1B 40 - #define REG_OOKAVG 0x1C 41 - #define REG_OOKFIX 0x1D 42 - #define REG_AFCFEI 0x1E 43 - #define REG_AFCMSB 0x1F 44 - #define REG_AFCLSB 0x20 45 - #define REG_FEIMSB 0x21 46 - #define REG_FEILSB 0x22 47 - #define REG_RSSICONFIG 0x23 48 - #define REG_RSSIVALUE 0x24 49 - #define REG_DIOMAPPING1 0x25 50 - #define REG_DIOMAPPING2 0x26 51 - #define REG_IRQFLAGS1 0x27 52 - #define REG_IRQFLAGS2 0x28 53 - #define REG_RSSITHRESH 0x29 54 - #define REG_RXTIMEOUT1 0x2A 55 - #define REG_RXTIMEOUT2 0x2B 56 - #define REG_PREAMBLE_MSB 0x2C 57 - #define REG_PREAMBLE_LSB 0x2D 58 - #define REG_SYNC_CONFIG 0x2E 59 - #define REG_SYNCVALUE1 0x2F 60 - #define REG_SYNCVALUE2 0x30 61 - #define REG_SYNCVALUE3 0x31 62 - #define REG_SYNCVALUE4 0x32 63 - #define REG_SYNCVALUE5 0x33 64 - #define REG_SYNCVALUE6 0x34 65 - #define REG_SYNCVALUE7 0x35 66 - #define REG_SYNCVALUE8 0x36 67 - #define REG_PACKETCONFIG1 0x37 68 - #define REG_PAYLOAD_LENGTH 0x38 69 - #define REG_NODEADRS 0x39 70 - #define REG_BROADCASTADRS 0x3A 71 - #define REG_AUTOMODES 0x3B 72 - #define REG_FIFO_THRESH 0x3C 73 - #define REG_PACKETCONFIG2 0x3D 74 - #define REG_AESKEY1 0x3E 75 - #define REG_AESKEY2 0x3F 76 - #define REG_AESKEY3 0x40 77 - #define REG_AESKEY4 0x41 78 - #define REG_AESKEY5 0x42 79 - #define REG_AESKEY6 0x43 80 - #define REG_AESKEY7 0x44 81 - #define REG_AESKEY8 0x45 82 - #define REG_AESKEY9 0x46 83 - #define REG_AESKEY10 0x47 84 - #define REG_AESKEY11 0x48 85 - #define REG_AESKEY12 0x49 86 - #define REG_AESKEY13 0x4A 87 - #define REG_AESKEY14 0x4B 88 - #define REG_AESKEY15 0x4C 89 - #define REG_AESKEY16 0x4D 90 - #define REG_TEMP1 0x4E 91 - #define REG_TEMP2 0x4F 92 - #define REG_TESTLNA 0x58 93 - #define REG_TESTPA1 0x5A /* only present on RFM69HW */ 94 - #define REG_TESTPA2 0x5C /* only present on RFM69HW */ 95 - #define REG_TESTDAGC 0x6F 96 - #define REG_TESTAFC 0x71 97 - 98 - /******************************************************/ 99 - /* RF69/SX1231 bit definition */ 100 - /******************************************************/ 101 - /* write bit */ 102 - #define WRITE_BIT 0x80 103 - 104 - /* RegOpMode */ 105 - #define MASK_OPMODE_SEQUENCER_OFF 0x80 106 - #define MASK_OPMODE_LISTEN_ON 0x40 107 - #define MASK_OPMODE_LISTEN_ABORT 0x20 108 - #define MASK_OPMODE_MODE 0x1C 109 - 110 - #define OPMODE_MODE_SLEEP 0x00 111 - #define OPMODE_MODE_STANDBY 0x04 /* default */ 112 - #define OPMODE_MODE_SYNTHESIZER 0x08 113 - #define OPMODE_MODE_TRANSMIT 0x0C 114 - #define OPMODE_MODE_RECEIVE 0x10 115 - 116 - /* RegDataModul */ 117 - #define MASK_DATAMODUL_MODE 0x06 118 - #define MASK_DATAMODUL_MODULATION_TYPE 0x18 119 - #define MASK_DATAMODUL_MODULATION_SHAPE 0x03 120 - 121 - #define DATAMODUL_MODE_PACKET 0x00 /* default */ 122 - #define DATAMODUL_MODE_CONTINUOUS 0x40 123 - #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60 124 - 125 - #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */ 126 - #define DATAMODUL_MODULATION_TYPE_OOK 0x08 127 - 128 - #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */ 129 - #define DATAMODUL_MODULATION_SHAPE_1_0 0x01 130 - #define DATAMODUL_MODULATION_SHAPE_0_5 0x02 131 - #define DATAMODUL_MODULATION_SHAPE_0_3 0x03 132 - #define DATAMODUL_MODULATION_SHAPE_BR 0x01 133 - #define DATAMODUL_MODULATION_SHAPE_2BR 0x02 134 - 135 - /* RegFDevMsb (0x05)*/ 136 - #define FDEVMASB_MASK 0x3f 137 - 138 - /* 139 - * // RegOsc1 140 - * #define OSC1_RCCAL_START 0x80 141 - * #define OSC1_RCCAL_DONE 0x40 142 - * 143 - * // RegLowBat 144 - * #define LOWBAT_MONITOR 0x10 145 - * #define LOWBAT_ON 0x08 146 - * #define LOWBAT_OFF 0x00 // Default 147 - * 148 - * #define LOWBAT_TRIM_1695 0x00 149 - * #define LOWBAT_TRIM_1764 0x01 150 - * #define LOWBAT_TRIM_1835 0x02 // Default 151 - * #define LOWBAT_TRIM_1905 0x03 152 - * #define LOWBAT_TRIM_1976 0x04 153 - * #define LOWBAT_TRIM_2045 0x05 154 - * #define LOWBAT_TRIM_2116 0x06 155 - * #define LOWBAT_TRIM_2185 0x07 156 - * 157 - * 158 - * // RegListen1 159 - * #define LISTEN1_RESOL_64 0x50 160 - * #define LISTEN1_RESOL_4100 0xA0 // Default 161 - * #define LISTEN1_RESOL_262000 0xF0 162 - * 163 - * #define LISTEN1_CRITERIA_RSSI 0x00 // Default 164 - * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08 165 - * 166 - * #define LISTEN1_END_00 0x00 167 - * #define LISTEN1_END_01 0x02 // Default 168 - * #define LISTEN1_END_10 0x04 169 - * 170 - * 171 - * // RegListen2 172 - * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default 173 - * 174 - * // RegListen3 175 - * #define LISTEN3_COEFRX_VALUE 0x20 // Default 176 - */ 177 - 178 - // RegPaLevel 179 - #define MASK_PALEVEL_PA0 0x80 180 - #define MASK_PALEVEL_PA1 0x40 181 - #define MASK_PALEVEL_PA2 0x20 182 - #define MASK_PALEVEL_OUTPUT_POWER 0x1F 183 - 184 - // RegPaRamp 185 - #define PARAMP_3400 0x00 186 - #define PARAMP_2000 0x01 187 - #define PARAMP_1000 0x02 188 - #define PARAMP_500 0x03 189 - #define PARAMP_250 0x04 190 - #define PARAMP_125 0x05 191 - #define PARAMP_100 0x06 192 - #define PARAMP_62 0x07 193 - #define PARAMP_50 0x08 194 - #define PARAMP_40 0x09 /* default */ 195 - #define PARAMP_31 0x0A 196 - #define PARAMP_25 0x0B 197 - #define PARAMP_20 0x0C 198 - #define PARAMP_15 0x0D 199 - #define PARAMP_12 0x0E 200 - #define PARAMP_10 0x0F 201 - 202 - #define MASK_PARAMP 0x0F 203 - 204 - /* 205 - * // RegOcp 206 - * #define OCP_OFF 0x0F 207 - * #define OCP_ON 0x1A // Default 208 - * 209 - * #define OCP_TRIM_45 0x00 210 - * #define OCP_TRIM_50 0x01 211 - * #define OCP_TRIM_55 0x02 212 - * #define OCP_TRIM_60 0x03 213 - * #define OCP_TRIM_65 0x04 214 - * #define OCP_TRIM_70 0x05 215 - * #define OCP_TRIM_75 0x06 216 - * #define OCP_TRIM_80 0x07 217 - * #define OCP_TRIM_85 0x08 218 - * #define OCP_TRIM_90 0x09 219 - * #define OCP_TRIM_95 0x0A 220 - * #define OCP_TRIM_100 0x0B // Default 221 - * #define OCP_TRIM_105 0x0C 222 - * #define OCP_TRIM_110 0x0D 223 - * #define OCP_TRIM_115 0x0E 224 - * #define OCP_TRIM_120 0x0F 225 - */ 226 - 227 - /* RegLna (0x18) */ 228 - #define MASK_LNA_ZIN 0x80 229 - #define MASK_LNA_CURRENT_GAIN 0x38 230 - #define MASK_LNA_GAIN 0x07 231 - 232 - #define LNA_GAIN_AUTO 0x00 /* default */ 233 - #define LNA_GAIN_MAX 0x01 234 - #define LNA_GAIN_MAX_MINUS_6 0x02 235 - #define LNA_GAIN_MAX_MINUS_12 0x03 236 - #define LNA_GAIN_MAX_MINUS_24 0x04 237 - #define LNA_GAIN_MAX_MINUS_36 0x05 238 - #define LNA_GAIN_MAX_MINUS_48 0x06 239 - 240 - /* RegRxBw (0x19) and RegAfcBw (0x1A) */ 241 - #define MASK_BW_DCC_FREQ 0xE0 242 - #define MASK_BW_MANTISSE 0x18 243 - #define MASK_BW_EXPONENT 0x07 244 - 245 - #define BW_DCC_16_PERCENT 0x00 246 - #define BW_DCC_8_PERCENT 0x20 247 - #define BW_DCC_4_PERCENT 0x40 /* default */ 248 - #define BW_DCC_2_PERCENT 0x60 249 - #define BW_DCC_1_PERCENT 0x80 250 - #define BW_DCC_0_5_PERCENT 0xA0 251 - #define BW_DCC_0_25_PERCENT 0xC0 252 - #define BW_DCC_0_125_PERCENT 0xE0 253 - 254 - #define BW_MANT_16 0x00 255 - #define BW_MANT_20 0x08 256 - #define BW_MANT_24 0x10 /* default */ 257 - 258 - /* RegOokPeak (0x1B) */ 259 - #define MASK_OOKPEAK_THRESTYPE 0xc0 260 - #define MASK_OOKPEAK_THRESSTEP 0x38 261 - #define MASK_OOKPEAK_THRESDEC 0x07 262 - 263 - #define OOKPEAK_THRESHTYPE_FIXED 0x00 264 - #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */ 265 - #define OOKPEAK_THRESHTYPE_AVERAGE 0x80 266 - 267 - #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */ 268 - #define OOKPEAK_THRESHSTEP_1_0_DB 0x08 269 - #define OOKPEAK_THRESHSTEP_1_5_DB 0x10 270 - #define OOKPEAK_THRESHSTEP_2_0_DB 0x18 271 - #define OOKPEAK_THRESHSTEP_3_0_DB 0x20 272 - #define OOKPEAK_THRESHSTEP_4_0_DB 0x28 273 - #define OOKPEAK_THRESHSTEP_5_0_DB 0x30 274 - #define OOKPEAK_THRESHSTEP_6_0_DB 0x38 275 - 276 - #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */ 277 - #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01 278 - #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02 279 - #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03 280 - #define OOKPEAK_THRESHDEC_TWICE 0x04 281 - #define OOKPEAK_THRESHDEC_4_TIMES 0x05 282 - #define OOKPEAK_THRESHDEC_8_TIMES 0x06 283 - #define OOKPEAK_THRESHDEC_16_TIMES 0x07 284 - 285 - /* 286 - * // RegOokAvg 287 - * #define OOKAVG_AVERAGETHRESHFILT_00 0x00 288 - * #define OOKAVG_AVERAGETHRESHFILT_01 0x40 289 - * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default 290 - * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0 291 - * 292 - * 293 - * // RegAfcFei 294 - * #define AFCFEI_FEI_DONE 0x40 295 - * #define AFCFEI_FEI_START 0x20 296 - * #define AFCFEI_AFC_DONE 0x10 297 - * #define AFCFEI_AFCAUTOCLEAR_ON 0x08 298 - * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default 299 - * 300 - * #define AFCFEI_AFCAUTO_ON 0x04 301 - * #define AFCFEI_AFCAUTO_OFF 0x00 // Default 302 - * 303 - * #define AFCFEI_AFC_CLEAR 0x02 304 - * #define AFCFEI_AFC_START 0x01 305 - * 306 - * // RegRssiConfig 307 - * #define RSSI_FASTRX_ON 0x08 308 - * #define RSSI_FASTRX_OFF 0x00 // Default 309 - * #define RSSI_DONE 0x02 310 - * #define RSSI_START 0x01 311 - */ 312 - 313 - /* RegDioMapping1 */ 314 - #define MASK_DIO0 0xC0 315 - #define MASK_DIO1 0x30 316 - #define MASK_DIO2 0x0C 317 - #define MASK_DIO3 0x03 318 - #define SHIFT_DIO0 6 319 - #define SHIFT_DIO1 4 320 - #define SHIFT_DIO2 2 321 - #define SHIFT_DIO3 0 322 - 323 - /* RegDioMapping2 */ 324 - #define MASK_DIO4 0xC0 325 - #define MASK_DIO5 0x30 326 - #define SHIFT_DIO4 6 327 - #define SHIFT_DIO5 4 328 - 329 - /* DIO numbers */ 330 - #define DIO0 0 331 - #define DIO1 1 332 - #define DIO2 2 333 - #define DIO3 3 334 - #define DIO4 4 335 - #define DIO5 5 336 - 337 - /* DIO Mapping values (packet mode) */ 338 - #define DIO_MODE_READY_DIO4 0x00 339 - #define DIO_MODE_READY_DIO5 0x03 340 - #define DIO_CLK_OUT 0x00 341 - #define DIO_DATA 0x01 342 - #define DIO_TIMEOUT_DIO1 0x03 343 - #define DIO_TIMEOUT_DIO4 0x00 344 - #define DIO_RSSI_DIO0 0x03 345 - #define DIO_RSSI_DIO3_4 0x01 346 - #define DIO_RX_READY 0x02 347 - #define DIO_PLL_LOCK 0x03 348 - #define DIO_TX_READY 0x01 349 - #define DIO_FIFO_FULL_DIO1 0x01 350 - #define DIO_FIFO_FULL_DIO3 0x00 351 - #define DIO_SYNC_ADDRESS 0x02 352 - #define DIO_FIFO_NOT_EMPTY_DIO1 0x02 353 - #define DIO_FIFO_NOT_EMPTY_FIO2 0x00 354 - #define DIO_AUTOMODE 0x04 355 - #define DIO_FIFO_LEVEL 0x00 356 - #define DIO_CRC_OK 0x00 357 - #define DIO_PAYLOAD_READY 0x01 358 - #define DIO_PACKET_SENT 0x00 359 - #define DIO_DCLK 0x00 360 - 361 - /* RegDioMapping2 CLK_OUT part */ 362 - #define MASK_DIOMAPPING2_CLK_OUT 0x07 363 - 364 - #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00 365 - #define DIOMAPPING2_CLK_OUT_DIV_2 0x01 366 - #define DIOMAPPING2_CLK_OUT_DIV_4 0x02 367 - #define DIOMAPPING2_CLK_OUT_DIV_8 0x03 368 - #define DIOMAPPING2_CLK_OUT_DIV_16 0x04 369 - #define DIOMAPPING2_CLK_OUT_DIV_32 0x05 370 - #define DIOMAPPING2_CLK_OUT_RC 0x06 371 - #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */ 372 - 373 - /* RegIrqFlags1 */ 374 - #define MASK_IRQFLAGS1_MODE_READY 0x80 375 - #define MASK_IRQFLAGS1_RX_READY 0x40 376 - #define MASK_IRQFLAGS1_TX_READY 0x20 377 - #define MASK_IRQFLAGS1_PLL_LOCK 0x10 378 - #define MASK_IRQFLAGS1_RSSI 0x08 379 - #define MASK_IRQFLAGS1_TIMEOUT 0x04 380 - #define MASK_IRQFLAGS1_AUTOMODE 0x02 381 - #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01 382 - 383 - /* RegIrqFlags2 */ 384 - #define MASK_IRQFLAGS2_FIFO_FULL 0x80 385 - #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40 386 - #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20 387 - #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10 388 - #define MASK_IRQFLAGS2_PACKET_SENT 0x08 389 - #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04 390 - #define MASK_IRQFLAGS2_CRC_OK 0x02 391 - #define MASK_IRQFLAGS2_LOW_BAT 0x01 392 - 393 - /* RegSyncConfig */ 394 - #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */ 395 - #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40 396 - #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38 397 - #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07 398 - 399 - /* RegPacketConfig1 */ 400 - #define MASK_PACKETCONFIG1_PACKET_FORMAT_VARIABLE 0x80 401 - #define MASK_PACKETCONFIG1_DCFREE 0x60 402 - #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */ 403 - #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08 404 - #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06 405 - 406 - #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */ 407 - #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20 408 - #define PACKETCONFIG1_DCFREE_WHITENING 0x40 409 - #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */ 410 - #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02 411 - #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04 412 - 413 - /* 414 - * // RegAutoModes 415 - * #define AUTOMODES_ENTER_OFF 0x00 // Default 416 - * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20 417 - * #define AUTOMODES_ENTER_FIFOLEVEL 0x40 418 - * #define AUTOMODES_ENTER_CRCOK 0x60 419 - * #define AUTOMODES_ENTER_PAYLOADREADY 0x80 420 - * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0 421 - * #define AUTOMODES_ENTER_PACKETSENT 0xC0 422 - * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0 423 - * 424 - * #define AUTOMODES_EXIT_OFF 0x00 // Default 425 - * #define AUTOMODES_EXIT_FIFOEMPTY 0x04 426 - * #define AUTOMODES_EXIT_FIFOLEVEL 0x08 427 - * #define AUTOMODES_EXIT_CRCOK 0x0C 428 - * #define AUTOMODES_EXIT_PAYLOADREADY 0x10 429 - * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14 430 - * #define AUTOMODES_EXIT_PACKETSENT 0x18 431 - * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C 432 - * 433 - * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default 434 - * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01 435 - * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02 436 - * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03 437 - * 438 - */ 439 - /* RegFifoThresh (0x3c) */ 440 - #define MASK_FIFO_THRESH_TXSTART 0x80 441 - #define MASK_FIFO_THRESH_VALUE 0x7F 442 - 443 - /* 444 - * 445 - * // RegPacketConfig2 446 - * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default 447 - * #define PACKET2_RXRESTARTDELAY_2BITS 0x10 448 - * #define PACKET2_RXRESTARTDELAY_4BITS 0x20 449 - * #define PACKET2_RXRESTARTDELAY_8BITS 0x30 450 - * #define PACKET2_RXRESTARTDELAY_16BITS 0x40 451 - * #define PACKET2_RXRESTARTDELAY_32BITS 0x50 452 - * #define PACKET2_RXRESTARTDELAY_64BITS 0x60 453 - * #define PACKET2_RXRESTARTDELAY_128BITS 0x70 454 - * #define PACKET2_RXRESTARTDELAY_256BITS 0x80 455 - * #define PACKET2_RXRESTARTDELAY_512BITS 0x90 456 - * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0 457 - * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0 458 - * #define PACKET2_RXRESTARTDELAY_NONE 0xC0 459 - * #define PACKET2_RXRESTART 0x04 460 - * 461 - * #define PACKET2_AUTORXRESTART_ON 0x02 // Default 462 - * #define PACKET2_AUTORXRESTART_OFF 0x00 463 - * 464 - * #define PACKET2_AES_ON 0x01 465 - * #define PACKET2_AES_OFF 0x00 // Default 466 - * 467 - * 468 - * // RegTemp1 469 - * #define TEMP1_MEAS_START 0x08 470 - * #define TEMP1_MEAS_RUNNING 0x04 471 - * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default 472 - * #define TEMP1_ADCLOWPOWER_OFF 0x00 473 - */ 474 - 475 - // RegTestDagc (0x6F) 476 - #define DAGC_NORMAL 0x00 /* Reset value */ 477 - #define DAGC_IMPROVED_LOWBETA1 0x20 478 - #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */