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i2c: i801: add helper i801_set_hstadd()

Factor out setting SMBHSTADD to a helper. The current code makes the
assumption that constant I2C_SMBUS_READ has bit 0 set, that's not ideal.
Therefore let the new helper explicitly check for I2C_SMBUS_READ.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Jean Delvare <jdelvare@suse.de>
Signed-off-by: Wolfram Sang <wsa@kernel.org>

authored by

Heiner Kallweit and committed by
Wolfram Sang eb4d8bac e98a3bc0

+16 -20
+16 -20
drivers/i2c/busses/i2c-i801.c
··· 727 727 return i801_check_post(priv, status); 728 728 } 729 729 730 + static void i801_set_hstadd(struct i801_priv *priv, u8 addr, char read_write) 731 + { 732 + outb_p((addr << 1) | (read_write & 0x01), SMBHSTADD(priv)); 733 + } 734 + 730 735 /* Block transaction function */ 731 736 static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data, 732 737 char read_write, int command) ··· 802 797 803 798 switch (size) { 804 799 case I2C_SMBUS_QUICK: 805 - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 806 - SMBHSTADD(priv)); 800 + i801_set_hstadd(priv, addr, read_write); 807 801 xact = I801_QUICK; 808 802 break; 809 803 case I2C_SMBUS_BYTE: 810 - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 811 - SMBHSTADD(priv)); 804 + i801_set_hstadd(priv, addr, read_write); 812 805 if (read_write == I2C_SMBUS_WRITE) 813 806 outb_p(command, SMBHSTCMD(priv)); 814 807 xact = I801_BYTE; 815 808 break; 816 809 case I2C_SMBUS_BYTE_DATA: 817 - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 818 - SMBHSTADD(priv)); 810 + i801_set_hstadd(priv, addr, read_write); 819 811 outb_p(command, SMBHSTCMD(priv)); 820 812 if (read_write == I2C_SMBUS_WRITE) 821 813 outb_p(data->byte, SMBHSTDAT0(priv)); 822 814 xact = I801_BYTE_DATA; 823 815 break; 824 816 case I2C_SMBUS_WORD_DATA: 825 - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 826 - SMBHSTADD(priv)); 817 + i801_set_hstadd(priv, addr, read_write); 827 818 outb_p(command, SMBHSTCMD(priv)); 828 819 if (read_write == I2C_SMBUS_WRITE) { 829 820 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); ··· 828 827 xact = I801_WORD_DATA; 829 828 break; 830 829 case I2C_SMBUS_PROC_CALL: 831 - outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 830 + i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 832 831 outb_p(command, SMBHSTCMD(priv)); 833 832 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 834 833 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); ··· 836 835 read_write = I2C_SMBUS_READ; 837 836 break; 838 837 case I2C_SMBUS_BLOCK_DATA: 839 - outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 840 - SMBHSTADD(priv)); 838 + i801_set_hstadd(priv, addr, read_write); 841 839 outb_p(command, SMBHSTCMD(priv)); 842 840 block = 1; 843 841 break; ··· 847 847 * However if SPD Write Disable is set (Lynx Point and later), 848 848 * the read will fail if we don't set the R/#W bit. 849 849 */ 850 - outb_p(((addr & 0x7f) << 1) | 851 - ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 852 - (read_write & 0x01) : 0), 853 - SMBHSTADD(priv)); 850 + i801_set_hstadd(priv, addr, 851 + priv->original_hstcfg & SMBHSTCFG_SPD_WD ? 852 + read_write : I2C_SMBUS_WRITE); 854 853 if (read_write == I2C_SMBUS_READ) { 855 854 /* NB: page 240 of ICH5 datasheet also shows 856 855 * that DATA1 is the cmd field when reading */ ··· 859 860 block = 1; 860 861 break; 861 862 case I2C_SMBUS_BLOCK_PROC_CALL: 862 - /* 863 - * Bit 0 of the slave address register always indicate a write 864 - * command. 865 - */ 866 - outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 863 + /* Needs to be flagged as write transaction */ 864 + i801_set_hstadd(priv, addr, I2C_SMBUS_WRITE); 867 865 outb_p(command, SMBHSTCMD(priv)); 868 866 block = 1; 869 867 break;