tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
ARM: dts: exynos: Add missing CPU frequencies for Exynos5422/5800
Add missing 2.0GHz, 1.9GHz & 1.8GHz OPPs (for A15 cores) and 1.4GHz
OPP (for A7 cores). Also update common Odroid-XU3 Lite/XU3/XU4
thermal cooling maps to account for new OPPs.
Since some new OPPs are not available on all Exynos5422/5800 boards
modify dts files for Odroid XU3 Lite (limited to 1.8 GHz / 1.3 GHz) &
Peach Pi (limited to 2.0 GHz / 1.3 GHz) accordingly.
This patch uses maximum voltages for new OPPs. This is a temporary
solution till proper Exynos ASV support is added.
Also while at it fix the number of cooling down steps for big cores
(should be 11 instead of 12 on Odroid XU3 Lite and 14 on XU3/XU4).
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
[mszyprow: rebased onto v5.5-rc1 and adapted to recent dts changes,
fixed removal of the 1.4GHz OPP for A7s on Peach-Pi]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
authored by
Bartlomiej Zolnierkiewicz
and committed by
Krzysztof Kozlowski
eaffc4de
6c43b5d3
+158
-71
+32
-32
arch/arm/boot/dts/exynos5422-odroidhc1.dts
+32
-32
arch/arm/boot/dts/exynos5422-odroidhc1.dts
···
72
72
*/
73
73
map1 {
74
74
trip = <&cpu0_alert1>;
75
-
cooling-device = <&cpu0 3 7>,
76
-
<&cpu1 3 7>,
77
-
<&cpu2 3 7>,
78
-
<&cpu3 3 7>,
79
-
<&cpu4 3 12>,
80
-
<&cpu5 3 12>,
81
-
<&cpu6 3 12>,
82
-
<&cpu7 3 12>;
75
+
cooling-device = <&cpu0 3 8>,
76
+
<&cpu1 3 8>,
77
+
<&cpu2 3 8>,
78
+
<&cpu3 3 8>,
79
+
<&cpu4 3 14>,
80
+
<&cpu5 3 14>,
81
+
<&cpu6 3 14>,
82
+
<&cpu7 3 14>;
83
83
};
84
84
};
85
85
};
···
116
116
};
117
117
map1 {
118
118
trip = <&cpu1_alert1>;
119
-
cooling-device = <&cpu0 3 7>,
120
-
<&cpu1 3 7>,
121
-
<&cpu2 3 7>,
122
-
<&cpu3 3 7>,
123
-
<&cpu4 3 12>,
124
-
<&cpu5 3 12>,
125
-
<&cpu6 3 12>,
126
-
<&cpu7 3 12>;
119
+
cooling-device = <&cpu0 3 8>,
120
+
<&cpu1 3 8>,
121
+
<&cpu2 3 8>,
122
+
<&cpu3 3 8>,
123
+
<&cpu4 3 14>,
124
+
<&cpu5 3 14>,
125
+
<&cpu6 3 14>,
126
+
<&cpu7 3 14>;
127
127
};
128
128
};
129
129
};
···
160
160
};
161
161
map1 {
162
162
trip = <&cpu2_alert1>;
163
-
cooling-device = <&cpu0 3 7>,
164
-
<&cpu1 3 7>,
165
-
<&cpu2 3 7>,
166
-
<&cpu3 3 7>,
167
-
<&cpu4 3 12>,
168
-
<&cpu5 3 12>,
169
-
<&cpu6 3 12>,
170
-
<&cpu7 3 12>;
163
+
cooling-device = <&cpu0 3 8>,
164
+
<&cpu1 3 8>,
165
+
<&cpu2 3 8>,
166
+
<&cpu3 3 8>,
167
+
<&cpu4 3 14>,
168
+
<&cpu5 3 14>,
169
+
<&cpu6 3 14>,
170
+
<&cpu7 3 14>;
171
171
};
172
172
};
173
173
};
···
204
204
};
205
205
map1 {
206
206
trip = <&cpu3_alert1>;
207
-
cooling-device = <&cpu0 3 7>,
208
-
<&cpu1 3 7>,
209
-
<&cpu2 3 7>,
210
-
<&cpu3 3 7>,
211
-
<&cpu4 3 12>,
212
-
<&cpu5 3 12>,
213
-
<&cpu6 3 12>,
214
-
<&cpu7 3 12>;
207
+
cooling-device = <&cpu0 3 8>,
208
+
<&cpu1 3 8>,
209
+
<&cpu2 3 8>,
210
+
<&cpu3 3 8>,
211
+
<&cpu4 3 14>,
212
+
<&cpu5 3 14>,
213
+
<&cpu6 3 14>,
214
+
<&cpu7 3 14>;
215
215
};
216
216
};
217
217
};
+39
-39
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+39
-39
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
···
107
107
/*
108
108
* When reaching cpu0_alert3, reduce CPU
109
109
* by 2 steps. On Exynos5422/5800 that would
110
-
* be: 1600 MHz and 1100 MHz.
110
+
* (usually) be: 1800 MHz and 1200 MHz.
111
111
*/
112
112
map3 {
113
113
trip = <&cpu0_alert3>;
···
122
122
};
123
123
/*
124
124
* When reaching cpu0_alert4, reduce CPU
125
-
* further, down to 600 MHz (12 steps for big,
126
-
* 7 steps for LITTLE).
125
+
* further, down to 600 MHz (14 steps for big,
126
+
* 8 steps for LITTLE).
127
127
*/
128
-
map4 {
128
+
cpu0_cooling_map4: map4 {
129
129
trip = <&cpu0_alert4>;
130
-
cooling-device = <&cpu0 3 7>,
131
-
<&cpu1 3 7>,
132
-
<&cpu2 3 7>,
133
-
<&cpu3 3 7>,
134
-
<&cpu4 3 12>,
135
-
<&cpu5 3 12>,
136
-
<&cpu6 3 12>,
137
-
<&cpu7 3 12>;
130
+
cooling-device = <&cpu0 3 8>,
131
+
<&cpu1 3 8>,
132
+
<&cpu2 3 8>,
133
+
<&cpu3 3 8>,
134
+
<&cpu4 3 14>,
135
+
<&cpu5 3 14>,
136
+
<&cpu6 3 14>,
137
+
<&cpu7 3 14>;
138
138
};
139
139
};
140
140
};
···
198
198
<&cpu6 0 2>,
199
199
<&cpu7 0 2>;
200
200
};
201
-
map4 {
201
+
cpu1_cooling_map4: map4 {
202
202
trip = <&cpu1_alert4>;
203
-
cooling-device = <&cpu0 3 7>,
204
-
<&cpu1 3 7>,
205
-
<&cpu2 3 7>,
206
-
<&cpu3 3 7>,
207
-
<&cpu4 3 12>,
208
-
<&cpu5 3 12>,
209
-
<&cpu6 3 12>,
210
-
<&cpu7 3 12>;
203
+
cooling-device = <&cpu0 3 8>,
204
+
<&cpu1 3 8>,
205
+
<&cpu2 3 8>,
206
+
<&cpu3 3 8>,
207
+
<&cpu4 3 14>,
208
+
<&cpu5 3 14>,
209
+
<&cpu6 3 14>,
210
+
<&cpu7 3 14>;
211
211
};
212
212
};
213
213
};
···
271
271
<&cpu6 0 2>,
272
272
<&cpu7 0 2>;
273
273
};
274
-
map4 {
274
+
cpu2_cooling_map4: map4 {
275
275
trip = <&cpu2_alert4>;
276
-
cooling-device = <&cpu0 3 7>,
277
-
<&cpu1 3 7>,
278
-
<&cpu2 3 7>,
279
-
<&cpu3 3 7>,
280
-
<&cpu4 3 12>,
281
-
<&cpu5 3 12>,
282
-
<&cpu6 3 12>,
283
-
<&cpu7 3 12>;
276
+
cooling-device = <&cpu0 3 8>,
277
+
<&cpu1 3 8>,
278
+
<&cpu2 3 8>,
279
+
<&cpu3 3 8>,
280
+
<&cpu4 3 14>,
281
+
<&cpu5 3 14>,
282
+
<&cpu6 3 14>,
283
+
<&cpu7 3 14>;
284
284
};
285
285
};
286
286
};
···
344
344
<&cpu6 0 2>,
345
345
<&cpu7 0 2>;
346
346
};
347
-
map4 {
347
+
cpu3_cooling_map4: map4 {
348
348
trip = <&cpu3_alert4>;
349
-
cooling-device = <&cpu0 3 7>,
350
-
<&cpu1 3 7>,
351
-
<&cpu2 3 7>,
352
-
<&cpu3 3 7>,
353
-
<&cpu4 3 12>,
354
-
<&cpu5 3 12>,
355
-
<&cpu6 3 12>,
356
-
<&cpu7 3 12>;
349
+
cooling-device = <&cpu0 3 8>,
350
+
<&cpu1 3 8>,
351
+
<&cpu2 3 8>,
352
+
<&cpu3 3 8>,
353
+
<&cpu4 3 14>,
354
+
<&cpu5 3 14>,
355
+
<&cpu6 3 14>,
356
+
<&cpu7 3 14>;
357
357
};
358
358
};
359
359
};
+58
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+58
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
···
30
30
samsung,asv-bin = <2>;
31
31
};
32
32
33
+
/*
34
+
* Odroid XU3-Lite board uses SoC revision with lower maximum frequencies
35
+
* than Odroid XU3/XU4 boards: 1.8 GHz for A15 cores & 1.3 GHz for A7 cores.
36
+
* Therefore we need to update OPPs tables and thermal maps accordingly.
37
+
*/
38
+
&cluster_a15_opp_table {
39
+
/delete-node/opp-2000000000;
40
+
/delete-node/opp-1900000000;
41
+
};
42
+
43
+
&cluster_a7_opp_table {
44
+
/delete-node/opp-1400000000;
45
+
};
46
+
47
+
&cpu0_cooling_map4 {
48
+
cooling-device = <&cpu0 3 7>,
49
+
<&cpu1 3 7>,
50
+
<&cpu2 3 7>,
51
+
<&cpu3 3 7>,
52
+
<&cpu4 3 12>,
53
+
<&cpu5 3 12>,
54
+
<&cpu6 3 12>,
55
+
<&cpu7 3 12>;
56
+
};
57
+
58
+
&cpu1_cooling_map4 {
59
+
cooling-device = <&cpu0 3 7>,
60
+
<&cpu1 3 7>,
61
+
<&cpu2 3 7>,
62
+
<&cpu3 3 7>,
63
+
<&cpu4 3 12>,
64
+
<&cpu5 3 12>,
65
+
<&cpu6 3 12>,
66
+
<&cpu7 3 12>;
67
+
};
68
+
69
+
&cpu2_cooling_map4 {
70
+
cooling-device = <&cpu0 3 7>,
71
+
<&cpu1 3 7>,
72
+
<&cpu2 3 7>,
73
+
<&cpu3 3 7>,
74
+
<&cpu4 3 12>,
75
+
<&cpu5 3 12>,
76
+
<&cpu6 3 12>,
77
+
<&cpu7 3 12>;
78
+
};
79
+
80
+
&cpu3_cooling_map4 {
81
+
cooling-device = <&cpu0 3 7>,
82
+
<&cpu1 3 7>,
83
+
<&cpu2 3 7>,
84
+
<&cpu3 3 7>,
85
+
<&cpu4 3 12>,
86
+
<&cpu5 3 12>,
87
+
<&cpu6 3 12>,
88
+
<&cpu7 3 12>;
89
+
};
90
+
33
91
&pwm {
34
92
/*
35
93
* PWM 0 -- fan
+9
arch/arm/boot/dts/exynos5800-peach-pi.dts
+9
arch/arm/boot/dts/exynos5800-peach-pi.dts
···
156
156
assigned-clock-parents = <&clock CLK_MAU_EPLL>;
157
157
};
158
158
159
+
/*
160
+
* Peach Pi board uses SoC revision with lower maximum frequency for A7 cores
161
+
* (1.3 GHz instead of 1.4 GHz) than Odroid XU3/XU4 boards. Thus we need to
162
+
* update A7 OPPs table accordingly.
163
+
*/
164
+
&cluster_a7_opp_table {
165
+
/delete-node/opp-1400000000;
166
+
};
167
+
159
168
&cpu0 {
160
169
cpu-supply = <&buck2_reg>;
161
170
};
+20
arch/arm/boot/dts/exynos5800.dtsi
+20
arch/arm/boot/dts/exynos5800.dtsi
···
21
21
};
22
22
23
23
&cluster_a15_opp_table {
24
+
opp-2000000000 {
25
+
opp-hz = /bits/ 64 <2000000000>;
26
+
opp-microvolt = <1312500>;
27
+
clock-latency-ns = <140000>;
28
+
};
29
+
opp-1900000000 {
30
+
opp-hz = /bits/ 64 <1900000000>;
31
+
opp-microvolt = <1262500>;
32
+
clock-latency-ns = <140000>;
33
+
};
34
+
opp-1800000000 {
35
+
opp-hz = /bits/ 64 <1800000000>;
36
+
opp-microvolt = <1237500>;
37
+
clock-latency-ns = <140000>;
38
+
};
24
39
opp-1700000000 {
25
40
opp-microvolt = <1250000 1250000 1500000>;
26
41
};
···
97
82
};
98
83
99
84
&cluster_a7_opp_table {
85
+
opp-1400000000 {
86
+
opp-hz = /bits/ 64 <1400000000>;
87
+
opp-microvolt = <1275000>;
88
+
clock-latency-ns = <140000>;
89
+
};
100
90
opp-1300000000 {
101
91
opp-microvolt = <1250000>;
102
92
};