Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6:
sh: Titan defconfig update.
sh: Fix IPR-IRQ's for IRQ-chip change breakage.
sh: Update r7780rp_defconfig.
video: Fix include in hp680_bl.
sh: Wire up new syscalls.

+517 -410
+8 -4
arch/sh/boards/renesas/hs7751rvoip/setup.c
··· 15 15 #include <asm/io.h> 16 16 #include <asm/machvec.h> 17 17 18 + static struct ipr_data hs77501rvoip_ipr_map[] = { 19 + #if defined(CONFIG_HS7751RVOIP_CODEC) 20 + { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 21 + { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 22 + #endif 23 + }; 24 + 18 25 static void __init hs7751rvoip_init_irq(void) 19 26 { 20 - #if defined(CONFIG_HS7751RVOIP_CODEC) 21 - make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 22 - make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 23 - #endif 27 + make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map)); 24 28 25 29 init_hs7751rvoip_IRQ(); 26 30 }
+46 -59
arch/sh/boards/renesas/sh7710voipgw/setup.c
··· 13 13 #include <asm/io.h> 14 14 #include <asm/irq.h> 15 15 16 + static struct ipr_data sh7710voipgw_ipr_map[] = { 17 + { TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY }, 18 + { WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY }, 19 + 20 + /* SCIF0 */ 21 + { SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 22 + { SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 23 + { SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 24 + { SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 25 + 26 + /* DMAC-1 */ 27 + { DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 28 + { DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 29 + { DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 30 + { DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 31 + 32 + /* DMAC-2 */ 33 + { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, 34 + { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, 35 + 36 + /* IPSEC */ 37 + { IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY }, 38 + 39 + /* EDMAC */ 40 + { EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, EDMAC0_PRIORITY }, 41 + { EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, EDMAC1_PRIORITY }, 42 + { EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, EDMAC2_PRIORITY }, 43 + 44 + /* SIOF0 */ 45 + { SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 46 + { SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 47 + { SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 48 + { SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 49 + 50 + /* SIOF1 */ 51 + { SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, 52 + { SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, 53 + { SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, 54 + { SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY }, 55 + 56 + /* SLIC IRQ's */ 57 + { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, 58 + { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, 59 + }; 60 + 16 61 /* 17 62 * Initialize IRQ setting 18 63 */ ··· 82 37 */ 83 38 ctrl_outw(0x2aa, INTC_ICR1); 84 39 85 - /* Now make IPR interrupts */ 86 - make_ipr_irq(TIMER2_IRQ, TIMER2_IPR_ADDR, 87 - TIMER2_IPR_POS, TIMER2_PRIORITY); 88 - make_ipr_irq(WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY); 89 - 90 - /* SCIF0 */ 91 - make_ipr_irq(SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, 92 - SCIF0_PRIORITY); 93 - make_ipr_irq(SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, 94 - SCIF0_PRIORITY); 95 - make_ipr_irq(SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, 96 - SCIF0_PRIORITY); 97 - make_ipr_irq(SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, 98 - SCIF0_PRIORITY); 99 - 100 - /* DMAC-1 */ 101 - make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 102 - make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 103 - make_ipr_irq(DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 104 - make_ipr_irq(DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 105 - 106 - /* DMAC-2 */ 107 - make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); 108 - make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); 109 - 110 - /* IPSEC */ 111 - make_ipr_irq(IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY); 112 - 113 - /* EDMAC */ 114 - make_ipr_irq(EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, 115 - EDMAC0_PRIORITY); 116 - make_ipr_irq(EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, 117 - EDMAC1_PRIORITY); 118 - make_ipr_irq(EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, 119 - EDMAC2_PRIORITY); 120 - 121 - /* SIOF0 */ 122 - make_ipr_irq(SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, 123 - SIOF0_PRIORITY); 124 - make_ipr_irq(SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, 125 - SIOF0_PRIORITY); 126 - make_ipr_irq(SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, 127 - SIOF0_PRIORITY); 128 - make_ipr_irq(SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, 129 - SIOF0_PRIORITY); 130 - 131 - /* SIOF1 */ 132 - make_ipr_irq(SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, 133 - SIOF1_PRIORITY); 134 - make_ipr_irq(SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, 135 - SIOF1_PRIORITY); 136 - make_ipr_irq(SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, 137 - SIOF1_PRIORITY); 138 - make_ipr_irq(SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, 139 - SIOF1_PRIORITY); 140 - 141 - /* SLIC IRQ's */ 142 - make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 143 - make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 40 + make_ipr_irq(sh7710voipgw_ipr_map, ARRAY_SIZE(sh7710voipgw_ipr_map)); 144 41 } 145 42 146 43 /*
+12 -8
arch/sh/boards/se/7300/irq.c
··· 13 13 #include <asm/io.h> 14 14 #include <asm/se7300.h> 15 15 16 + static struct ipr_data se7300_ipr_map[] = { 17 + /* PC_IRQ[0-3] -> IRQ0 (32) */ 18 + { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ }, 19 + /* A_IRQ[0-3] -> IRQ1 (33) */ 20 + { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ }, 21 + { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 22 + { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 23 + { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 24 + { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 25 + }; 26 + 16 27 /* 17 28 * Initialize IRQ setting 18 29 */ ··· 34 23 ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */ 35 24 ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */ 36 25 37 - /* PC_IRQ[0-3] -> IRQ0 (32) */ 38 - make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ); 39 - /* A_IRQ[0-3] -> IRQ1 (33) */ 40 - make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ); 41 - make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 42 - make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 43 - make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 44 - make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 26 + make_ipr_irq(se7300_ipr_map, ARRAY_SIZE(se7300_ipr_map)); 45 27 46 28 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 47 29 }
+28 -19
arch/sh/boards/se/73180/irq.c
··· 87 87 return irq; 88 88 } 89 89 90 + static struct ipr_data se73180_siof0_ipr_map[] = { 91 + { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 92 + }; 93 + static struct ipr_data se73180_vpu_ipr_map[] = { 94 + { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 }, 95 + }; 96 + static struct ipr_data se73180_other_ipr_map[] = { 97 + { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 98 + { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 99 + { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, 100 + { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 101 + { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 102 + { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 103 + { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 104 + { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 105 + { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY }, 106 + 107 + /* VIO interrupt */ 108 + { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 109 + { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 110 + { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 111 + 112 + { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY }, 113 + }; 114 + 90 115 /* 91 116 * Initialize IRQ setting 92 117 */ 93 118 void __init 94 119 init_73180se_IRQ(void) 95 120 { 96 - make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 121 + make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map)); 97 122 98 123 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 99 124 ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */ ··· 126 101 ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */ 127 102 make_intreq_irq(10); 128 103 129 - make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); 104 + make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map)); 130 105 131 106 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ 132 107 133 - make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 134 - make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 135 - make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); 136 - make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); 137 - make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, 138 - IIC0_PRIORITY); 139 - make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, 140 - IIC0_PRIORITY); 141 - make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); 142 - make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 143 - make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY); 108 + make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map)); 144 109 145 - /* VIO interrupt */ 146 - make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 147 - make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 148 - make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 149 - 150 - make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY); 151 110 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 152 111 }
+49 -41
arch/sh/boards/se/7343/irq.c
··· 102 102 static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade", 103 103 NULL, NULL}; 104 104 105 + static struct ipr_data se7343_irq5_ipr_map[] = { 106 + { IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY }, 107 + }; 108 + static struct ipr_data se7343_siof0_vpu_ipr_map[] = { 109 + { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 110 + { VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 }, 111 + }; 112 + static struct ipr_data se7343_other_ipr_map[] = { 113 + { DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 114 + { DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 115 + { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 116 + { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 117 + { DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, 118 + { DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY }, 119 + 120 + /* I2C block */ 121 + { IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 122 + { IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 123 + { IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 124 + { IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY }, 125 + 126 + { IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, 127 + { IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, 128 + { IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, 129 + { IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY }, 130 + 131 + /* SIOF */ 132 + { SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY }, 133 + 134 + /* SIU */ 135 + { SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY }, 136 + 137 + /* VIO interrupt */ 138 + { CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 139 + { BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 140 + { VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 141 + 142 + /*MFI interrupt*/ 143 + 144 + { MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY }, 145 + 146 + /* LCD controller */ 147 + { LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY }, 148 + }; 149 + 105 150 /* 106 151 * Initialize IRQ setting 107 152 */ ··· 183 138 /* Setup all external interrupts to be active low */ 184 139 ctrl_outw(0xaaaa, INTC_ICR1); 185 140 186 - make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY); 141 + make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map)); 142 + 187 143 setup_irq(IRQ5_IRQ, &irq5); 188 144 /* Set port control to use IRQ5 */ 189 145 *(u16 *)0xA4050108 &= ~0xc; 190 146 191 - make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 192 - make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8); 147 + make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map)); 193 148 194 149 ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */ 195 150 196 - make_ipr_irq(DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 197 - make_ipr_irq(DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 198 - make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 199 - make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 200 - make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); 201 - make_ipr_irq(DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY); 151 + make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map)); 202 152 203 - /* I2C block */ 204 - make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); 205 - make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, 206 - IIC0_PRIORITY); 207 - make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, 208 - IIC0_PRIORITY); 209 - make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY); 210 - 211 - make_ipr_irq(IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY); 212 - make_ipr_irq(IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, 213 - IIC1_PRIORITY); 214 - make_ipr_irq(IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, 215 - IIC1_PRIORITY); 216 - make_ipr_irq(IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY); 217 - 218 - /* SIOF */ 219 - make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY); 220 - 221 - /* SIU */ 222 - make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY); 223 - 224 - /* VIO interrupt */ 225 - make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 226 - make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 227 - make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 228 - 229 - /*MFI interrupt*/ 230 - 231 - make_ipr_irq(MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY); 232 - 233 - /* LCD controller */ 234 - make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY); 235 153 ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */ 236 154 }
+43 -37
arch/sh/boards/se/770x/irq.c
··· 13 13 #include <asm/io.h> 14 14 #include <asm/se.h> 15 15 16 + static struct ipr_data se770x_ipr_map[] = { 17 + #if defined(CONFIG_CPU_SUBTYPE_SH7705) 18 + /* This is default value */ 19 + { 0xf-0x2, BCR_ILCRA, 2, 0x2 }, 20 + { 0xf-0xa, BCR_ILCRA, 1, 0xa }, 21 + { 0xf-0x5, BCR_ILCRB, 0, 0x5 }, 22 + { 0xf-0x8, BCR_ILCRC, 1, 0x8 }, 23 + { 0xf-0xc, BCR_ILCRC, 0, 0xc }, 24 + { 0xf-0xe, BCR_ILCRD, 3, 0xe }, 25 + { 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */ 26 + { 0xf-0xd, BCR_ILCRE, 2, 0xd }, 27 + { 0xf-0x9, BCR_ILCRE, 1, 0x9 }, 28 + { 0xf-0x1, BCR_ILCRE, 0, 0x1 }, 29 + { 0xf-0xf, BCR_ILCRF, 3, 0xf }, 30 + { 0xf-0xb, BCR_ILCRF, 1, 0xb }, 31 + { 0xf-0x7, BCR_ILCRG, 3, 0x7 }, 32 + { 0xf-0x6, BCR_ILCRG, 2, 0x6 }, 33 + { 0xf-0x4, BCR_ILCRG, 1, 0x4 }, 34 + #else 35 + { 14, BCR_ILCRA, 2, 0x0f-14 }, 36 + { 12, BCR_ILCRA, 1, 0x0f-12 }, 37 + { 8, BCR_ILCRB, 1, 0x0f- 8 }, 38 + { 6, BCR_ILCRC, 3, 0x0f- 6 }, 39 + { 5, BCR_ILCRC, 2, 0x0f- 5 }, 40 + { 4, BCR_ILCRC, 1, 0x0f- 4 }, 41 + { 3, BCR_ILCRC, 0, 0x0f- 3 }, 42 + { 1, BCR_ILCRD, 3, 0x0f- 1 }, 43 + 44 + { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ 45 + 46 + { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ 47 + { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ 48 + { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ 49 + { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ 50 + 51 + /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 52 + /* NOTE: #2 and #13 are not used on PC */ 53 + { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ 54 + { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ 55 + #endif 56 + }; 57 + 16 58 /* 17 59 * Initialize IRQ setting 18 60 */ ··· 80 38 ctrl_outw(0, BCR_ILCRE); 81 39 ctrl_outw(0, BCR_ILCRF); 82 40 ctrl_outw(0, BCR_ILCRG); 83 - /* This is default value */ 84 - make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2); 85 - make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa); 86 - make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5); 87 - make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8); 88 - make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc); 89 - make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe); 90 - make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */ 91 - make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd); 92 - make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9); 93 - make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1); 94 - make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf); 95 - make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb); 96 - make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7); 97 - make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6); 98 - make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4); 99 - #else 100 - make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14); 101 - make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12); 102 - make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8); 103 - make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6); 104 - make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5); 105 - make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4); 106 - make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3); 107 - make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1); 108 - 109 - make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */ 110 - 111 - make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */ 112 - make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */ 113 - make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */ 114 - make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */ 115 - 116 - /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 117 - /* NOTE: #2 and #13 are not used on PC */ 118 - make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */ 119 - make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */ 120 41 #endif 42 + make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map)); 121 43 }
+41 -44
arch/sh/boards/se/7751/irq.c
··· 14 14 #include <asm/irq.h> 15 15 #include <asm/se7751.h> 16 16 17 + static struct ipr_data se7751_ipr_map[] = { 18 + /* Leave old Solution Engine code in for reference. */ 19 + #if defined(CONFIG_SH_SOLUTION_ENGINE) 20 + /* 21 + * Super I/O (Just mimic PC): 22 + * 1: keyboard 23 + * 3: serial 0 24 + * 4: serial 1 25 + * 5: printer 26 + * 6: floppy 27 + * 8: rtc 28 + * 12: mouse 29 + * 14: ide0 30 + */ 31 + { 14, BCR_ILCRA, 2, 0x0f-14 }, 32 + { 12, BCR_ILCRA, 1, 0x0f-12 }, 33 + { 8, BCR_ILCRB, 1, 0x0f- 8 }, 34 + { 6, BCR_ILCRC, 3, 0x0f- 6 }, 35 + { 5, BCR_ILCRC, 2, 0x0f- 5 }, 36 + { 4, BCR_ILCRC, 1, 0x0f- 4 }, 37 + { 3, BCR_ILCRC, 0, 0x0f- 3 }, 38 + { 1, BCR_ILCRD, 3, 0x0f- 1 }, 39 + 40 + { 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */ 41 + 42 + { 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */ 43 + { 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */ 44 + { 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */ 45 + { 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */ 46 + 47 + /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 48 + /* NOTE: #2 and #13 are not used on PC */ 49 + { 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */ 50 + { 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */ 51 + #elif defined(CONFIG_SH_7751_SOLUTION_ENGINE) 52 + { 13, BCR_ILCRD, 3, 2 }, 53 + /* Add additional entries here as drivers are added and tested. */ 54 + #endif 55 + }; 56 + 17 57 /* 18 58 * Initialize IRQ setting 19 59 */ 20 60 void __init init_7751se_IRQ(void) 21 61 { 22 - 23 - /* Leave old Solution Engine code in for reference. */ 24 - #if defined(CONFIG_SH_SOLUTION_ENGINE) 25 - /* 26 - * Super I/O (Just mimic PC): 27 - * 1: keyboard 28 - * 3: serial 0 29 - * 4: serial 1 30 - * 5: printer 31 - * 6: floppy 32 - * 8: rtc 33 - * 12: mouse 34 - * 14: ide0 35 - */ 36 - make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14); 37 - make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12); 38 - make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8); 39 - make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6); 40 - make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5); 41 - make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4); 42 - make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3); 43 - make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1); 44 - 45 - make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */ 46 - 47 - make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */ 48 - make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */ 49 - make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */ 50 - make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */ 51 - 52 - /* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */ 53 - /* NOTE: #2 and #13 are not used on PC */ 54 - make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */ 55 - make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */ 56 - 57 - #elif defined(CONFIG_SH_7751_SOLUTION_ENGINE) 58 - 59 - make_ipr_irq(13, BCR_ILCRD, 3, 2); 60 - 61 - /* Add additional calls to make_ipr_irq() as drivers are added 62 - * and tested. 63 - */ 64 - #endif 65 - 62 + make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map)); 66 63 }
+8 -5
arch/sh/boards/sh03/setup.c
··· 14 14 #include <asm/sh03/sh03.h> 15 15 #include <asm/addrspace.h> 16 16 17 + static struct ipr_data sh03_ipr_map[] = { 18 + { IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY }, 19 + { IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY }, 20 + { IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY }, 21 + { IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY }, 22 + }; 23 + 17 24 static void __init init_sh03_IRQ(void) 18 25 { 19 26 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 20 - 21 - make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); 22 - make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); 23 - make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); 24 - make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); 27 + make_ipr_irq(sh03_ipr_map, ARRAY_SIZE(sh03_ipr_map)); 25 28 } 26 29 27 30 extern void *cf_io_base;
+8 -4
arch/sh/boards/snapgear/setup.c
··· 68 68 * IRL3 = crypto 69 69 */ 70 70 71 + static struct ipr_data snapgear_ipr_map[] = { 72 + make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); 73 + make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); 74 + make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); 75 + make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); 76 + }; 77 + 71 78 static void __init init_snapgear_IRQ(void) 72 79 { 73 80 /* enable individual interrupt mode for externals */ ··· 82 75 83 76 printk("Setup SnapGear IRQ/IPR ...\n"); 84 77 85 - make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); 86 - make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); 87 - make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); 88 - make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); 78 + make_ipr_irq(snapgear_ipr_map, ARRAY_SIZE(snapgear_ipr_map)); 89 79 } 90 80 91 81 /*
+8 -4
arch/sh/boards/titan/setup.c
··· 9 9 10 10 extern void __init pcibios_init_platform(void); 11 11 12 + static struct ipr_data titan_ipr_map[] = { 13 + { TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY }, 14 + { TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY }, 15 + { TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY }, 16 + { TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY }, 17 + }; 18 + 12 19 static void __init init_titan_irq(void) 13 20 { 14 21 /* enable individual interrupt mode for externals */ 15 22 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 16 23 17 - make_ipr_irq( TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); /* PCIRQ0 */ 18 - make_ipr_irq( TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); /* PCIRQ1 */ 19 - make_ipr_irq( TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); /* PCIRQ2 */ 20 - make_ipr_irq( TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); /* PCIRQ3 */ 24 + make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map)); 21 25 } 22 26 23 27 struct sh_machine_vector mv_titan __initmv = {
+98 -76
arch/sh/configs/r7780rp_defconfig
··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 - # Linux kernel version: 2.6.18 4 - # Tue Oct 3 11:32:47 2006 3 + # Linux kernel version: 2.6.19-rc3 4 + # Tue Oct 31 12:32:06 2006 5 5 # 6 6 CONFIG_SUPERH=y 7 7 CONFIG_RWSEM_GENERIC_SPINLOCK=y ··· 10 10 CONFIG_GENERIC_HARDIRQS=y 11 11 CONFIG_GENERIC_IRQ_PROBE=y 12 12 CONFIG_GENERIC_CALIBRATE_DELAY=y 13 + # CONFIG_GENERIC_TIME is not set 13 14 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 14 15 15 16 # ··· 179 178 CONFIG_PAGE_OFFSET=0x80000000 180 179 CONFIG_MEMORY_START=0x08000000 181 180 CONFIG_MEMORY_SIZE=0x08000000 182 - CONFIG_32BIT=y 181 + # CONFIG_32BIT is not set 183 182 CONFIG_VSYSCALL=y 184 183 CONFIG_HUGETLB_PAGE_SIZE_64K=y 185 184 # CONFIG_HUGETLB_PAGE_SIZE_1MB is not set ··· 230 229 # 231 230 # DMA support 232 231 # 233 - CONFIG_SH_DMA=y 234 - CONFIG_NR_ONCHIP_DMA_CHANNELS=6 235 - # CONFIG_NR_DMA_CHANNELS_BOOL is not set 232 + # CONFIG_SH_DMA is not set 236 233 237 234 # 238 235 # Companion Chips ··· 258 259 CONFIG_BOOT_LINK_OFFSET=0x00800000 259 260 # CONFIG_UBC_WAKEUP is not set 260 261 CONFIG_CMDLINE_BOOL=y 261 - CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/hda1" 262 + CONFIG_CMDLINE="mem=128M console=ttySC0,115200 root=/dev/sda1" 262 263 263 264 # 264 265 # Bus options ··· 335 336 # CONFIG_INET_TUNNEL is not set 336 337 CONFIG_INET_XFRM_MODE_TRANSPORT=y 337 338 CONFIG_INET_XFRM_MODE_TUNNEL=y 339 + CONFIG_INET_XFRM_MODE_BEET=y 338 340 CONFIG_INET_DIAG=y 339 341 CONFIG_INET_TCP_DIAG=y 340 342 # CONFIG_TCP_CONG_ADVANCED is not set ··· 441 441 # CONFIG_ATA_OVER_ETH is not set 442 442 443 443 # 444 + # Misc devices 445 + # 446 + # CONFIG_SGI_IOC4 is not set 447 + # CONFIG_TIFM_CORE is not set 448 + 449 + # 444 450 # ATA/ATAPI/MFM/RLL support 445 451 # 446 - CONFIG_IDE=m 447 - CONFIG_IDE_MAX_HWIFS=4 448 - CONFIG_BLK_DEV_IDE=m 449 - 450 - # 451 - # Please see Documentation/ide.txt for help/info on IDE drives 452 - # 453 - CONFIG_BLK_DEV_IDE_SATA=y 454 - CONFIG_BLK_DEV_IDEDISK=m 455 - CONFIG_IDEDISK_MULTI_MODE=y 456 - # CONFIG_BLK_DEV_IDECD is not set 457 - # CONFIG_BLK_DEV_IDETAPE is not set 458 - # CONFIG_BLK_DEV_IDEFLOPPY is not set 459 - CONFIG_BLK_DEV_IDESCSI=m 460 - # CONFIG_IDE_TASK_IOCTL is not set 461 - 462 - # 463 - # IDE chipset support/bugfixes 464 - # 465 - CONFIG_IDE_GENERIC=m 466 - CONFIG_BLK_DEV_IDEPCI=y 467 - CONFIG_IDEPCI_SHARE_IRQ=y 468 - # CONFIG_BLK_DEV_OFFBOARD is not set 469 - CONFIG_BLK_DEV_GENERIC=m 470 - # CONFIG_BLK_DEV_OPTI621 is not set 471 - CONFIG_BLK_DEV_IDEDMA_PCI=y 472 - # CONFIG_BLK_DEV_IDEDMA_FORCED is not set 473 - CONFIG_IDEDMA_PCI_AUTO=y 474 - # CONFIG_IDEDMA_ONLYDISK is not set 475 - CONFIG_BLK_DEV_AEC62XX=m 476 - # CONFIG_BLK_DEV_ALI15X3 is not set 477 - # CONFIG_BLK_DEV_AMD74XX is not set 478 - # CONFIG_BLK_DEV_CMD64X is not set 479 - # CONFIG_BLK_DEV_TRIFLEX is not set 480 - # CONFIG_BLK_DEV_CY82C693 is not set 481 - # CONFIG_BLK_DEV_CS5520 is not set 482 - # CONFIG_BLK_DEV_CS5530 is not set 483 - # CONFIG_BLK_DEV_HPT34X is not set 484 - # CONFIG_BLK_DEV_HPT366 is not set 485 - # CONFIG_BLK_DEV_SC1200 is not set 486 - # CONFIG_BLK_DEV_PIIX is not set 487 - # CONFIG_BLK_DEV_IT821X is not set 488 - # CONFIG_BLK_DEV_NS87415 is not set 489 - # CONFIG_BLK_DEV_PDC202XX_OLD is not set 490 - CONFIG_BLK_DEV_PDC202XX_NEW=m 491 - # CONFIG_BLK_DEV_SVWKS is not set 492 - CONFIG_BLK_DEV_SIIMAGE=m 493 - # CONFIG_BLK_DEV_SLC90E66 is not set 494 - # CONFIG_BLK_DEV_TRM290 is not set 495 - # CONFIG_BLK_DEV_VIA82CXXX is not set 496 - # CONFIG_IDE_ARM is not set 497 - CONFIG_BLK_DEV_IDEDMA=y 498 - # CONFIG_IDEDMA_IVB is not set 499 - CONFIG_IDEDMA_AUTO=y 500 - # CONFIG_BLK_DEV_HD is not set 452 + # CONFIG_IDE is not set 501 453 502 454 # 503 455 # SCSI device support 504 456 # 505 457 # CONFIG_RAID_ATTRS is not set 506 - CONFIG_SCSI=m 458 + CONFIG_SCSI=y 507 459 # CONFIG_SCSI_NETLINK is not set 508 460 CONFIG_SCSI_PROC_FS=y 509 461 510 462 # 511 463 # SCSI support type (disk, tape, CD-ROM) 512 464 # 513 - CONFIG_BLK_DEV_SD=m 465 + CONFIG_BLK_DEV_SD=y 514 466 # CONFIG_CHR_DEV_ST is not set 515 467 # CONFIG_CHR_DEV_OSST is not set 516 468 # CONFIG_BLK_DEV_SR is not set ··· 513 561 # CONFIG_SCSI_IPR is not set 514 562 # CONFIG_SCSI_QLOGIC_1280 is not set 515 563 # CONFIG_SCSI_QLA_FC is not set 564 + # CONFIG_SCSI_QLA_ISCSI is not set 516 565 # CONFIG_SCSI_LPFC is not set 517 566 # CONFIG_SCSI_DC395x is not set 518 567 # CONFIG_SCSI_DC390T is not set ··· 523 570 # 524 571 # Serial ATA (prod) and Parallel ATA (experimental) drivers 525 572 # 526 - # CONFIG_ATA is not set 573 + CONFIG_ATA=y 574 + # CONFIG_SATA_AHCI is not set 575 + # CONFIG_SATA_SVW is not set 576 + # CONFIG_ATA_PIIX is not set 577 + # CONFIG_SATA_MV is not set 578 + # CONFIG_SATA_NV is not set 579 + # CONFIG_PDC_ADMA is not set 580 + # CONFIG_SATA_QSTOR is not set 581 + # CONFIG_SATA_PROMISE is not set 582 + # CONFIG_SATA_SX4 is not set 583 + CONFIG_SATA_SIL=y 584 + # CONFIG_SATA_SIL24 is not set 585 + # CONFIG_SATA_SIS is not set 586 + # CONFIG_SATA_ULI is not set 587 + # CONFIG_SATA_VIA is not set 588 + # CONFIG_SATA_VITESSE is not set 589 + # CONFIG_PATA_ALI is not set 590 + # CONFIG_PATA_AMD is not set 591 + # CONFIG_PATA_ARTOP is not set 592 + # CONFIG_PATA_ATIIXP is not set 593 + # CONFIG_PATA_CMD64X is not set 594 + # CONFIG_PATA_CS5520 is not set 595 + # CONFIG_PATA_CS5530 is not set 596 + # CONFIG_PATA_CYPRESS is not set 597 + # CONFIG_PATA_EFAR is not set 598 + # CONFIG_ATA_GENERIC is not set 599 + # CONFIG_PATA_HPT366 is not set 600 + # CONFIG_PATA_HPT37X is not set 601 + # CONFIG_PATA_HPT3X2N is not set 602 + # CONFIG_PATA_HPT3X3 is not set 603 + # CONFIG_PATA_IT821X is not set 604 + # CONFIG_PATA_JMICRON is not set 605 + # CONFIG_PATA_TRIFLEX is not set 606 + # CONFIG_PATA_MPIIX is not set 607 + # CONFIG_PATA_OLDPIIX is not set 608 + # CONFIG_PATA_NETCELL is not set 609 + # CONFIG_PATA_NS87410 is not set 610 + # CONFIG_PATA_OPTI is not set 611 + # CONFIG_PATA_OPTIDMA is not set 612 + # CONFIG_PATA_PDC_OLD is not set 613 + # CONFIG_PATA_RADISYS is not set 614 + # CONFIG_PATA_RZ1000 is not set 615 + # CONFIG_PATA_SC1200 is not set 616 + # CONFIG_PATA_SERVERWORKS is not set 617 + # CONFIG_PATA_PDC2027X is not set 618 + # CONFIG_PATA_SIL680 is not set 619 + # CONFIG_PATA_SIS is not set 620 + # CONFIG_PATA_VIA is not set 621 + # CONFIG_PATA_WINBOND is not set 527 622 528 623 # 529 624 # Multi-device support (RAID and LVM) ··· 841 840 # TPM devices 842 841 # 843 842 # CONFIG_TCG_TPM is not set 844 - # CONFIG_TELCLOCK is not set 845 843 846 844 # 847 845 # I2C support ··· 856 856 # 857 857 # Dallas's 1-wire bus 858 858 # 859 + # CONFIG_W1 is not set 859 860 860 861 # 861 862 # Hardware Monitoring support ··· 869 868 # CONFIG_HWMON_DEBUG_CHIP is not set 870 869 871 870 # 872 - # Misc devices 873 - # 874 - 875 - # 876 871 # Multimedia devices 877 872 # 878 873 # CONFIG_VIDEO_DEV is not set 879 - CONFIG_VIDEO_V4L2=y 880 874 881 875 # 882 876 # Digital Video Broadcasting Devices ··· 955 959 # 956 960 # Real Time Clock 957 961 # 958 - # CONFIG_RTC_CLASS is not set 962 + CONFIG_RTC_LIB=y 963 + CONFIG_RTC_CLASS=y 964 + CONFIG_RTC_HCTOSYS=y 965 + CONFIG_RTC_HCTOSYS_DEVICE="rtc0" 966 + # CONFIG_RTC_DEBUG is not set 967 + 968 + # 969 + # RTC interfaces 970 + # 971 + CONFIG_RTC_INTF_SYSFS=y 972 + CONFIG_RTC_INTF_PROC=y 973 + CONFIG_RTC_INTF_DEV=y 974 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 975 + 976 + # 977 + # RTC drivers 978 + # 979 + # CONFIG_RTC_DRV_DS1553 is not set 980 + # CONFIG_RTC_DRV_DS1742 is not set 981 + # CONFIG_RTC_DRV_M48T86 is not set 982 + CONFIG_RTC_DRV_SH=y 983 + # CONFIG_RTC_DRV_TEST is not set 984 + # CONFIG_RTC_DRV_V3020 is not set 959 985 960 986 # 961 987 # DMA Engine support ··· 1002 984 CONFIG_EXT3_FS_XATTR=y 1003 985 # CONFIG_EXT3_FS_POSIX_ACL is not set 1004 986 # CONFIG_EXT3_FS_SECURITY is not set 987 + # CONFIG_EXT4DEV_FS is not set 1005 988 CONFIG_JBD=y 1006 989 # CONFIG_JBD_DEBUG is not set 1007 990 CONFIG_FS_MBCACHE=y ··· 1010 991 # CONFIG_JFS_FS is not set 1011 992 CONFIG_FS_POSIX_ACL=y 1012 993 # CONFIG_XFS_FS is not set 994 + # CONFIG_GFS2_FS is not set 1013 995 # CONFIG_OCFS2_FS is not set 1014 996 CONFIG_MINIX_FS=y 1015 997 # CONFIG_ROMFS_FS is not set ··· 1047 1027 CONFIG_PROC_KCORE=y 1048 1028 CONFIG_PROC_SYSCTL=y 1049 1029 CONFIG_SYSFS=y 1050 - # CONFIG_TMPFS is not set 1030 + CONFIG_TMPFS=y 1031 + # CONFIG_TMPFS_POSIX_ACL is not set 1051 1032 CONFIG_HUGETLBFS=y 1052 1033 CONFIG_HUGETLB_PAGE=y 1053 1034 CONFIG_RAMFS=y ··· 1180 1159 # CONFIG_DEBUG_LIST is not set 1181 1160 CONFIG_FRAME_POINTER=y 1182 1161 CONFIG_FORCED_INLINING=y 1162 + # CONFIG_HEADERS_CHECK is not set 1183 1163 # CONFIG_RCU_TORTURE_TEST is not set 1184 1164 # CONFIG_SH_STANDARD_BIOS is not set 1185 1165 # CONFIG_EARLY_SCIF_CONSOLE is not set ··· 1200 1178 # 1201 1179 CONFIG_CRYPTO=y 1202 1180 CONFIG_CRYPTO_ALGAPI=y 1203 - CONFIG_CRYPTO_BLKCIPHER=m 1181 + CONFIG_CRYPTO_BLKCIPHER=y 1204 1182 CONFIG_CRYPTO_HASH=y 1205 - CONFIG_CRYPTO_MANAGER=m 1183 + CONFIG_CRYPTO_MANAGER=y 1206 1184 CONFIG_CRYPTO_HMAC=y 1207 1185 # CONFIG_CRYPTO_NULL is not set 1208 1186 # CONFIG_CRYPTO_MD4 is not set ··· 1213 1191 # CONFIG_CRYPTO_WP512 is not set 1214 1192 # CONFIG_CRYPTO_TGR192 is not set 1215 1193 CONFIG_CRYPTO_ECB=m 1216 - CONFIG_CRYPTO_CBC=m 1194 + CONFIG_CRYPTO_CBC=y 1217 1195 CONFIG_CRYPTO_DES=y 1218 1196 # CONFIG_CRYPTO_BLOWFISH is not set 1219 1197 # CONFIG_CRYPTO_TWOFISH is not set
+72 -29
arch/sh/configs/titan_defconfig
··· 1 1 # 2 2 # Automatically generated make config: don't edit 3 - # Linux kernel version: 2.6.18 4 - # Tue Oct 3 12:59:14 2006 3 + # Linux kernel version: 2.6.19-rc3 4 + # Mon Oct 30 18:04:49 2006 5 5 # 6 6 CONFIG_SUPERH=y 7 7 CONFIG_RWSEM_GENERIC_SPINLOCK=y ··· 10 10 CONFIG_GENERIC_HARDIRQS=y 11 11 CONFIG_GENERIC_IRQ_PROBE=y 12 12 CONFIG_GENERIC_CALIBRATE_DELAY=y 13 + # CONFIG_GENERIC_TIME is not set 13 14 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 14 15 15 16 # ··· 24 23 # General setup 25 24 # 26 25 CONFIG_LOCALVERSION="" 27 - CONFIG_LOCALVERSION_AUTO=y 26 + # CONFIG_LOCALVERSION_AUTO is not set 28 27 CONFIG_SWAP=y 29 28 CONFIG_SYSVIPC=y 30 29 # CONFIG_IPC_NS is not set ··· 237 236 CONFIG_HZ=250 238 237 # CONFIG_KEXEC is not set 239 238 # CONFIG_SMP is not set 240 - CONFIG_PREEMPT_NONE=y 241 - # CONFIG_PREEMPT_VOLUNTARY is not set 239 + # CONFIG_PREEMPT_NONE is not set 240 + CONFIG_PREEMPT_VOLUNTARY=y 242 241 # CONFIG_PREEMPT is not set 243 242 244 243 # ··· 248 247 CONFIG_BOOT_LINK_OFFSET=0x009e0000 249 248 # CONFIG_UBC_WAKEUP is not set 250 249 CONFIG_CMDLINE_BOOL=y 251 - CONFIG_CMDLINE="console=ttySC1,38400N81 root=/dev/nfs ip=:::::eth1:autoconf" 250 + CONFIG_CMDLINE="console=ttySC1,38400N81 root=/dev/nfs ip=:::::eth1:autoconf rw" 252 251 253 252 # 254 253 # Bus options ··· 335 334 CONFIG_INET_TUNNEL=y 336 335 CONFIG_INET_XFRM_MODE_TRANSPORT=y 337 336 CONFIG_INET_XFRM_MODE_TUNNEL=y 337 + CONFIG_INET_XFRM_MODE_BEET=y 338 338 CONFIG_INET_DIAG=m 339 339 CONFIG_INET_TCP_DIAG=m 340 340 # CONFIG_TCP_CONG_ADVANCED is not set ··· 357 355 CONFIG_INET6_TUNNEL=y 358 356 CONFIG_INET6_XFRM_MODE_TRANSPORT=y 359 357 CONFIG_INET6_XFRM_MODE_TUNNEL=y 358 + CONFIG_INET6_XFRM_MODE_BEET=y 360 359 # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set 360 + CONFIG_IPV6_SIT=m 361 361 CONFIG_IPV6_TUNNEL=y 362 - # CONFIG_IPV6_SUBTREES is not set 363 362 # CONFIG_IPV6_MULTIPLE_TABLES is not set 364 363 # CONFIG_NETWORK_SECMARK is not set 365 364 CONFIG_NETFILTER=y ··· 717 714 CONFIG_ATA_OVER_ETH=m 718 715 719 716 # 717 + # Misc devices 718 + # 719 + # CONFIG_SGI_IOC4 is not set 720 + # CONFIG_TIFM_CORE is not set 721 + 722 + # 720 723 # ATA/ATAPI/MFM/RLL support 721 724 # 722 725 # CONFIG_IDE is not set ··· 787 778 # CONFIG_SCSI_INIA100 is not set 788 779 # CONFIG_SCSI_STEX is not set 789 780 # CONFIG_SCSI_SYM53C8XX_2 is not set 790 - # CONFIG_SCSI_IPR is not set 791 781 # CONFIG_SCSI_QLOGIC_1280 is not set 792 782 # CONFIG_SCSI_QLA_FC is not set 783 + # CONFIG_SCSI_QLA_ISCSI is not set 793 784 # CONFIG_SCSI_LPFC is not set 794 785 # CONFIG_SCSI_DC395x is not set 795 786 # CONFIG_SCSI_DC390T is not set ··· 1104 1095 # TPM devices 1105 1096 # 1106 1097 # CONFIG_TCG_TPM is not set 1107 - # CONFIG_TELCLOCK is not set 1108 1098 1109 1099 # 1110 1100 # I2C support ··· 1132 1124 # CONFIG_HWMON_DEBUG_CHIP is not set 1133 1125 1134 1126 # 1135 - # Misc devices 1136 - # 1137 - 1138 - # 1139 1127 # Multimedia devices 1140 1128 # 1141 1129 # CONFIG_VIDEO_DEV is not set 1142 - CONFIG_VIDEO_V4L2=y 1143 1130 1144 1131 # 1145 1132 # Digital Video Broadcasting Devices ··· 1180 1177 # USB Host Controller Drivers 1181 1178 # 1182 1179 CONFIG_USB_EHCI_HCD=y 1183 - # CONFIG_USB_EHCI_SPLIT_ISO is not set 1184 - # CONFIG_USB_EHCI_ROOT_HUB_TT is not set 1185 - # CONFIG_USB_EHCI_TT_NEWSCHED is not set 1180 + CONFIG_USB_EHCI_SPLIT_ISO=y 1181 + CONFIG_USB_EHCI_ROOT_HUB_TT=y 1182 + CONFIG_USB_EHCI_TT_NEWSCHED=y 1186 1183 # CONFIG_USB_ISP116X_HCD is not set 1187 1184 CONFIG_USB_OHCI_HCD=y 1188 1185 # CONFIG_USB_OHCI_BIG_ENDIAN is not set ··· 1238 1235 # CONFIG_USB_ATI_REMOTE2 is not set 1239 1236 # CONFIG_USB_KEYSPAN_REMOTE is not set 1240 1237 # CONFIG_USB_APPLETOUCH is not set 1241 - # CONFIG_USB_TRANCEVIBRATOR is not set 1242 1238 1243 1239 # 1244 1240 # USB Imaging devices ··· 1248 1246 # 1249 1247 # USB Network Adapters 1250 1248 # 1251 - # CONFIG_USB_CATC is not set 1252 - # CONFIG_USB_KAWETH is not set 1253 - # CONFIG_USB_PEGASUS is not set 1254 - # CONFIG_USB_RTL8150 is not set 1255 - # CONFIG_USB_USBNET is not set 1249 + CONFIG_USB_CATC=m 1250 + CONFIG_USB_KAWETH=m 1251 + CONFIG_USB_PEGASUS=m 1252 + CONFIG_USB_RTL8150=m 1253 + CONFIG_USB_USBNET=m 1254 + CONFIG_USB_NET_AX8817X=m 1255 + CONFIG_USB_NET_CDCETHER=m 1256 + # CONFIG_USB_NET_GL620A is not set 1257 + CONFIG_USB_NET_NET1080=m 1258 + CONFIG_USB_NET_PLUSB=m 1259 + # CONFIG_USB_NET_MCS7830 is not set 1260 + # CONFIG_USB_NET_RNDIS_HOST is not set 1261 + # CONFIG_USB_NET_CDC_SUBSET is not set 1262 + CONFIG_USB_NET_ZAURUS=m 1256 1263 CONFIG_USB_MON=y 1257 1264 1258 1265 # ··· 1296 1285 # CONFIG_USB_SERIAL_KLSI is not set 1297 1286 # CONFIG_USB_SERIAL_KOBIL_SCT is not set 1298 1287 # CONFIG_USB_SERIAL_MCT_U232 is not set 1288 + # CONFIG_USB_SERIAL_MOS7720 is not set 1299 1289 # CONFIG_USB_SERIAL_MOS7840 is not set 1300 1290 # CONFIG_USB_SERIAL_NAVMAN is not set 1301 1291 CONFIG_USB_SERIAL_PL2303=m ··· 1328 1316 # CONFIG_USB_APPLEDISPLAY is not set 1329 1317 # CONFIG_USB_SISUSBVGA is not set 1330 1318 # CONFIG_USB_LD is not set 1319 + # CONFIG_USB_TRANCEVIBRATOR is not set 1331 1320 # CONFIG_USB_TEST is not set 1332 1321 1333 1322 # ··· 1370 1357 # 1371 1358 # Real Time Clock 1372 1359 # 1373 - # CONFIG_RTC_CLASS is not set 1360 + CONFIG_RTC_LIB=m 1361 + CONFIG_RTC_CLASS=m 1362 + 1363 + # 1364 + # RTC interfaces 1365 + # 1366 + CONFIG_RTC_INTF_SYSFS=m 1367 + CONFIG_RTC_INTF_PROC=m 1368 + CONFIG_RTC_INTF_DEV=m 1369 + # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 1370 + 1371 + # 1372 + # RTC drivers 1373 + # 1374 + # CONFIG_RTC_DRV_DS1553 is not set 1375 + # CONFIG_RTC_DRV_DS1742 is not set 1376 + # CONFIG_RTC_DRV_M48T86 is not set 1377 + CONFIG_RTC_DRV_SH=m 1378 + # CONFIG_RTC_DRV_TEST is not set 1379 + # CONFIG_RTC_DRV_V3020 is not set 1374 1380 1375 1381 # 1376 1382 # DMA Engine support ··· 1412 1380 # CONFIG_EXT2_FS_XIP is not set 1413 1381 CONFIG_EXT3_FS=y 1414 1382 # CONFIG_EXT3_FS_XATTR is not set 1383 + CONFIG_EXT4DEV_FS=m 1384 + # CONFIG_EXT4DEV_FS_XATTR is not set 1415 1385 CONFIG_JBD=y 1416 1386 # CONFIG_JBD_DEBUG is not set 1387 + CONFIG_JBD2=m 1388 + # CONFIG_JBD2_DEBUG is not set 1417 1389 CONFIG_REISERFS_FS=m 1418 1390 # CONFIG_REISERFS_CHECK is not set 1419 1391 # CONFIG_REISERFS_PROC_INFO is not set ··· 1429 1393 # CONFIG_XFS_SECURITY is not set 1430 1394 # CONFIG_XFS_POSIX_ACL is not set 1431 1395 # CONFIG_XFS_RT is not set 1396 + # CONFIG_GFS2_FS is not set 1432 1397 # CONFIG_OCFS2_FS is not set 1433 1398 # CONFIG_MINIX_FS is not set 1434 - # CONFIG_ROMFS_FS is not set 1399 + CONFIG_ROMFS_FS=y 1435 1400 CONFIG_INOTIFY=y 1436 1401 CONFIG_INOTIFY_USER=y 1437 1402 # CONFIG_QUOTA is not set ··· 1517 1480 # CONFIG_RPCSEC_GSS_SPKM3 is not set 1518 1481 CONFIG_SMB_FS=m 1519 1482 # CONFIG_SMB_NLS_DEFAULT is not set 1520 - # CONFIG_CIFS is not set 1483 + CONFIG_CIFS=m 1484 + # CONFIG_CIFS_STATS is not set 1485 + CONFIG_CIFS_WEAK_PW_HASH=y 1486 + # CONFIG_CIFS_XATTR is not set 1487 + # CONFIG_CIFS_DEBUG2 is not set 1488 + # CONFIG_CIFS_EXPERIMENTAL is not set 1521 1489 # CONFIG_NCP_FS is not set 1522 1490 # CONFIG_CODA_FS is not set 1523 1491 # CONFIG_AFS_FS is not set ··· 1625 1583 # CONFIG_DEBUG_LIST is not set 1626 1584 # CONFIG_FRAME_POINTER is not set 1627 1585 # CONFIG_FORCED_INLINING is not set 1586 + # CONFIG_HEADERS_CHECK is not set 1628 1587 # CONFIG_RCU_TORTURE_TEST is not set 1629 1588 # CONFIG_SH_STANDARD_BIOS is not set 1630 - CONFIG_EARLY_SCIF_CONSOLE=y 1589 + # CONFIG_EARLY_SCIF_CONSOLE is not set 1631 1590 # CONFIG_EARLY_PRINTK is not set 1632 1591 # CONFIG_DEBUG_STACKOVERFLOW is not set 1633 1592 # CONFIG_DEBUG_STACK_USAGE is not set ··· 1648 1605 CONFIG_CRYPTO_ALGAPI=y 1649 1606 CONFIG_CRYPTO_BLKCIPHER=y 1650 1607 CONFIG_CRYPTO_HASH=y 1651 - CONFIG_CRYPTO_MANAGER=m 1608 + CONFIG_CRYPTO_MANAGER=y 1652 1609 CONFIG_CRYPTO_HMAC=y 1653 1610 CONFIG_CRYPTO_NULL=m 1654 1611 CONFIG_CRYPTO_MD4=m ··· 1658 1615 CONFIG_CRYPTO_SHA512=m 1659 1616 CONFIG_CRYPTO_WP512=m 1660 1617 CONFIG_CRYPTO_TGR192=m 1661 - CONFIG_CRYPTO_ECB=m 1618 + CONFIG_CRYPTO_ECB=y 1662 1619 CONFIG_CRYPTO_CBC=y 1663 1620 CONFIG_CRYPTO_DES=y 1664 1621 CONFIG_CRYPTO_BLOWFISH=m
+26 -16
arch/sh/drivers/dma/dma-sh.c
··· 19 19 #include <asm/io.h> 20 20 #include "dma-sh.h" 21 21 22 - static inline unsigned int get_dmte_irq(unsigned int chan) 23 - { 24 - unsigned int irq = 0; 25 22 23 + 24 + #ifdef CONFIG_CPU_SH4 25 + static struct ipr_data dmae_ipr_map[] = { 26 + { DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 27 + }; 28 + #endif 29 + static struct ipr_data dmte_ipr_map[] = { 26 30 /* 27 31 * Normally we could just do DMTE0_IRQ + chan outright, though in the 28 32 * case of the 7751R, the DMTE IRQs for channels > 4 start right above 29 33 * the SCIF 30 34 */ 31 - if (chan < 4) { 32 - irq = DMTE0_IRQ + chan; 33 - } else { 34 - #ifdef DMTE4_IRQ 35 - irq = DMTE4_IRQ + chan - 4; 36 - #endif 37 - } 35 + { DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 36 + { DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 37 + { DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 38 + { DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 39 + { DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 40 + { DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 41 + { DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 42 + { DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY }, 43 + }; 38 44 45 + static inline unsigned int get_dmte_irq(unsigned int chan) 46 + { 47 + unsigned int irq = 0; 48 + if (chan < ARRAY_SIZE(dmte_ipr_map)) 49 + irq = dmte_ipr_map[chan].irq; 39 50 return irq; 40 51 } 41 52 ··· 269 258 int i; 270 259 271 260 #ifdef CONFIG_CPU_SH4 272 - make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 261 + make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map)); 273 262 i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0); 274 263 if (unlikely(i < 0)) 275 264 return i; 276 265 #endif 277 266 278 - for (i = 0; i < info->nr_channels; i++) { 279 - int irq = get_dmte_irq(i); 280 - 281 - make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY); 282 - } 267 + i = info->nr_channels; 268 + if (i > ARRAY_SIZE(dmte_ipr_map)) 269 + i = ARRAY_SIZE(dmte_ipr_map); 270 + make_ipr_irq(dmte_ipr_map, i); 283 271 284 272 /* 285 273 * Initialize DMAOR, and clean up any error flags that may have
+48 -58
arch/sh/kernel/cpu/irq/ipr.c
··· 23 23 #include <asm/io.h> 24 24 #include <asm/machvec.h> 25 25 26 - struct ipr_data { 27 - unsigned int addr; /* Address of Interrupt Priority Register */ 28 - int shift; /* Shifts of the 16-bit data */ 29 - int priority; /* The priority */ 30 - }; 31 26 32 27 static void disable_ipr_irq(unsigned int irq) 33 28 { 34 29 struct ipr_data *p = get_irq_chip_data(irq); 30 + int shift = p->shift*4; 35 31 /* Set the priority in IPR to 0 */ 36 - ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); 32 + ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr); 37 33 } 38 34 39 35 static void enable_ipr_irq(unsigned int irq) 40 36 { 41 37 struct ipr_data *p = get_irq_chip_data(irq); 38 + int shift = p->shift*4; 42 39 /* Set priority in IPR back to original value */ 43 - ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); 40 + ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr); 44 41 } 45 42 46 43 static struct irq_chip ipr_irq_chip = { ··· 47 50 .mask_ack = disable_ipr_irq, 48 51 }; 49 52 50 - void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority) 53 + void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs) 51 54 { 52 - struct ipr_data ipr_data; 55 + int i; 53 56 54 - disable_irq_nosync(irq); 55 - 56 - ipr_data.addr = addr; 57 - ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */ 58 - ipr_data.priority = priority; 59 - 60 - set_irq_chip_and_handler_name(irq, &ipr_irq_chip, 57 + for (i = 0; i < nr_irqs; i++) { 58 + unsigned int irq = table[i].irq; 59 + disable_irq_nosync(irq); 60 + set_irq_chip_and_handler_name(irq, &ipr_irq_chip, 61 61 handle_level_irq, "level"); 62 - set_irq_chip_data(irq, &ipr_data); 63 - 64 - enable_ipr_irq(irq); 62 + set_irq_chip_data(irq, &table[i]); 63 + enable_ipr_irq(irq); 64 + } 65 65 } 66 + EXPORT_SYMBOL(make_ipr_irq); 66 67 67 - /* XXX: This needs to die a horrible death.. */ 68 - void __init init_IRQ(void) 69 - { 68 + static struct ipr_data sys_ipr_map[] = { 70 69 #ifndef CONFIG_CPU_SUBTYPE_SH7780 71 - make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY); 72 - make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY); 70 + { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY }, 71 + { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY }, 73 72 #ifdef RTC_IRQ 74 - make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY); 73 + { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY }, 75 74 #endif 76 - 77 75 #ifdef SCI_ERI_IRQ 78 - make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 79 - make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 80 - make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY); 76 + { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 77 + { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 78 + { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 81 79 #endif 82 - 83 80 #ifdef SCIF1_ERI_IRQ 84 - make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 85 - make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 86 - make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 87 - make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY); 81 + { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 82 + { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 83 + { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 84 + { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 88 85 #endif 89 - 90 86 #if defined(CONFIG_CPU_SUBTYPE_SH7300) 91 - make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY); 92 - make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 93 - make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY); 94 - make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY); 87 + { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 88 + { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 89 + { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 90 + { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 95 91 #endif 96 - 97 92 #ifdef SCIF_ERI_IRQ 98 - make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 99 - make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 100 - make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 101 - make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY); 93 + { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 94 + { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 95 + { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 96 + { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 102 97 #endif 103 - 104 98 #ifdef IRDA_ERI_IRQ 105 - make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 106 - make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 107 - make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 108 - make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY); 99 + { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 100 + { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 101 + { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 102 + { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 109 103 #endif 110 - 111 104 #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 112 105 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 113 106 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) ··· 111 124 * You should set corresponding bits of PFC to "00" 112 125 * to enable these interrupts. 113 126 */ 114 - make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY); 115 - make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY); 116 - make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY); 117 - make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY); 118 - make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY); 119 - make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY); 127 + { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY }, 128 + { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, 129 + { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, 130 + { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY }, 131 + { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY }, 132 + { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY }, 120 133 #endif 121 134 #endif 135 + }; 136 + 137 + void __init init_IRQ(void) 138 + { 139 + make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map)); 122 140 123 141 #ifdef CONFIG_CPU_HAS_PINT_IRQ 124 142 init_IRQ_pint(); ··· 145 153 return irq; 146 154 } 147 155 #endif 148 - 149 - EXPORT_SYMBOL(make_ipr_irq);
+6 -2
arch/sh/kernel/cpu/irq/pint.c
··· 84 84 disable_pint_irq(irq); 85 85 } 86 86 87 + static struct ipr_data pint_ipr_map[] = { 88 + { PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY }, 89 + { PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY }, 90 + }; 91 + 87 92 void __init init_IRQ_pint(void) 88 93 { 89 94 int i; 90 95 91 - make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY); 92 - make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY); 96 + make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map)); 93 97 94 98 enable_irq(PINT0_IRQ); 95 99 enable_irq(PINT8_IRQ);
+3
arch/sh/kernel/syscalls.S
··· 351 351 .long sys_sync_file_range 352 352 .long sys_tee /* 315 */ 353 353 .long sys_vmsplice 354 + .long sys_move_pages 355 + .long sys_getcpu 356 + .long sys_epoll_pwait
+1 -1
drivers/video/backlight/hp680_bl.c
··· 19 19 #include <linux/backlight.h> 20 20 21 21 #include <asm/cpu/dac.h> 22 - #include <asm/hp6xx/hp6xx.h> 22 + #include <asm/hp6xx.h> 23 23 #include <asm/hd64461.h> 24 24 25 25 #define HP680_MAX_INTENSITY 255
+8 -2
include/asm-sh/irq.h
··· 327 327 */ 328 328 void init_IRQ_pint(void); 329 329 330 + struct ipr_data { 331 + unsigned int irq; 332 + unsigned int addr; /* Address of Interrupt Priority Register */ 333 + int shift; /* Shifts of the 16-bit data */ 334 + int priority; /* The priority */ 335 + }; 336 + 330 337 /* 331 338 * Function for "on chip support modules". 332 339 */ 333 - extern void make_ipr_irq(unsigned int irq, unsigned int addr, 334 - int pos, int priority); 340 + extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); 335 341 extern void make_imask_irq(unsigned int irq); 336 342 337 343 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
+4 -1
include/asm-sh/unistd.h
··· 324 324 #define __NR_sync_file_range 314 325 325 #define __NR_tee 315 326 326 #define __NR_vmsplice 316 327 + #define __NR_move_pages 317 328 + #define __NR_getcpu 318 329 + #define __NR_epoll_pwait 319 327 330 328 - #define NR_syscalls 317 331 + #define NR_syscalls 320 329 332 330 333 #ifdef __KERNEL__ 331 334