tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull perf fixes from Ingo Molnar:
"Misc kernel side fixes.

Generic:
- cgroup events counting fix

x86:
- Intel PMU truncated-parameter fix

- RDPMC fix

- API naming fix/rename

- uncore driver big-hardware PCI enumeration fix

- uncore driver filter constraint fix"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
perf/cgroup: Fix child event counting bug
perf/x86/intel/uncore: Fix multi-domain PCI CHA enumeration bug on Skylake servers
perf/x86/intel: Rename confusing 'freerunning PEBS' API and implementation to 'large PEBS'
perf/x86/intel/uncore: Add missing filter constraint for SKX CHA event
perf/x86/intel: Don't accidentally clear high bits in bdw_limit_period()
perf/x86/intel: Disable userspace RDPMC usage for large PEBS

Linus Torvalds eaf67993 6bacf660

options
unified split
Changed files
+49 -33
arch
x86
events
core.c
intel
core.c
ds.c
uncore_snbep.c
perf_event.h
kernel
events
core.c
+2 -1
arch/x86/events/core.c
··· 2118 2118 event->destroy(event); 2119 2119 } 2120 2120 2121 - if (READ_ONCE(x86_pmu.attr_rdpmc)) 2121 + if (READ_ONCE(x86_pmu.attr_rdpmc) && 2122 + !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) 2122 2123 event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; 2123 2124 2124 2125 return err;
+7 -7
arch/x86/events/intel/core.c
··· 2952 2952 return intel_pebs_aliases_precdist(event); 2953 2953 } 2954 2954 2955 - static unsigned long intel_pmu_free_running_flags(struct perf_event *event) 2955 + static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event) 2956 2956 { 2957 - unsigned long flags = x86_pmu.free_running_flags; 2957 + unsigned long flags = x86_pmu.large_pebs_flags; 2958 2958 2959 2959 if (event->attr.use_clockid) 2960 2960 flags &= ~PERF_SAMPLE_TIME; ··· 2976 2976 if (!event->attr.freq) { 2977 2977 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD; 2978 2978 if (!(event->attr.sample_type & 2979 - ~intel_pmu_free_running_flags(event))) 2980 - event->hw.flags |= PERF_X86_EVENT_FREERUNNING; 2979 + ~intel_pmu_large_pebs_flags(event))) 2980 + event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS; 2981 2981 } 2982 2982 if (x86_pmu.pebs_aliases) 2983 2983 x86_pmu.pebs_aliases(event); ··· 3194 3194 X86_CONFIG(.event=0xc0, .umask=0x01)) { 3195 3195 if (left < 128) 3196 3196 left = 128; 3197 - left &= ~0x3fu; 3197 + left &= ~0x3fULL; 3198 3198 } 3199 3199 return left; 3200 3200 } ··· 3460 3460 .event_map = intel_pmu_event_map, 3461 3461 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3462 3462 .apic = 1, 3463 - .free_running_flags = PEBS_FREERUNNING_FLAGS, 3463 + .large_pebs_flags = LARGE_PEBS_FLAGS, 3464 3464 3465 3465 /* 3466 3466 * Intel PMCs cannot be accessed sanely above 32-bit width, ··· 3502 3502 .event_map = intel_pmu_event_map, 3503 3503 .max_events = ARRAY_SIZE(intel_perfmon_event_map), 3504 3504 .apic = 1, 3505 - .free_running_flags = PEBS_FREERUNNING_FLAGS, 3505 + .large_pebs_flags = LARGE_PEBS_FLAGS, 3506 3506 /* 3507 3507 * Intel PMCs cannot be accessed sanely above 32 bit width, 3508 3508 * so we install an artificial 1<<31 period regardless of
+3 -3
arch/x86/events/intel/ds.c
··· 935 935 bool needed_cb = pebs_needs_sched_cb(cpuc); 936 936 937 937 cpuc->n_pebs++; 938 - if (hwc->flags & PERF_X86_EVENT_FREERUNNING) 938 + if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 939 939 cpuc->n_large_pebs++; 940 940 941 941 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); ··· 975 975 bool needed_cb = pebs_needs_sched_cb(cpuc); 976 976 977 977 cpuc->n_pebs--; 978 - if (hwc->flags & PERF_X86_EVENT_FREERUNNING) 978 + if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS) 979 979 cpuc->n_large_pebs--; 980 980 981 981 pebs_update_state(needed_cb, cpuc, event->ctx->pmu); ··· 1530 1530 x86_pmu.pebs_record_size = 1531 1531 sizeof(struct pebs_record_skl); 1532 1532 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm; 1533 - x86_pmu.free_running_flags |= PERF_SAMPLE_TIME; 1533 + x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; 1534 1534 break; 1535 1535 1536 1536 default:
+18 -14
arch/x86/events/intel/uncore_snbep.c
··· 3343 3343 SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4), 3344 3344 SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8), 3345 3345 SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8), 3346 + SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3), 3346 3347 EVENT_EXTRA_END 3347 3348 }; 3348 3349 ··· 3563 3562 NULL, 3564 3563 }; 3565 3564 3565 + /* 3566 + * To determine the number of CHAs, it should read bits 27:0 in the CAPID6 3567 + * register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083. 3568 + */ 3569 + #define SKX_CAPID6 0x9c 3570 + #define SKX_CHA_BIT_MASK GENMASK(27, 0) 3571 + 3566 3572 static int skx_count_chabox(void) 3567 3573 { 3568 - struct pci_dev *chabox_dev = NULL; 3569 - int bus, count = 0; 3574 + struct pci_dev *dev = NULL; 3575 + u32 val = 0; 3570 3576 3571 - while (1) { 3572 - chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev); 3573 - if (!chabox_dev) 3574 - break; 3575 - if (count == 0) 3576 - bus = chabox_dev->bus->number; 3577 - if (bus != chabox_dev->bus->number) 3578 - break; 3579 - count++; 3580 - } 3577 + dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev); 3578 + if (!dev) 3579 + goto out; 3581 3580 3582 - pci_dev_put(chabox_dev); 3583 - return count; 3581 + pci_read_config_dword(dev, SKX_CAPID6, &val); 3582 + val &= SKX_CHA_BIT_MASK; 3583 + out: 3584 + pci_dev_put(dev); 3585 + return hweight32(val); 3584 3586 } 3585 3587 3586 3588 void skx_uncore_cpu_init(void)
+3 -3
arch/x86/events/perf_event.h
··· 69 69 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */ 70 70 #define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */ 71 71 #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */ 72 - #define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */ 72 + #define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */ 73 73 74 74 75 75 struct amd_nb { ··· 88 88 * REGS_USER can be handled for events limited to ring 3. 89 89 * 90 90 */ 91 - #define PEBS_FREERUNNING_FLAGS \ 91 + #define LARGE_PEBS_FLAGS \ 92 92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \ 93 93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \ 94 94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \ ··· 608 608 struct event_constraint *pebs_constraints; 609 609 void (*pebs_aliases)(struct perf_event *event); 610 610 int max_pebs_events; 611 - unsigned long free_running_flags; 611 + unsigned long large_pebs_flags; 612 612 613 613 /* 614 614 * Intel LBR
+16 -5
kernel/events/core.c
··· 724 724 725 725 static inline void update_cgrp_time_from_cpuctx(struct perf_cpu_context *cpuctx) 726 726 { 727 - struct perf_cgroup *cgrp_out = cpuctx->cgrp; 728 - if (cgrp_out) 729 - __update_cgrp_time(cgrp_out); 727 + struct perf_cgroup *cgrp = cpuctx->cgrp; 728 + struct cgroup_subsys_state *css; 729 + 730 + if (cgrp) { 731 + for (css = &cgrp->css; css; css = css->parent) { 732 + cgrp = container_of(css, struct perf_cgroup, css); 733 + __update_cgrp_time(cgrp); 734 + } 735 + } 730 736 } 731 737 732 738 static inline void update_cgrp_time_from_event(struct perf_event *event) ··· 760 754 { 761 755 struct perf_cgroup *cgrp; 762 756 struct perf_cgroup_info *info; 757 + struct cgroup_subsys_state *css; 763 758 764 759 /* 765 760 * ctx->lock held by caller ··· 771 764 return; 772 765 773 766 cgrp = perf_cgroup_from_task(task, ctx); 774 - info = this_cpu_ptr(cgrp->info); 775 - info->timestamp = ctx->timestamp; 767 + 768 + for (css = &cgrp->css; css; css = css->parent) { 769 + cgrp = container_of(css, struct perf_cgroup, css); 770 + info = this_cpu_ptr(cgrp->info); 771 + info->timestamp = ctx->timestamp; 772 + } 776 773 } 777 774 778 775 static DEFINE_PER_CPU(struct list_head, cgrp_cpuctx_list);