tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge branch 'drm-fixes-3.19' of git://people.freedesktop.org/~agd5f/linux into drm-fixes

some minor radeon fixes.

* 'drm-fixes-3.19' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: integer underflow in radeon_cp_dispatch_texture()
drm/radeon: adjust default bapm settings for KV
drm/radeon: properly filter DP1.2 4k modes on non-DP1.2 hw
drm/radeon: fix sad_count check for dce3
drm/radeon: KV has three PPLLs (v2)

Dave Airlie eaee8ec4 f6624888

+14 -12
+4 -4
drivers/gpu/drm/radeon/atombios_crtc.c
··· 1851 1851 return pll; 1852 1852 } 1853 1853 /* otherwise, pick one of the plls */ 1854 - if ((rdev->family == CHIP_KAVERI) || 1855 - (rdev->family == CHIP_KABINI) || 1854 + if ((rdev->family == CHIP_KABINI) || 1856 1855 (rdev->family == CHIP_MULLINS)) { 1857 - /* KB/KV/ML has PPLL1 and PPLL2 */ 1856 + /* KB/ML has PPLL1 and PPLL2 */ 1858 1857 pll_in_use = radeon_get_pll_use_mask(crtc); 1859 1858 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1860 1859 return ATOM_PPLL2; ··· 1862 1863 DRM_ERROR("unable to allocate a PPLL\n"); 1863 1864 return ATOM_PPLL_INVALID; 1864 1865 } else { 1865 - /* CI has PPLL0, PPLL1, and PPLL2 */ 1866 + /* CI/KV has PPLL0, PPLL1, and PPLL2 */ 1866 1867 pll_in_use = radeon_get_pll_use_mask(crtc); 1867 1868 if (!(pll_in_use & (1 << ATOM_PPLL2))) 1868 1869 return ATOM_PPLL2; ··· 2154 2155 case ATOM_PPLL0: 2155 2156 /* disable the ppll */ 2156 2157 if ((rdev->family == CHIP_ARUBA) || 2158 + (rdev->family == CHIP_KAVERI) || 2157 2159 (rdev->family == CHIP_BONAIRE) || 2158 2160 (rdev->family == CHIP_HAWAII)) 2159 2161 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
+4
drivers/gpu/drm/radeon/atombios_dp.c
··· 492 492 struct radeon_connector_atom_dig *dig_connector; 493 493 int dp_clock; 494 494 495 + if ((mode->clock > 340000) && 496 + (!radeon_connector_is_dp12_capable(connector))) 497 + return MODE_CLOCK_HIGH; 498 + 495 499 if (!radeon_connector->con_priv) 496 500 return MODE_CLOCK_HIGH; 497 501 dig_connector = radeon_connector->con_priv;
+1 -1
drivers/gpu/drm/radeon/dce3_1_afmt.c
··· 103 103 } 104 104 105 105 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads); 106 - if (sad_count < 0) { 106 + if (sad_count <= 0) { 107 107 DRM_ERROR("Couldn't read SADs: %d\n", sad_count); 108 108 return; 109 109 }
+4 -6
drivers/gpu/drm/radeon/kv_dpm.c
··· 2745 2745 pi->enable_auto_thermal_throttling = true; 2746 2746 pi->disable_nb_ps3_in_battery = false; 2747 2747 if (radeon_bapm == -1) { 2748 - /* There are stability issues reported on with 2749 - * bapm enabled on an asrock system. 2750 - */ 2751 - if (rdev->pdev->subsystem_vendor == 0x1849) 2752 - pi->bapm_enable = false; 2753 - else 2748 + /* only enable bapm on KB, ML by default */ 2749 + if (rdev->family == CHIP_KABINI || rdev->family == CHIP_MULLINS) 2754 2750 pi->bapm_enable = true; 2751 + else 2752 + pi->bapm_enable = false; 2755 2753 } else if (radeon_bapm == 0) { 2756 2754 pi->bapm_enable = false; 2757 2755 } else {
+1 -1
drivers/gpu/drm/radeon/radeon_state.c
··· 1703 1703 u32 format; 1704 1704 u32 *buffer; 1705 1705 const u8 __user *data; 1706 - int size, dwords, tex_width, blit_width, spitch; 1706 + unsigned int size, dwords, tex_width, blit_width, spitch; 1707 1707 u32 height; 1708 1708 int i; 1709 1709 u32 texpitch, microtile;