[MIPS] Unify mips_fpu_soft_struct and mips_fpu_hard_structs.

+33 -33

arch/mips/kernel/asm-offsets.c

··· 141 141 void output_thread_fpu_defines(void) 142 142 { 143 143 offset("#define THREAD_FPR0 ", 144 - struct task_struct, thread.fpu.hard.fpr[0]); 144 + struct task_struct, thread.fpu.fpr[0]); 145 145 offset("#define THREAD_FPR1 ", 146 - struct task_struct, thread.fpu.hard.fpr[1]); 146 + struct task_struct, thread.fpu.fpr[1]); 147 147 offset("#define THREAD_FPR2 ", 148 - struct task_struct, thread.fpu.hard.fpr[2]); 148 + struct task_struct, thread.fpu.fpr[2]); 149 149 offset("#define THREAD_FPR3 ", 150 - struct task_struct, thread.fpu.hard.fpr[3]); 150 + struct task_struct, thread.fpu.fpr[3]); 151 151 offset("#define THREAD_FPR4 ", 152 - struct task_struct, thread.fpu.hard.fpr[4]); 152 + struct task_struct, thread.fpu.fpr[4]); 153 153 offset("#define THREAD_FPR5 ", 154 - struct task_struct, thread.fpu.hard.fpr[5]); 154 + struct task_struct, thread.fpu.fpr[5]); 155 155 offset("#define THREAD_FPR6 ", 156 - struct task_struct, thread.fpu.hard.fpr[6]); 156 + struct task_struct, thread.fpu.fpr[6]); 157 157 offset("#define THREAD_FPR7 ", 158 - struct task_struct, thread.fpu.hard.fpr[7]); 158 + struct task_struct, thread.fpu.fpr[7]); 159 159 offset("#define THREAD_FPR8 ", 160 - struct task_struct, thread.fpu.hard.fpr[8]); 160 + struct task_struct, thread.fpu.fpr[8]); 161 161 offset("#define THREAD_FPR9 ", 162 - struct task_struct, thread.fpu.hard.fpr[9]); 162 + struct task_struct, thread.fpu.fpr[9]); 163 163 offset("#define THREAD_FPR10 ", 164 - struct task_struct, thread.fpu.hard.fpr[10]); 164 + struct task_struct, thread.fpu.fpr[10]); 165 165 offset("#define THREAD_FPR11 ", 166 - struct task_struct, thread.fpu.hard.fpr[11]); 166 + struct task_struct, thread.fpu.fpr[11]); 167 167 offset("#define THREAD_FPR12 ", 168 - struct task_struct, thread.fpu.hard.fpr[12]); 168 + struct task_struct, thread.fpu.fpr[12]); 169 169 offset("#define THREAD_FPR13 ", 170 - struct task_struct, thread.fpu.hard.fpr[13]); 170 + struct task_struct, thread.fpu.fpr[13]); 171 171 offset("#define THREAD_FPR14 ", 172 - struct task_struct, thread.fpu.hard.fpr[14]); 172 + struct task_struct, thread.fpu.fpr[14]); 173 173 offset("#define THREAD_FPR15 ", 174 - struct task_struct, thread.fpu.hard.fpr[15]); 174 + struct task_struct, thread.fpu.fpr[15]); 175 175 offset("#define THREAD_FPR16 ", 176 - struct task_struct, thread.fpu.hard.fpr[16]); 176 + struct task_struct, thread.fpu.fpr[16]); 177 177 offset("#define THREAD_FPR17 ", 178 - struct task_struct, thread.fpu.hard.fpr[17]); 178 + struct task_struct, thread.fpu.fpr[17]); 179 179 offset("#define THREAD_FPR18 ", 180 - struct task_struct, thread.fpu.hard.fpr[18]); 180 + struct task_struct, thread.fpu.fpr[18]); 181 181 offset("#define THREAD_FPR19 ", 182 - struct task_struct, thread.fpu.hard.fpr[19]); 182 + struct task_struct, thread.fpu.fpr[19]); 183 183 offset("#define THREAD_FPR20 ", 184 - struct task_struct, thread.fpu.hard.fpr[20]); 184 + struct task_struct, thread.fpu.fpr[20]); 185 185 offset("#define THREAD_FPR21 ", 186 - struct task_struct, thread.fpu.hard.fpr[21]); 186 + struct task_struct, thread.fpu.fpr[21]); 187 187 offset("#define THREAD_FPR22 ", 188 - struct task_struct, thread.fpu.hard.fpr[22]); 188 + struct task_struct, thread.fpu.fpr[22]); 189 189 offset("#define THREAD_FPR23 ", 190 - struct task_struct, thread.fpu.hard.fpr[23]); 190 + struct task_struct, thread.fpu.fpr[23]); 191 191 offset("#define THREAD_FPR24 ", 192 - struct task_struct, thread.fpu.hard.fpr[24]); 192 + struct task_struct, thread.fpu.fpr[24]); 193 193 offset("#define THREAD_FPR25 ", 194 - struct task_struct, thread.fpu.hard.fpr[25]); 194 + struct task_struct, thread.fpu.fpr[25]); 195 195 offset("#define THREAD_FPR26 ", 196 - struct task_struct, thread.fpu.hard.fpr[26]); 196 + struct task_struct, thread.fpu.fpr[26]); 197 197 offset("#define THREAD_FPR27 ", 198 - struct task_struct, thread.fpu.hard.fpr[27]); 198 + struct task_struct, thread.fpu.fpr[27]); 199 199 offset("#define THREAD_FPR28 ", 200 - struct task_struct, thread.fpu.hard.fpr[28]); 200 + struct task_struct, thread.fpu.fpr[28]); 201 201 offset("#define THREAD_FPR29 ", 202 - struct task_struct, thread.fpu.hard.fpr[29]); 202 + struct task_struct, thread.fpu.fpr[29]); 203 203 offset("#define THREAD_FPR30 ", 204 - struct task_struct, thread.fpu.hard.fpr[30]); 204 + struct task_struct, thread.fpu.fpr[30]); 205 205 offset("#define THREAD_FPR31 ", 206 - struct task_struct, thread.fpu.hard.fpr[31]); 206 + struct task_struct, thread.fpu.fpr[31]); 207 207 208 208 offset("#define THREAD_FCR31 ", 209 - struct task_struct, thread.fpu.hard.fcr31); 209 + struct task_struct, thread.fpu.fcr31); 210 210 linefeed; 211 211 } 212 212

+1 -1

arch/mips/kernel/branch.c

··· 178 178 if (is_fpu_owner()) 179 179 asm volatile("cfc1\t%0,$31" : "=r" (fcr31)); 180 180 else 181 - fcr31 = current->thread.fpu.hard.fcr31; 181 + fcr31 = current->thread.fpu.fcr31; 182 182 preempt_enable(); 183 183 184 184 bit = (insn.i_format.rt >> 2);

+1 -1

arch/mips/kernel/irixsig.c

··· 260 260 261 261 for(i = 0; i < 32; i++) 262 262 error |= __get_user(fregs[i], &context->fpregs[i]); 263 - error |= __get_user(current->thread.fpu.hard.fcr31, &context->fpcsr); 263 + error |= __get_user(current->thread.fpu.fcr31, &context->fpcsr); 264 264 } 265 265 266 266 /* XXX do sigstack crapola here... XXX */

+8 -18

arch/mips/kernel/ptrace.c

··· 120 120 __put_user ((__u64) -1, i + (__u64 __user *) data); 121 121 } 122 122 123 + __put_user (child->thread.fpu.fcr31, data + 64); 124 + 123 125 if (cpu_has_fpu) { 124 126 unsigned int flags, tmp; 125 - 126 - __put_user (child->thread.fpu.hard.fcr31, data + 64); 127 127 128 128 preempt_disable(); 129 129 if (cpu_has_mipsmt) { ··· 142 142 preempt_enable(); 143 143 __put_user (tmp, data + 65); 144 144 } else { 145 - __put_user (child->thread.fpu.soft.fcr31, data + 64); 146 145 __put_user ((__u32) 0, data + 65); 147 146 } 148 147 ··· 161 162 for (i = 0; i < 32; i++) 162 163 __get_user (fregs[i], i + (__u64 __user *) data); 163 164 164 - if (cpu_has_fpu) 165 - __get_user (child->thread.fpu.hard.fcr31, data + 64); 166 - else 167 - __get_user (child->thread.fpu.soft.fcr31, data + 64); 165 + __get_user (child->thread.fpu.fcr31, data + 64); 168 166 169 167 /* FIR may not be written. */ 170 168 ··· 237 241 tmp = regs->lo; 238 242 break; 239 243 case FPC_CSR: 240 - if (cpu_has_fpu) 241 - tmp = child->thread.fpu.hard.fcr31; 242 - else 243 - tmp = child->thread.fpu.soft.fcr31; 244 + tmp = child->thread.fpu.fcr31; 244 245 break; 245 246 case FPC_EIR: { /* implementation / version register */ 246 247 unsigned int flags; ··· 329 336 330 337 if (!tsk_used_math(child)) { 331 338 /* FP not yet used */ 332 - memset(&child->thread.fpu.hard, ~0, 333 - sizeof(child->thread.fpu.hard)); 334 - child->thread.fpu.hard.fcr31 = 0; 339 + memset(&child->thread.fpu, ~0, 340 + sizeof(child->thread.fpu)); 341 + child->thread.fpu.fcr31 = 0; 335 342 } 336 343 #ifdef CONFIG_32BIT 337 344 /* ··· 362 369 regs->lo = data; 363 370 break; 364 371 case FPC_CSR: 365 - if (cpu_has_fpu) 366 - child->thread.fpu.hard.fcr31 = data; 367 - else 368 - child->thread.fpu.soft.fcr31 = data; 372 + child->thread.fpu.fcr31 = data; 369 373 break; 370 374 case DSP_BASE ... DSP_BASE + 5: { 371 375 dspreg_t *dregs;

+5 -11

arch/mips/kernel/ptrace32.c

··· 166 166 tmp = regs->lo; 167 167 break; 168 168 case FPC_CSR: 169 - if (cpu_has_fpu) 170 - tmp = child->thread.fpu.hard.fcr31; 171 - else 172 - tmp = child->thread.fpu.soft.fcr31; 169 + tmp = child->thread.fpu.fcr31; 173 170 break; 174 171 case FPC_EIR: { /* implementation / version register */ 175 172 unsigned int flags; ··· 285 288 286 289 if (!tsk_used_math(child)) { 287 290 /* FP not yet used */ 288 - memset(&child->thread.fpu.hard, ~0, 289 - sizeof(child->thread.fpu.hard)); 290 - child->thread.fpu.hard.fcr31 = 0; 291 + memset(&child->thread.fpu, ~0, 292 + sizeof(child->thread.fpu)); 293 + child->thread.fpu.fcr31 = 0; 291 294 } 292 295 /* 293 296 * The odd registers are actually the high order bits ··· 315 318 regs->lo = data; 316 319 break; 317 320 case FPC_CSR: 318 - if (cpu_has_fpu) 319 - child->thread.fpu.hard.fcr31 = data; 320 - else 321 - child->thread.fpu.soft.fcr31 = data; 321 + child->thread.fpu.fcr31 = data; 322 322 break; 323 323 case DSP_BASE ... DSP_BASE + 5: { 324 324 dspreg_t *dregs;

+4 -5

arch/mips/kernel/traps.c

··· 65 65 extern asmlinkage void handle_reserved(void); 66 66 67 67 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 68 - struct mips_fpu_soft_struct *ctx); 68 + struct mips_fpu_struct *ctx); 69 69 70 70 void (*board_be_init)(void); 71 71 int (*board_be_handler)(struct pt_regs *regs, int is_fixup); ··· 600 600 preempt_enable(); 601 601 602 602 /* Run the emulator */ 603 - sig = fpu_emulator_cop1Handler (regs, 604 - &current->thread.fpu.soft); 603 + sig = fpu_emulator_cop1Handler (regs, &current->thread.fpu); 605 604 606 605 preempt_disable(); 607 606 ··· 609 610 * We can't allow the emulated instruction to leave any of 610 611 * the cause bit set in $fcr31. 611 612 */ 612 - current->thread.fpu.soft.fcr31 &= ~FPU_CSR_ALL_X; 613 + current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X; 613 614 614 615 /* Restore the hardware register state */ 615 616 restore_fp(current); ··· 754 755 755 756 if (!cpu_has_fpu) { 756 757 int sig = fpu_emulator_cop1Handler(regs, 757 - &current->thread.fpu.soft); 758 + &current->thread.fpu); 758 759 if (sig) 759 760 force_sig(sig, current); 760 761 #ifdef CONFIG_MIPS_MT_FPAFF

+7 -8

arch/mips/math-emu/cp1emu.c

··· 60 60 61 61 /* Function which emulates a floating point instruction. */ 62 62 63 - static int fpu_emu(struct pt_regs *, struct mips_fpu_soft_struct *, 63 + static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *, 64 64 mips_instruction); 65 65 66 66 #if __mips >= 4 && __mips != 32 67 67 static int fpux_emu(struct pt_regs *, 68 - struct mips_fpu_soft_struct *, mips_instruction); 68 + struct mips_fpu_struct *, mips_instruction); 69 69 #endif 70 70 71 - /* Further private data for which no space exists in mips_fpu_soft_struct */ 71 + /* Further private data for which no space exists in mips_fpu_struct */ 72 72 73 73 struct mips_fpu_emulator_stats fpuemustats; 74 74 ··· 203 203 * Two instructions if the instruction is in a branch delay slot. 204 204 */ 205 205 206 - static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) 206 + static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) 207 207 { 208 208 mips_instruction ir; 209 209 void * emulpc, *contpc; ··· 595 595 DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg); 596 596 DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg); 597 597 598 - static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, 598 + static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 599 599 mips_instruction ir) 600 600 { 601 601 unsigned rcsr = 0; /* resulting csr */ ··· 759 759 /* 760 760 * Emulate a single COP1 arithmetic instruction. 761 761 */ 762 - static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, 762 + static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, 763 763 mips_instruction ir) 764 764 { 765 765 int rfmt; /* resulting format */ ··· 1233 1233 return 0; 1234 1234 } 1235 1235 1236 - int fpu_emulator_cop1Handler(struct pt_regs *xcp, 1237 - struct mips_fpu_soft_struct *ctx) 1236 + int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx) 1238 1237 { 1239 1238 unsigned long oldepc, prevepc; 1240 1239 mips_instruction insn;

+1 -1

arch/mips/math-emu/ieee754.h

··· 329 329 unsigned pad0:7; 330 330 #endif 331 331 }; 332 - #define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.soft.fcr31)) 332 + #define ieee754_csr (*(struct _ieee754_csr *)(&current->thread.fpu.fcr31)) 333 333 334 334 static inline unsigned ieee754_getrm(void) 335 335 {

+10 -14

arch/mips/math-emu/kernel_linkage.c

··· 39 39 printk("Algorithmics/MIPS FPU Emulator v1.5\n"); 40 40 } 41 41 42 - current->thread.fpu.soft.fcr31 = 0; 42 + current->thread.fpu.fcr31 = 0; 43 43 for (i = 0; i < 32; i++) { 44 - current->thread.fpu.soft.fpr[i] = SIGNALLING_NAN; 44 + current->thread.fpu.fpr[i] = SIGNALLING_NAN; 45 45 } 46 46 } 47 47 ··· 59 59 60 60 for (i = 0; i < 32; i++) { 61 61 err |= 62 - __put_user(current->thread.fpu.soft.fpr[i], 63 - &sc->sc_fpregs[i]); 62 + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 64 63 } 65 - err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 64 + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); 66 65 67 66 return err; 68 67 } ··· 73 74 74 75 for (i = 0; i < 32; i++) { 75 76 err |= 76 - __get_user(current->thread.fpu.soft.fpr[i], 77 - &sc->sc_fpregs[i]); 77 + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 78 78 } 79 - err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 79 + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); 80 80 81 81 return err; 82 82 } ··· 92 94 93 95 for (i = 0; i < 32; i+=2) { 94 96 err |= 95 - __put_user(current->thread.fpu.soft.fpr[i], 96 - &sc->sc_fpregs[i]); 97 + __put_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 97 98 } 98 - err |= __put_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 99 + err |= __put_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); 99 100 100 101 return err; 101 102 } ··· 106 109 107 110 for (i = 0; i < 32; i+=2) { 108 111 err |= 109 - __get_user(current->thread.fpu.soft.fpr[i], 110 - &sc->sc_fpregs[i]); 112 + __get_user(current->thread.fpu.fpr[i], &sc->sc_fpregs[i]); 111 113 } 112 - err |= __get_user(current->thread.fpu.soft.fcr31, &sc->sc_fpc_csr); 114 + err |= __get_user(current->thread.fpu.fcr31, &sc->sc_fpc_csr); 113 115 114 116 return err; 115 117 }

+1 -2

include/asm-mips/fpu.h

··· 138 138 if (cpu_has_fpu) { 139 139 if ((tsk == current) && __is_fpu_owner()) 140 140 _save_fp(current); 141 - return tsk->thread.fpu.hard.fpr; 142 141 } 143 142 144 - return tsk->thread.fpu.soft.fpr; 143 + return tsk->thread.fpu.fpr; 145 144 } 146 145 147 146 #endif /* _ASM_FPU_H */

+2 -2

include/asm-mips/fpu_emulator.h

··· 12 12 * with this program; if not, write to the Free Software Foundation, Inc., 13 13 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 14 14 * 15 - * Further private data for which no space exists in mips_fpu_soft_struct. 16 - * This should be subsumed into the mips_fpu_soft_struct structure as 15 + * Further private data for which no space exists in mips_fpu_struct. 16 + * This should be subsumed into the mips_fpu_struct structure as 17 17 * defined in processor.h as soon as the absurd wired absolute assembler 18 18 * offsets become dynamic at compile time. 19 19 *

+3 -13

include/asm-mips/processor.h

··· 71 71 72 72 typedef __u64 fpureg_t; 73 73 74 - struct mips_fpu_hard_struct { 75 - fpureg_t fpr[NUM_FPU_REGS]; 76 - unsigned int fcr31; 77 - }; 78 - 79 74 /* 80 75 * It would be nice to add some more fields for emulator statistics, but there 81 76 * are a number of fixed offsets in offset.h and elsewhere that would have to ··· 78 83 * the FPU emulator for now. See asm-mips/fpu_emulator.h. 79 84 */ 80 85 81 - struct mips_fpu_soft_struct { 86 + struct mips_fpu_struct { 82 87 fpureg_t fpr[NUM_FPU_REGS]; 83 88 unsigned int fcr31; 84 89 }; 85 90 86 - union mips_fpu_union { 87 - struct mips_fpu_hard_struct hard; 88 - struct mips_fpu_soft_struct soft; 89 - }; 90 - 91 91 #define INIT_FPU { \ 92 - {{0,},} \ 92 + {0,} \ 93 93 } 94 94 95 95 #define NUM_DSP_REGS 6 ··· 123 133 unsigned long cp0_status; 124 134 125 135 /* Saved fpu/fpu emulator stuff. */ 126 - union mips_fpu_union fpu; 136 + struct mips_fpu_struct fpu; 127 137 #ifdef CONFIG_MIPS_MT_FPAFF 128 138 /* Emulated instruction count */ 129 139 unsigned long emulated_fp;