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I/OAT: do not set DCACTRL_CMPL_WRITE_ENABLE for I/OAT ver.3

Flag DCACTRL_CMPL_WRITE_ENABLE is valid only for I/OAT ver.2
so it should not be set for I/OAT ver.3.

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Shannon Nelson <shannon.nelson@intel.com>
Acked-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

authored by

Maciej Sosnowski and committed by
Dan Williams ea9c717d 49bc4636

+7 -5
+7 -5
drivers/dma/ioat_dma.c
··· 189 189 ioat_chan->xfercap = xfercap; 190 190 ioat_chan->desccount = 0; 191 191 INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2); 192 - if (ioat_chan->device->version != IOAT_VER_1_2) { 193 - writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE 194 - | IOAT_DMA_DCA_ANY_CPU, 195 - ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 196 - } 192 + if (ioat_chan->device->version == IOAT_VER_2_0) 193 + writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE | 194 + IOAT_DMA_DCA_ANY_CPU, 195 + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 196 + else if (ioat_chan->device->version == IOAT_VER_3_0) 197 + writel(IOAT_DMA_DCA_ANY_CPU, 198 + ioat_chan->reg_base + IOAT_DCACTRL_OFFSET); 197 199 spin_lock_init(&ioat_chan->cleanup_lock); 198 200 spin_lock_init(&ioat_chan->desc_lock); 199 201 INIT_LIST_HEAD(&ioat_chan->free_desc);