Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

counter: stm32-timer-cnt: Provide defines for slave mode selection

The STM32 timer permits configuration of the counter encoder mode via
the slave mode control register (SMCR) slave mode selection (SMS) bits.
This patch provides preprocessor defines for the supported encoder
modes.

Cc: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Reviewed-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Link: https://lore.kernel.org/r/ad3d9cd7af580d586316d368f74964cbc394f981.1630031207.git.vilhelm.gray@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

authored by

William Breathitt Gray and committed by
Jonathan Cameron
ea434ff8 05593a3f

+12 -8
+8 -8
drivers/counter/stm32-timer-cnt.c
··· 93 93 regmap_read(priv->regmap, TIM_SMCR, &smcr); 94 94 95 95 switch (smcr & TIM_SMCR_SMS) { 96 - case 0: 96 + case TIM_SMCR_SMS_SLAVE_MODE_DISABLED: 97 97 *function = STM32_COUNT_SLAVE_MODE_DISABLED; 98 98 return 0; 99 - case 1: 99 + case TIM_SMCR_SMS_ENCODER_MODE_1: 100 100 *function = STM32_COUNT_ENCODER_MODE_1; 101 101 return 0; 102 - case 2: 102 + case TIM_SMCR_SMS_ENCODER_MODE_2: 103 103 *function = STM32_COUNT_ENCODER_MODE_2; 104 104 return 0; 105 - case 3: 105 + case TIM_SMCR_SMS_ENCODER_MODE_3: 106 106 *function = STM32_COUNT_ENCODER_MODE_3; 107 107 return 0; 108 108 default: ··· 119 119 120 120 switch (function) { 121 121 case STM32_COUNT_SLAVE_MODE_DISABLED: 122 - sms = 0; 122 + sms = TIM_SMCR_SMS_SLAVE_MODE_DISABLED; 123 123 break; 124 124 case STM32_COUNT_ENCODER_MODE_1: 125 - sms = 1; 125 + sms = TIM_SMCR_SMS_ENCODER_MODE_1; 126 126 break; 127 127 case STM32_COUNT_ENCODER_MODE_2: 128 - sms = 2; 128 + sms = TIM_SMCR_SMS_ENCODER_MODE_2; 129 129 break; 130 130 case STM32_COUNT_ENCODER_MODE_3: 131 - sms = 3; 131 + sms = TIM_SMCR_SMS_ENCODER_MODE_3; 132 132 break; 133 133 default: 134 134 return -EINVAL;
+4
include/linux/mfd/stm32-timers.h
··· 82 82 #define MAX_TIM_ICPSC 0x3 83 83 #define TIM_CR2_MMS_SHIFT 4 84 84 #define TIM_CR2_MMS2_SHIFT 20 85 + #define TIM_SMCR_SMS_SLAVE_MODE_DISABLED 0 /* counts on internal clock when CEN=1 */ 86 + #define TIM_SMCR_SMS_ENCODER_MODE_1 1 /* counts TI1FP1 edges, depending on TI2FP2 level */ 87 + #define TIM_SMCR_SMS_ENCODER_MODE_2 2 /* counts TI2FP2 edges, depending on TI1FP1 level */ 88 + #define TIM_SMCR_SMS_ENCODER_MODE_3 3 /* counts on both TI1FP1 and TI2FP2 edges */ 85 89 #define TIM_SMCR_TS_SHIFT 4 86 90 #define TIM_BDTR_BKF_MASK 0xF 87 91 #define TIM_BDTR_BKF_SHIFT(x) (16 + (x) * 4)