tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'qcom-ebi2-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/drivers
Pull "Qualcomm EBI2 bindings and bus driver" from Linus Walleij
* tag 'qcom-ebi2-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
bus: qcom: add EBI2 driver
bus: qcom: add EBI2 device tree bindings
Acked-by: Andy Gross <andy.gross@linaro.org>
+554
+138
Documentation/devicetree/bindings/bus/qcom,ebi2.txt
+138
Documentation/devicetree/bindings/bus/qcom,ebi2.txt
···
1
+
Qualcomm External Bus Interface 2 (EBI2)
2
+
3
+
The EBI2 contains two peripheral blocks: XMEM and LCDC. The XMEM handles any
4
+
external memory (such as NAND or other memory-mapped peripherals) whereas
5
+
LCDC handles LCD displays.
6
+
7
+
As it says it connects devices to an external bus interface, meaning address
8
+
lines (up to 9 address lines so can only address 1KiB external memory space),
9
+
data lines (16 bits), OE (output enable), ADV (address valid, used on some
10
+
NOR flash memories), WE (write enable). This on top of 6 different chip selects
11
+
(CS0 thru CS5) so that in theory 6 different devices can be connected.
12
+
13
+
Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
14
+
and the bus can only come out on these pins, however if some of the pins are
15
+
unused they can be left unconnected or remuxed to be used as GPIO or in some
16
+
cases other orthogonal functions as well.
17
+
18
+
Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
19
+
20
+
The chip selects have the following memory range assignments. This region of
21
+
memory is referred to as "Chip Peripheral SS FPB0" and is 168MB big.
22
+
23
+
Chip Select Physical address base
24
+
CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
25
+
CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
26
+
CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
27
+
CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
28
+
CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
29
+
CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
30
+
31
+
The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
32
+
August 6, 2012 contains some incomplete documentation of the EBI2.
33
+
34
+
FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
35
+
We have not been able to figure out which bit fields these correspond to
36
+
in the hardware, or what valid values exist. The current hypothesis is that
37
+
this is something just used on the FAST chip selects and that the SLOW
38
+
chip selects are understood fully. There is also a "byte device enable"
39
+
flag somewhere for 8bit memories.
40
+
41
+
FIXME: The chipselects have SLOW and FAST configuration registers. It's a bit
42
+
unclear what this means, if they are mutually exclusive or can be used
43
+
together, or if some chip selects are hardwired to be FAST and others are SLOW
44
+
by design.
45
+
46
+
The XMEM registers are totally undocumented but could be partially decoded
47
+
because the Cypress AN49576 Antioch Westbridge apparently has suspiciously
48
+
similar register layout, see: http://www.cypress.com/file/105771/download
49
+
50
+
Required properties:
51
+
- compatible: should be one of:
52
+
"qcom,msm8660-ebi2"
53
+
"qcom,apq8060-ebi2"
54
+
- #address-cells: shoule be <2>: the first cell is the chipselect,
55
+
the second cell is the offset inside the memory range
56
+
- #size-cells: should be <1>
57
+
- ranges: should be set to:
58
+
ranges = <0 0x0 0x1a800000 0x00800000>,
59
+
<1 0x0 0x1b000000 0x00800000>,
60
+
<2 0x0 0x1b800000 0x00800000>,
61
+
<3 0x0 0x1d000000 0x08000000>,
62
+
<4 0x0 0x1c800000 0x00800000>,
63
+
<5 0x0 0x1c000000 0x00800000>;
64
+
- reg: two ranges of registers: EBI2 config and XMEM config areas
65
+
- reg-names: should be "ebi2", "xmem"
66
+
- clocks: two clocks, EBI_2X and EBI
67
+
- clock-names: shoule be "ebi2x", "ebi2"
68
+
69
+
Optional subnodes:
70
+
- Nodes inside the EBI2 will be considered device nodes.
71
+
72
+
The following optional properties are properties that can be tagged onto
73
+
any device subnode. We are assuming that there can be only ONE device per
74
+
chipselect subnode, else the properties will become ambigous.
75
+
76
+
Optional properties arrays for SLOW chip selects:
77
+
- qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
78
+
drive the data bus after OE is de-asserted, in order to avoid contention on
79
+
the data bus. They are inserted when reading one CS and switching to another
80
+
CS or read followed by write on the same CS. Valid values 0 thru 15. Minimum
81
+
value is actually 1, so a value of 0 will still yield 1 recovery cycle.
82
+
- qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
83
+
inserted after every write minimum 1. The data out is driven from the time
84
+
WE is asserted until CS is asserted. With a hold of 1 (value = 0), the CS
85
+
stays active for 1 extra cycle etc. Valid values 0 thru 15.
86
+
- qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
87
+
the first write to a page or burst memory. Valid values 0 thru 255.
88
+
- qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
89
+
first read to a page or burst memory. Valid values 0 thru 255.
90
+
- qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
91
+
cycle. Valid values 0 thru 15.
92
+
- qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
93
+
cycle. Valid values 0 thru 15.
94
+
95
+
Optional properties arrays for FAST chip selects:
96
+
- qcom,xmem-address-hold-enable: this is a boolean property stating that we
97
+
shall hold the address for an extra cycle to meet hold time requirements
98
+
with ADV assertion.
99
+
- qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
100
+
assertion, with respect to the cycle where ADV (address valid) is asserted.
101
+
2 means 2 cycles between ADV and OE. Valid values 0, 1, 2 or 3.
102
+
- qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
103
+
read transfer. For a single read trandfer this will be the time from CS
104
+
assertion to OE assertion. Valid values 0 thru 15.
105
+
106
+
107
+
Example:
108
+
109
+
ebi2@1a100000 {
110
+
compatible = "qcom,apq8060-ebi2";
111
+
#address-cells = <2>;
112
+
#size-cells = <1>;
113
+
ranges = <0 0x0 0x1a800000 0x00800000>,
114
+
<1 0x0 0x1b000000 0x00800000>,
115
+
<2 0x0 0x1b800000 0x00800000>,
116
+
<3 0x0 0x1d000000 0x08000000>,
117
+
<4 0x0 0x1c800000 0x00800000>,
118
+
<5 0x0 0x1c000000 0x00800000>;
119
+
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
120
+
reg-names = "ebi2", "xmem";
121
+
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
122
+
clock-names = "ebi2x", "ebi2";
123
+
/* Make sure to set up the pin control for the EBI2 */
124
+
pinctrl-names = "default";
125
+
pinctrl-0 = <&foo_ebi2_pins>;
126
+
127
+
foo-ebi2@2,0 {
128
+
compatible = "foo";
129
+
reg = <2 0x0 0x100>;
130
+
(...)
131
+
qcom,xmem-recovery-cycles = <0>;
132
+
qcom,xmem-write-hold-cycles = <3>;
133
+
qcom,xmem-write-delta-cycles = <31>;
134
+
qcom,xmem-read-delta-cycles = <28>;
135
+
qcom,xmem-write-wait-cycles = <9>;
136
+
qcom,xmem-read-wait-cycles = <9>;
137
+
};
138
+
};
+7
drivers/bus/Kconfig
+7
drivers/bus/Kconfig
···
108
108
OCP2SCP and in OMAP5, both USB PHY and SATA PHY is connected via
109
109
OCP2SCP.
110
110
111
+
config QCOM_EBI2
112
+
bool "Qualcomm External Bus Interface 2 (EBI2)"
113
+
help
114
+
Say y here to enable support for the Qualcomm External Bus
115
+
Interface 2, which can be used to connect things like NAND Flash,
116
+
SRAM, ethernet adapters, FPGAs and LCD displays.
117
+
111
118
config SIMPLE_PM_BUS
112
119
bool "Simple Power-Managed Bus Driver"
113
120
depends on OF && PM
+1
drivers/bus/Makefile
+1
drivers/bus/Makefile
···
15
15
obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
16
16
17
17
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
18
+
obj-$(CONFIG_QCOM_EBI2) += qcom-ebi2.o
18
19
obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
19
20
obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
20
21
obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
+408
drivers/bus/qcom-ebi2.c
+408
drivers/bus/qcom-ebi2.c
···
1
+
/*
2
+
* Qualcomm External Bus Interface 2 (EBI2) driver
3
+
* an older version of the Qualcomm Parallel Interface Controller (QPIC)
4
+
*
5
+
* Copyright (C) 2016 Linaro Ltd.
6
+
*
7
+
* Author: Linus Walleij <linus.walleij@linaro.org>
8
+
*
9
+
* This program is free software; you can redistribute it and/or modify
10
+
* it under the terms of the GNU General Public License version 2, as
11
+
* published by the Free Software Foundation.
12
+
*
13
+
* See the device tree bindings for this block for more details on the
14
+
* hardware.
15
+
*/
16
+
17
+
#include <linux/module.h>
18
+
#include <linux/clk.h>
19
+
#include <linux/err.h>
20
+
#include <linux/io.h>
21
+
#include <linux/of.h>
22
+
#include <linux/of_platform.h>
23
+
#include <linux/init.h>
24
+
#include <linux/io.h>
25
+
#include <linux/slab.h>
26
+
#include <linux/platform_device.h>
27
+
#include <linux/bitops.h>
28
+
29
+
/*
30
+
* CS0, CS1, CS4 and CS5 are two bits wide, CS2 and CS3 are one bit.
31
+
*/
32
+
#define EBI2_CS0_ENABLE_MASK BIT(0)|BIT(1)
33
+
#define EBI2_CS1_ENABLE_MASK BIT(2)|BIT(3)
34
+
#define EBI2_CS2_ENABLE_MASK BIT(4)
35
+
#define EBI2_CS3_ENABLE_MASK BIT(5)
36
+
#define EBI2_CS4_ENABLE_MASK BIT(6)|BIT(7)
37
+
#define EBI2_CS5_ENABLE_MASK BIT(8)|BIT(9)
38
+
#define EBI2_CSN_MASK GENMASK(9, 0)
39
+
40
+
#define EBI2_XMEM_CFG 0x0000 /* Power management etc */
41
+
42
+
/*
43
+
* SLOW CSn CFG
44
+
*
45
+
* Bits 31-28: RECOVERY recovery cycles (0 = 1, 1 = 2 etc) this is the time the
46
+
* memory continues to drive the data bus after OE is de-asserted.
47
+
* Inserted when reading one CS and switching to another CS or read
48
+
* followed by write on the same CS. Valid values 0 thru 15.
49
+
* Bits 27-24: WR_HOLD write hold cycles, these are extra cycles inserted after
50
+
* every write minimum 1. The data out is driven from the time WE is
51
+
* asserted until CS is asserted. With a hold of 1, the CS stays
52
+
* active for 1 extra cycle etc. Valid values 0 thru 15.
53
+
* Bits 23-16: WR_DELTA initial latency for write cycles inserted for the first
54
+
* write to a page or burst memory
55
+
* Bits 15-8: RD_DELTA initial latency for read cycles inserted for the first
56
+
* read to a page or burst memory
57
+
* Bits 7-4: WR_WAIT number of wait cycles for every write access, 0=1 cycle
58
+
* so 1 thru 16 cycles.
59
+
* Bits 3-0: RD_WAIT number of wait cycles for every read access, 0=1 cycle
60
+
* so 1 thru 16 cycles.
61
+
*/
62
+
#define EBI2_XMEM_CS0_SLOW_CFG 0x0008
63
+
#define EBI2_XMEM_CS1_SLOW_CFG 0x000C
64
+
#define EBI2_XMEM_CS2_SLOW_CFG 0x0010
65
+
#define EBI2_XMEM_CS3_SLOW_CFG 0x0014
66
+
#define EBI2_XMEM_CS4_SLOW_CFG 0x0018
67
+
#define EBI2_XMEM_CS5_SLOW_CFG 0x001C
68
+
69
+
#define EBI2_XMEM_RECOVERY_SHIFT 28
70
+
#define EBI2_XMEM_WR_HOLD_SHIFT 24
71
+
#define EBI2_XMEM_WR_DELTA_SHIFT 16
72
+
#define EBI2_XMEM_RD_DELTA_SHIFT 8
73
+
#define EBI2_XMEM_WR_WAIT_SHIFT 4
74
+
#define EBI2_XMEM_RD_WAIT_SHIFT 0
75
+
76
+
/*
77
+
* FAST CSn CFG
78
+
* Bits 31-28: ?
79
+
* Bits 27-24: RD_HOLD: the length in cycles of the first segment of a read
80
+
* transfer. For a single read trandfer this will be the time
81
+
* from CS assertion to OE assertion.
82
+
* Bits 18-24: ?
83
+
* Bits 17-16: ADV_OE_RECOVERY, the number of cycles elapsed before an OE
84
+
* assertion, with respect to the cycle where ADV is asserted.
85
+
* 2 means 2 cycles between ADV and OE. Values 0, 1, 2 or 3.
86
+
* Bits 5: ADDR_HOLD_ENA, The address is held for an extra cycle to meet
87
+
* hold time requirements with ADV assertion.
88
+
*
89
+
* The manual mentions "write precharge cycles" and "precharge cycles".
90
+
* We have not been able to figure out which bit fields these correspond to
91
+
* in the hardware, or what valid values exist. The current hypothesis is that
92
+
* this is something just used on the FAST chip selects. There is also a "byte
93
+
* device enable" flag somewhere for 8bit memories.
94
+
*/
95
+
#define EBI2_XMEM_CS0_FAST_CFG 0x0028
96
+
#define EBI2_XMEM_CS1_FAST_CFG 0x002C
97
+
#define EBI2_XMEM_CS2_FAST_CFG 0x0030
98
+
#define EBI2_XMEM_CS3_FAST_CFG 0x0034
99
+
#define EBI2_XMEM_CS4_FAST_CFG 0x0038
100
+
#define EBI2_XMEM_CS5_FAST_CFG 0x003C
101
+
102
+
#define EBI2_XMEM_RD_HOLD_SHIFT 24
103
+
#define EBI2_XMEM_ADV_OE_RECOVERY_SHIFT 16
104
+
#define EBI2_XMEM_ADDR_HOLD_ENA_SHIFT 5
105
+
106
+
/**
107
+
* struct cs_data - struct with info on a chipselect setting
108
+
* @enable_mask: mask to enable the chipselect in the EBI2 config
109
+
* @slow_cfg0: offset to XMEMC slow CS config
110
+
* @fast_cfg1: offset to XMEMC fast CS config
111
+
*/
112
+
struct cs_data {
113
+
u32 enable_mask;
114
+
u16 slow_cfg;
115
+
u16 fast_cfg;
116
+
};
117
+
118
+
static const struct cs_data cs_info[] = {
119
+
{
120
+
/* CS0 */
121
+
.enable_mask = EBI2_CS0_ENABLE_MASK,
122
+
.slow_cfg = EBI2_XMEM_CS0_SLOW_CFG,
123
+
.fast_cfg = EBI2_XMEM_CS0_FAST_CFG,
124
+
},
125
+
{
126
+
/* CS1 */
127
+
.enable_mask = EBI2_CS1_ENABLE_MASK,
128
+
.slow_cfg = EBI2_XMEM_CS1_SLOW_CFG,
129
+
.fast_cfg = EBI2_XMEM_CS1_FAST_CFG,
130
+
},
131
+
{
132
+
/* CS2 */
133
+
.enable_mask = EBI2_CS2_ENABLE_MASK,
134
+
.slow_cfg = EBI2_XMEM_CS2_SLOW_CFG,
135
+
.fast_cfg = EBI2_XMEM_CS2_FAST_CFG,
136
+
},
137
+
{
138
+
/* CS3 */
139
+
.enable_mask = EBI2_CS3_ENABLE_MASK,
140
+
.slow_cfg = EBI2_XMEM_CS3_SLOW_CFG,
141
+
.fast_cfg = EBI2_XMEM_CS3_FAST_CFG,
142
+
},
143
+
{
144
+
/* CS4 */
145
+
.enable_mask = EBI2_CS4_ENABLE_MASK,
146
+
.slow_cfg = EBI2_XMEM_CS4_SLOW_CFG,
147
+
.fast_cfg = EBI2_XMEM_CS4_FAST_CFG,
148
+
},
149
+
{
150
+
/* CS5 */
151
+
.enable_mask = EBI2_CS5_ENABLE_MASK,
152
+
.slow_cfg = EBI2_XMEM_CS5_SLOW_CFG,
153
+
.fast_cfg = EBI2_XMEM_CS5_FAST_CFG,
154
+
},
155
+
};
156
+
157
+
/**
158
+
* struct ebi2_xmem_prop - describes an XMEM config property
159
+
* @prop: the device tree binding name
160
+
* @max: maximum value for the property
161
+
* @slowreg: true if this property is in the SLOW CS config register
162
+
* else it is assumed to be in the FAST config register
163
+
* @shift: the bit field start in the SLOW or FAST register for this
164
+
* property
165
+
*/
166
+
struct ebi2_xmem_prop {
167
+
const char *prop;
168
+
u32 max;
169
+
bool slowreg;
170
+
u16 shift;
171
+
};
172
+
173
+
static const struct ebi2_xmem_prop xmem_props[] = {
174
+
{
175
+
.prop = "qcom,xmem-recovery-cycles",
176
+
.max = 15,
177
+
.slowreg = true,
178
+
.shift = EBI2_XMEM_RECOVERY_SHIFT,
179
+
},
180
+
{
181
+
.prop = "qcom,xmem-write-hold-cycles",
182
+
.max = 15,
183
+
.slowreg = true,
184
+
.shift = EBI2_XMEM_WR_HOLD_SHIFT,
185
+
},
186
+
{
187
+
.prop = "qcom,xmem-write-delta-cycles",
188
+
.max = 255,
189
+
.slowreg = true,
190
+
.shift = EBI2_XMEM_WR_DELTA_SHIFT,
191
+
},
192
+
{
193
+
.prop = "qcom,xmem-read-delta-cycles",
194
+
.max = 255,
195
+
.slowreg = true,
196
+
.shift = EBI2_XMEM_RD_DELTA_SHIFT,
197
+
},
198
+
{
199
+
.prop = "qcom,xmem-write-wait-cycles",
200
+
.max = 15,
201
+
.slowreg = true,
202
+
.shift = EBI2_XMEM_WR_WAIT_SHIFT,
203
+
},
204
+
{
205
+
.prop = "qcom,xmem-read-wait-cycles",
206
+
.max = 15,
207
+
.slowreg = true,
208
+
.shift = EBI2_XMEM_RD_WAIT_SHIFT,
209
+
},
210
+
{
211
+
.prop = "qcom,xmem-address-hold-enable",
212
+
.max = 1, /* boolean prop */
213
+
.slowreg = false,
214
+
.shift = EBI2_XMEM_ADDR_HOLD_ENA_SHIFT,
215
+
},
216
+
{
217
+
.prop = "qcom,xmem-adv-to-oe-recovery-cycles",
218
+
.max = 3,
219
+
.slowreg = false,
220
+
.shift = EBI2_XMEM_ADV_OE_RECOVERY_SHIFT,
221
+
},
222
+
{
223
+
.prop = "qcom,xmem-read-hold-cycles",
224
+
.max = 15,
225
+
.slowreg = false,
226
+
.shift = EBI2_XMEM_RD_HOLD_SHIFT,
227
+
},
228
+
};
229
+
230
+
static void qcom_ebi2_setup_chipselect(struct device_node *np,
231
+
struct device *dev,
232
+
void __iomem *ebi2_base,
233
+
void __iomem *ebi2_xmem,
234
+
u32 csindex)
235
+
{
236
+
const struct cs_data *csd;
237
+
u32 slowcfg, fastcfg;
238
+
u32 val;
239
+
int ret;
240
+
int i;
241
+
242
+
csd = &cs_info[csindex];
243
+
val = readl(ebi2_base);
244
+
val |= csd->enable_mask;
245
+
writel(val, ebi2_base);
246
+
dev_dbg(dev, "enabled CS%u\n", csindex);
247
+
248
+
/* Next set up the XMEMC */
249
+
slowcfg = 0;
250
+
fastcfg = 0;
251
+
252
+
for (i = 0; i < ARRAY_SIZE(xmem_props); i++) {
253
+
const struct ebi2_xmem_prop *xp = &xmem_props[i];
254
+
255
+
/* All are regular u32 values */
256
+
ret = of_property_read_u32(np, xp->prop, &val);
257
+
if (ret) {
258
+
dev_dbg(dev, "could not read %s for CS%d\n",
259
+
xp->prop, csindex);
260
+
continue;
261
+
}
262
+
263
+
/* First check boolean props */
264
+
if (xp->max == 1 && val) {
265
+
if (xp->slowreg)
266
+
slowcfg |= BIT(xp->shift);
267
+
else
268
+
fastcfg |= BIT(xp->shift);
269
+
dev_dbg(dev, "set %s flag\n", xp->prop);
270
+
continue;
271
+
}
272
+
273
+
/* We're dealing with an u32 */
274
+
if (val > xp->max) {
275
+
dev_err(dev,
276
+
"too high value for %s: %u, capped at %u\n",
277
+
xp->prop, val, xp->max);
278
+
val = xp->max;
279
+
}
280
+
if (xp->slowreg)
281
+
slowcfg |= (val << xp->shift);
282
+
else
283
+
fastcfg |= (val << xp->shift);
284
+
dev_dbg(dev, "set %s to %u\n", xp->prop, val);
285
+
}
286
+
287
+
dev_info(dev, "CS%u: SLOW CFG 0x%08x, FAST CFG 0x%08x\n",
288
+
csindex, slowcfg, fastcfg);
289
+
290
+
if (slowcfg)
291
+
writel(slowcfg, ebi2_xmem + csd->slow_cfg);
292
+
if (fastcfg)
293
+
writel(fastcfg, ebi2_xmem + csd->fast_cfg);
294
+
}
295
+
296
+
static int qcom_ebi2_probe(struct platform_device *pdev)
297
+
{
298
+
struct device_node *np = pdev->dev.of_node;
299
+
struct device_node *child;
300
+
struct device *dev = &pdev->dev;
301
+
struct resource *res;
302
+
void __iomem *ebi2_base;
303
+
void __iomem *ebi2_xmem;
304
+
struct clk *ebi2xclk;
305
+
struct clk *ebi2clk;
306
+
bool have_children = false;
307
+
u32 val;
308
+
int ret;
309
+
310
+
ebi2xclk = devm_clk_get(dev, "ebi2x");
311
+
if (IS_ERR(ebi2xclk))
312
+
return PTR_ERR(ebi2xclk);
313
+
314
+
ret = clk_prepare_enable(ebi2xclk);
315
+
if (ret) {
316
+
dev_err(dev, "could not enable EBI2X clk (%d)\n", ret);
317
+
return ret;
318
+
}
319
+
320
+
ebi2clk = devm_clk_get(dev, "ebi2");
321
+
if (IS_ERR(ebi2clk)) {
322
+
ret = PTR_ERR(ebi2clk);
323
+
goto err_disable_2x_clk;
324
+
}
325
+
326
+
ret = clk_prepare_enable(ebi2clk);
327
+
if (ret) {
328
+
dev_err(dev, "could not enable EBI2 clk\n");
329
+
goto err_disable_2x_clk;
330
+
}
331
+
332
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
333
+
ebi2_base = devm_ioremap_resource(dev, res);
334
+
if (IS_ERR(ebi2_base)) {
335
+
ret = PTR_ERR(ebi2_base);
336
+
goto err_disable_clk;
337
+
}
338
+
339
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
340
+
ebi2_xmem = devm_ioremap_resource(dev, res);
341
+
if (IS_ERR(ebi2_xmem)) {
342
+
ret = PTR_ERR(ebi2_xmem);
343
+
goto err_disable_clk;
344
+
}
345
+
346
+
/* Allegedly this turns the power save mode off */
347
+
writel(0UL, ebi2_xmem + EBI2_XMEM_CFG);
348
+
349
+
/* Disable all chipselects */
350
+
val = readl(ebi2_base);
351
+
val &= ~EBI2_CSN_MASK;
352
+
writel(val, ebi2_base);
353
+
354
+
/* Walk over the child nodes and see what chipselects we use */
355
+
for_each_available_child_of_node(np, child) {
356
+
u32 csindex;
357
+
358
+
/* Figure out the chipselect */
359
+
ret = of_property_read_u32(child, "reg", &csindex);
360
+
if (ret)
361
+
return ret;
362
+
363
+
if (csindex > 5) {
364
+
dev_err(dev,
365
+
"invalid chipselect %u, we only support 0-5\n",
366
+
csindex);
367
+
continue;
368
+
}
369
+
370
+
qcom_ebi2_setup_chipselect(child,
371
+
dev,
372
+
ebi2_base,
373
+
ebi2_xmem,
374
+
csindex);
375
+
376
+
/* We have at least one child */
377
+
have_children = true;
378
+
}
379
+
380
+
if (have_children)
381
+
return of_platform_default_populate(np, NULL, dev);
382
+
return 0;
383
+
384
+
err_disable_clk:
385
+
clk_disable_unprepare(ebi2clk);
386
+
err_disable_2x_clk:
387
+
clk_disable_unprepare(ebi2xclk);
388
+
389
+
return ret;
390
+
}
391
+
392
+
static const struct of_device_id qcom_ebi2_of_match[] = {
393
+
{ .compatible = "qcom,msm8660-ebi2", },
394
+
{ .compatible = "qcom,apq8060-ebi2", },
395
+
{ }
396
+
};
397
+
398
+
static struct platform_driver qcom_ebi2_driver = {
399
+
.probe = qcom_ebi2_probe,
400
+
.driver = {
401
+
.name = "qcom-ebi2",
402
+
.of_match_table = qcom_ebi2_of_match,
403
+
},
404
+
};
405
+
module_platform_driver(qcom_ebi2_driver);
406
+
MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
407
+
MODULE_DESCRIPTION("Qualcomm EBI2 driver");
408
+
MODULE_LICENSE("GPL");