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ASoC: qcom: qdsp6: q6prm: add new clocks
Add support to new clocks that are added in Q6DSP as part of newer version
of LPASS support on SM8450 and SC8280XP.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20220816170118.13470-1-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Srinivas Kandagatla
and committed by
Mark Brown
ea15d3bd
43a70fb5
+46
+18
include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
+18
include/dt-bindings/sound/qcom,q6dsp-lpass-ports.h
···
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#define LPASS_CLK_ID_RX_CORE_MCLK 59
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#define LPASS_CLK_ID_RX_CORE_NPL_MCLK 60
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#define LPASS_CLK_ID_VA_CORE_2X_MCLK 61
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+
/* Clock ID for MCLK for WSA2 core */
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#define LPASS_CLK_ID_WSA2_CORE_MCLK 62
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/* Clock ID for NPL MCLK for WSA2 core */
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#define LPASS_CLK_ID_WSA2_CORE_2X_MCLK 63
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/* Clock ID for RX Core TX MCLK */
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#define LPASS_CLK_ID_RX_CORE_TX_MCLK 64
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/* Clock ID for RX CORE TX 2X MCLK */
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#define LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 65
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/* Clock ID for WSA core TX MCLK */
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#define LPASS_CLK_ID_WSA_CORE_TX_MCLK 66
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/* Clock ID for WSA core TX 2X MCLK */
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#define LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 67
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/* Clock ID for WSA2 core TX MCLK */
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#define LPASS_CLK_ID_WSA2_CORE_TX_MCLK 68
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/* Clock ID for WSA2 core TX 2X MCLK */
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#define LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 69
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/* Clock ID for RX CORE MCLK2 2X MCLK */
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#define LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 70
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#define LPASS_HW_AVTIMER_VOTE 101
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#define LPASS_HW_MACRO_VOTE 102
+9
sound/soc/qcom/qdsp6/q6prm-clocks.c
+9
sound/soc/qcom/qdsp6/q6prm-clocks.c
···
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
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+
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
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+
Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
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+
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
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+
Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
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Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
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"LPASS_HW_MACRO"),
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Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
+19
sound/soc/qcom/qdsp6/q6prm.h
+19
sound/soc/qcom/qdsp6/q6prm.h
···
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
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+
/* Clock ID for MCLK for WSA2 core */
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#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_MCLK 0x310
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+
/* Clock ID for NPL MCLK for WSA2 core */
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#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_2X_MCLK 0x311
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+
/* Clock ID for RX Core TX MCLK */
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_MCLK 0x312
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+
/* Clock ID for RX CORE TX 2X MCLK */
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#define Q6PRM_LPASS_CLK_ID_RX_CORE_TX_2X_MCLK 0x313
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+
/* Clock ID for WSA core TX MCLK */
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#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_MCLK 0x314
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+
/* Clock ID for WSA core TX 2X MCLK */
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#define Q6PRM_LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK 0x315
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+
/* Clock ID for WSA2 core TX MCLK */
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#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_MCLK 0x316
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+
/* Clock ID for WSA2 core TX 2X MCLK */
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#define Q6PRM_LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK 0x317
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+
/* Clock ID for RX CORE MCLK2 2X MCLK */
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+
#define Q6PRM_LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK 0x318
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+
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#define Q6PRM_LPASS_CLK_SRC_INTERNAL 1
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#define Q6PRM_LPASS_CLK_ROOT_DEFAULT 0
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#define Q6PRM_HW_CORE_ID_LPASS 1