sh: sh775x/titan fixes for irq header changes.

+3

arch/sh/Kconfig

··· 375 375 config CPU_HAS_INTC2_IRQ 376 376 bool 377 377 378 + config CPU_HAS_IPR_IRQ 379 + bool 380 + 378 381 config CPU_HAS_SR_RB 379 382 bool "CPU has SR.RB" 380 383 depends on CPU_SH3 || CPU_SH4

+15 -12

arch/sh/boards/titan/setup.c

··· 1 1 /* 2 - * Setup for Titan 2 + * arch/sh/boards/titan/setup.c - Setup for Titan 3 + * 4 + * Copyright (C) 2006 Jamie Lenehan 5 + * 6 + * This file is subject to the terms and conditions of the GNU General Public 7 + * License. See the file "COPYING" in the main directory of this archive 8 + * for more details. 3 9 */ 4 - 5 10 #include <linux/init.h> 6 - #include <asm/irq.h> 11 + #include <linux/irq.h> 7 12 #include <asm/titan.h> 8 13 #include <asm/io.h> 9 14 10 - extern void __init pcibios_init_platform(void); 11 - 12 15 static struct ipr_data titan_ipr_map[] = { 13 - { TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY }, 14 - { TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY }, 15 - { TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY }, 16 - { TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY }, 16 + /* IRQ, IPR idx, shift, prio */ 17 + { TITAN_IRQ_WAN, 3, 12, 8 }, /* eth0 (WAN) */ 18 + { TITAN_IRQ_LAN, 3, 8, 8 }, /* eth1 (LAN) */ 19 + { TITAN_IRQ_MPCIA, 3, 4, 8 }, /* mPCI A (top) */ 20 + { TITAN_IRQ_USB, 3, 0, 8 }, /* mPCI B (bottom), USB */ 17 21 }; 18 22 19 23 static void __init init_titan_irq(void) 20 24 { 21 25 /* enable individual interrupt mode for externals */ 22 - ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 23 - 26 + ipr_irq_enable_irlm(); 27 + /* register ipr irqs */ 24 28 make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map)); 25 29 } 26 30 ··· 51 47 .mv_ioport_map = titan_ioport_map, 52 48 53 49 .mv_init_irq = init_titan_irq, 54 - .mv_init_pci = pcibios_init_platform, 55 50 }; 56 51 ALIAS_MV(titan)

+10 -14

arch/sh/drivers/pci/ops-titan.c

··· 15 15 #include <linux/types.h> 16 16 #include <linux/init.h> 17 17 #include <linux/pci.h> 18 - #include <asm/io.h> 18 + #include <linux/io.h> 19 19 #include <asm/titan.h> 20 20 #include "pci-sh4.h" 21 21 22 + static char titan_irq_tab[] __initdata = { 23 + TITAN_IRQ_WAN, 24 + TITAN_IRQ_LAN, 25 + TITAN_IRQ_MPCIA, 26 + TITAN_IRQ_MPCIB, 27 + TITAN_IRQ_USB, 28 + }; 29 + 22 30 int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) 23 31 { 24 - int irq = -1; 25 - 26 - switch (slot) { 27 - case 0: irq = TITAN_IRQ_WAN; break; /* eth0 (WAN) */ 28 - case 1: irq = TITAN_IRQ_LAN; break; /* eth1 (LAN) */ 29 - case 2: irq = TITAN_IRQ_MPCIA; break; /* mPCI A */ 30 - case 3: irq = TITAN_IRQ_MPCIB; break; /* mPCI B */ 31 - case 4: irq = TITAN_IRQ_USB; break; /* USB */ 32 - default: 33 - printk(KERN_INFO "PCI: Bad IRQ mapping " 34 - "request for slot %d\n", slot); 35 - return -1; 36 - } 32 + int irq = titan_irq_tab[slot]; 37 33 38 34 printk("PCI: Mapping TITAN IRQ for slot %d, pin %c to irq %d\n", 39 35 slot, pin - 1 + 'A', irq);

+2 -1

arch/sh/kernel/cpu/irq/Makefile

··· 1 1 # 2 2 # Makefile for the Linux/SuperH CPU-specifc IRQ handlers. 3 3 # 4 - obj-y += ipr.o imask.o 4 + obj-y += imask.o 5 5 6 + obj-$(CONFIG_CPU_HAS_IPR_IRQ) += ipr.o 6 7 obj-$(CONFIG_CPU_HAS_PINT_IRQ) += pint.o 7 8 obj-$(CONFIG_CPU_HAS_MASKREG_IRQ) += maskreg.o 8 9 obj-$(CONFIG_CPU_HAS_INTC2_IRQ) += intc2.o

+6 -97

arch/sh/kernel/cpu/irq/ipr.c

··· 25 25 static void disable_ipr_irq(unsigned int irq) 26 26 { 27 27 struct ipr_data *p = get_irq_chip_data(irq); 28 - int shift = p->shift*4; 29 28 /* Set the priority in IPR to 0 */ 30 - ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr); 29 + ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr); 31 30 } 32 31 33 32 static void enable_ipr_irq(unsigned int irq) 34 33 { 35 34 struct ipr_data *p = get_irq_chip_data(irq); 36 - int shift = p->shift*4; 37 35 /* Set priority in IPR back to original value */ 38 - ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr); 36 + ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr); 39 37 } 40 38 41 39 static struct irq_chip ipr_irq_chip = { ··· 49 51 50 52 for (i = 0; i < nr_irqs; i++) { 51 53 unsigned int irq = table[i].irq; 54 + table[i].addr = map_ipridx_to_addr(table[i].ipr_idx); 55 + /* could the IPR index be mapped, if not we ignore this */ 56 + if (table[i].addr == 0) 57 + continue; 52 58 disable_irq_nosync(irq); 53 59 set_irq_chip_and_handler_name(irq, &ipr_irq_chip, 54 60 handle_level_irq, "level"); ··· 61 59 } 62 60 } 63 61 EXPORT_SYMBOL(make_ipr_irq); 64 - 65 - /* 66 - * XXX: Move this garbage in to the drivers, and kill off the ridiculous CPU 67 - * subtype checks. 68 - */ 69 - static struct ipr_data sys_ipr_map[] = { 70 - #ifndef CONFIG_CPU_SUBTYPE_SH7780 71 - { TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY }, 72 - { TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY }, 73 - #ifdef RTC_IRQ 74 - { RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY }, 75 - #endif 76 - #ifdef SCI_ERI_IRQ 77 - { SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 78 - { SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 79 - { SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY }, 80 - #endif 81 - #ifdef SCIF1_ERI_IRQ 82 - { SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 83 - { SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 84 - { SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 85 - { SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY }, 86 - #endif 87 - #ifdef SCIF2_ERI_IRQ 88 - { SCIF2_ERI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, 89 - { SCIF2_RXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, 90 - { SCIF2_BRI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, 91 - { SCIF2_TXI_IRQ, SCIF2_IPR_ADDR, SCIF2_IPR_POS, SCIF2_PRIORITY }, 92 - #endif 93 - #ifdef SCIF3_ERI_IRQ 94 - { SCIF3_ERI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, 95 - { SCIF3_RXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, 96 - { SCIF3_BRI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, 97 - { SCIF3_TXI_IRQ, SCIF3_IPR_ADDR, SCIF3_IPR_POS, SCIF3_PRIORITY }, 98 - #endif 99 - #if defined(CONFIG_CPU_SUBTYPE_SH7300) 100 - { SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY }, 101 - { DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 102 - { DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY }, 103 - { VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY }, 104 - #endif 105 - #ifdef SCIF_ERI_IRQ 106 - { SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 107 - { SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 108 - { SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 109 - { SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY }, 110 - #endif 111 - #ifdef IRDA_ERI_IRQ 112 - { IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 113 - { IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 114 - { IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 115 - { IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY }, 116 - #endif 117 - #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 118 - defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 119 - defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 120 - /* 121 - * Initialize the Interrupt Controller (INTC) 122 - * registers to their power on values 123 - */ 124 - 125 - /* 126 - * Enable external irq (INTC IRQ mode). 127 - * You should set corresponding bits of PFC to "00" 128 - * to enable these interrupts. 129 - */ 130 - { IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY }, 131 - { IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY }, 132 - { IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY }, 133 - { IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY }, 134 - { IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY }, 135 - { IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY }, 136 - #endif 137 - #endif 138 - }; 139 - 140 - void __init init_IRQ(void) 141 - { 142 - make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map)); 143 - 144 - #ifdef CONFIG_CPU_HAS_PINT_IRQ 145 - init_IRQ_pint(); 146 - #endif 147 - 148 - #ifdef CONFIG_CPU_HAS_INTC2_IRQ 149 - init_IRQ_intc2(); 150 - #endif 151 - /* Perform the machine specific initialisation */ 152 - if (sh_mv.mv_init_irq != NULL) 153 - sh_mv.mv_init_irq(); 154 - 155 - irq_ctx_init(smp_processor_id()); 156 - } 157 62 158 63 #if !defined(CONFIG_CPU_HAS_PINT_IRQ) 159 64 int ipr_irq_demux(int irq)

+70

arch/sh/kernel/cpu/sh4/setup-sh7750.c

··· 2 2 * SH7750/SH7751 Setup 3 3 * 4 4 * Copyright (C) 2006 Paul Mundt 5 + * Copyright (C) 2006 Jamie Lenehan 5 6 * 6 7 * This file is subject to the terms and conditions of the GNU General Public 7 8 * License. See the file "COPYING" in the main directory of this archive ··· 11 10 #include <linux/platform_device.h> 12 11 #include <linux/init.h> 13 12 #include <linux/serial.h> 13 + #include <linux/io.h> 14 14 #include <asm/sci.h> 15 15 16 16 static struct plat_sci_port sci_platform_data[] = { ··· 48 46 ARRAY_SIZE(sh7750_devices)); 49 47 } 50 48 __initcall(sh7750_devices_setup); 49 + 50 + static struct ipr_data sh7750_ipr_map[] = { 51 + /* IRQ, IPR-idx, shift, priority */ 52 + { 16, 0, 12, 2 }, /* TMU0 TUNI*/ 53 + { 17, 0, 12, 2 }, /* TMU1 TUNI */ 54 + { 18, 0, 4, 2 }, /* TMU2 TUNI */ 55 + { 19, 0, 4, 2 }, /* TMU2 TIPCI */ 56 + { 27, 1, 12, 2 }, /* WDT ITI */ 57 + { 20, 0, 0, 2 }, /* RTC ATI (alarm) */ 58 + { 21, 0, 0, 2 }, /* RTC PRI (period) */ 59 + { 22, 0, 0, 2 }, /* RTC CUI (carry) */ 60 + { 23, 1, 4, 3 }, /* SCI ERI */ 61 + { 24, 1, 4, 3 }, /* SCI RXI */ 62 + { 25, 1, 4, 3 }, /* SCI TXI */ 63 + { 40, 2, 4, 3 }, /* SCIF ERI */ 64 + { 41, 2, 4, 3 }, /* SCIF RXI */ 65 + { 42, 2, 4, 3 }, /* SCIF BRI */ 66 + { 43, 2, 4, 3 }, /* SCIF TXI */ 67 + { 34, 2, 8, 7 }, /* DMAC DMTE0 */ 68 + { 35, 2, 8, 7 }, /* DMAC DMTE1 */ 69 + { 36, 2, 8, 7 }, /* DMAC DMTE2 */ 70 + { 37, 2, 8, 7 }, /* DMAC DMTE3 */ 71 + { 28, 2, 8, 7 }, /* DMAC DMAE */ 72 + }; 73 + 74 + static struct ipr_data sh7751_ipr_map[] = { 75 + { 44, 2, 8, 7 }, /* DMAC DMTE4 */ 76 + { 45, 2, 8, 7 }, /* DMAC DMTE5 */ 77 + { 46, 2, 8, 7 }, /* DMAC DMTE6 */ 78 + { 47, 2, 8, 7 }, /* DMAC DMTE7 */ 79 + /* The following use INTC_INPRI00 for masking, which is a 32-bit 80 + register, not a 16-bit register like the IPRx registers, so it 81 + would need special support */ 82 + /*{ 72, INTPRI00, 8, ? },*/ /* TMU3 TUNI */ 83 + /*{ 76, INTPRI00, 12, ? },*/ /* TMU4 TUNI */ 84 + }; 85 + 86 + static unsigned long ipr_offsets[] = { 87 + 0xffd00004UL, /* 0: IPRA */ 88 + 0xffd00008UL, /* 1: IPRB */ 89 + 0xffd0000cUL, /* 2: IPRC */ 90 + 0xffd00010UL, /* 3: IPRD */ 91 + }; 92 + 93 + /* given the IPR index return the address of the IPR register */ 94 + unsigned int map_ipridx_to_addr(int idx) 95 + { 96 + if (idx >= ARRAY_SIZE(ipr_offsets)) 97 + return 0; 98 + return ipr_offsets[idx]; 99 + } 100 + 101 + #define INTC_ICR 0xffd00000UL 102 + #define INTC_ICR_IRLM (1<<7) 103 + 104 + /* enable individual interrupt mode for external interupts */ 105 + void ipr_irq_enable_irlm(void) 106 + { 107 + ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 108 + } 109 + 110 + void __init init_IRQ_ipr() 111 + { 112 + make_ipr_irq(sh7750_ipr_map, ARRAY_SIZE(sh7750_ipr_map)); 113 + #ifdef CONFIG_CPU_SUBTYPE_SH7751 114 + make_ipr_irq(sh7751_ipr_map, ARRAY_SIZE(sh7751_ipr_map)); 115 + #endif 116 + }

+23 -2

arch/sh/kernel/irq.c

··· 12 12 #include <linux/kernel_stat.h> 13 13 #include <linux/seq_file.h> 14 14 #include <linux/io.h> 15 - #include <asm/irq.h> 15 + #include <linux/irq.h> 16 16 #include <asm/processor.h> 17 17 #include <asm/uaccess.h> 18 18 #include <asm/thread_info.h> ··· 112 112 #endif 113 113 114 114 #ifdef CONFIG_CPU_HAS_INTEVT 115 - irq = (ctrl_inl(INTEVT) >> 5) - 16; 115 + irq = evt2irq(ctrl_inl(INTEVT)); 116 116 #else 117 117 irq = r4; 118 118 #endif ··· 261 261 } 262 262 EXPORT_SYMBOL(do_softirq); 263 263 #endif 264 + 265 + void __init init_IRQ(void) 266 + { 267 + #ifdef CONFIG_CPU_HAS_PINT_IRQ 268 + init_IRQ_pint(); 269 + #endif 270 + 271 + #ifdef CONFIG_CPU_HAS_INTC2_IRQ 272 + init_IRQ_intc2(); 273 + #endif 274 + 275 + #ifdef CONFIG_CPU_HAS_IPR_IRQ 276 + init_IRQ_ipr(); 277 + #endif 278 + 279 + /* Perform the machine specific initialisation */ 280 + if (sh_mv.mv_init_irq) 281 + sh_mv.mv_init_irq(); 282 + 283 + irq_ctx_init(smp_processor_id()); 284 + }

+5

arch/sh/mm/Kconfig

··· 104 104 config CPU_SUBTYPE_SH7750 105 105 bool "Support SH7750 processor" 106 106 select CPU_SH4 107 + select CPU_HAS_IPR_IRQ 107 108 help 108 109 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU. 109 110 ··· 120 119 bool "Support SH7750R processor" 121 120 select CPU_SH4 122 121 select CPU_SUBTYPE_SH7750 122 + select CPU_HAS_IPR_IRQ 123 123 124 124 config CPU_SUBTYPE_SH7750S 125 125 bool "Support SH7750S processor" 126 126 select CPU_SH4 127 127 select CPU_SUBTYPE_SH7750 128 + select CPU_HAS_IPR_IRQ 128 129 129 130 config CPU_SUBTYPE_SH7751 130 131 bool "Support SH7751 processor" 131 132 select CPU_SH4 133 + select CPU_HAS_IPR_IRQ 132 134 help 133 135 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU, 134 136 or if you have a HD6417751R CPU. ··· 140 136 bool "Support SH7751R processor" 141 137 select CPU_SH4 142 138 select CPU_SUBTYPE_SH7751 139 + select CPU_HAS_IPR_IRQ 143 140 144 141 config CPU_SUBTYPE_SH7760 145 142 bool "Support SH7760 processor"

+28 -4

include/asm-sh/irq.h

··· 93 93 #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) 94 94 95 95 /* 96 + * Convert back and forth between INTEVT and IRQ values. 97 + */ 98 + #define evt2irq(evt) (((evt) >> 5) - 16) 99 + #define irq2evt(irq) (((irq) + 16) << 5) 100 + 101 + /* 96 102 * Simple Mask Register Support 97 103 */ 98 104 extern void make_maskreg_irq(unsigned int irq); ··· 109 103 */ 110 104 void init_IRQ_pint(void); 111 105 106 + /* 107 + * The shift value is now the number of bits to shift, not the number of 108 + * bits/4. This is to make it easier to read the value directly from the 109 + * datasheets. The IPR address, addr, will be set from ipr_idx via the 110 + * map_ipridx_to_addr function. 111 + */ 112 112 struct ipr_data { 113 113 unsigned int irq; 114 - unsigned int addr; /* Address of Interrupt Priority Register */ 115 - int shift; /* Shifts of the 16-bit data */ 114 + int ipr_idx; /* Index for the IPR registered */ 115 + int shift; /* Number of bits to shift the data */ 116 116 int priority; /* The priority */ 117 + unsigned int addr; /* Address of Interrupt Priority Register */ 117 118 }; 119 + 120 + /* 121 + * Given an IPR IDX, map the value to an IPR register address. 122 + */ 123 + unsigned int map_ipridx_to_addr(int idx); 124 + 125 + /* 126 + * Enable individual interrupt mode for external IPR IRQs. 127 + */ 128 + void ipr_irq_enable_irlm(void); 118 129 119 130 /* 120 131 * Function for "on chip support modules". 121 132 */ 122 - extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); 123 - extern void make_imask_irq(unsigned int irq); 133 + void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); 134 + void make_imask_irq(unsigned int irq); 135 + void init_IRQ_ipr(void); 124 136 125 137 struct intc2_data { 126 138 unsigned short irq;

+3 -29

include/asm-sh/titan.h

··· 1 1 /* 2 2 * Platform defintions for Titan 3 3 */ 4 - 5 - #ifndef _ASM_SH_TITAN_TITAN_H 6 - #define _ASM_SH_TITAN_TITAN_H 4 + #ifndef _ASM_SH_TITAN_H 5 + #define _ASM_SH_TITAN_H 7 6 8 7 #define __IO_PREFIX titan 9 8 #include <asm/io_generic.h> ··· 14 15 #define TITAN_IRQ_MPCIB 11 /* mPCI B */ 15 16 #define TITAN_IRQ_USB 11 /* USB */ 16 17 17 - /* 18 - * The external interrupt lines, these take up ints 0 - 15 inclusive 19 - * depending on the priority for the interrupt. In fact the priority 20 - * is the interrupt :-) 21 - */ 22 - #define IRL0_IRQ 0 23 - #define IRL0_IPR_ADDR INTC_IPRD 24 - #define IRL0_IPR_POS 3 25 - #define IRL0_PRIORITY 8 26 - 27 - #define IRL1_IRQ 1 28 - #define IRL1_IPR_ADDR INTC_IPRD 29 - #define IRL1_IPR_POS 2 30 - #define IRL1_PRIORITY 8 31 - 32 - #define IRL2_IRQ 2 33 - #define IRL2_IPR_ADDR INTC_IPRD 34 - #define IRL2_IPR_POS 1 35 - #define IRL2_PRIORITY 8 36 - 37 - #define IRL3_IRQ 3 38 - #define IRL3_IPR_ADDR INTC_IPRD 39 - #define IRL3_IPR_POS 0 40 - #define IRL3_PRIORITY 8 41 - 42 - #endif 18 + #endif /* __ASM_SH_TITAN_H */