tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

clk: rockchip: rk3588: drop RK3588_LINKED_CLK

With the proper GATE_LINK support, we no longer need to keep the
linked clocks always on. Thus it's time to drop the CLK_IS_CRITICAL
flag for them.

Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20241211165957.94922-6-sebastian.reichel@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

authored by

Sebastian Reichel and committed by
Heiko Stuebner e9cdd7d6 c62fa612

+12 -15
+12 -15
drivers/clk/rockchip/clk-rk3588.c
··· 12 12 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 13 13 #include "clk.h" 14 14 15 - #define RK3588_LINKED_CLK CLK_IS_CRITICAL 16 - 17 - 18 15 #define RK3588_GRF_SOC_STATUS0 0x600 19 16 #define RK3588_PHYREF_ALT_GATE 0xc38 20 17 ··· 1436 1439 COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0, 1437 1440 RK3588_CLKSEL_CON(77), 0, 2, MFLAGS, 1438 1441 RK3588_CLKGATE_CON(31), 0, GFLAGS), 1439 - COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK, 1442 + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0, 1440 1443 RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS, 1441 1444 RK3588_CLKGATE_CON(31), 1, GFLAGS), 1442 1445 GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, ··· 1665 1668 RK3588_CLKGATE_CON(42), 9, GFLAGS), 1666 1669 1667 1670 /* vdpu */ 1668 - COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK, 1671 + COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0, 1669 1672 RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS, 1670 1673 RK3588_CLKGATE_CON(44), 0, GFLAGS), 1671 1674 COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0, 1672 1675 RK3588_CLKSEL_CON(98), 7, 2, MFLAGS, 1673 1676 RK3588_CLKGATE_CON(44), 1, GFLAGS), 1674 - COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1677 + COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0, 1675 1678 RK3588_CLKSEL_CON(98), 9, 2, MFLAGS, 1676 1679 RK3588_CLKGATE_CON(44), 2, GFLAGS), 1677 1680 COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0, ··· 1722 1725 COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0, 1723 1726 RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS, 1724 1727 RK3588_CLKGATE_CON(47), 1, GFLAGS), 1725 - GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK, 1728 + GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0, 1726 1729 RK3588_CLKGATE_CON(47), 4, GFLAGS), 1727 - GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK, 1730 + GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0, 1728 1731 RK3588_CLKGATE_CON(47), 5, GFLAGS), 1729 1732 COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0, 1730 1733 RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS, ··· 1734 1737 RK3588_CLKGATE_CON(48), 6, GFLAGS), 1735 1738 1736 1739 /* vi */ 1737 - COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK, 1740 + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0, 1738 1741 RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS, 1739 1742 RK3588_CLKGATE_CON(49), 0, GFLAGS), 1740 - COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1743 + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0, 1741 1744 RK3588_CLKSEL_CON(106), 8, 2, MFLAGS, 1742 1745 RK3588_CLKGATE_CON(49), 1, GFLAGS), 1743 1746 COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, ··· 1907 1910 COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0, 1908 1911 RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS, 1909 1912 RK3588_CLKGATE_CON(52), 0, GFLAGS), 1910 - COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK, 1913 + COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0, 1911 1914 RK3588_CLKSEL_CON(110), 8, 2, MFLAGS, 1912 1915 RK3588_CLKGATE_CON(52), 1, GFLAGS), 1913 - COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK, 1916 + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0, 1914 1917 RK3588_CLKSEL_CON(110), 10, 2, MFLAGS, 1915 1918 RK3588_CLKGATE_CON(52), 2, GFLAGS), 1916 1919 COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, ··· 2413 2416 static struct rockchip_clk_branch rk3588_clk_branches[] = { 2414 2417 GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", ACLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 6, GFLAGS), 2415 2418 GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", HCLK_VI_ROOT, 0, RK3588_CLKGATE_CON(26), 8, GFLAGS), 2416 - GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS), 2419 + GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", ACLK_NVM_ROOT, 0, RK3588_CLKGATE_CON(31), 2, GFLAGS), 2417 2420 GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 2, GFLAGS), 2418 2421 GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(42), 3, GFLAGS), 2419 2422 GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(44), 7, GFLAGS), ··· 2425 2428 GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 4, GFLAGS), 2426 2429 GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(41), 5, GFLAGS), 2427 2430 GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", ACLK_VOP_LOW_ROOT, 0, RK3588_CLKGATE_CON(55), 9, GFLAGS), 2428 - GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS), 2431 + GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", HCLK_VOP_ROOT, 0, RK3588_CLKGATE_CON(55), 5, GFLAGS), 2429 2432 GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", ACLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 6, GFLAGS), 2430 - GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS), 2433 + GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", HCLK_VO1USB_TOP_ROOT, 0, RK3588_CLKGATE_CON(59), 9, GFLAGS), 2431 2434 GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", ACLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 1, GFLAGS), 2432 2435 GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", HCLK_VDPU_ROOT, 0, RK3588_CLKGATE_CON(68), 4, GFLAGS), 2433 2436 GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", HCLK_NVM, 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),