tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: ti: am33xx: rename existing clkctrl data as compat data
Rename the existing clkctrl data in preparation of upcoming clkdm
based split for it. Once the DT data has transitioned also, the
compat data can be removed.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Tony Lindgren <tony@atomide.com>
+224
-198
+2
-1
drivers/clk/ti/Makefile
+2
-1
drivers/clk/ti/Makefile
···
6
6
fixed-factor.o mux.o apll.o \
7
7
clkt_dpll.o clkt_iclk.o clkt_dflt.o \
8
8
clkctrl.o
9
-
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
9
+
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o \
10
+
clk-33xx-compat.o
10
11
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o clk-816x.o
11
12
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
12
13
obj-$(CONFIG_ARCH_OMAP3) += $(clk-common) interface.o \
+218
drivers/clk/ti/clk-33xx-compat.c
+218
drivers/clk/ti/clk-33xx-compat.c
···
1
+
/*
2
+
* AM33XX Clock init
3
+
*
4
+
* Copyright (C) 2013 Texas Instruments, Inc
5
+
* Tero Kristo (t-kristo@ti.com)
6
+
*
7
+
* This program is free software; you can redistribute it and/or
8
+
* modify it under the terms of the GNU General Public License as
9
+
* published by the Free Software Foundation version 2.
10
+
*
11
+
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
12
+
* kind, whether express or implied; without even the implied warranty
13
+
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*/
16
+
17
+
#include <linux/kernel.h>
18
+
#include <linux/list.h>
19
+
#include <linux/clk.h>
20
+
#include <linux/clk-provider.h>
21
+
#include <linux/clk/ti.h>
22
+
#include <dt-bindings/clock/am3.h>
23
+
24
+
#include "clock.h"
25
+
26
+
static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27
+
"l4_per_cm:clk:0138:0",
28
+
NULL,
29
+
};
30
+
31
+
static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32
+
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33
+
{ 0 },
34
+
};
35
+
36
+
static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37
+
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38
+
{ 0 },
39
+
};
40
+
41
+
static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42
+
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43
+
{ 0 },
44
+
};
45
+
46
+
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47
+
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48
+
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
49
+
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50
+
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51
+
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52
+
{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53
+
{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54
+
{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55
+
{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56
+
{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57
+
{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58
+
{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59
+
{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60
+
{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61
+
{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62
+
{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63
+
{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64
+
{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65
+
{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66
+
{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67
+
{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68
+
{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69
+
{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70
+
{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71
+
{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72
+
{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73
+
{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74
+
{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75
+
{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76
+
{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77
+
{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78
+
{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79
+
{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80
+
{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81
+
{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82
+
{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83
+
{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84
+
{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85
+
{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86
+
{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87
+
{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88
+
{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89
+
{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90
+
{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91
+
{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92
+
{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93
+
{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94
+
{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95
+
{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96
+
{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97
+
{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98
+
{ 0 },
99
+
};
100
+
101
+
static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102
+
"gpio0_dbclk_mux_ck",
103
+
NULL,
104
+
};
105
+
106
+
static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107
+
{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108
+
{ 0 },
109
+
};
110
+
111
+
static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112
+
"sys_clkin_ck",
113
+
NULL,
114
+
};
115
+
116
+
static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117
+
"l4_wkup_cm:clk:0010:19",
118
+
"l4_wkup_cm:clk:0010:30",
119
+
NULL,
120
+
};
121
+
122
+
static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123
+
"l4_wkup_cm:clk:0010:20",
124
+
NULL,
125
+
};
126
+
127
+
static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128
+
.max_div = 64,
129
+
.flags = CLK_DIVIDER_POWER_OF_TWO,
130
+
};
131
+
132
+
static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133
+
"l4_wkup_cm:clk:0010:22",
134
+
NULL,
135
+
};
136
+
137
+
static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138
+
.max_div = 64,
139
+
.flags = CLK_DIVIDER_POWER_OF_TWO,
140
+
};
141
+
142
+
static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143
+
"dpll_core_m4_ck",
144
+
NULL,
145
+
};
146
+
147
+
static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148
+
{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149
+
{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150
+
{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151
+
{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152
+
{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153
+
{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154
+
{ 0 },
155
+
};
156
+
157
+
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158
+
{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159
+
{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160
+
{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161
+
{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162
+
{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163
+
{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164
+
{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165
+
{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166
+
{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167
+
{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168
+
{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169
+
{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170
+
{ 0 },
171
+
};
172
+
173
+
static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174
+
{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175
+
{ 0 },
176
+
};
177
+
178
+
static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179
+
{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180
+
{ 0 },
181
+
};
182
+
183
+
static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184
+
{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185
+
{ 0 },
186
+
};
187
+
188
+
static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189
+
{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190
+
{ 0 },
191
+
};
192
+
193
+
const struct omap_clkctrl_data am3_clkctrl_compat_data[] __initconst = {
194
+
{ 0x44e00014, am3_l4_per_clkctrl_regs },
195
+
{ 0x44e00404, am3_l4_wkup_clkctrl_regs },
196
+
{ 0x44e00604, am3_mpu_clkctrl_regs },
197
+
{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
198
+
{ 0x44e00904, am3_gfx_l3_clkctrl_regs },
199
+
{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200
+
{ 0 },
201
+
};
202
+
203
+
struct ti_dt_clk am33xx_compat_clks[] = {
204
+
DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
205
+
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206
+
DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
207
+
DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
208
+
DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
209
+
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
210
+
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
211
+
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
212
+
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
213
+
DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
214
+
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
215
+
DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
216
+
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
217
+
{ .node_name = NULL },
218
+
};
+1
-195
drivers/clk/ti/clk-33xx.c
+1
-195
drivers/clk/ti/clk-33xx.c
···
23
23
24
24
#include "clock.h"
25
25
26
-
static const char * const am3_gpio1_dbclk_parents[] __initconst = {
27
-
"l4_per_cm:clk:0138:0",
28
-
NULL,
29
-
};
30
-
31
-
static const struct omap_clkctrl_bit_data am3_gpio2_bit_data[] __initconst = {
32
-
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
33
-
{ 0 },
34
-
};
35
-
36
-
static const struct omap_clkctrl_bit_data am3_gpio3_bit_data[] __initconst = {
37
-
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
38
-
{ 0 },
39
-
};
40
-
41
-
static const struct omap_clkctrl_bit_data am3_gpio4_bit_data[] __initconst = {
42
-
{ 18, TI_CLK_GATE, am3_gpio1_dbclk_parents, NULL },
43
-
{ 0 },
44
-
};
45
-
46
-
static const struct omap_clkctrl_reg_data am3_l4_per_clkctrl_regs[] __initconst = {
47
-
{ AM3_CPGMAC0_CLKCTRL, NULL, CLKF_SW_SUP, "cpsw_125mhz_gclk", "cpsw_125mhz_clkdm" },
48
-
{ AM3_LCDC_CLKCTRL, NULL, CLKF_SW_SUP | CLKF_SET_RATE_PARENT, "lcd_gclk", "lcdc_clkdm" },
49
-
{ AM3_USB_OTG_HS_CLKCTRL, NULL, CLKF_SW_SUP, "usbotg_fck", "l3s_clkdm" },
50
-
{ AM3_TPTC0_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
51
-
{ AM3_EMIF_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_ddr_m2_div2_ck", "l3_clkdm" },
52
-
{ AM3_OCMCRAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
53
-
{ AM3_GPMC_CLKCTRL, NULL, CLKF_SW_SUP, "l3s_gclk", "l3s_clkdm" },
54
-
{ AM3_MCASP0_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp0_fck", "l3s_clkdm" },
55
-
{ AM3_UART6_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
56
-
{ AM3_MMC1_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
57
-
{ AM3_ELM_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
58
-
{ AM3_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
59
-
{ AM3_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
60
-
{ AM3_SPI0_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
61
-
{ AM3_SPI1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
62
-
{ AM3_L4_LS_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
63
-
{ AM3_MCASP1_CLKCTRL, NULL, CLKF_SW_SUP, "mcasp1_fck", "l3s_clkdm" },
64
-
{ AM3_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
65
-
{ AM3_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
66
-
{ AM3_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
67
-
{ AM3_UART5_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_ck" },
68
-
{ AM3_TIMER7_CLKCTRL, NULL, CLKF_SW_SUP, "timer7_fck" },
69
-
{ AM3_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "timer2_fck" },
70
-
{ AM3_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "timer3_fck" },
71
-
{ AM3_TIMER4_CLKCTRL, NULL, CLKF_SW_SUP, "timer4_fck" },
72
-
{ AM3_RNG_CLKCTRL, NULL, CLKF_SW_SUP, "rng_fck" },
73
-
{ AM3_AES_CLKCTRL, NULL, CLKF_SW_SUP, "aes0_fck", "l3_clkdm" },
74
-
{ AM3_SHAM_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
75
-
{ AM3_GPIO2_CLKCTRL, am3_gpio2_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
76
-
{ AM3_GPIO3_CLKCTRL, am3_gpio3_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
77
-
{ AM3_GPIO4_CLKCTRL, am3_gpio4_bit_data, CLKF_SW_SUP, "l4ls_gclk" },
78
-
{ AM3_TPCC_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
79
-
{ AM3_D_CAN0_CLKCTRL, NULL, CLKF_SW_SUP, "dcan0_fck" },
80
-
{ AM3_D_CAN1_CLKCTRL, NULL, CLKF_SW_SUP, "dcan1_fck" },
81
-
{ AM3_EPWMSS1_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
82
-
{ AM3_EPWMSS0_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
83
-
{ AM3_EPWMSS2_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
84
-
{ AM3_L3_INSTR_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
85
-
{ AM3_L3_MAIN_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
86
-
{ AM3_PRUSS_CLKCTRL, NULL, CLKF_SW_SUP, "pruss_ocp_gclk", "pruss_ocp_clkdm" },
87
-
{ AM3_TIMER5_CLKCTRL, NULL, CLKF_SW_SUP, "timer5_fck" },
88
-
{ AM3_TIMER6_CLKCTRL, NULL, CLKF_SW_SUP, "timer6_fck" },
89
-
{ AM3_MMC2_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk" },
90
-
{ AM3_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "mmc_clk", "l3s_clkdm" },
91
-
{ AM3_TPTC1_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
92
-
{ AM3_TPTC2_CLKCTRL, NULL, CLKF_SW_SUP, "l3_gclk", "l3_clkdm" },
93
-
{ AM3_SPINLOCK_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
94
-
{ AM3_MAILBOX_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
95
-
{ AM3_L4_HS_CLKCTRL, NULL, CLKF_SW_SUP, "l4hs_gclk", "l4hs_clkdm" },
96
-
{ AM3_OCPWP_CLKCTRL, NULL, CLKF_SW_SUP, "l4ls_gclk" },
97
-
{ AM3_CLKDIV32K_CLKCTRL, NULL, CLKF_SW_SUP, "clkdiv32k_ck", "clk_24mhz_clkdm" },
98
-
{ 0 },
99
-
};
100
-
101
-
static const char * const am3_gpio0_dbclk_parents[] __initconst = {
102
-
"gpio0_dbclk_mux_ck",
103
-
NULL,
104
-
};
105
-
106
-
static const struct omap_clkctrl_bit_data am3_gpio1_bit_data[] __initconst = {
107
-
{ 18, TI_CLK_GATE, am3_gpio0_dbclk_parents, NULL },
108
-
{ 0 },
109
-
};
110
-
111
-
static const char * const am3_dbg_sysclk_ck_parents[] __initconst = {
112
-
"sys_clkin_ck",
113
-
NULL,
114
-
};
115
-
116
-
static const char * const am3_trace_pmd_clk_mux_ck_parents[] __initconst = {
117
-
"l4_wkup_cm:clk:0010:19",
118
-
"l4_wkup_cm:clk:0010:30",
119
-
NULL,
120
-
};
121
-
122
-
static const char * const am3_trace_clk_div_ck_parents[] __initconst = {
123
-
"l4_wkup_cm:clk:0010:20",
124
-
NULL,
125
-
};
126
-
127
-
static const struct omap_clkctrl_div_data am3_trace_clk_div_ck_data __initconst = {
128
-
.max_div = 64,
129
-
.flags = CLK_DIVIDER_POWER_OF_TWO,
130
-
};
131
-
132
-
static const char * const am3_stm_clk_div_ck_parents[] __initconst = {
133
-
"l4_wkup_cm:clk:0010:22",
134
-
NULL,
135
-
};
136
-
137
-
static const struct omap_clkctrl_div_data am3_stm_clk_div_ck_data __initconst = {
138
-
.max_div = 64,
139
-
.flags = CLK_DIVIDER_POWER_OF_TWO,
140
-
};
141
-
142
-
static const char * const am3_dbg_clka_ck_parents[] __initconst = {
143
-
"dpll_core_m4_ck",
144
-
NULL,
145
-
};
146
-
147
-
static const struct omap_clkctrl_bit_data am3_debugss_bit_data[] __initconst = {
148
-
{ 19, TI_CLK_GATE, am3_dbg_sysclk_ck_parents, NULL },
149
-
{ 20, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
150
-
{ 22, TI_CLK_MUX, am3_trace_pmd_clk_mux_ck_parents, NULL },
151
-
{ 24, TI_CLK_DIVIDER, am3_trace_clk_div_ck_parents, &am3_trace_clk_div_ck_data },
152
-
{ 27, TI_CLK_DIVIDER, am3_stm_clk_div_ck_parents, &am3_stm_clk_div_ck_data },
153
-
{ 30, TI_CLK_GATE, am3_dbg_clka_ck_parents, NULL },
154
-
{ 0 },
155
-
};
156
-
157
-
static const struct omap_clkctrl_reg_data am3_l4_wkup_clkctrl_regs[] __initconst = {
158
-
{ AM3_CONTROL_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
159
-
{ AM3_GPIO1_CLKCTRL, am3_gpio1_bit_data, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
160
-
{ AM3_L4_WKUP_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_core_m4_div2_ck" },
161
-
{ AM3_DEBUGSS_CLKCTRL, am3_debugss_bit_data, CLKF_SW_SUP, "l4_wkup_cm:clk:0010:24", "l3_aon_clkdm" },
162
-
{ AM3_WKUP_M3_CLKCTRL, NULL, CLKF_NO_IDLEST, "dpll_core_m4_div2_ck", "l4_wkup_aon_clkdm" },
163
-
{ AM3_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
164
-
{ AM3_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_per_m2_div4_wkupdm_ck" },
165
-
{ AM3_ADC_TSC_CLKCTRL, NULL, CLKF_SW_SUP, "adc_tsc_fck" },
166
-
{ AM3_SMARTREFLEX0_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex0_fck" },
167
-
{ AM3_TIMER1_CLKCTRL, NULL, CLKF_SW_SUP, "timer1_fck" },
168
-
{ AM3_SMARTREFLEX1_CLKCTRL, NULL, CLKF_SW_SUP, "smartreflex1_fck" },
169
-
{ AM3_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "wdt1_fck" },
170
-
{ 0 },
171
-
};
172
-
173
-
static const struct omap_clkctrl_reg_data am3_mpu_clkctrl_regs[] __initconst = {
174
-
{ AM3_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "dpll_mpu_m2_ck" },
175
-
{ 0 },
176
-
};
177
-
178
-
static const struct omap_clkctrl_reg_data am3_l4_rtc_clkctrl_regs[] __initconst = {
179
-
{ AM3_RTC_CLKCTRL, NULL, CLKF_SW_SUP, "clk_32768_ck" },
180
-
{ 0 },
181
-
};
182
-
183
-
static const struct omap_clkctrl_reg_data am3_gfx_l3_clkctrl_regs[] __initconst = {
184
-
{ AM3_GFX_CLKCTRL, NULL, CLKF_SW_SUP, "gfx_fck_div_ck" },
185
-
{ 0 },
186
-
};
187
-
188
-
static const struct omap_clkctrl_reg_data am3_l4_cefuse_clkctrl_regs[] __initconst = {
189
-
{ AM3_CEFUSE_CLKCTRL, NULL, CLKF_SW_SUP, "sys_clkin_ck" },
190
-
{ 0 },
191
-
};
192
-
193
-
const struct omap_clkctrl_data am3_clkctrl_data[] __initconst = {
194
-
{ 0x44e00014, am3_l4_per_clkctrl_regs },
195
-
{ 0x44e00404, am3_l4_wkup_clkctrl_regs },
196
-
{ 0x44e00604, am3_mpu_clkctrl_regs },
197
-
{ 0x44e00800, am3_l4_rtc_clkctrl_regs },
198
-
{ 0x44e00904, am3_gfx_l3_clkctrl_regs },
199
-
{ 0x44e00a20, am3_l4_cefuse_clkctrl_regs },
200
-
{ 0 },
201
-
};
202
-
203
-
static struct ti_dt_clk am33xx_clks[] = {
204
-
DT_CLK(NULL, "timer_32k_ck", "l4_per_cm:0138:0"),
205
-
DT_CLK(NULL, "timer_sys_ck", "sys_clkin_ck"),
206
-
DT_CLK(NULL, "clkdiv32k_ick", "l4_per_cm:0138:0"),
207
-
DT_CLK(NULL, "dbg_clka_ck", "l4_wkup_cm:0010:30"),
208
-
DT_CLK(NULL, "dbg_sysclk_ck", "l4_wkup_cm:0010:19"),
209
-
DT_CLK(NULL, "gpio0_dbclk", "l4_wkup_cm:0004:18"),
210
-
DT_CLK(NULL, "gpio1_dbclk", "l4_per_cm:0098:18"),
211
-
DT_CLK(NULL, "gpio2_dbclk", "l4_per_cm:009c:18"),
212
-
DT_CLK(NULL, "gpio3_dbclk", "l4_per_cm:00a0:18"),
213
-
DT_CLK(NULL, "stm_clk_div_ck", "l4_wkup_cm:0010:27"),
214
-
DT_CLK(NULL, "stm_pmd_clock_mux_ck", "l4_wkup_cm:0010:22"),
215
-
DT_CLK(NULL, "trace_clk_div_ck", "l4_wkup_cm:0010:24"),
216
-
DT_CLK(NULL, "trace_pmd_clk_mux_ck", "l4_wkup_cm:0010:20"),
217
-
{ .node_name = NULL },
218
-
};
219
-
220
26
static const char *enable_init_clks[] = {
221
27
"dpll_ddr_m2_ck",
222
28
"dpll_mpu_m2_ck",
···
38
232
{
39
233
struct clk *clk1, *clk2;
40
234
41
-
ti_dt_clocks_register(am33xx_clks);
235
+
ti_dt_clocks_register(am33xx_compat_clks);
42
236
43
237
omap2_clk_disable_autoidle_all();
44
238
+1
-1
drivers/clk/ti/clkctrl.c
+1
-1
drivers/clk/ti/clkctrl.c
+2
-1
drivers/clk/ti/clock.h
+2
-1
drivers/clk/ti/clock.h
···
184
184
extern const struct omap_clkctrl_data omap4_clkctrl_data[];
185
185
extern const struct omap_clkctrl_data omap5_clkctrl_data[];
186
186
extern const struct omap_clkctrl_data dra7_clkctrl_data[];
187
-
extern const struct omap_clkctrl_data am3_clkctrl_data[];
187
+
extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
188
+
extern struct ti_dt_clk am33xx_compat_clks[];
188
189
extern const struct omap_clkctrl_data am4_clkctrl_data[];
189
190
extern const struct omap_clkctrl_data am438x_clkctrl_data[];
190
191
extern const struct omap_clkctrl_data dm814_clkctrl_data[];