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kernel
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linux
PCI: rockchip-dwc: Add legacy interrupt support
The legacy interrupts on the rk356x PCIe controller are handled by a
single muxed interrupt. Add IRQ domain support to the pcie-dw-rockchip
driver to support the virtual domain.
Link: https://lore.kernel.org/r/20220429123832.2376381-4-pgwipeout@gmail.com
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
authored by
Peter Geis
and committed by
Lorenzo Pieralisi
e8aae154
431e7d2e
+94
-2
+94
-2
drivers/pci/controller/dwc/pcie-dw-rockchip.c
+94
-2
drivers/pci/controller/dwc/pcie-dw-rockchip.c
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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*/
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#define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
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#define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
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#define HIWORD_DISABLE_BIT(val) HIWORD_UPDATE(val, ~val)
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#define to_rockchip_pcie(x) dev_get_drvdata((x)->dev)
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···
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#define PCIE_LINKUP (PCIE_SMLH_LINKUP | PCIE_RDLH_LINKUP)
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#define PCIE_L0S_ENTRY 0x11
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#define PCIE_CLIENT_GENERAL_CONTROL 0x0
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#define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
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#define PCIE_CLIENT_INTR_MASK_LEGACY 0x1c
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#define PCIE_CLIENT_GENERAL_DEBUG 0x104
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
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#define PCIE_CLIENT_LTSSM_STATUS 0x300
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_ENABLE_ENHANCE BIT(4)
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#define PCIE_LTSSM_STATUS_MASK GENMASK(5, 0)
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struct rockchip_pcie {
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struct reset_control *rst;
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struct gpio_desc *rst_gpio;
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struct regulator *vpcie3v3;
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struct irq_domain *irq_domain;
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};
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static int rockchip_pcie_readl_apb(struct rockchip_pcie *rockchip,
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u32 val, u32 reg)
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{
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writel_relaxed(val, rockchip->apb_base + reg);
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}
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static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
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unsigned long reg, hwirq;
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chained_irq_enter(chip, desc);
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reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_LEGACY);
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for_each_set_bit(hwirq, ®, 4)
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generic_handle_domain_irq(rockchip->irq_domain, hwirq);
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chained_irq_exit(chip, desc);
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}
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static void rockchip_intx_mask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_UPDATE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static void rockchip_intx_unmask(struct irq_data *data)
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{
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rockchip_pcie_writel_apb(irq_data_get_irq_chip_data(data),
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HIWORD_DISABLE_BIT(BIT(data->hwirq)),
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PCIE_CLIENT_INTR_MASK_LEGACY);
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};
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static struct irq_chip rockchip_intx_irq_chip = {
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.name = "INTx",
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.irq_mask = rockchip_intx_mask,
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.irq_unmask = rockchip_intx_unmask,
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.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
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};
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static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &rockchip_intx_irq_chip, handle_level_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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static const struct irq_domain_ops intx_domain_ops = {
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.map = rockchip_pcie_intx_map,
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};
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static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
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{
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struct device *dev = rockchip->pci.dev;
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struct device_node *intc;
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intc = of_get_child_by_name(dev->of_node, "legacy-interrupt-controller");
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if (!intc) {
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dev_err(dev, "missing child interrupt-controller node\n");
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return -EINVAL;
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}
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rockchip->irq_domain = irq_domain_add_linear(intc, PCI_NUM_INTX,
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&intx_domain_ops, rockchip);
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of_node_put(intc);
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if (!rockchip->irq_domain) {
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dev_err(dev, "failed to get a INTx IRQ domain\n");
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return -EINVAL;
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}
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return 0;
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}
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static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
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struct device *dev = rockchip->pci.dev;
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u32 val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
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int irq, ret;
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irq = of_irq_get_byname(dev->of_node, "legacy");
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if (irq < 0)
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return irq;
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ret = rockchip_pcie_init_irq_domain(rockchip);
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if (ret < 0)
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dev_err(dev, "failed to init irq domain\n");
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irq_set_chained_handler_and_data(irq, rockchip_pcie_legacy_int_handler,
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rockchip);
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/* LTSSM enable control mode */
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rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);