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powerpc/64s: Remove MSR[ISF] bit

No supported processor implements this mode. Setting the bit in
MSR values can be a bit confusing (and would prevent the bit from
ever being reused). Remove it.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20201106045340.1935841-1-npiggin@gmail.com

authored by

Nicholas Piggin and committed by
Michael Ellerman e89a8ca9 c33cd1ed

+4 -8
+1 -4
arch/powerpc/include/asm/reg.h
··· 29 29 #include <asm/reg_8xx.h> 30 30 31 31 #define MSR_SF_LG 63 /* Enable 64 bit mode */ 32 - #define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 33 32 #define MSR_HV_LG 60 /* Hypervisor state */ 34 33 #define MSR_TS_T_LG 34 /* Trans Mem state: Transactional */ 35 34 #define MSR_TS_S_LG 33 /* Trans Mem state: Suspended */ ··· 68 69 69 70 #ifdef CONFIG_PPC64 70 71 #define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */ 71 - #define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */ 72 72 #define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */ 73 73 #define MSR_S __MASK(MSR_S_LG) /* Secure state */ 74 74 #else 75 75 /* so tests for these bits fail on 32-bit */ 76 76 #define MSR_SF 0 77 - #define MSR_ISF 0 78 77 #define MSR_HV 0 79 78 #define MSR_S 0 80 79 #endif ··· 131 134 #define MSR_64BIT MSR_SF 132 135 133 136 /* Server variant */ 134 - #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV) 137 + #define __MSR (MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_HV) 135 138 #ifdef __BIG_ENDIAN__ 136 139 #define MSR_ __MSR 137 140 #define MSR_IDLE (MSR_ME | MSR_SF | MSR_HV)
+1 -1
arch/powerpc/kernel/entry_64.S
··· 969 969 mtsrr1 r11 970 970 rfi 971 971 #else /* CONFIG_PPC_BOOK3E */ 972 - LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_ISF | MSR_LE) 972 + LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_LE) 973 973 andc r11,r11,r12 974 974 mtsrr1 r11 975 975 RFI_TO_KERNEL
+1 -2
arch/powerpc/kernel/head_64.S
··· 870 870 oris r11,r11,0x8000 /* CM bit set, we'll set ICM later */ 871 871 mtmsr r11 872 872 #else /* CONFIG_PPC_BOOK3E */ 873 - li r12,(MSR_64BIT | MSR_ISF)@highest 874 - sldi r12,r12,48 873 + LOAD_REG_IMMEDIATE(r12, MSR_64BIT) 875 874 or r11,r11,r12 876 875 mtmsrd r11 877 876 isync
+1 -1
arch/powerpc/kvm/book3s_pr.c
··· 239 239 smsr |= (guest_msr & vcpu->arch.guest_owned_ext); 240 240 /* 64-bit Process MSR values */ 241 241 #ifdef CONFIG_PPC_BOOK3S_64 242 - smsr |= MSR_ISF | MSR_HV; 242 + smsr |= MSR_HV; 243 243 #endif 244 244 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM 245 245 /*