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dt-bindings: pinctrl : qcom: document SAR2130P TLMM
Add bindings for the pin controller (TLMM) present on the
Qualcomm SAR2130P platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20241018-sar2130p-tlmm-v2-1-11a1d09a6e5f@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
authored by
Dmitry Baryshkov
and committed by
Linus Walleij
e89768f6
0c4cd2cc
+138
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Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml
+138
Documentation/devicetree/bindings/pinctrl/qcom,sar2130p-tlmm.yaml
···
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sar2130p-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SAR2130P TLMM block
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm SAR2130P SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sar2130p-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 78
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gpio-line-names:
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maxItems: 156
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sar2130p-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sar2130p-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sar2130p-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|15[0-5])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ aoss_cti, atest_char, atest_char0, atest_char1, atest_char2,
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atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
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atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, dp0_hot, ext_mclk0, ext_mclk1,
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gcc_gp1, gcc_gp2, gcc_gp3, gpio, host2wlan_sol, i2s0_data0,
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i2s0_data1, i2s0_sck, i2s0_ws, ibi_i3c, jitter_bist, mdp_vsync,
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mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, pcie0_clkreqn,
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pcie1_clkreqn, phase_flag0, phase_flag1, phase_flag10,
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phase_flag11, phase_flag12, phase_flag13, phase_flag14,
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phase_flag15, phase_flag16, phase_flag17, phase_flag18,
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phase_flag19, phase_flag2, phase_flag20, phase_flag21,
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phase_flag22, phase_flag23, phase_flag24, phase_flag25,
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phase_flag26, phase_flag27, phase_flag28, phase_flag29,
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phase_flag3, phase_flag30, phase_flag31, phase_flag4,
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phase_flag5, phase_flag6, phase_flag7, phase_flag8,
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phase_flag9, pll_bist, pll_clk, prng_rosc0, prng_rosc1,
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prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0,
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qdss_gpio1, qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13,
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qdss_gpio14, qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4,
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qdss_gpio5, qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9,
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qspi0, qspi1, qspi2, qspi3, qspi_clk, qspi_cs0, qspi_cs1, qup0,
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qup1, qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup10,
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qup11, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
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tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
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tsense_pwm1, tsense_pwm2, usb0_phy, vsense_trigger ]
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required:
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- pins
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required:
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- compatible
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- reg
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl@f100000 {
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compatible = "qcom,sar2130p-tlmm";
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reg = <0x0f100000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 156>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-wo-state {
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pins = "gpio1";
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function = "gpio";
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};
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uart-w-state {
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rx-pins {
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pins = "gpio26";
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function = "qup7";
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bias-pull-up;
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};
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tx-pins {
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pins = "gpio27";
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function = "qup7";
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bias-disable;
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};
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};
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};
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...