tjh.dev / kernel
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kernel os linux
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drm/msm: Remove idle function hook

There isn't any generic code that uses ->idle so remove it.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

authored by

Jordan Crouse and committed by
Rob Clark e895c7bd 167b606a

+10 -11
+2 -2
drivers/gpu/drm/msm/adreno/a3xx_gpu.c
··· 40 40 extern bool hang_debug; 41 41 42 42 static void a3xx_dump(struct msm_gpu *gpu); 43 + static bool a3xx_idle(struct msm_gpu *gpu); 43 44 44 45 static bool a3xx_me_init(struct msm_gpu *gpu) 45 46 { ··· 66 65 OUT_RING(ring, 0x00000000); 67 66 68 67 gpu->funcs->flush(gpu); 69 - return gpu->funcs->idle(gpu); 68 + return a3xx_idle(gpu); 70 69 } 71 70 72 71 static int a3xx_hw_init(struct msm_gpu *gpu) ··· 447 446 .last_fence = adreno_last_fence, 448 447 .submit = adreno_submit, 449 448 .flush = adreno_flush, 450 - .idle = a3xx_idle, 451 449 .irq = a3xx_irq, 452 450 .destroy = a3xx_destroy, 453 451 #ifdef CONFIG_DEBUG_FS
+2 -2
drivers/gpu/drm/msm/adreno/a4xx_gpu.c
··· 31 31 32 32 extern bool hang_debug; 33 33 static void a4xx_dump(struct msm_gpu *gpu); 34 + static bool a4xx_idle(struct msm_gpu *gpu); 34 35 35 36 /* 36 37 * a4xx_enable_hwcg() - Program the clock control registers ··· 138 137 OUT_RING(ring, 0x00000000); 139 138 140 139 gpu->funcs->flush(gpu); 141 - return gpu->funcs->idle(gpu); 140 + return a4xx_idle(gpu); 142 141 } 143 142 144 143 static int a4xx_hw_init(struct msm_gpu *gpu) ··· 535 534 .last_fence = adreno_last_fence, 536 535 .submit = adreno_submit, 537 536 .flush = adreno_flush, 538 - .idle = a4xx_idle, 539 537 .irq = a4xx_irq, 540 538 .destroy = a4xx_destroy, 541 539 #ifdef CONFIG_DEBUG_FS
+4 -5
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
··· 287 287 288 288 gpu->funcs->flush(gpu); 289 289 290 - return gpu->funcs->idle(gpu) ? 0 : -EINVAL; 290 + return a5xx_idle(gpu) ? 0 : -EINVAL; 291 291 } 292 292 293 293 static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu, ··· 638 638 OUT_RING(gpu->rb, 0x0F); 639 639 640 640 gpu->funcs->flush(gpu); 641 - if (!gpu->funcs->idle(gpu)) 641 + if (!a5xx_idle(gpu)) 642 642 return -EINVAL; 643 643 } 644 644 ··· 655 655 OUT_RING(gpu->rb, 0x00000000); 656 656 657 657 gpu->funcs->flush(gpu); 658 - if (!gpu->funcs->idle(gpu)) 658 + if (!a5xx_idle(gpu)) 659 659 return -EINVAL; 660 660 } else { 661 661 /* Print a warning so if we die, we know why */ ··· 732 732 A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT); 733 733 } 734 734 735 - static bool a5xx_idle(struct msm_gpu *gpu) 735 + bool a5xx_idle(struct msm_gpu *gpu) 736 736 { 737 737 /* wait for CP to drain ringbuffer: */ 738 738 if (!adreno_idle(gpu)) ··· 1037 1037 .last_fence = adreno_last_fence, 1038 1038 .submit = a5xx_submit, 1039 1039 .flush = adreno_flush, 1040 - .idle = a5xx_idle, 1041 1040 .irq = a5xx_irq, 1042 1041 .destroy = a5xx_destroy, 1043 1042 #ifdef CONFIG_DEBUG_FS
+1
drivers/gpu/drm/msm/adreno/a5xx_gpu.h
··· 58 58 return -ETIMEDOUT; 59 59 } 60 60 61 + bool a5xx_idle(struct msm_gpu *gpu); 61 62 62 63 #endif /* __A5XX_GPU_H__ */
+1 -1
drivers/gpu/drm/msm/adreno/a5xx_power.c
··· 194 194 195 195 gpu->funcs->flush(gpu); 196 196 197 - if (!gpu->funcs->idle(gpu)) { 197 + if (!a5xx_idle(gpu)) { 198 198 DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n", 199 199 gpu->name); 200 200 return -EINVAL;
-1
drivers/gpu/drm/msm/msm_gpu.h
··· 50 50 void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit, 51 51 struct msm_file_private *ctx); 52 52 void (*flush)(struct msm_gpu *gpu); 53 - bool (*idle)(struct msm_gpu *gpu); 54 53 irqreturn_t (*irq)(struct msm_gpu *irq); 55 54 uint32_t (*last_fence)(struct msm_gpu *gpu); 56 55 void (*recover)(struct msm_gpu *gpu);