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ARM: OMAP5: Make L4SEC clock domain SWSUP only

Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

authored by Tero Kristo and committed by Tony Lindgren e88ba436 f18e314a

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unified split
Changed files
+1 -1
arch
arm
mach-omap2
clockdomains54xx_data.c
+1 -1
arch/arm/mach-omap2/clockdomains54xx_data.c
··· 170 170 .dep_bit = OMAP54XX_L4SEC_STATDEP_SHIFT, 171 171 .wkdep_srcs = l4sec_wkup_sleep_deps, 172 172 .sleepdep_srcs = l4sec_wkup_sleep_deps, 173 - .flags = CLKDM_CAN_HWSUP_SWSUP, 173 + .flags = CLKDM_CAN_SWSUP, 174 174 }; 175 175 176 176 static struct clockdomain iva_54xx_clkdm = {