tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
fork atom

Merge branch 'pci/misc'

- Add NumaChip SPDX header (Krzysztof Wilczynski)

- Replace EXTRA_CFLAGS with ccflags-y (Krzysztof Wilczynski)

- Remove unused includes (Krzysztof Wilczynski)

- Avoid AMD FCH XHCI USB PME# from D0 defect that prevents wakeup on USB
2.0 or 1.1 connect events (Kai-Heng Feng)

- Removed unused sysfs attribute groups (Ben Dooks)

- Remove PTM and ASPM dependencies on PCIEPORTBUS (Bjorn Helgaas)

- Add PCIe Link Control 2 register field definitions to replace magic
numbers in AMDGPU and Radeon CIK/SI (Bjorn Helgaas)

- Fix incorrect Link Control 2 Transmit Margin usage in AMDGPU and Radeon
CIK/SI PCIe Gen3 link training (Bjorn Helgaas)

- Use pcie_capability_read_word() instead of pci_read_config_word() in
AMDGPU and Radeon CIK/SI (Frederick Lawler)

* pci/misc:
drm/radeon: Prefer pcie_capability_read_word()
drm/radeon: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/radeon: Correct Transmit Margin masks
drm/amdgpu: Prefer pcie_capability_read_word()
drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions
drm/amdgpu: Correct Transmit Margin masks
PCI: Add #defines for Enter Compliance, Transmit Margin
PCI: Allow building PCIe things without PCIEPORTBUS
PCI: Remove PCIe Kconfig dependencies on PCI
PCI/ASPM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove dependency on PCIEPORTBUS
PCI/PTM: Remove spurious "d" from granularity message
PCI: sysfs: Remove unused attribute groups
x86/PCI: Avoid AMD FCH XHCI USB PME# from D0 defect
PCI: Remove unused includes and superfluous struct declaration
x86/PCI: Replace deprecated EXTRA_CFLAGS with ccflags-y
x86/PCI: Correct SPDX comment style
x86/PCI: Add NumaChip SPDX GPL-2.0 to replace COPYING boilerplate

Bjorn Helgaas e87eb585 2df08822

+267 -172
+1 -3
arch/x86/pci/Makefile
··· 24 24 obj-$(CONFIG_AMD_NB) += amd_bus.o 25 25 obj-$(CONFIG_PCI_CNB20LE_QUIRK) += broadcom_bus.o 26 26 27 - ifeq ($(CONFIG_PCI_DEBUG),y) 28 - EXTRA_CFLAGS += -DDEBUG 29 - endif 27 + ccflags-$(CONFIG_PCI_DEBUG) += -DDEBUG
+11
arch/x86/pci/fixup.c
··· 589 589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7808, pci_fixup_amd_ehci_pme); 590 590 591 591 /* 592 + * Device [1022:7914] 593 + * When in D0, PME# doesn't get asserted when plugging USB 2.0 device. 594 + */ 595 + static void pci_fixup_amd_fch_xhci_pme(struct pci_dev *dev) 596 + { 597 + dev_info(&dev->dev, "PME# does not work under D0, disabling it\n"); 598 + dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 599 + } 600 + DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x7914, pci_fixup_amd_fch_xhci_pme); 601 + 602 + /* 592 603 * Apple MacBook Pro: Avoid [mem 0x7fa00000-0x7fbfffff] 593 604 * 594 605 * Using the [mem 0x7fa00000-0x7fbfffff] region, e.g., by assigning it to
+1 -4
arch/x86/pci/numachip.c
··· 1 + // SPDX-License-Identifier: GPL-2.0 1 2 /* 2 - * This file is subject to the terms and conditions of the GNU General Public 3 - * License. See the file "COPYING" in the main directory of this archive 4 - * for more details. 5 - * 6 3 * Numascale NumaConnect-specific PCI code 7 4 * 8 5 * Copyright (C) 2012 Numascale AS. All rights reserved.
+59 -34
drivers/gpu/drm/amd/amdgpu/cik.c
··· 1384 1384 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1385 1385 { 1386 1386 struct pci_dev *root = adev->pdev->bus->self; 1387 - int bridge_pos, gpu_pos; 1388 1387 u32 speed_cntl, current_data_rate; 1389 1388 int i; 1390 1389 u16 tmp16; ··· 1418 1419 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1419 1420 } 1420 1421 1421 - bridge_pos = pci_pcie_cap(root); 1422 - if (!bridge_pos) 1423 - return; 1424 - 1425 - gpu_pos = pci_pcie_cap(adev->pdev); 1426 - if (!gpu_pos) 1422 + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1427 1423 return; 1428 1424 1429 1425 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { ··· 1428 1434 u16 bridge_cfg2, gpu_cfg2; 1429 1435 u32 max_lw, current_lw, tmp; 1430 1436 1431 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1432 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1437 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1438 + &bridge_cfg); 1439 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1440 + &gpu_cfg); 1433 1441 1434 1442 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1435 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1443 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1436 1444 1437 1445 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1438 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1446 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1447 + tmp16); 1439 1448 1440 1449 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1441 1450 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> ··· 1462 1465 1463 1466 for (i = 0; i < 10; i++) { 1464 1467 /* check status */ 1465 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1468 + pcie_capability_read_word(adev->pdev, 1469 + PCI_EXP_DEVSTA, 1470 + &tmp16); 1466 1471 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1467 1472 break; 1468 1473 1469 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1470 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1474 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1475 + &bridge_cfg); 1476 + pcie_capability_read_word(adev->pdev, 1477 + PCI_EXP_LNKCTL, 1478 + &gpu_cfg); 1471 1479 1472 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1473 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1480 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1481 + &bridge_cfg2); 1482 + pcie_capability_read_word(adev->pdev, 1483 + PCI_EXP_LNKCTL2, 1484 + &gpu_cfg2); 1474 1485 1475 1486 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1476 1487 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; ··· 1491 1486 msleep(100); 1492 1487 1493 1488 /* linkctl */ 1494 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1489 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1490 + &tmp16); 1495 1491 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1496 1492 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1497 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1493 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1494 + tmp16); 1498 1495 1499 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1496 + pcie_capability_read_word(adev->pdev, 1497 + PCI_EXP_LNKCTL, 1498 + &tmp16); 1500 1499 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1501 1500 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1502 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1501 + pcie_capability_write_word(adev->pdev, 1502 + PCI_EXP_LNKCTL, 1503 + tmp16); 1503 1504 1504 1505 /* linkctl2 */ 1505 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1506 - tmp16 &= ~((1 << 4) | (7 << 9)); 1507 - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 1508 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1506 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1507 + &tmp16); 1508 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1509 + PCI_EXP_LNKCTL2_TX_MARGIN); 1510 + tmp16 |= (bridge_cfg2 & 1511 + (PCI_EXP_LNKCTL2_ENTER_COMP | 1512 + PCI_EXP_LNKCTL2_TX_MARGIN)); 1513 + pcie_capability_write_word(root, 1514 + PCI_EXP_LNKCTL2, 1515 + tmp16); 1509 1516 1510 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1511 - tmp16 &= ~((1 << 4) | (7 << 9)); 1512 - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 1513 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1517 + pcie_capability_read_word(adev->pdev, 1518 + PCI_EXP_LNKCTL2, 1519 + &tmp16); 1520 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1521 + PCI_EXP_LNKCTL2_TX_MARGIN); 1522 + tmp16 |= (gpu_cfg2 & 1523 + (PCI_EXP_LNKCTL2_ENTER_COMP | 1524 + PCI_EXP_LNKCTL2_TX_MARGIN)); 1525 + pcie_capability_write_word(adev->pdev, 1526 + PCI_EXP_LNKCTL2, 1527 + tmp16); 1514 1528 1515 1529 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1516 1530 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; ··· 1544 1520 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1545 1521 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1546 1522 1547 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1548 - tmp16 &= ~0xf; 1523 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1524 + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1525 + 1549 1526 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1550 - tmp16 |= 3; /* gen3 */ 1527 + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1551 1528 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1552 - tmp16 |= 2; /* gen2 */ 1529 + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1553 1530 else 1554 - tmp16 |= 1; /* gen1 */ 1555 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1531 + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1532 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1556 1533 1557 1534 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1558 1535 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK;
+59 -34
drivers/gpu/drm/amd/amdgpu/si.c
··· 1633 1633 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 1634 1634 { 1635 1635 struct pci_dev *root = adev->pdev->bus->self; 1636 - int bridge_pos, gpu_pos; 1637 1636 u32 speed_cntl, current_data_rate; 1638 1637 int i; 1639 1638 u16 tmp16; ··· 1667 1668 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1668 1669 } 1669 1670 1670 - bridge_pos = pci_pcie_cap(root); 1671 - if (!bridge_pos) 1672 - return; 1673 - 1674 - gpu_pos = pci_pcie_cap(adev->pdev); 1675 - if (!gpu_pos) 1671 + if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1676 1672 return; 1677 1673 1678 1674 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { ··· 1676 1682 u16 bridge_cfg2, gpu_cfg2; 1677 1683 u32 max_lw, current_lw, tmp; 1678 1684 1679 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1680 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1685 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1686 + &bridge_cfg); 1687 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1688 + &gpu_cfg); 1681 1689 1682 1690 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1683 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1691 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1684 1692 1685 1693 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1686 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1694 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1695 + tmp16); 1687 1696 1688 1697 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 1689 1698 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; ··· 1703 1706 } 1704 1707 1705 1708 for (i = 0; i < 10; i++) { 1706 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1709 + pcie_capability_read_word(adev->pdev, 1710 + PCI_EXP_DEVSTA, 1711 + &tmp16); 1707 1712 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1708 1713 break; 1709 1714 1710 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1711 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1715 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1716 + &bridge_cfg); 1717 + pcie_capability_read_word(adev->pdev, 1718 + PCI_EXP_LNKCTL, 1719 + &gpu_cfg); 1712 1720 1713 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1714 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1721 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1722 + &bridge_cfg2); 1723 + pcie_capability_read_word(adev->pdev, 1724 + PCI_EXP_LNKCTL2, 1725 + &gpu_cfg2); 1715 1726 1716 1727 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1717 1728 tmp |= LC_SET_QUIESCE; ··· 1731 1726 1732 1727 mdelay(100); 1733 1728 1734 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1729 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1730 + &tmp16); 1735 1731 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1736 1732 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1737 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1733 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1734 + tmp16); 1738 1735 1739 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1736 + pcie_capability_read_word(adev->pdev, 1737 + PCI_EXP_LNKCTL, 1738 + &tmp16); 1740 1739 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1741 1740 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1742 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1741 + pcie_capability_write_word(adev->pdev, 1742 + PCI_EXP_LNKCTL, 1743 + tmp16); 1743 1744 1744 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1745 - tmp16 &= ~((1 << 4) | (7 << 9)); 1746 - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 1747 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1745 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1746 + &tmp16); 1747 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1748 + PCI_EXP_LNKCTL2_TX_MARGIN); 1749 + tmp16 |= (bridge_cfg2 & 1750 + (PCI_EXP_LNKCTL2_ENTER_COMP | 1751 + PCI_EXP_LNKCTL2_TX_MARGIN)); 1752 + pcie_capability_write_word(root, 1753 + PCI_EXP_LNKCTL2, 1754 + tmp16); 1748 1755 1749 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1750 - tmp16 &= ~((1 << 4) | (7 << 9)); 1751 - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 1752 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1756 + pcie_capability_read_word(adev->pdev, 1757 + PCI_EXP_LNKCTL2, 1758 + &tmp16); 1759 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1760 + PCI_EXP_LNKCTL2_TX_MARGIN); 1761 + tmp16 |= (gpu_cfg2 & 1762 + (PCI_EXP_LNKCTL2_ENTER_COMP | 1763 + PCI_EXP_LNKCTL2_TX_MARGIN)); 1764 + pcie_capability_write_word(adev->pdev, 1765 + PCI_EXP_LNKCTL2, 1766 + tmp16); 1753 1767 1754 1768 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1755 1769 tmp &= ~LC_SET_QUIESCE; ··· 1781 1757 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 1782 1758 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1783 1759 1784 - pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1785 - tmp16 &= ~0xf; 1760 + pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1761 + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1762 + 1786 1763 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1787 - tmp16 |= 3; 1764 + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1788 1765 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1789 - tmp16 |= 2; 1766 + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1790 1767 else 1791 - tmp16 |= 1; 1792 - pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1768 + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1769 + pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1793 1770 1794 1771 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1795 1772 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
+58 -34
drivers/gpu/drm/radeon/cik.c
··· 9504 9504 { 9505 9505 struct pci_dev *root = rdev->pdev->bus->self; 9506 9506 enum pci_bus_speed speed_cap; 9507 - int bridge_pos, gpu_pos; 9508 9507 u32 speed_cntl, current_data_rate; 9509 9508 int i; 9510 9509 u16 tmp16; ··· 9545 9546 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 9546 9547 } 9547 9548 9548 - bridge_pos = pci_pcie_cap(root); 9549 - if (!bridge_pos) 9550 - return; 9551 - 9552 - gpu_pos = pci_pcie_cap(rdev->pdev); 9553 - if (!gpu_pos) 9549 + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) 9554 9550 return; 9555 9551 9556 9552 if (speed_cap == PCIE_SPEED_8_0GT) { ··· 9555 9561 u16 bridge_cfg2, gpu_cfg2; 9556 9562 u32 max_lw, current_lw, tmp; 9557 9563 9558 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 9559 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 9564 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 9565 + &bridge_cfg); 9566 + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, 9567 + &gpu_cfg); 9560 9568 9561 9569 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 9562 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 9570 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 9563 9571 9564 9572 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 9565 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 9573 + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, 9574 + tmp16); 9566 9575 9567 9576 tmp = RREG32_PCIE_PORT(PCIE_LC_STATUS1); 9568 9577 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; ··· 9583 9586 9584 9587 for (i = 0; i < 10; i++) { 9585 9588 /* check status */ 9586 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 9589 + pcie_capability_read_word(rdev->pdev, 9590 + PCI_EXP_DEVSTA, 9591 + &tmp16); 9587 9592 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 9588 9593 break; 9589 9594 9590 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 9591 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 9595 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 9596 + &bridge_cfg); 9597 + pcie_capability_read_word(rdev->pdev, 9598 + PCI_EXP_LNKCTL, 9599 + &gpu_cfg); 9592 9600 9593 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 9594 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 9601 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 9602 + &bridge_cfg2); 9603 + pcie_capability_read_word(rdev->pdev, 9604 + PCI_EXP_LNKCTL2, 9605 + &gpu_cfg2); 9595 9606 9596 9607 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 9597 9608 tmp |= LC_SET_QUIESCE; ··· 9612 9607 msleep(100); 9613 9608 9614 9609 /* linkctl */ 9615 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 9610 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 9611 + &tmp16); 9616 9612 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 9617 9613 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 9618 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 9614 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, 9615 + tmp16); 9619 9616 9620 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 9617 + pcie_capability_read_word(rdev->pdev, 9618 + PCI_EXP_LNKCTL, 9619 + &tmp16); 9621 9620 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 9622 9621 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 9623 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 9622 + pcie_capability_write_word(rdev->pdev, 9623 + PCI_EXP_LNKCTL, 9624 + tmp16); 9624 9625 9625 9626 /* linkctl2 */ 9626 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 9627 - tmp16 &= ~((1 << 4) | (7 << 9)); 9628 - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 9629 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 9627 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 9628 + &tmp16); 9629 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 9630 + PCI_EXP_LNKCTL2_TX_MARGIN); 9631 + tmp16 |= (bridge_cfg2 & 9632 + (PCI_EXP_LNKCTL2_ENTER_COMP | 9633 + PCI_EXP_LNKCTL2_TX_MARGIN)); 9634 + pcie_capability_write_word(root, 9635 + PCI_EXP_LNKCTL2, 9636 + tmp16); 9630 9637 9631 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 9632 - tmp16 &= ~((1 << 4) | (7 << 9)); 9633 - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 9634 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 9638 + pcie_capability_read_word(rdev->pdev, 9639 + PCI_EXP_LNKCTL2, 9640 + &tmp16); 9641 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 9642 + PCI_EXP_LNKCTL2_TX_MARGIN); 9643 + tmp16 |= (gpu_cfg2 & 9644 + (PCI_EXP_LNKCTL2_ENTER_COMP | 9645 + PCI_EXP_LNKCTL2_TX_MARGIN)); 9646 + pcie_capability_write_word(rdev->pdev, 9647 + PCI_EXP_LNKCTL2, 9648 + tmp16); 9635 9649 9636 9650 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 9637 9651 tmp &= ~LC_SET_QUIESCE; ··· 9664 9640 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 9665 9641 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 9666 9642 9667 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 9668 - tmp16 &= ~0xf; 9643 + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); 9644 + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 9669 9645 if (speed_cap == PCIE_SPEED_8_0GT) 9670 - tmp16 |= 3; /* gen3 */ 9646 + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 9671 9647 else if (speed_cap == PCIE_SPEED_5_0GT) 9672 - tmp16 |= 2; /* gen2 */ 9648 + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 9673 9649 else 9674 - tmp16 |= 1; /* gen1 */ 9675 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 9650 + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 9651 + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); 9676 9652 9677 9653 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 9678 9654 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
+60 -35
drivers/gpu/drm/radeon/si.c
··· 3257 3257 /* XXX what about 12? */ 3258 3258 rdev->config.si.tile_config |= (3 << 0); 3259 3259 break; 3260 - } 3260 + } 3261 3261 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { 3262 3262 case 0: /* four banks */ 3263 3263 rdev->config.si.tile_config |= 0 << 4; ··· 7087 7087 { 7088 7088 struct pci_dev *root = rdev->pdev->bus->self; 7089 7089 enum pci_bus_speed speed_cap; 7090 - int bridge_pos, gpu_pos; 7091 7090 u32 speed_cntl, current_data_rate; 7092 7091 int i; 7093 7092 u16 tmp16; ··· 7128 7129 DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n"); 7129 7130 } 7130 7131 7131 - bridge_pos = pci_pcie_cap(root); 7132 - if (!bridge_pos) 7133 - return; 7134 - 7135 - gpu_pos = pci_pcie_cap(rdev->pdev); 7136 - if (!gpu_pos) 7132 + if (!pci_is_pcie(root) || !pci_is_pcie(rdev->pdev)) 7137 7133 return; 7138 7134 7139 7135 if (speed_cap == PCIE_SPEED_8_0GT) { ··· 7138 7144 u16 bridge_cfg2, gpu_cfg2; 7139 7145 u32 max_lw, current_lw, tmp; 7140 7146 7141 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 7142 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 7147 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 7148 + &bridge_cfg); 7149 + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL, 7150 + &gpu_cfg); 7143 7151 7144 7152 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 7145 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 7153 + pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 7146 7154 7147 7155 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 7148 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 7156 + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL, 7157 + tmp16); 7149 7158 7150 7159 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 7151 7160 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; ··· 7166 7169 7167 7170 for (i = 0; i < 10; i++) { 7168 7171 /* check status */ 7169 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 7172 + pcie_capability_read_word(rdev->pdev, 7173 + PCI_EXP_DEVSTA, 7174 + &tmp16); 7170 7175 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 7171 7176 break; 7172 7177 7173 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 7174 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 7178 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 7179 + &bridge_cfg); 7180 + pcie_capability_read_word(rdev->pdev, 7181 + PCI_EXP_LNKCTL, 7182 + &gpu_cfg); 7175 7183 7176 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 7177 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 7184 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 7185 + &bridge_cfg2); 7186 + pcie_capability_read_word(rdev->pdev, 7187 + PCI_EXP_LNKCTL2, 7188 + &gpu_cfg2); 7178 7189 7179 7190 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 7180 7191 tmp |= LC_SET_QUIESCE; ··· 7195 7190 msleep(100); 7196 7191 7197 7192 /* linkctl */ 7198 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 7193 + pcie_capability_read_word(root, PCI_EXP_LNKCTL, 7194 + &tmp16); 7199 7195 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 7200 7196 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 7201 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 7197 + pcie_capability_write_word(root, 7198 + PCI_EXP_LNKCTL, 7199 + tmp16); 7202 7200 7203 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 7201 + pcie_capability_read_word(rdev->pdev, 7202 + PCI_EXP_LNKCTL, 7203 + &tmp16); 7204 7204 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 7205 7205 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 7206 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 7206 + pcie_capability_write_word(rdev->pdev, 7207 + PCI_EXP_LNKCTL, 7208 + tmp16); 7207 7209 7208 7210 /* linkctl2 */ 7209 - pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 7210 - tmp16 &= ~((1 << 4) | (7 << 9)); 7211 - tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 7212 - pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 7211 + pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 7212 + &tmp16); 7213 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 7214 + PCI_EXP_LNKCTL2_TX_MARGIN); 7215 + tmp16 |= (bridge_cfg2 & 7216 + (PCI_EXP_LNKCTL2_ENTER_COMP | 7217 + PCI_EXP_LNKCTL2_TX_MARGIN)); 7218 + pcie_capability_write_word(root, 7219 + PCI_EXP_LNKCTL2, 7220 + tmp16); 7213 7221 7214 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 7215 - tmp16 &= ~((1 << 4) | (7 << 9)); 7216 - tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 7217 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 7222 + pcie_capability_read_word(rdev->pdev, 7223 + PCI_EXP_LNKCTL2, 7224 + &tmp16); 7225 + tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 7226 + PCI_EXP_LNKCTL2_TX_MARGIN); 7227 + tmp16 |= (gpu_cfg2 & 7228 + (PCI_EXP_LNKCTL2_ENTER_COMP | 7229 + PCI_EXP_LNKCTL2_TX_MARGIN)); 7230 + pcie_capability_write_word(rdev->pdev, 7231 + PCI_EXP_LNKCTL2, 7232 + tmp16); 7218 7233 7219 7234 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 7220 7235 tmp &= ~LC_SET_QUIESCE; ··· 7248 7223 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 7249 7224 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 7250 7225 7251 - pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 7252 - tmp16 &= ~0xf; 7226 + pcie_capability_read_word(rdev->pdev, PCI_EXP_LNKCTL2, &tmp16); 7227 + tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 7253 7228 if (speed_cap == PCIE_SPEED_8_0GT) 7254 - tmp16 |= 3; /* gen3 */ 7229 + tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 7255 7230 else if (speed_cap == PCIE_SPEED_5_0GT) 7256 - tmp16 |= 2; /* gen2 */ 7231 + tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 7257 7232 else 7258 - tmp16 |= 1; /* gen1 */ 7259 - pci_write_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 7233 + tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 7234 + pcie_capability_write_word(rdev->pdev, PCI_EXP_LNKCTL2, tmp16); 7260 7235 7261 7236 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 7262 7237 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE;
+2
drivers/iommu/of_iommu.c
··· 8 8 #include <linux/export.h> 9 9 #include <linux/iommu.h> 10 10 #include <linux/limits.h> 11 + #include <linux/pci.h> 12 + #include <linux/msi.h> 11 13 #include <linux/of.h> 12 14 #include <linux/of_iommu.h> 13 15 #include <linux/of_pci.h>
+1
drivers/irqchip/irq-gic-v2m.c
··· 17 17 #include <linux/irq.h> 18 18 #include <linux/irqdomain.h> 19 19 #include <linux/kernel.h> 20 + #include <linux/pci.h> 20 21 #include <linux/msi.h> 21 22 #include <linux/of_address.h> 22 23 #include <linux/of_pci.h>
+1
drivers/irqchip/irq-gic-v3-its-pci-msi.c
··· 5 5 */ 6 6 7 7 #include <linux/acpi_iort.h> 8 + #include <linux/pci.h> 8 9 #include <linux/msi.h> 9 10 #include <linux/of.h> 10 11 #include <linux/of_irq.h>
+2 -1
drivers/pci/Makefile
··· 7 7 pci-sysfs.o rom.o setup-res.o irq.o vpd.o \ 8 8 setup-bus.o vc.o mmap.o setup-irq.o 9 9 10 + obj-$(CONFIG_PCI) += pcie/ 11 + 10 12 ifdef CONFIG_PCI 11 13 obj-$(CONFIG_PROC_FS) += proc.o 12 14 obj-$(CONFIG_SYSFS) += slot.o ··· 17 15 18 16 obj-$(CONFIG_OF) += of.o 19 17 obj-$(CONFIG_PCI_QUIRKS) += quirks.o 20 - obj-$(CONFIG_PCIEPORTBUS) += pcie/ 21 18 obj-$(CONFIG_HOTPLUG_PCI) += hotplug/ 22 19 obj-$(CONFIG_PCI_MSI) += msi.o 23 20 obj-$(CONFIG_PCI_ATS) += ats.o
+1
drivers/pci/controller/dwc/pcie-designware-host.c
··· 10 10 11 11 #include <linux/irqchip/chained_irq.h> 12 12 #include <linux/irqdomain.h> 13 + #include <linux/msi.h> 13 14 #include <linux/of_address.h> 14 15 #include <linux/of_pci.h> 15 16 #include <linux/pci_regs.h>
+1
drivers/pci/controller/pci-aardvark.c
··· 16 16 #include <linux/pci.h> 17 17 #include <linux/init.h> 18 18 #include <linux/platform_device.h> 19 + #include <linux/msi.h> 19 20 #include <linux/of_address.h> 20 21 #include <linux/of_pci.h> 21 22
+1
drivers/pci/controller/pci-thunder-pem.c
··· 6 6 #include <linux/bitfield.h> 7 7 #include <linux/kernel.h> 8 8 #include <linux/init.h> 9 + #include <linux/pci.h> 9 10 #include <linux/of_address.h> 10 11 #include <linux/of_pci.h> 11 12 #include <linux/pci-acpi.h>
+1 -1
drivers/pci/controller/pcie-cadence.h
··· 1 - // SPDX-License-Identifier: GPL-2.0 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 2 // Copyright (c) 2017 Cadence 3 3 // Cadence PCIe controller driver. 4 4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
+1 -1
drivers/pci/controller/pcie-rockchip.h
··· 1 - // SPDX-License-Identifier: GPL-2.0+ 1 + /* SPDX-License-Identifier: GPL-2.0+ */ 2 2 /* 3 3 * Rockchip AXI PCIe controller driver 4 4 *
-18
drivers/pci/pci-sysfs.c
··· 1536 1536 NULL, 1537 1537 }; 1538 1538 1539 - static const struct attribute_group pci_bridge_group = { 1540 - .attrs = pci_bridge_attrs, 1541 - }; 1542 - 1543 - const struct attribute_group *pci_bridge_groups[] = { 1544 - &pci_bridge_group, 1545 - NULL, 1546 - }; 1547 - 1548 - static const struct attribute_group pcie_dev_group = { 1549 - .attrs = pcie_dev_attrs, 1550 - }; 1551 - 1552 - const struct attribute_group *pcie_dev_groups[] = { 1553 - &pcie_dev_group, 1554 - NULL, 1555 - }; 1556 - 1557 1539 static const struct attribute_group pci_dev_hp_attr_group = { 1558 1540 .attrs = pci_dev_hp_attrs, 1559 1541 .is_visible = pci_dev_hp_attrs_are_visible,
+1
drivers/pci/pci.c
··· 13 13 #include <linux/delay.h> 14 14 #include <linux/dmi.h> 15 15 #include <linux/init.h> 16 + #include <linux/msi.h> 16 17 #include <linux/of.h> 17 18 #include <linux/of_pci.h> 18 19 #include <linux/pci.h>
-3
drivers/pci/pcie/Kconfig
··· 4 4 # 5 5 config PCIEPORTBUS 6 6 bool "PCI Express Port Bus support" 7 - depends on PCI 8 7 help 9 8 This enables PCI Express Port Bus support. Users can then enable 10 9 support for Native Hot-Plug, Advanced Error Reporting, Power ··· 62 63 # 63 64 config PCIEASPM 64 65 bool "PCI Express ASPM control" if EXPERT 65 - depends on PCI && PCIEPORTBUS 66 66 default y 67 67 help 68 68 This enables OS control over PCI Express ASPM (Active State ··· 126 128 127 129 config PCIE_PTM 128 130 bool "PCI Express Precision Time Measurement support" 129 - depends on PCIEPORTBUS 130 131 help 131 132 This enables PCI Express Precision Time Measurement (PTM) 132 133 support.
+1 -1
drivers/pci/pcie/ptm.c
··· 21 21 snprintf(clock_desc, sizeof(clock_desc), ">254ns"); 22 22 break; 23 23 default: 24 - snprintf(clock_desc, sizeof(clock_desc), "%udns", 24 + snprintf(clock_desc, sizeof(clock_desc), "%uns", 25 25 dev->ptm_granularity); 26 26 break; 27 27 }
+1
drivers/pci/probe.c
··· 7 7 #include <linux/delay.h> 8 8 #include <linux/init.h> 9 9 #include <linux/pci.h> 10 + #include <linux/msi.h> 10 11 #include <linux/of_device.h> 11 12 #include <linux/of_pci.h> 12 13 #include <linux/pci_hotplug.h>
+2 -3
include/linux/of_pci.h
··· 2 2 #ifndef __OF_PCI_H 3 3 #define __OF_PCI_H 4 4 5 - #include <linux/pci.h> 6 - #include <linux/msi.h> 5 + #include <linux/types.h> 6 + #include <linux/errno.h> 7 7 8 8 struct pci_dev; 9 - struct of_phandle_args; 10 9 struct device_node; 11 10 12 11 #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_PCI)
+2
include/uapi/linux/pci_regs.h
··· 673 673 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ 674 674 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */ 675 675 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 /* Supported Speed 32GT/s */ 676 + #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ 677 + #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ 676 678 #define PCI_EXP_LNKSTA2 50 /* Link Status 2 */ 677 679 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */ 678 680 #define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */