Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux

clk: tegra: Add stubs needed for compile-testing

Add stubs needed for compile-testing of Tegra memory drivers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

authored by

Dmitry Osipenko and committed by
Thierry Reding
e848edae 4782c0a5

+79 -26
-5
drivers/soc/tegra/pmc.c
··· 743 743 return err; 744 744 } 745 745 746 - int __weak tegra210_clk_handle_mbist_war(unsigned int id) 747 - { 748 - return 0; 749 - } 750 - 751 746 static int tegra_powergate_power_up(struct tegra_powergate *pg, 752 747 bool disable_clocks) 753 748 {
+79 -21
include/linux/clk/tegra.h
··· 123 123 } 124 124 #endif 125 125 126 - extern int tegra210_plle_hw_sequence_start(void); 127 - extern bool tegra210_plle_hw_sequence_is_enabled(void); 128 - extern void tegra210_xusb_pll_hw_control_enable(void); 129 - extern void tegra210_xusb_pll_hw_sequence_start(void); 130 - extern void tegra210_sata_pll_hw_control_enable(void); 131 - extern void tegra210_sata_pll_hw_sequence_start(void); 132 - extern void tegra210_set_sata_pll_seq_sw(bool state); 133 - extern void tegra210_put_utmipll_in_iddq(void); 134 - extern void tegra210_put_utmipll_out_iddq(void); 135 - extern int tegra210_clk_handle_mbist_war(unsigned int id); 136 - extern void tegra210_clk_emc_dll_enable(bool flag); 137 - extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); 138 - extern void tegra210_clk_emc_update_setting(u32 emc_src_value); 139 - 140 126 struct clk; 141 127 struct tegra_emc; 142 128 ··· 130 144 unsigned long min_rate, 131 145 unsigned long max_rate, 132 146 void *arg); 133 - 134 - void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, 135 - void *cb_arg); 136 - int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); 137 - 138 147 typedef int (tegra124_emc_prepare_timing_change_cb)(struct tegra_emc *emc, 139 148 unsigned long rate); 140 149 typedef void (tegra124_emc_complete_timing_change_cb)(struct tegra_emc *emc, 141 150 unsigned long rate); 142 - void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, 143 - tegra124_emc_complete_timing_change_cb *complete_cb); 144 151 145 152 struct tegra210_clk_emc_config { 146 153 unsigned long rate; ··· 155 176 const struct tegra210_clk_emc_config *config); 156 177 }; 157 178 179 + #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) 180 + void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, 181 + void *cb_arg); 182 + int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same); 183 + #else 184 + static inline void 185 + tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb, 186 + void *cb_arg) 187 + { 188 + } 189 + 190 + static inline int 191 + tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same) 192 + { 193 + return 0; 194 + } 195 + #endif 196 + 197 + #ifdef CONFIG_TEGRA124_CLK_EMC 198 + void tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, 199 + tegra124_emc_complete_timing_change_cb *complete_cb); 200 + #else 201 + static inline void 202 + tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb, 203 + tegra124_emc_complete_timing_change_cb *complete_cb) 204 + { 205 + } 206 + #endif 207 + 208 + #ifdef CONFIG_ARCH_TEGRA_210_SOC 209 + int tegra210_plle_hw_sequence_start(void); 210 + bool tegra210_plle_hw_sequence_is_enabled(void); 211 + void tegra210_xusb_pll_hw_control_enable(void); 212 + void tegra210_xusb_pll_hw_sequence_start(void); 213 + void tegra210_sata_pll_hw_control_enable(void); 214 + void tegra210_sata_pll_hw_sequence_start(void); 215 + void tegra210_set_sata_pll_seq_sw(bool state); 216 + void tegra210_put_utmipll_in_iddq(void); 217 + void tegra210_put_utmipll_out_iddq(void); 218 + int tegra210_clk_handle_mbist_war(unsigned int id); 219 + void tegra210_clk_emc_dll_enable(bool flag); 220 + void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value); 221 + void tegra210_clk_emc_update_setting(u32 emc_src_value); 222 + 158 223 int tegra210_clk_emc_attach(struct clk *clk, 159 224 struct tegra210_clk_emc_provider *provider); 160 225 void tegra210_clk_emc_detach(struct clk *clk); 226 + #else 227 + static inline int tegra210_plle_hw_sequence_start(void) 228 + { 229 + return 0; 230 + } 231 + 232 + static inline bool tegra210_plle_hw_sequence_is_enabled(void) 233 + { 234 + return false; 235 + } 236 + 237 + static inline int tegra210_clk_handle_mbist_war(unsigned int id) 238 + { 239 + return 0; 240 + } 241 + 242 + static inline int 243 + tegra210_clk_emc_attach(struct clk *clk, 244 + struct tegra210_clk_emc_provider *provider) 245 + { 246 + return 0; 247 + } 248 + 249 + static inline void tegra210_xusb_pll_hw_control_enable(void) {} 250 + static inline void tegra210_xusb_pll_hw_sequence_start(void) {} 251 + static inline void tegra210_sata_pll_hw_control_enable(void) {} 252 + static inline void tegra210_sata_pll_hw_sequence_start(void) {} 253 + static inline void tegra210_set_sata_pll_seq_sw(bool state) {} 254 + static inline void tegra210_put_utmipll_in_iddq(void) {} 255 + static inline void tegra210_put_utmipll_out_iddq(void) {} 256 + static inline void tegra210_clk_emc_dll_enable(bool flag) {} 257 + static inline void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) {} 258 + static inline void tegra210_clk_emc_update_setting(u32 emc_src_value) {} 259 + static inline void tegra210_clk_emc_detach(struct clk *clk) {} 260 + #endif 161 261 162 262 #endif /* __LINUX_CLK_TEGRA_H_ */