tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Disintegrate asm/system.h for SH
Disintegrate asm/system.h for SH.
Signed-off-by: David Howells <dhowells@redhat.com>
cc: linux-sh@vger.kernel.org
+503
-396
-1
arch/sh/boards/mach-microdev/irq.c
-1
arch/sh/boards/mach-microdev/irq.c
+2
arch/sh/include/asm/atomic-irq.h
+2
arch/sh/include/asm/atomic-irq.h
+1
-1
arch/sh/include/asm/atomic.h
+1
-1
arch/sh/include/asm/atomic.h
+2
arch/sh/include/asm/auxvec.h
+2
arch/sh/include/asm/auxvec.h
+54
arch/sh/include/asm/barrier.h
+54
arch/sh/include/asm/barrier.h
···
1
+
/*
2
+
* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
3
+
* Copyright (C) 2002 Paul Mundt
4
+
*/
5
+
#ifndef __ASM_SH_BARRIER_H
6
+
#define __ASM_SH_BARRIER_H
7
+
8
+
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
9
+
#include <asm/cache_insns.h>
10
+
#endif
11
+
12
+
/*
13
+
* A brief note on ctrl_barrier(), the control register write barrier.
14
+
*
15
+
* Legacy SH cores typically require a sequence of 8 nops after
16
+
* modification of a control register in order for the changes to take
17
+
* effect. On newer cores (like the sh4a and sh5) this is accomplished
18
+
* with icbi.
19
+
*
20
+
* Also note that on sh4a in the icbi case we can forego a synco for the
21
+
* write barrier, as it's not necessary for control registers.
22
+
*
23
+
* Historically we have only done this type of barrier for the MMUCR, but
24
+
* it's also necessary for the CCR, so we make it generic here instead.
25
+
*/
26
+
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
27
+
#define mb() __asm__ __volatile__ ("synco": : :"memory")
28
+
#define rmb() mb()
29
+
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
30
+
#define ctrl_barrier() __icbi(PAGE_OFFSET)
31
+
#define read_barrier_depends() do { } while(0)
32
+
#else
33
+
#define mb() __asm__ __volatile__ ("": : :"memory")
34
+
#define rmb() mb()
35
+
#define wmb() __asm__ __volatile__ ("": : :"memory")
36
+
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
37
+
#define read_barrier_depends() do { } while(0)
38
+
#endif
39
+
40
+
#ifdef CONFIG_SMP
41
+
#define smp_mb() mb()
42
+
#define smp_rmb() rmb()
43
+
#define smp_wmb() wmb()
44
+
#define smp_read_barrier_depends() read_barrier_depends()
45
+
#else
46
+
#define smp_mb() barrier()
47
+
#define smp_rmb() barrier()
48
+
#define smp_wmb() barrier()
49
+
#define smp_read_barrier_depends() do { } while(0)
50
+
#endif
51
+
52
+
#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
53
+
54
+
#endif /* __ASM_SH_BARRIER_H */
-1
arch/sh/include/asm/bitops.h
-1
arch/sh/include/asm/bitops.h
+10
arch/sh/include/asm/bl_bit.h
+10
arch/sh/include/asm/bl_bit.h
+33
arch/sh/include/asm/bl_bit_32.h
+33
arch/sh/include/asm/bl_bit_32.h
···
1
+
#ifndef __ASM_SH_BL_BIT_32_H
2
+
#define __ASM_SH_BL_BIT_32_H
3
+
4
+
static inline void set_bl_bit(void)
5
+
{
6
+
unsigned long __dummy0, __dummy1;
7
+
8
+
__asm__ __volatile__ (
9
+
"stc sr, %0\n\t"
10
+
"or %2, %0\n\t"
11
+
"and %3, %0\n\t"
12
+
"ldc %0, sr\n\t"
13
+
: "=&r" (__dummy0), "=r" (__dummy1)
14
+
: "r" (0x10000000), "r" (0xffffff0f)
15
+
: "memory"
16
+
);
17
+
}
18
+
19
+
static inline void clear_bl_bit(void)
20
+
{
21
+
unsigned long __dummy0, __dummy1;
22
+
23
+
__asm__ __volatile__ (
24
+
"stc sr, %0\n\t"
25
+
"and %2, %0\n\t"
26
+
"ldc %0, sr\n\t"
27
+
: "=&r" (__dummy0), "=r" (__dummy1)
28
+
: "1" (~0x10000000)
29
+
: "memory"
30
+
);
31
+
}
32
+
33
+
#endif /* __ASM_SH_BL_BIT_32_H */
+40
arch/sh/include/asm/bl_bit_64.h
+40
arch/sh/include/asm/bl_bit_64.h
···
1
+
/*
2
+
* Copyright (C) 2000, 2001 Paolo Alberelli
3
+
* Copyright (C) 2003 Paul Mundt
4
+
* Copyright (C) 2004 Richard Curnow
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_SH_BL_BIT_64_H
11
+
#define __ASM_SH_BL_BIT_64_H
12
+
13
+
#include <asm/processor.h>
14
+
15
+
#define SR_BL_LL 0x0000000010000000LL
16
+
17
+
static inline void set_bl_bit(void)
18
+
{
19
+
unsigned long long __dummy0, __dummy1 = SR_BL_LL;
20
+
21
+
__asm__ __volatile__("getcon " __SR ", %0\n\t"
22
+
"or %0, %1, %0\n\t"
23
+
"putcon %0, " __SR "\n\t"
24
+
: "=&r" (__dummy0)
25
+
: "r" (__dummy1));
26
+
27
+
}
28
+
29
+
static inline void clear_bl_bit(void)
30
+
{
31
+
unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
32
+
33
+
__asm__ __volatile__("getcon " __SR ", %0\n\t"
34
+
"and %0, %1, %0\n\t"
35
+
"putcon %0, " __SR "\n\t"
36
+
: "=&r" (__dummy0)
37
+
: "r" (__dummy1));
38
+
}
39
+
40
+
#endif /* __ASM_SH_BL_BIT_64_H */
+5
arch/sh/include/asm/bug.h
+5
arch/sh/include/asm/bug.h
···
1
1
#ifndef __ASM_SH_BUG_H
2
2
#define __ASM_SH_BUG_H
3
3
4
+
#include <linux/linkage.h>
5
+
4
6
#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
5
7
#define BUGFLAG_UNWINDER (1 << 1)
6
8
···
108
106
#endif /* CONFIG_GENERIC_BUG */
109
107
110
108
#include <asm-generic/bug.h>
109
+
110
+
struct pt_regs;
111
+
extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
111
112
112
113
#endif /* __ASM_SH_BUG_H */
+11
arch/sh/include/asm/cache_insns.h
+11
arch/sh/include/asm/cache_insns.h
+21
arch/sh/include/asm/cache_insns_32.h
+21
arch/sh/include/asm/cache_insns_32.h
···
1
+
#ifndef __ASM_SH_CACHE_INSNS_32_H
2
+
#define __ASM_SH_CACHE_INSNS_32_H
3
+
4
+
#include <linux/types.h>
5
+
6
+
#if defined(CONFIG_CPU_SH4A)
7
+
#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
8
+
#else
9
+
#define __icbi(addr) mb()
10
+
#endif
11
+
12
+
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
13
+
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
14
+
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
15
+
16
+
static inline reg_size_t register_align(void *val)
17
+
{
18
+
return (unsigned long)(signed long)val;
19
+
}
20
+
21
+
#endif /* __ASM_SH_CACHE_INSNS_32_H */
+23
arch/sh/include/asm/cache_insns_64.h
+23
arch/sh/include/asm/cache_insns_64.h
···
1
+
/*
2
+
* Copyright (C) 2000, 2001 Paolo Alberelli
3
+
* Copyright (C) 2003 Paul Mundt
4
+
* Copyright (C) 2004 Richard Curnow
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_SH_CACHE_INSNS_64_H
11
+
#define __ASM_SH_CACHE_INSNS_64_H
12
+
13
+
#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
14
+
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
15
+
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
16
+
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
17
+
18
+
static inline reg_size_t register_align(void *val)
19
+
{
20
+
return (unsigned long long)(signed long long)(signed long)val;
21
+
}
22
+
23
+
#endif /* __ASM_SH_CACHE_INSNS_64_H */
+2
arch/sh/include/asm/cmpxchg-irq.h
+2
arch/sh/include/asm/cmpxchg-irq.h
+70
arch/sh/include/asm/cmpxchg.h
+70
arch/sh/include/asm/cmpxchg.h
···
1
+
#ifndef __ASM_SH_CMPXCHG_H
2
+
#define __ASM_SH_CMPXCHG_H
3
+
4
+
/*
5
+
* Atomic operations that C can't guarantee us. Useful for
6
+
* resource counting etc..
7
+
*/
8
+
9
+
#include <linux/compiler.h>
10
+
#include <linux/types.h>
11
+
12
+
#if defined(CONFIG_GUSA_RB)
13
+
#include <asm/cmpxchg-grb.h>
14
+
#elif defined(CONFIG_CPU_SH4A)
15
+
#include <asm/cmpxchg-llsc.h>
16
+
#else
17
+
#include <asm/cmpxchg-irq.h>
18
+
#endif
19
+
20
+
extern void __xchg_called_with_bad_pointer(void);
21
+
22
+
#define __xchg(ptr, x, size) \
23
+
({ \
24
+
unsigned long __xchg__res; \
25
+
volatile void *__xchg_ptr = (ptr); \
26
+
switch (size) { \
27
+
case 4: \
28
+
__xchg__res = xchg_u32(__xchg_ptr, x); \
29
+
break; \
30
+
case 1: \
31
+
__xchg__res = xchg_u8(__xchg_ptr, x); \
32
+
break; \
33
+
default: \
34
+
__xchg_called_with_bad_pointer(); \
35
+
__xchg__res = x; \
36
+
break; \
37
+
} \
38
+
\
39
+
__xchg__res; \
40
+
})
41
+
42
+
#define xchg(ptr,x) \
43
+
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
44
+
45
+
/* This function doesn't exist, so you'll get a linker error
46
+
* if something tries to do an invalid cmpxchg(). */
47
+
extern void __cmpxchg_called_with_bad_pointer(void);
48
+
49
+
#define __HAVE_ARCH_CMPXCHG 1
50
+
51
+
static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
52
+
unsigned long new, int size)
53
+
{
54
+
switch (size) {
55
+
case 4:
56
+
return __cmpxchg_u32(ptr, old, new);
57
+
}
58
+
__cmpxchg_called_with_bad_pointer();
59
+
return old;
60
+
}
61
+
62
+
#define cmpxchg(ptr,o,n) \
63
+
({ \
64
+
__typeof__(*(ptr)) _o_ = (o); \
65
+
__typeof__(*(ptr)) _n_ = (n); \
66
+
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
67
+
(unsigned long)_n_, sizeof(*(ptr))); \
68
+
})
69
+
70
+
#endif /* __ASM_SH_CMPXCHG_H */
+10
arch/sh/include/asm/exec.h
+10
arch/sh/include/asm/exec.h
-1
arch/sh/include/asm/futex-irq.h
-1
arch/sh/include/asm/futex-irq.h
-1
arch/sh/include/asm/io.h
-1
arch/sh/include/asm/io.h
+15
arch/sh/include/asm/processor.h
+15
arch/sh/include/asm/processor.h
···
101
101
#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
102
102
#define cpu_relax() barrier()
103
103
104
+
void default_idle(void);
105
+
void cpu_idle_wait(void);
106
+
void stop_this_cpu(void *);
107
+
104
108
/* Forward decl */
105
109
struct seq_operations;
106
110
struct task_struct;
···
163
159
int vsyscall_init(void);
164
160
#else
165
161
#define vsyscall_init() do { } while (0)
162
+
#endif
163
+
164
+
/*
165
+
* SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
166
+
*/
167
+
#ifdef CONFIG_CPU_SH2A
168
+
extern unsigned int instruction_size(unsigned int insn);
169
+
#elif defined(CONFIG_SUPERH32)
170
+
#define instruction_size(insn) (2)
171
+
#else
172
+
#define instruction_size(insn) (4)
166
173
#endif
167
174
168
175
#endif /* __ASSEMBLY__ */
-1
arch/sh/include/asm/ptrace.h
-1
arch/sh/include/asm/ptrace.h
+1
arch/sh/include/asm/setup.h
+1
arch/sh/include/asm/setup.h
+19
arch/sh/include/asm/switch_to.h
+19
arch/sh/include/asm/switch_to.h
···
1
+
/*
2
+
* Copyright (C) 2000, 2001 Paolo Alberelli
3
+
* Copyright (C) 2003 Paul Mundt
4
+
* Copyright (C) 2004 Richard Curnow
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_SH_SWITCH_TO_H
11
+
#define __ASM_SH_SWITCH_TO_H
12
+
13
+
#ifdef CONFIG_SUPERH32
14
+
# include "switch_to_32.h"
15
+
#else
16
+
# include "switch_to_64.h"
17
+
#endif
18
+
19
+
#endif /* __ASM_SH_SWITCH_TO_H */
+35
arch/sh/include/asm/switch_to_64.h
+35
arch/sh/include/asm/switch_to_64.h
···
1
+
/*
2
+
* Copyright (C) 2000, 2001 Paolo Alberelli
3
+
* Copyright (C) 2003 Paul Mundt
4
+
* Copyright (C) 2004 Richard Curnow
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_SH_SWITCH_TO_64_H
11
+
#define __ASM_SH_SWITCH_TO_64_H
12
+
13
+
struct thread_struct;
14
+
struct task_struct;
15
+
16
+
/*
17
+
* switch_to() should switch tasks to task nr n, first
18
+
*/
19
+
struct task_struct *sh64_switch_to(struct task_struct *prev,
20
+
struct thread_struct *prev_thread,
21
+
struct task_struct *next,
22
+
struct thread_struct *next_thread);
23
+
24
+
#define switch_to(prev,next,last) \
25
+
do { \
26
+
if (last_task_used_math != next) { \
27
+
struct pt_regs *regs = next->thread.uregs; \
28
+
if (regs) regs->sr |= SR_FD; \
29
+
} \
30
+
last = sh64_switch_to(prev, &prev->thread, next, \
31
+
&next->thread); \
32
+
} while (0)
33
+
34
+
35
+
#endif /* __ASM_SH_SWITCH_TO_64_H */
+8
-183
arch/sh/include/asm/system.h
+8
-183
arch/sh/include/asm/system.h
···
1
-
#ifndef __ASM_SH_SYSTEM_H
2
-
#define __ASM_SH_SYSTEM_H
3
-
4
-
/*
5
-
* Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima
6
-
* Copyright (C) 2002 Paul Mundt
7
-
*/
8
-
9
-
#include <linux/irqflags.h>
10
-
#include <linux/compiler.h>
11
-
#include <linux/linkage.h>
12
-
#include <asm/types.h>
13
-
#include <asm/uncached.h>
14
-
15
-
#define AT_VECTOR_SIZE_ARCH 5 /* entries in ARCH_DLINFO */
16
-
17
-
/*
18
-
* A brief note on ctrl_barrier(), the control register write barrier.
19
-
*
20
-
* Legacy SH cores typically require a sequence of 8 nops after
21
-
* modification of a control register in order for the changes to take
22
-
* effect. On newer cores (like the sh4a and sh5) this is accomplished
23
-
* with icbi.
24
-
*
25
-
* Also note that on sh4a in the icbi case we can forego a synco for the
26
-
* write barrier, as it's not necessary for control registers.
27
-
*
28
-
* Historically we have only done this type of barrier for the MMUCR, but
29
-
* it's also necessary for the CCR, so we make it generic here instead.
30
-
*/
31
-
#if defined(CONFIG_CPU_SH4A) || defined(CONFIG_CPU_SH5)
32
-
#define mb() __asm__ __volatile__ ("synco": : :"memory")
33
-
#define rmb() mb()
34
-
#define wmb() __asm__ __volatile__ ("synco": : :"memory")
35
-
#define ctrl_barrier() __icbi(PAGE_OFFSET)
36
-
#define read_barrier_depends() do { } while(0)
37
-
#else
38
-
#define mb() __asm__ __volatile__ ("": : :"memory")
39
-
#define rmb() mb()
40
-
#define wmb() __asm__ __volatile__ ("": : :"memory")
41
-
#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop")
42
-
#define read_barrier_depends() do { } while(0)
43
-
#endif
44
-
45
-
#ifdef CONFIG_SMP
46
-
#define smp_mb() mb()
47
-
#define smp_rmb() rmb()
48
-
#define smp_wmb() wmb()
49
-
#define smp_read_barrier_depends() read_barrier_depends()
50
-
#else
51
-
#define smp_mb() barrier()
52
-
#define smp_rmb() barrier()
53
-
#define smp_wmb() barrier()
54
-
#define smp_read_barrier_depends() do { } while(0)
55
-
#endif
56
-
57
-
#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
58
-
59
-
#ifdef CONFIG_GUSA_RB
60
-
#include <asm/cmpxchg-grb.h>
61
-
#elif defined(CONFIG_CPU_SH4A)
62
-
#include <asm/cmpxchg-llsc.h>
63
-
#else
64
-
#include <asm/cmpxchg-irq.h>
65
-
#endif
66
-
67
-
extern void __xchg_called_with_bad_pointer(void);
68
-
69
-
#define __xchg(ptr, x, size) \
70
-
({ \
71
-
unsigned long __xchg__res; \
72
-
volatile void *__xchg_ptr = (ptr); \
73
-
switch (size) { \
74
-
case 4: \
75
-
__xchg__res = xchg_u32(__xchg_ptr, x); \
76
-
break; \
77
-
case 1: \
78
-
__xchg__res = xchg_u8(__xchg_ptr, x); \
79
-
break; \
80
-
default: \
81
-
__xchg_called_with_bad_pointer(); \
82
-
__xchg__res = x; \
83
-
break; \
84
-
} \
85
-
\
86
-
__xchg__res; \
87
-
})
88
-
89
-
#define xchg(ptr,x) \
90
-
((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr))))
91
-
92
-
/* This function doesn't exist, so you'll get a linker error
93
-
* if something tries to do an invalid cmpxchg(). */
94
-
extern void __cmpxchg_called_with_bad_pointer(void);
95
-
96
-
#define __HAVE_ARCH_CMPXCHG 1
97
-
98
-
static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
99
-
unsigned long new, int size)
100
-
{
101
-
switch (size) {
102
-
case 4:
103
-
return __cmpxchg_u32(ptr, old, new);
104
-
}
105
-
__cmpxchg_called_with_bad_pointer();
106
-
return old;
107
-
}
108
-
109
-
#define cmpxchg(ptr,o,n) \
110
-
({ \
111
-
__typeof__(*(ptr)) _o_ = (o); \
112
-
__typeof__(*(ptr)) _n_ = (n); \
113
-
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
114
-
(unsigned long)_n_, sizeof(*(ptr))); \
115
-
})
116
-
117
-
struct pt_regs;
118
-
119
-
extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
1
+
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
2
+
#include <asm/barrier.h>
3
+
#include <asm/bl_bit.h>
4
+
#include <asm/cache_insns.h>
5
+
#include <asm/cmpxchg.h>
6
+
#include <asm/exec.h>
7
+
#include <asm/switch_to.h>
8
+
#include <asm/traps.h>
120
9
void free_initmem(void);
121
-
void free_initrd_mem(unsigned long start, unsigned long end);
122
-
123
-
extern void *set_exception_table_vec(unsigned int vec, void *handler);
124
-
125
-
static inline void *set_exception_table_evt(unsigned int evt, void *handler)
126
-
{
127
-
return set_exception_table_vec(evt >> 5, handler);
128
-
}
129
-
130
-
/*
131
-
* SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
132
-
*/
133
-
#ifdef CONFIG_CPU_SH2A
134
-
extern unsigned int instruction_size(unsigned int insn);
135
-
#elif defined(CONFIG_SUPERH32)
136
-
#define instruction_size(insn) (2)
137
-
#else
138
-
#define instruction_size(insn) (4)
139
-
#endif
140
-
141
-
void per_cpu_trap_init(void);
142
-
void default_idle(void);
143
-
void cpu_idle_wait(void);
144
-
void stop_this_cpu(void *);
145
-
146
-
#ifdef CONFIG_SUPERH32
147
-
#define BUILD_TRAP_HANDLER(name) \
148
-
asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
149
-
unsigned long r6, unsigned long r7, \
150
-
struct pt_regs __regs)
151
-
152
-
#define TRAP_HANDLER_DECL \
153
-
struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
154
-
unsigned int vec = regs->tra; \
155
-
(void)vec;
156
-
#else
157
-
#define BUILD_TRAP_HANDLER(name) \
158
-
asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
159
-
#define TRAP_HANDLER_DECL
160
-
#endif
161
-
162
-
BUILD_TRAP_HANDLER(address_error);
163
-
BUILD_TRAP_HANDLER(debug);
164
-
BUILD_TRAP_HANDLER(bug);
165
-
BUILD_TRAP_HANDLER(breakpoint);
166
-
BUILD_TRAP_HANDLER(singlestep);
167
-
BUILD_TRAP_HANDLER(fpu_error);
168
-
BUILD_TRAP_HANDLER(fpu_state_restore);
169
-
BUILD_TRAP_HANDLER(nmi);
170
-
171
-
#define arch_align_stack(x) (x)
172
-
173
-
struct mem_access {
174
-
unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
175
-
unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
176
-
};
177
-
178
-
#ifdef CONFIG_SUPERH32
179
-
# include "system_32.h"
180
-
#else
181
-
# include "system_64.h"
182
-
#endif
183
-
184
-
#endif
+3
-105
arch/sh/include/asm/system_32.h
arch/sh/include/asm/switch_to_32.h
+3
-105
arch/sh/include/asm/system_32.h
arch/sh/include/asm/switch_to_32.h
···
1
-
#ifndef __ASM_SH_SYSTEM_32_H
2
-
#define __ASM_SH_SYSTEM_32_H
3
-
4
-
#include <linux/types.h>
5
-
#include <asm/mmu.h>
1
+
#ifndef __ASM_SH_SWITCH_TO_32_H
2
+
#define __ASM_SH_SWITCH_TO_32_H
6
3
7
4
#ifdef CONFIG_SH_DSP
8
5
···
28
31
"ldc.l @r2+, mod\n\t" \
29
32
: : "r" (__ts2)); \
30
33
} while (0)
31
-
32
34
33
35
#define __save_dsp(tsk) \
34
36
do { \
···
59
63
#define __save_dsp(tsk) do { } while (0)
60
64
#define __restore_dsp(tsk) do { } while (0)
61
65
#endif
62
-
63
-
#if defined(CONFIG_CPU_SH4A)
64
-
#define __icbi(addr) __asm__ __volatile__ ( "icbi @%0\n\t" : : "r" (addr))
65
-
#else
66
-
#define __icbi(addr) mb()
67
-
#endif
68
-
69
-
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp @%0\n\t" : : "r" (addr))
70
-
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi @%0\n\t" : : "r" (addr))
71
-
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb @%0\n\t" : : "r" (addr))
72
66
73
67
struct task_struct *__switch_to(struct task_struct *prev,
74
68
struct task_struct *next);
···
131
145
__restore_dsp(prev); \
132
146
} while (0)
133
147
134
-
#ifdef CONFIG_CPU_HAS_SR_RB
135
-
#define lookup_exception_vector() \
136
-
({ \
137
-
unsigned long _vec; \
138
-
\
139
-
__asm__ __volatile__ ( \
140
-
"stc r2_bank, %0\n\t" \
141
-
: "=r" (_vec) \
142
-
); \
143
-
\
144
-
_vec; \
145
-
})
146
-
#else
147
-
#define lookup_exception_vector() \
148
-
({ \
149
-
unsigned long _vec; \
150
-
__asm__ __volatile__ ( \
151
-
"mov r4, %0\n\t" \
152
-
: "=r" (_vec) \
153
-
); \
154
-
\
155
-
_vec; \
156
-
})
157
-
#endif
158
-
159
-
static inline reg_size_t register_align(void *val)
160
-
{
161
-
return (unsigned long)(signed long)val;
162
-
}
163
-
164
-
int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
165
-
struct mem_access *ma, int, unsigned long address);
166
-
167
-
static inline void trigger_address_error(void)
168
-
{
169
-
__asm__ __volatile__ (
170
-
"ldc %0, sr\n\t"
171
-
"mov.l @%1, %0"
172
-
:
173
-
: "r" (0x10000000), "r" (0x80000001)
174
-
);
175
-
}
176
-
177
-
asmlinkage void do_address_error(struct pt_regs *regs,
178
-
unsigned long writeaccess,
179
-
unsigned long address);
180
-
asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
181
-
unsigned long r6, unsigned long r7,
182
-
struct pt_regs __regs);
183
-
asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
184
-
unsigned long r6, unsigned long r7,
185
-
struct pt_regs __regs);
186
-
asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
187
-
unsigned long r6, unsigned long r7,
188
-
struct pt_regs __regs);
189
-
asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
190
-
unsigned long r6, unsigned long r7,
191
-
struct pt_regs __regs);
192
-
193
-
static inline void set_bl_bit(void)
194
-
{
195
-
unsigned long __dummy0, __dummy1;
196
-
197
-
__asm__ __volatile__ (
198
-
"stc sr, %0\n\t"
199
-
"or %2, %0\n\t"
200
-
"and %3, %0\n\t"
201
-
"ldc %0, sr\n\t"
202
-
: "=&r" (__dummy0), "=r" (__dummy1)
203
-
: "r" (0x10000000), "r" (0xffffff0f)
204
-
: "memory"
205
-
);
206
-
}
207
-
208
-
static inline void clear_bl_bit(void)
209
-
{
210
-
unsigned long __dummy0, __dummy1;
211
-
212
-
__asm__ __volatile__ (
213
-
"stc sr, %0\n\t"
214
-
"and %2, %0\n\t"
215
-
"ldc %0, sr\n\t"
216
-
: "=&r" (__dummy0), "=r" (__dummy1)
217
-
: "1" (~0x10000000)
218
-
: "memory"
219
-
);
220
-
}
221
-
222
-
#endif /* __ASM_SH_SYSTEM_32_H */
148
+
#endif /* __ASM_SH_SWITCH_TO_32_H */
-79
arch/sh/include/asm/system_64.h
-79
arch/sh/include/asm/system_64.h
···
1
-
#ifndef __ASM_SH_SYSTEM_64_H
2
-
#define __ASM_SH_SYSTEM_64_H
3
-
4
-
/*
5
-
* include/asm-sh/system_64.h
6
-
*
7
-
* Copyright (C) 2000, 2001 Paolo Alberelli
8
-
* Copyright (C) 2003 Paul Mundt
9
-
* Copyright (C) 2004 Richard Curnow
10
-
*
11
-
* This file is subject to the terms and conditions of the GNU General Public
12
-
* License. See the file "COPYING" in the main directory of this archive
13
-
* for more details.
14
-
*/
15
-
#include <cpu/registers.h>
16
-
#include <asm/processor.h>
17
-
18
-
/*
19
-
* switch_to() should switch tasks to task nr n, first
20
-
*/
21
-
struct thread_struct;
22
-
struct task_struct *sh64_switch_to(struct task_struct *prev,
23
-
struct thread_struct *prev_thread,
24
-
struct task_struct *next,
25
-
struct thread_struct *next_thread);
26
-
27
-
#define switch_to(prev,next,last) \
28
-
do { \
29
-
if (last_task_used_math != next) { \
30
-
struct pt_regs *regs = next->thread.uregs; \
31
-
if (regs) regs->sr |= SR_FD; \
32
-
} \
33
-
last = sh64_switch_to(prev, &prev->thread, next, \
34
-
&next->thread); \
35
-
} while (0)
36
-
37
-
#define __icbi(addr) __asm__ __volatile__ ( "icbi %0, 0\n\t" : : "r" (addr))
38
-
#define __ocbp(addr) __asm__ __volatile__ ( "ocbp %0, 0\n\t" : : "r" (addr))
39
-
#define __ocbi(addr) __asm__ __volatile__ ( "ocbi %0, 0\n\t" : : "r" (addr))
40
-
#define __ocbwb(addr) __asm__ __volatile__ ( "ocbwb %0, 0\n\t" : : "r" (addr))
41
-
42
-
static inline reg_size_t register_align(void *val)
43
-
{
44
-
return (unsigned long long)(signed long long)(signed long)val;
45
-
}
46
-
47
-
extern void phys_stext(void);
48
-
49
-
static inline void trigger_address_error(void)
50
-
{
51
-
phys_stext();
52
-
}
53
-
54
-
#define SR_BL_LL 0x0000000010000000LL
55
-
56
-
static inline void set_bl_bit(void)
57
-
{
58
-
unsigned long long __dummy0, __dummy1 = SR_BL_LL;
59
-
60
-
__asm__ __volatile__("getcon " __SR ", %0\n\t"
61
-
"or %0, %1, %0\n\t"
62
-
"putcon %0, " __SR "\n\t"
63
-
: "=&r" (__dummy0)
64
-
: "r" (__dummy1));
65
-
66
-
}
67
-
68
-
static inline void clear_bl_bit(void)
69
-
{
70
-
unsigned long long __dummy0, __dummy1 = ~SR_BL_LL;
71
-
72
-
__asm__ __volatile__("getcon " __SR ", %0\n\t"
73
-
"and %0, %1, %0\n\t"
74
-
"putcon %0, " __SR "\n\t"
75
-
: "=&r" (__dummy0)
76
-
: "r" (__dummy1));
77
-
}
78
-
79
-
#endif /* __ASM_SH_SYSTEM_64_H */
+21
arch/sh/include/asm/traps.h
+21
arch/sh/include/asm/traps.h
···
1
+
#ifndef __ASM_SH_TRAPS_H
2
+
#define __ASM_SH_TRAPS_H
3
+
4
+
#include <linux/compiler.h>
5
+
6
+
#ifdef CONFIG_SUPERH32
7
+
# include "traps_32.h"
8
+
#else
9
+
# include "traps_64.h"
10
+
#endif
11
+
12
+
BUILD_TRAP_HANDLER(address_error);
13
+
BUILD_TRAP_HANDLER(debug);
14
+
BUILD_TRAP_HANDLER(bug);
15
+
BUILD_TRAP_HANDLER(breakpoint);
16
+
BUILD_TRAP_HANDLER(singlestep);
17
+
BUILD_TRAP_HANDLER(fpu_error);
18
+
BUILD_TRAP_HANDLER(fpu_state_restore);
19
+
BUILD_TRAP_HANDLER(nmi);
20
+
21
+
#endif /* __ASM_SH_TRAPS_H */
+68
arch/sh/include/asm/traps_32.h
+68
arch/sh/include/asm/traps_32.h
···
1
+
#ifndef __ASM_SH_TRAPS_32_H
2
+
#define __ASM_SH_TRAPS_32_H
3
+
4
+
#include <linux/types.h>
5
+
#include <asm/mmu.h>
6
+
7
+
#ifdef CONFIG_CPU_HAS_SR_RB
8
+
#define lookup_exception_vector() \
9
+
({ \
10
+
unsigned long _vec; \
11
+
\
12
+
__asm__ __volatile__ ( \
13
+
"stc r2_bank, %0\n\t" \
14
+
: "=r" (_vec) \
15
+
); \
16
+
\
17
+
_vec; \
18
+
})
19
+
#else
20
+
#define lookup_exception_vector() \
21
+
({ \
22
+
unsigned long _vec; \
23
+
__asm__ __volatile__ ( \
24
+
"mov r4, %0\n\t" \
25
+
: "=r" (_vec) \
26
+
); \
27
+
\
28
+
_vec; \
29
+
})
30
+
#endif
31
+
32
+
static inline void trigger_address_error(void)
33
+
{
34
+
__asm__ __volatile__ (
35
+
"ldc %0, sr\n\t"
36
+
"mov.l @%1, %0"
37
+
:
38
+
: "r" (0x10000000), "r" (0x80000001)
39
+
);
40
+
}
41
+
42
+
asmlinkage void do_address_error(struct pt_regs *regs,
43
+
unsigned long writeaccess,
44
+
unsigned long address);
45
+
asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
46
+
unsigned long r6, unsigned long r7,
47
+
struct pt_regs __regs);
48
+
asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
49
+
unsigned long r6, unsigned long r7,
50
+
struct pt_regs __regs);
51
+
asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
52
+
unsigned long r6, unsigned long r7,
53
+
struct pt_regs __regs);
54
+
asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
55
+
unsigned long r6, unsigned long r7,
56
+
struct pt_regs __regs);
57
+
58
+
#define BUILD_TRAP_HANDLER(name) \
59
+
asmlinkage void name##_trap_handler(unsigned long r4, unsigned long r5, \
60
+
unsigned long r6, unsigned long r7, \
61
+
struct pt_regs __regs)
62
+
63
+
#define TRAP_HANDLER_DECL \
64
+
struct pt_regs *regs = RELOC_HIDE(&__regs, 0); \
65
+
unsigned int vec = regs->tra; \
66
+
(void)vec;
67
+
68
+
#endif /* __ASM_SH_TRAPS_32_H */
+24
arch/sh/include/asm/traps_64.h
+24
arch/sh/include/asm/traps_64.h
···
1
+
/*
2
+
* Copyright (C) 2000, 2001 Paolo Alberelli
3
+
* Copyright (C) 2003 Paul Mundt
4
+
* Copyright (C) 2004 Richard Curnow
5
+
*
6
+
* This file is subject to the terms and conditions of the GNU General Public
7
+
* License. See the file "COPYING" in the main directory of this archive
8
+
* for more details.
9
+
*/
10
+
#ifndef __ASM_SH_TRAPS_64_H
11
+
#define __ASM_SH_TRAPS_64_H
12
+
13
+
extern void phys_stext(void);
14
+
15
+
static inline void trigger_address_error(void)
16
+
{
17
+
phys_stext();
18
+
}
19
+
20
+
#define BUILD_TRAP_HANDLER(name) \
21
+
asmlinkage void name##_trap_handler(unsigned int vec, struct pt_regs *regs)
22
+
#define TRAP_HANDLER_DECL
23
+
24
+
#endif /* __ASM_SH_TRAPS_64_H */
+14
arch/sh/include/asm/uaccess.h
+14
arch/sh/include/asm/uaccess.h
···
254
254
unsigned long search_exception_table(unsigned long addr);
255
255
const struct exception_table_entry *search_exception_tables(unsigned long addr);
256
256
257
+
extern void *set_exception_table_vec(unsigned int vec, void *handler);
258
+
259
+
static inline void *set_exception_table_evt(unsigned int evt, void *handler)
260
+
{
261
+
return set_exception_table_vec(evt >> 5, handler);
262
+
}
263
+
264
+
struct mem_access {
265
+
unsigned long (*from)(void *dst, const void __user *src, unsigned long cnt);
266
+
unsigned long (*to)(void __user *dst, const void *src, unsigned long cnt);
267
+
};
268
+
269
+
int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
270
+
struct mem_access *ma, int, unsigned long address);
257
271
258
272
#endif /* __ASM_SH_UACCESS_H */
+1
-1
arch/sh/kernel/cpu/init.c
+1
-1
arch/sh/kernel/cpu/init.c
···
18
18
#include <asm/processor.h>
19
19
#include <asm/uaccess.h>
20
20
#include <asm/page.h>
21
-
#include <asm/system.h>
22
21
#include <asm/cacheflush.h>
23
22
#include <asm/cache.h>
24
23
#include <asm/elf.h>
25
24
#include <asm/io.h>
26
25
#include <asm/smp.h>
27
26
#include <asm/sh_bios.h>
27
+
#include <asm/setup.h>
28
28
29
29
#ifdef CONFIG_SH_FPU
30
30
#define cpu_has_fpu 1
-1
arch/sh/kernel/cpu/irq/imask.c
-1
arch/sh/kernel/cpu/irq/imask.c
-1
arch/sh/kernel/cpu/sh2a/opcode_helper.c
-1
arch/sh/kernel/cpu/sh2a/opcode_helper.c
-1
arch/sh/kernel/cpu/sh4/fpu.c
-1
arch/sh/kernel/cpu/sh4/fpu.c
+1
arch/sh/kernel/hw_breakpoint.c
+1
arch/sh/kernel/hw_breakpoint.c
+1
-1
arch/sh/kernel/idle.c
+1
-1
arch/sh/kernel/idle.c
-1
arch/sh/kernel/io_trapped.c
-1
arch/sh/kernel/io_trapped.c
-1
arch/sh/kernel/process_32.c
-1
arch/sh/kernel/process_32.c
+1
arch/sh/kernel/process_64.c
+1
arch/sh/kernel/process_64.c
-1
arch/sh/kernel/ptrace_32.c
-1
arch/sh/kernel/ptrace_32.c
+1
-1
arch/sh/kernel/ptrace_64.c
+1
-1
arch/sh/kernel/ptrace_64.c
···
34
34
#include <asm/io.h>
35
35
#include <asm/uaccess.h>
36
36
#include <asm/pgtable.h>
37
-
#include <asm/system.h>
38
37
#include <asm/processor.h>
39
38
#include <asm/mmu_context.h>
40
39
#include <asm/syscalls.h>
41
40
#include <asm/fpu.h>
41
+
#include <asm/traps.h>
42
42
43
43
#define CREATE_TRACE_POINTS
44
44
#include <trace/events/syscalls.h>
+1
-1
arch/sh/kernel/reboot.c
+1
-1
arch/sh/kernel/reboot.c
-1
arch/sh/kernel/signal_32.c
-1
arch/sh/kernel/signal_32.c
-1
arch/sh/kernel/smp.c
-1
arch/sh/kernel/smp.c
+1
-1
arch/sh/kernel/traps.c
+1
-1
arch/sh/kernel/traps.c
+2
-1
arch/sh/kernel/traps_32.c
+2
-1
arch/sh/kernel/traps_32.c
···
27
27
#include <linux/sysfs.h>
28
28
#include <linux/uaccess.h>
29
29
#include <linux/perf_event.h>
30
-
#include <asm/system.h>
31
30
#include <asm/alignment.h>
32
31
#include <asm/fpu.h>
33
32
#include <asm/kprobes.h>
33
+
#include <asm/traps.h>
34
+
#include <asm/bl_bit.h>
34
35
35
36
#ifdef CONFIG_CPU_SH2
36
37
# define TRAP_RESERVED_INST 4
-1
arch/sh/kernel/traps_64.c
-1
arch/sh/kernel/traps_64.c
-1
arch/sh/math-emu/math.c
-1
arch/sh/math-emu/math.c
+1
-1
arch/sh/mm/fault_32.c
+1
-1
arch/sh/mm/fault_32.c
···
17
17
#include <linux/kprobes.h>
18
18
#include <linux/perf_event.h>
19
19
#include <asm/io_trapped.h>
20
-
#include <asm/system.h>
21
20
#include <asm/mmu_context.h>
22
21
#include <asm/tlbflush.h>
22
+
#include <asm/traps.h>
23
23
24
24
static inline int notify_page_fault(struct pt_regs *regs, int trap)
25
25
{
-1
arch/sh/mm/fault_64.c
-1
arch/sh/mm/fault_64.c
+1
arch/sh/mm/flush-sh4.c
+1
arch/sh/mm/flush-sh4.c
-1
arch/sh/mm/pmb.c
-1
arch/sh/mm/pmb.c
-1
arch/sh/mm/tlb-pteaex.c
-1
arch/sh/mm/tlb-pteaex.c
-1
arch/sh/mm/tlb-sh3.c
-1
arch/sh/mm/tlb-sh3.c
-1
arch/sh/mm/tlb-sh4.c
-1
arch/sh/mm/tlb-sh4.c