tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpio/mxc: get rid of the uses of cpu_is_mx()
The patch removes all the uses of cpu_is_mx(). Instead, it utilizes
platform_device_id to distinguish the different gpio types, IMX1_GPIO
on i.mx1, IMX21_GPIO on i.mx21 and i.mx27, IMX31_GPIO on all other
i.mx SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
authored by
Shawn Guo
and committed by
Grant Likely
e7fc6ae7
fb149218
+163
-64
+8
-4
arch/arm/mach-imx/mm-imx1.c
+8
-4
arch/arm/mach-imx/mm-imx1.c
···
50
50
51
51
void __init imx1_soc_init(void)
52
52
{
53
-
mxc_register_gpio(0, MX1_GPIO1_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTA, 0);
54
-
mxc_register_gpio(1, MX1_GPIO2_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTB, 0);
55
-
mxc_register_gpio(2, MX1_GPIO3_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTC, 0);
56
-
mxc_register_gpio(3, MX1_GPIO4_BASE_ADDR, SZ_4K, MX1_GPIO_INT_PORTD, 0);
53
+
mxc_register_gpio("imx1-gpio", 0, MX1_GPIO1_BASE_ADDR, SZ_256,
54
+
MX1_GPIO_INT_PORTA, 0);
55
+
mxc_register_gpio("imx1-gpio", 1, MX1_GPIO2_BASE_ADDR, SZ_256,
56
+
MX1_GPIO_INT_PORTB, 0);
57
+
mxc_register_gpio("imx1-gpio", 2, MX1_GPIO3_BASE_ADDR, SZ_256,
58
+
MX1_GPIO_INT_PORTC, 0);
59
+
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
60
+
MX1_GPIO_INT_PORTD, 0);
57
61
}
+6
-6
arch/arm/mach-imx/mm-imx21.c
+6
-6
arch/arm/mach-imx/mm-imx21.c
···
76
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77
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void __init imx21_soc_init(void)
78
78
{
79
-
mxc_register_gpio(0, MX21_GPIO1_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
80
-
mxc_register_gpio(1, MX21_GPIO2_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
81
-
mxc_register_gpio(2, MX21_GPIO3_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
82
-
mxc_register_gpio(3, MX21_GPIO4_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
83
-
mxc_register_gpio(4, MX21_GPIO5_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
84
-
mxc_register_gpio(5, MX21_GPIO6_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0);
79
+
mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
80
+
mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
81
+
mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
82
+
mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
83
+
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
84
+
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
85
85
}
+5
-4
arch/arm/mach-imx/mm-imx25.c
+5
-4
arch/arm/mach-imx/mm-imx25.c
···
63
63
64
64
void __init imx25_soc_init(void)
65
65
{
66
-
mxc_register_gpio(0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
67
-
mxc_register_gpio(1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
68
-
mxc_register_gpio(2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
69
-
mxc_register_gpio(3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
66
+
/* i.mx25 has the i.mx31 type gpio */
67
+
mxc_register_gpio("imx31-gpio", 0, MX25_GPIO1_BASE_ADDR, SZ_16K, MX25_INT_GPIO1, 0);
68
+
mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
69
+
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
70
+
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
70
71
}
+7
-6
arch/arm/mach-imx/mm-imx27.c
+7
-6
arch/arm/mach-imx/mm-imx27.c
···
76
76
77
77
void __init imx27_soc_init(void)
78
78
{
79
-
mxc_register_gpio(0, MX27_GPIO1_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
80
-
mxc_register_gpio(1, MX27_GPIO2_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
81
-
mxc_register_gpio(2, MX27_GPIO3_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
82
-
mxc_register_gpio(3, MX27_GPIO4_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
83
-
mxc_register_gpio(4, MX27_GPIO5_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
84
-
mxc_register_gpio(5, MX27_GPIO6_BASE_ADDR, SZ_4K, MX27_INT_GPIO, 0);
79
+
/* i.mx27 has the i.mx21 type gpio */
80
+
mxc_register_gpio("imx21-gpio", 0, MX27_GPIO1_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
81
+
mxc_register_gpio("imx21-gpio", 1, MX27_GPIO2_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
82
+
mxc_register_gpio("imx21-gpio", 2, MX27_GPIO3_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
83
+
mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
84
+
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
85
+
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
85
86
}
+3
-3
arch/arm/mach-imx/mm-imx31.c
+3
-3
arch/arm/mach-imx/mm-imx31.c
···
59
59
60
60
void __init imx31_soc_init(void)
61
61
{
62
-
mxc_register_gpio(0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
63
-
mxc_register_gpio(1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
64
-
mxc_register_gpio(2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
62
+
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
63
+
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
64
+
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
65
65
}
+4
-3
arch/arm/mach-imx/mm-imx35.c
+4
-3
arch/arm/mach-imx/mm-imx35.c
···
56
56
57
57
void __init imx35_soc_init(void)
58
58
{
59
-
mxc_register_gpio(0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
60
-
mxc_register_gpio(1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
61
-
mxc_register_gpio(2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
59
+
/* i.mx35 has the i.mx31 type gpio */
60
+
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
61
+
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
62
+
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
62
63
}
+7
-6
arch/arm/mach-mx5/mm-mx50.c
+7
-6
arch/arm/mach-mx5/mm-mx50.c
···
62
62
63
63
void __init imx50_soc_init(void)
64
64
{
65
-
mxc_register_gpio(0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
66
-
mxc_register_gpio(1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
67
-
mxc_register_gpio(2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
68
-
mxc_register_gpio(3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
69
-
mxc_register_gpio(4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
70
-
mxc_register_gpio(5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
65
+
/* i.mx50 has the i.mx31 type gpio */
66
+
mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
67
+
mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
68
+
mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
69
+
mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
70
+
mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
71
+
mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
71
72
}
+13
-11
arch/arm/mach-mx5/mm.c
+13
-11
arch/arm/mach-mx5/mm.c
···
102
102
103
103
void __init imx51_soc_init(void)
104
104
{
105
-
mxc_register_gpio(0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
106
-
mxc_register_gpio(1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
107
-
mxc_register_gpio(2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
108
-
mxc_register_gpio(3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
105
+
/* i.mx51 has the i.mx31 type gpio */
106
+
mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO1_LOW, MX51_MXC_INT_GPIO1_HIGH);
107
+
mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
108
+
mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
109
+
mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
109
110
}
110
111
111
112
void __init imx53_soc_init(void)
112
113
{
113
-
mxc_register_gpio(0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
114
-
mxc_register_gpio(1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
115
-
mxc_register_gpio(2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
116
-
mxc_register_gpio(3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
117
-
mxc_register_gpio(4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
118
-
mxc_register_gpio(5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
119
-
mxc_register_gpio(6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
114
+
/* i.mx53 has the i.mx31 type gpio */
115
+
mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
116
+
mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
117
+
mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
118
+
mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
119
+
mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
120
+
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
121
+
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
120
122
}
+2
-2
arch/arm/plat-mxc/devices/platform-gpio-mxc.c
+2
-2
arch/arm/plat-mxc/devices/platform-gpio-mxc.c
···
8
8
*/
9
9
#include <mach/devices-common.h>
10
10
11
-
struct platform_device *__init mxc_register_gpio(int id,
11
+
struct platform_device *__init mxc_register_gpio(char *name, int id,
12
12
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high)
13
13
{
14
14
struct resource res[] = {
···
28
28
};
29
29
30
30
return platform_device_register_resndata(&mxc_aips_bus,
31
-
"gpio-mxc", id, res, ARRAY_SIZE(res), NULL, 0);
31
+
name, id, res, ARRAY_SIZE(res), NULL, 0);
32
32
}
+1
-1
arch/arm/plat-mxc/include/mach/common.h
+1
-1
arch/arm/plat-mxc/include/mach/common.h
···
64
64
unsigned long ckih1, unsigned long ckih2);
65
65
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
66
66
unsigned long ckih1, unsigned long ckih2);
67
-
extern struct platform_device *mxc_register_gpio(int id,
67
+
extern struct platform_device *mxc_register_gpio(char *name, int id,
68
68
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
69
69
extern int mxc_register_device(struct platform_device *pdev, void *data);
70
70
extern void mxc_set_cpu_type(unsigned int type);
+107
-18
drivers/gpio/gpio-mxc.c
+107
-18
drivers/gpio/gpio-mxc.c
···
27
27
#include <linux/platform_device.h>
28
28
#include <linux/slab.h>
29
29
#include <linux/basic_mmio_gpio.h>
30
-
#include <mach/hardware.h>
31
30
#include <asm-generic/bug.h>
31
+
32
+
enum mxc_gpio_hwtype {
33
+
IMX1_GPIO, /* runs on i.mx1 */
34
+
IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
35
+
IMX31_GPIO, /* runs on all other i.mx */
36
+
};
37
+
38
+
/* device type dependent stuff */
39
+
struct mxc_gpio_hwdata {
40
+
unsigned dr_reg;
41
+
unsigned gdir_reg;
42
+
unsigned psr_reg;
43
+
unsigned icr1_reg;
44
+
unsigned icr2_reg;
45
+
unsigned imr_reg;
46
+
unsigned isr_reg;
47
+
unsigned low_level;
48
+
unsigned high_level;
49
+
unsigned rise_edge;
50
+
unsigned fall_edge;
51
+
};
32
52
33
53
struct mxc_gpio_port {
34
54
struct list_head node;
···
60
40
u32 both_edges;
61
41
};
62
42
43
+
static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
44
+
.dr_reg = 0x1c,
45
+
.gdir_reg = 0x00,
46
+
.psr_reg = 0x24,
47
+
.icr1_reg = 0x28,
48
+
.icr2_reg = 0x2c,
49
+
.imr_reg = 0x30,
50
+
.isr_reg = 0x34,
51
+
.low_level = 0x03,
52
+
.high_level = 0x02,
53
+
.rise_edge = 0x00,
54
+
.fall_edge = 0x01,
55
+
};
56
+
57
+
static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
58
+
.dr_reg = 0x00,
59
+
.gdir_reg = 0x04,
60
+
.psr_reg = 0x08,
61
+
.icr1_reg = 0x0c,
62
+
.icr2_reg = 0x10,
63
+
.imr_reg = 0x14,
64
+
.isr_reg = 0x18,
65
+
.low_level = 0x00,
66
+
.high_level = 0x01,
67
+
.rise_edge = 0x02,
68
+
.fall_edge = 0x03,
69
+
};
70
+
71
+
static enum mxc_gpio_hwtype mxc_gpio_hwtype;
72
+
static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
73
+
74
+
#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
75
+
#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
76
+
#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
77
+
#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
78
+
#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
79
+
#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
80
+
#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
81
+
82
+
#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
83
+
#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
84
+
#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
85
+
#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
86
+
#define GPIO_INT_NONE 0x4
87
+
88
+
static struct platform_device_id mxc_gpio_devtype[] = {
89
+
{
90
+
.name = "imx1-gpio",
91
+
.driver_data = IMX1_GPIO,
92
+
}, {
93
+
.name = "imx21-gpio",
94
+
.driver_data = IMX21_GPIO,
95
+
}, {
96
+
.name = "imx31-gpio",
97
+
.driver_data = IMX31_GPIO,
98
+
}, {
99
+
/* sentinel */
100
+
}
101
+
};
102
+
63
103
/*
64
104
* MX2 has one interrupt *for all* gpio ports. The list is used
65
105
* to save the references to all ports, so that mx2_gpio_irq_handler
66
106
* can walk through all interrupt status registers.
67
107
*/
68
108
static LIST_HEAD(mxc_gpio_ports);
69
-
70
-
#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
71
-
72
-
#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
73
-
#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
74
-
#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
75
-
#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
76
-
#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
77
-
#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
78
-
#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
79
-
80
-
#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
81
-
#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
82
-
#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
83
-
#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
84
-
#define GPIO_INT_NONE 0x4
85
109
86
110
/* Note: This driver assumes 32 GPIOs are handled in one register */
87
111
···
300
236
IRQ_NOREQUEST, 0);
301
237
}
302
238
239
+
static void __devinit mxc_gpio_get_hw(struct platform_device *pdev)
240
+
{
241
+
enum mxc_gpio_hwtype hwtype = pdev->id_entry->driver_data;
242
+
243
+
if (mxc_gpio_hwtype) {
244
+
/*
245
+
* The driver works with a reasonable presupposition,
246
+
* that is all gpio ports must be the same type when
247
+
* running on one soc.
248
+
*/
249
+
BUG_ON(mxc_gpio_hwtype != hwtype);
250
+
return;
251
+
}
252
+
253
+
if (hwtype == IMX31_GPIO)
254
+
mxc_gpio_hwdata = &imx31_gpio_hwdata;
255
+
else
256
+
mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
257
+
258
+
mxc_gpio_hwtype = hwtype;
259
+
}
260
+
303
261
static int __devinit mxc_gpio_probe(struct platform_device *pdev)
304
262
{
305
263
struct mxc_gpio_port *port;
306
264
struct resource *iores;
307
265
int err;
266
+
267
+
mxc_gpio_get_hw(pdev);
308
268
309
269
port = kzalloc(sizeof(struct mxc_gpio_port), GFP_KERNEL);
310
270
if (!port)
···
368
280
/* gpio-mxc can be a generic irq chip */
369
281
mxc_gpio_init_gc(port);
370
282
371
-
if (cpu_is_mx2()) {
283
+
if (mxc_gpio_hwtype == IMX21_GPIO) {
372
284
/* setup one handler for all GPIO interrupts */
373
285
if (pdev->id == 0)
374
286
irq_set_chained_handler(port->irq,
···
422
334
.owner = THIS_MODULE,
423
335
},
424
336
.probe = mxc_gpio_probe,
337
+
.id_table = mxc_gpio_devtype,
425
338
};
426
339
427
340
static int __init gpio_mxc_init(void)