drm/amd/amdgpu: add thm 14.0.2 header file

Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git

kernel os linux

add thm 14.0.2 header file

v2: add license, update to latest changes (Alex)

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>

authored by

Kenneth Feng and committed by

Alex Deucher 2 years ago e7d1f116 64af3d3d

+1168

2 changed files

expand all

drivers

gpu

drm

amd

include

asic_reg

thm

thm_14_0_2_offset.h

thm_14_0_2_sh_mask.h

+228

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_offset.h

+940

drivers/gpu/drm/amd/include/asic_reg/thm/thm_14_0_2_sh_mask.h

··· 1 + /* 2 + * Copyright 2024 Advanced Micro Devices, Inc. 3 + * 4 + * Permission is hereby granted, free of charge, to any person obtaining a 5 + * copy of this software and associated documentation files (the "Software"), 6 + * to deal in the Software without restriction, including without limitation 7 + * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 + * and/or sell copies of the Software, and to permit persons to whom the 9 + * Software is furnished to do so, subject to the following conditions: 10 + * 11 + * The above copyright notice and this permission notice shall be included in 12 + * all copies or substantial portions of the Software. 13 + * 14 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 + * OTHER DEALINGS IN THE SOFTWARE. 21 + * 22 + * 23 + */ 24 + #ifndef _thm_14_0_2_SH_MASK_HEADER 25 + #define _thm_14_0_2_SH_MASK_HEADER 26 + 27 + 28 + // addressBlock: thm_thm_SmuThmDec 29 + //THM_TCON_CUR_TMP 30 + #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 31 + #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 32 + #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 33 + #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 34 + #define THM_TCON_CUR_TMP__REMOTE_TJ_SEL__SHIFT 0xd 35 + #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 36 + #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 37 + #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 38 + #define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 39 + #define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 40 + #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL 41 + #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L 42 + #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L 43 + #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L 44 + #define THM_TCON_CUR_TMP__REMOTE_TJ_SEL_MASK 0x00006000L 45 + #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L 46 + #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L 47 + #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L 48 + #define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L 49 + #define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L 50 + //THM_TCON_HTC 51 + #define THM_TCON_HTC__HTC_EN__SHIFT 0x0 52 + #define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 53 + #define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 54 + #define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 55 + #define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 56 + #define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 57 + #define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT__SHIFT 0x9 58 + #define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa 59 + #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb 60 + #define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc 61 + #define THM_TCON_HTC__DIS_PROCHOT_PIN_IN__SHIFT 0xf 62 + #define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 63 + #define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 64 + #define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b 65 + #define THM_TCON_HTC__HTC_EN_MASK 0x00000001L 66 + #define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L 67 + #define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L 68 + #define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L 69 + #define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L 70 + #define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L 71 + #define THM_TCON_HTC__DIS_PROCHOT_PIN_OUT_MASK 0x00000200L 72 + #define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L 73 + #define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L 74 + #define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L 75 + #define THM_TCON_HTC__DIS_PROCHOT_PIN_IN_MASK 0x00008000L 76 + #define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L 77 + #define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L 78 + #define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L 79 + //THM_TCON_THERM_TRIP 80 + #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 81 + #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 82 + #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 83 + #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 84 + #define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 85 + #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 86 + #define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 87 + #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 88 + #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 89 + #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 90 + #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 91 + #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 92 + #define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 93 + #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 94 + #define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 95 + #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 96 + //THM_CTF_DELAY 97 + #define THM_CTF_DELAY__CTF_DELAY_CNT__SHIFT 0x0 98 + #define THM_CTF_DELAY__CTF_DELAY_CNT_MASK 0x000FFFFFL 99 + //THM_GPIO_PROCHOT_CTRL 100 + #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 101 + #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 102 + #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 103 + #define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 104 + #define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 105 + #define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 106 + #define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 107 + #define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 108 + #define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 109 + #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 110 + #define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 111 + #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 112 + #define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 113 + #define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f 114 + #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L 115 + #define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L 116 + #define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L 117 + #define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L 118 + #define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L 119 + #define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L 120 + #define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L 121 + #define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L 122 + #define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L 123 + #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L 124 + #define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L 125 + #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L 126 + #define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L 127 + #define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L 128 + //THM_GPIO_THERMTRIP_CTRL 129 + #define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 130 + #define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 131 + #define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 132 + #define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 133 + #define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 134 + #define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 135 + #define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 136 + #define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 137 + #define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 138 + #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 139 + #define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 140 + #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 141 + #define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 142 + #define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 143 + #define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f 144 + #define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L 145 + #define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L 146 + #define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L 147 + #define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L 148 + #define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L 149 + #define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L 150 + #define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L 151 + #define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L 152 + #define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L 153 + #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L 154 + #define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L 155 + #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L 156 + #define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L 157 + #define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L 158 + #define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L 159 + //THM_GPIO_PWM_CTRL 160 + #define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 161 + #define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 162 + #define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 163 + #define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 164 + #define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 165 + #define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 166 + #define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 167 + #define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 168 + #define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 169 + #define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 170 + #define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 171 + #define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 172 + #define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 173 + #define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f 174 + #define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L 175 + #define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L 176 + #define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L 177 + #define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L 178 + #define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L 179 + #define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L 180 + #define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L 181 + #define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L 182 + #define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L 183 + #define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L 184 + #define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L 185 + #define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L 186 + #define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L 187 + #define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L 188 + //THM_GPIO_TACHIN_CTRL 189 + #define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 190 + #define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 191 + #define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 192 + #define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 193 + #define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 194 + #define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 195 + #define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 196 + #define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 197 + #define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 198 + #define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 199 + #define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 200 + #define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 201 + #define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 202 + #define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f 203 + #define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L 204 + #define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L 205 + #define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L 206 + #define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L 207 + #define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L 208 + #define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L 209 + #define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L 210 + #define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L 211 + #define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L 212 + #define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 213 + #define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L 214 + #define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L 215 + #define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L 216 + #define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L 217 + //THM_GPIO_PUMPOUT_CTRL 218 + #define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0 219 + #define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1 220 + #define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2 221 + #define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3 222 + #define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4 223 + #define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5 224 + #define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6 225 + #define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7 226 + #define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8 227 + #define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10 228 + #define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11 229 + #define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12 230 + #define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13 231 + #define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f 232 + #define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L 233 + #define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L 234 + #define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L 235 + #define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L 236 + #define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L 237 + #define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L 238 + #define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L 239 + #define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L 240 + #define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L 241 + #define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L 242 + #define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L 243 + #define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L 244 + #define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L 245 + #define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L 246 + //THM_GPIO_PUMPIN_CTRL 247 + #define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0 248 + #define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1 249 + #define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2 250 + #define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3 251 + #define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4 252 + #define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5 253 + #define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6 254 + #define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7 255 + #define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8 256 + #define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10 257 + #define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11 258 + #define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12 259 + #define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13 260 + #define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f 261 + #define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L 262 + #define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L 263 + #define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L 264 + #define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L 265 + #define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L 266 + #define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L 267 + #define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L 268 + #define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L 269 + #define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L 270 + #define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 271 + #define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L 272 + #define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L 273 + #define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L 274 + #define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L 275 + //THM_THERMAL_INT_ENA 276 + #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 277 + #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 278 + #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 279 + #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 280 + #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 281 + #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 282 + #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 283 + #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 284 + #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 285 + #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 286 + #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 287 + #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 288 + //THM_THERMAL_INT_CTRL 289 + #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 290 + #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 291 + #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 292 + #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 293 + #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 294 + #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 295 + #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 296 + #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 297 + #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 298 + #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 299 + #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 300 + #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 301 + #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 302 + #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 303 + #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 304 + #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 305 + #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 306 + #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 307 + //THM_THERMAL_INT_STATUS 308 + #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 309 + #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 310 + #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 311 + #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 312 + #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L 313 + #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L 314 + #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L 315 + #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L 316 + //THM_SW_TEMP 317 + #define THM_SW_TEMP__SW_TEMP__SHIFT 0x0 318 + #define THM_SW_TEMP__SW_TEMP_MASK 0x000001FFL 319 + //CG_MULT_THERMAL_CTRL 320 + #define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 321 + #define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 322 + #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 323 + #define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 324 + #define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL 325 + #define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L 326 + #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L 327 + #define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 328 + //CG_MULT_THERMAL_STATUS 329 + #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 330 + #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 331 + #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 332 + #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 333 + //CG_THERMAL_RANGE 334 + #define CG_THERMAL_RANGE__ASIC_T_MAX__SHIFT 0x0 335 + #define CG_THERMAL_RANGE__ASIC_T_MIN__SHIFT 0x10 336 + #define CG_THERMAL_RANGE__ASIC_T_MAX_MASK 0x000001FFL 337 + #define CG_THERMAL_RANGE__ASIC_T_MIN_MASK 0x01FF0000L 338 + //CG_FDO_CTRL0 339 + #define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 340 + #define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 341 + #define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 342 + #define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 343 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 344 + #define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 345 + #define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 346 + #define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L 347 + #define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L 348 + #define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L 349 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L 350 + #define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L 351 + //CG_FDO_CTRL1 352 + #define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 353 + #define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 354 + #define CG_FDO_CTRL1__M__SHIFT 0x10 355 + #define CG_FDO_CTRL1__TACH_IN_MAX__SHIFT 0x18 356 + #define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 357 + #define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L 358 + #define CG_FDO_CTRL1__M_MASK 0x00FF0000L 359 + #define CG_FDO_CTRL1__TACH_IN_MAX_MASK 0xFF000000L 360 + //CG_FDO_CTRL2 361 + #define CG_FDO_CTRL2__TMIN__SHIFT 0x0 362 + #define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 363 + #define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 364 + #define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 365 + #define CG_FDO_CTRL2__TMAX__SHIFT 0x11 366 + #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 367 + #define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 368 + #define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L 369 + #define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 370 + #define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 371 + #define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L 372 + #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 373 + //CG_TACH_CTRL 374 + #define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 375 + #define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 376 + #define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 377 + #define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 378 + //CG_TACH_STATUS 379 + #define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 380 + #define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 381 + //CG_THERMAL_STATUS 382 + #define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 383 + #define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT__SHIFT 0x11 384 + #define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L 385 + #define CG_THERMAL_STATUS__TACH_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L 386 + //CG_PUMP_CTRL0 387 + #define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0 388 + #define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8 389 + #define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10 390 + #define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11 391 + #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17 392 + #define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18 393 + #define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL 394 + #define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L 395 + #define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L 396 + #define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L 397 + #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L 398 + #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L 399 + //CG_PUMP_CTRL1 400 + #define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0 401 + #define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8 402 + #define CG_PUMP_CTRL1__M__SHIFT 0x10 403 + #define CG_PUMP_CTRL1__TACH_IN_MAX__SHIFT 0x18 404 + #define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL 405 + #define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L 406 + #define CG_PUMP_CTRL1__M_MASK 0x00FF0000L 407 + #define CG_PUMP_CTRL1__TACH_IN_MAX_MASK 0xFF000000L 408 + //CG_PUMP_CTRL2 409 + #define CG_PUMP_CTRL2__TMIN__SHIFT 0x0 410 + #define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8 411 + #define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb 412 + #define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe 413 + #define CG_PUMP_CTRL2__TMAX__SHIFT 0x11 414 + #define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 415 + #define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL 416 + #define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L 417 + #define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L 418 + #define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 419 + #define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L 420 + #define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 421 + //CG_PUMP_TACH_CTRL 422 + #define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 423 + #define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 424 + #define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 425 + #define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 426 + //CG_PUMP_TACH_STATUS 427 + #define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 428 + #define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 429 + //CG_PUMP_STATUS 430 + #define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9 431 + #define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT__SHIFT 0x11 432 + #define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L 433 + #define CG_PUMP_STATUS__PUMP_IN_H_DEGLITCH_CNT_MASK 0xFFFE0000L 434 + //THM_TCON_LOCAL2 435 + #define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 436 + #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 437 + #define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 438 + #define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 439 + #define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa 440 + #define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 441 + #define THM_TCON_LOCAL2__use_tsen_for_temp_sel__SHIFT 0xc 442 + #define THM_TCON_LOCAL2__use_tro_for_temp_sel__SHIFT 0xd 443 + #define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L 444 + #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL 445 + #define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L 446 + #define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L 447 + #define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L 448 + #define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L 449 + #define THM_TCON_LOCAL2__use_tsen_for_temp_sel_MASK 0x00001000L 450 + #define THM_TCON_LOCAL2__use_tro_for_temp_sel_MASK 0x00002000L 451 + //THM_TCON_LOCAL3 452 + #define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 453 + #define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL 454 + //THM_TCON_LOCAL4 455 + #define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 456 + #define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL 457 + //THM_TCON_LOCAL5 458 + #define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 459 + #define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL 460 + //THM_TCON_LOCAL6 461 + #define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 462 + #define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL 463 + //THM_TCON_LOCAL7 464 + #define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 465 + #define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL 466 + //THM_TCON_LOCAL8 467 + #define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 468 + #define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL 469 + //THM_TCON_LOCAL9 470 + #define THM_TCON_LOCAL9__Tj_Max_TSEN0__SHIFT 0x0 471 + #define THM_TCON_LOCAL9__Tj_Max_TSEN0_MASK 0x000007FFL 472 + //THM_TCON_LOCAL10 473 + #define THM_TCON_LOCAL10__TSEN0_Tj_Max_RS_ID__SHIFT 0x0 474 + #define THM_TCON_LOCAL10__TSEN0_Tj_Max_RS_ID_MASK 0x000000FFL 475 + //THM_TCON_LOCAL11 476 + #define THM_TCON_LOCAL11__Tj_Max_TSEN1__SHIFT 0x0 477 + #define THM_TCON_LOCAL11__Tj_Max_TSEN1_MASK 0x000007FFL 478 + //THM_TCON_LOCAL12 479 + #define THM_TCON_LOCAL12__TSEN1_Tj_Max_RS_ID__SHIFT 0x0 480 + #define THM_TCON_LOCAL12__TSEN1_Tj_Max_RS_ID_MASK 0x000000FFL 481 + //THM_TCON_LOCAL13 482 + #define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 483 + #define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L 484 + //THM_TCON_LOCAL14 485 + #define THM_TCON_LOCAL14__Tj_Max_TSEN2__SHIFT 0x0 486 + #define THM_TCON_LOCAL14__Tj_Max_TSEN2_MASK 0x000007FFL 487 + //THM_TCON_LOCAL15 488 + #define THM_TCON_LOCAL15__TSEN2_Tj_Max_RS_ID__SHIFT 0x0 489 + #define THM_TCON_LOCAL15__TSEN2_Tj_Max_RS_ID_MASK 0x000000FFL 490 + //THM_BACO_CNTL 491 + #define THM_BACO_CNTL__BACO_MODE__SHIFT 0x0 492 + #define THM_BACO_CNTL__BACO_ISO_EN__SHIFT 0x1 493 + #define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT 0x2 494 + #define THM_BACO_CNTL__BACO_RESET_EN__SHIFT 0x3 495 + #define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT 0x4 496 + #define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT 0x5 497 + #define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT 0x6 498 + #define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT 0x7 499 + #define THM_BACO_CNTL__BACO_EXIT__SHIFT 0x8 500 + #define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT 0x9 501 + #define THM_BACO_CNTL__BACO_HW_EXIT_DISABLE__SHIFT 0xa 502 + #define THM_BACO_CNTL__BACO_ROGATING__SHIFT 0xb 503 + #define THM_BACO_CNTL__BACO_ISO_EN_DFX__SHIFT 0xc 504 + #define THM_BACO_CNTL__BACO_CLK_ISO_EN__SHIFT 0xd 505 + #define THM_BACO_CNTL__BACO_CLK_ISO_EN_DFX__SHIFT 0xe 506 + #define THM_BACO_CNTL__BACO_CLEAR_TEMP_DATA_EN__SHIFT 0xf 507 + #define THM_BACO_CNTL__BACO_SCRATCH_SWITCH__SHIFT 0x1d 508 + #define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT 0x1e 509 + #define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT 0x1f 510 + #define THM_BACO_CNTL__BACO_MODE_MASK 0x00000001L 511 + #define THM_BACO_CNTL__BACO_ISO_EN_MASK 0x00000002L 512 + #define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK 0x00000004L 513 + #define THM_BACO_CNTL__BACO_RESET_EN_MASK 0x00000008L 514 + #define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK 0x00000010L 515 + #define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK 0x00000020L 516 + #define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK 0x00000040L 517 + #define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK 0x00000080L 518 + #define THM_BACO_CNTL__BACO_EXIT_MASK 0x00000100L 519 + #define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK 0x00000200L 520 + #define THM_BACO_CNTL__BACO_HW_EXIT_DISABLE_MASK 0x00000400L 521 + #define THM_BACO_CNTL__BACO_ROGATING_MASK 0x00000800L 522 + #define THM_BACO_CNTL__BACO_ISO_EN_DFX_MASK 0x00001000L 523 + #define THM_BACO_CNTL__BACO_CLK_ISO_EN_MASK 0x00002000L 524 + #define THM_BACO_CNTL__BACO_CLK_ISO_EN_DFX_MASK 0x00004000L 525 + #define THM_BACO_CNTL__BACO_CLEAR_TEMP_DATA_EN_MASK 0x00008000L 526 + #define THM_BACO_CNTL__BACO_SCRATCH_SWITCH_MASK 0x20000000L 527 + #define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK 0x40000000L 528 + #define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK 0x80000000L 529 + //THM_BACO_TIMING0 530 + #define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT 0x0 531 + #define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT 0x8 532 + #define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT 0x10 533 + #define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT 0x18 534 + #define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK 0x000000FFL 535 + #define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK 0x0000FF00L 536 + #define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK 0x00FF0000L 537 + #define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK 0xFF000000L 538 + //THM_BACO_TIMING1 539 + #define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT 0x0 540 + #define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT 0x8 541 + #define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT 0x10 542 + #define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT 0x18 543 + #define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK 0x000000FFL 544 + #define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK 0x0000FF00L 545 + #define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK 0x00FF0000L 546 + #define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK 0xFF000000L 547 + //THM_BACO_TIMING2 548 + #define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT 0x0 549 + #define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT 0x8 550 + #define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT 0x10 551 + #define THM_BACO_TIMING2__BACO_SOC_PWROK_OVERRIDE__SHIFT 0x18 552 + #define THM_BACO_TIMING2__BACO_VDDP_PWROK_OVERRIDE__SHIFT 0x19 553 + #define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK 0x000000FFL 554 + #define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK 0x0000FF00L 555 + #define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK 0x00FF0000L 556 + #define THM_BACO_TIMING2__BACO_SOC_PWROK_OVERRIDE_MASK 0x01000000L 557 + #define THM_BACO_TIMING2__BACO_VDDP_PWROK_OVERRIDE_MASK 0x02000000L 558 + //THM_BACO_TIMING 559 + #define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT 0x0 560 + #define THM_BACO_TIMING__BACO_RESET_DELAY_MASK 0x0000FFFFL 561 + //XTAL_CNTL 562 + #define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0 563 + #define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4 564 + #define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8 565 + #define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc 566 + #define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L 567 + #define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L 568 + #define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L 569 + #define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L 570 + //THM_PWRMGT 571 + #define THM_PWRMGT__CLK_GATE_EN__SHIFT 0x0 572 + #define THM_PWRMGT__CLK_GATE_ST__SHIFT 0x1 573 + #define THM_PWRMGT__DBG_CLK_GATE_EN__SHIFT 0x2 574 + #define THM_PWRMGT__PUMP_CTL_GATE_EN__SHIFT 0x6 575 + #define THM_PWRMGT__FAN_CTL_GATE_EN__SHIFT 0x7 576 + #define THM_PWRMGT__CLK_GATE_MAX_CNT__SHIFT 0x8 577 + #define THM_PWRMGT__CLK_GATE_EN_MASK 0x00000001L 578 + #define THM_PWRMGT__CLK_GATE_ST_MASK 0x00000002L 579 + #define THM_PWRMGT__DBG_CLK_GATE_EN_MASK 0x00000004L 580 + #define THM_PWRMGT__PUMP_CTL_GATE_EN_MASK 0x00000040L 581 + #define THM_PWRMGT__FAN_CTL_GATE_EN_MASK 0x00000080L 582 + #define THM_PWRMGT__CLK_GATE_MAX_CNT_MASK 0x00FFFF00L 583 + #define HM_MAX_HOLD_TEMP_SHADOW_REG_ADDR__MAX_HOLD_TEMP_SHADOW_RD_IDX__SHIFT 0x0 584 + #define HM_MAX_HOLD_TEMP_SHADOW_REG_ADDR__MAX_HOLD_TEMP_SHADOW_RD_IDX_MASK 0x0000007FL 585 + //SMUSBI_SBIREGADDR 586 + #define SMUSBI_SBIREGADDR__Address__SHIFT 0x0 587 + #define SMUSBI_SBIREGADDR__TSI_RMI_SEL__SHIFT 0x8 588 + #define SMUSBI_SBIREGADDR__SIZE__SHIFT 0x9 589 + #define SMUSBI_SBIREGADDR__Address_MASK 0x000000FFL 590 + #define SMUSBI_SBIREGADDR__TSI_RMI_SEL_MASK 0x00000100L 591 + #define SMUSBI_SBIREGADDR__SIZE_MASK 0x00000600L 592 + //SMUSBI_SBIREGDATA 593 + #define SMUSBI_SBIREGDATA__SBI_REGDATA__SHIFT 0x0 594 + #define SMUSBI_SBIREGDATA__SBI_REGDATA_MASK 0xFFFFFFFFL 595 + //SMUSBI_ERRATA_STAT_REG 596 + #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG__SHIFT 0x0 597 + #define SMUSBI_ERRATA_STAT_REG__ERRATA_STAT_REG_MASK 0xFFFFFFFFL 598 + //SMUSBI_SBICTRL 599 + #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE__SHIFT 0x0 600 + #define SMUSBI_SBICTRL__NB_SBISELECT__SHIFT 0x1 601 + #define SMUSBI_SBICTRL__NB_SBIADDR__SHIFT 0x2 602 + #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE__SHIFT 0x5 603 + #define SMUSBI_SBICTRL__CK_SPRSBIWRDONE_MASK 0x00000001L 604 + #define SMUSBI_SBICTRL__NB_SBISELECT_MASK 0x00000002L 605 + #define SMUSBI_SBICTRL__NB_SBIADDR_MASK 0x0000001CL 606 + #define SMUSBI_SBICTRL__NB_SBIADDR_OVERRIDE_MASK 0x00000020L 607 + //SMUSBI_CKNBIRESET 608 + #define SMUSBI_CKNBIRESET__CKNBIRESET__SHIFT 0x0 609 + #define SMUSBI_CKNBIRESET__CKNBIRESET_MASK 0x00000001L 610 + //SMUSBI_TIMING 611 + #define SMUSBI_TIMING__SETUP_TIME__SHIFT 0x0 612 + #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE__SHIFT 0x8 613 + #define SMUSBI_TIMING__HOLD_TIME__SHIFT 0x10 614 + #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE__SHIFT 0x18 615 + #define SMUSBI_TIMING__DGLT_LMT_OVERRIDE__SHIFT 0x1b 616 + #define SMUSBI_TIMING__DGLT_LMT__SHIFT 0x1c 617 + #define SMUSBI_TIMING__SETUP_TIME_MASK 0x0000003FL 618 + #define SMUSBI_TIMING__SETUP_TIME_OVERRIDE_MASK 0x00000100L 619 + #define SMUSBI_TIMING__HOLD_TIME_MASK 0x00FF0000L 620 + #define SMUSBI_TIMING__HOLD_TIME_OVERRIDE_MASK 0x01000000L 621 + #define SMUSBI_TIMING__DGLT_LMT_OVERRIDE_MASK 0x08000000L 622 + #define SMUSBI_TIMING__DGLT_LMT_MASK 0xF0000000L 623 + //SMUSBI_HS_TIMING 624 + #define SMUSBI_HS_TIMING__HS_SETUP_TIME__SHIFT 0x0 625 + #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE__SHIFT 0x8 626 + #define SMUSBI_HS_TIMING__HS_HOLD_TIME__SHIFT 0x10 627 + #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE__SHIFT 0x18 628 + #define SMUSBI_HS_TIMING__HS_SETUP_TIME_MASK 0x0000003FL 629 + #define SMUSBI_HS_TIMING__HS_SETUP_TIME_OVERRIDE_MASK 0x00000100L 630 + #define SMUSBI_HS_TIMING__HS_HOLD_TIME_MASK 0x00FF0000L 631 + #define SMUSBI_HS_TIMING__HS_HOLD_TIME_OVERRIDE_MASK 0x01000000L 632 + //SBTSI_REMOTE_TEMP 633 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 634 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb 635 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 636 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL 637 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L 638 + #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L 639 + //SBRMI_CONTROL 640 + #define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 641 + #define SBRMI_CONTROL__DPD__SHIFT 0x1 642 + #define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 643 + #define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L 644 + #define SBRMI_CONTROL__DPD_MASK 0x00000002L 645 + #define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L 646 + //SBRMI_COMMAND 647 + #define SBRMI_COMMAND__Command__SHIFT 0x0 648 + #define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 649 + #define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 650 + #define SBRMI_COMMAND__CommandSent__SHIFT 0x18 651 + #define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 652 + #define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a 653 + #define SBRMI_COMMAND__Status__SHIFT 0x1c 654 + #define SBRMI_COMMAND__Command_MASK 0x000000FFL 655 + #define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L 656 + #define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L 657 + #define SBRMI_COMMAND__CommandSent_MASK 0x01000000L 658 + #define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L 659 + #define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L 660 + #define SBRMI_COMMAND__Status_MASK 0xF0000000L 661 + //SBRMI_WRITE_DATA0 662 + #define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 663 + #define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 664 + #define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 665 + #define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 666 + #define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL 667 + #define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L 668 + #define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L 669 + #define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L 670 + //SBRMI_WRITE_DATA1 671 + #define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 672 + #define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 673 + #define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 674 + #define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 675 + #define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL 676 + #define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L 677 + #define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L 678 + #define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L 679 + //SBRMI_WRITE_DATA2 680 + #define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 681 + #define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 682 + #define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 683 + #define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 684 + #define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL 685 + #define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L 686 + #define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L 687 + #define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L 688 + //SBRMI_READ_DATA0 689 + #define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 690 + #define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 691 + #define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 692 + #define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 693 + #define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL 694 + #define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L 695 + #define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L 696 + #define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L 697 + //SBRMI_READ_DATA1 698 + #define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 699 + #define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 700 + #define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 701 + #define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 702 + #define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL 703 + #define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L 704 + #define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L 705 + #define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L 706 + //SBRMI_CORE_EN_NUMBER 707 + #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 708 + #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL 709 + //SBRMI_CORE_EN_STATUS0 710 + #define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 711 + #define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL 712 + //SBRMI_CORE_EN_STATUS1 713 + #define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 714 + #define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL 715 + //SBRMI_APIC_STATUS0 716 + #define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 717 + #define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL 718 + //SBRMI_APIC_STATUS1 719 + #define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 720 + #define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL 721 + //SBRMI_MCE_STATUS0 722 + #define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 723 + #define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL 724 + //SBRMI_MCE_STATUS1 725 + #define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 726 + #define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL 727 + //SMBUS_CNTL0 728 + #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 729 + #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 730 + #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 731 + #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 732 + #define SMBUS_CNTL0__THM_READY__SHIFT 0x14 733 + #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L 734 + #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL 735 + #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L 736 + #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L 737 + #define SMBUS_CNTL0__THM_READY_MASK 0x00100000L 738 + //SMBUS_CNTL1 739 + #define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 740 + #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 741 + #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 742 + #define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L 743 + #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL 744 + #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L 745 + //SMBUS_BLKWR_CMD_CTRL0 746 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 747 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 748 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 749 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 750 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL 751 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L 752 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L 753 + #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L 754 + //SMBUS_BLKWR_CMD_CTRL1 755 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 756 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 757 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 758 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 759 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL 760 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L 761 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L 762 + #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L 763 + //SMBUS_BLKRD_CMD_CTRL0 764 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 765 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 766 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 767 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 768 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL 769 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L 770 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L 771 + #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L 772 + //SMBUS_BLKRD_CMD_CTRL1 773 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 774 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 775 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 776 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 777 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL 778 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L 779 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L 780 + #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L 781 + //SMBUS_TIMING_CNTL0 782 + #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 783 + #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 784 + #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL 785 + #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L 786 + //SMBUS_TIMING_CNTL1 787 + #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 788 + #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 789 + #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb 790 + #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 791 + #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL 792 + #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L 793 + #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L 794 + #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L 795 + //SMBUS_TIMING_CNTL2 796 + #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 797 + #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd 798 + #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL 799 + #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L 800 + //SMBUS_TRIGGER_CNTL 801 + #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 802 + #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 803 + #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L 804 + #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L 805 + //SMBUS_UDID_CNTL0 806 + #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 807 + #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f 808 + #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL 809 + #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L 810 + //SMBUS_UDID_CNTL1 811 + #define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 812 + #define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL 813 + //SMBUS_UDID_CNTL2 814 + #define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 815 + #define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 816 + #define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 817 + #define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 818 + #define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 819 + #define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa 820 + #define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L 821 + #define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL 822 + #define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L 823 + #define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L 824 + #define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L 825 + #define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L 826 + //SMUSBI_SMBUS 827 + #define SMUSBI_SMBUS__Spare0__SHIFT 0x0 828 + #define SMUSBI_SMBUS__Spare1__SHIFT 0x1 829 + #define SMUSBI_SMBUS__ResBiasEn__SHIFT 0x2 830 + #define SMUSBI_SMBUS__CompSel__SHIFT 0x3 831 + #define SMUSBI_SMBUS__NG__SHIFT 0x4 832 + #define SMUSBI_SMBUS__I2cRxSel0__SHIFT 0x8 833 + #define SMUSBI_SMBUS__I2cRxSel1__SHIFT 0x9 834 + #define SMUSBI_SMBUS__PdEn0__SHIFT 0xa 835 + #define SMUSBI_SMBUS__PdEn1__SHIFT 0xb 836 + #define SMUSBI_SMBUS__FallSlewSel0__SHIFT 0xc 837 + #define SMUSBI_SMBUS__FallSlewSel1__SHIFT 0xd 838 + #define SMUSBI_SMBUS__Slewn__SHIFT 0xe 839 + #define SMUSBI_SMBUS__SpikeRcEn__SHIFT 0xf 840 + #define SMUSBI_SMBUS__SpikeRcSel__SHIFT 0x10 841 + #define SMUSBI_SMBUS__CSel0p9__SHIFT 0x11 842 + #define SMUSBI_SMBUS__CSel1p1__SHIFT 0x12 843 + #define SMUSBI_SMBUS__RSel0p9__SHIFT 0x13 844 + #define SMUSBI_SMBUS__RSel1p1__SHIFT 0x14 845 + #define SMUSBI_SMBUS__BiasCrtEn__SHIFT 0x15 846 + #define SMUSBI_SMBUS__DI2C0__SHIFT 0x16 847 + #define SMUSBI_SMBUS__DI2C1__SHIFT 0x17 848 + #define SMUSBI_SMBUS__DI2C0_OVERRIDE__SHIFT 0x18 849 + #define SMUSBI_SMBUS__DI2C1_OVERRIDE__SHIFT 0x19 850 + #define SMUSBI_SMBUS__Y0__SHIFT 0x1e 851 + #define SMUSBI_SMBUS__Y1__SHIFT 0x1f 852 + #define SMUSBI_SMBUS__Spare0_MASK 0x00000001L 853 + #define SMUSBI_SMBUS__Spare1_MASK 0x00000002L 854 + #define SMUSBI_SMBUS__ResBiasEn_MASK 0x00000004L 855 + #define SMUSBI_SMBUS__CompSel_MASK 0x00000008L 856 + #define SMUSBI_SMBUS__NG_MASK 0x000000F0L 857 + #define SMUSBI_SMBUS__I2cRxSel0_MASK 0x00000100L 858 + #define SMUSBI_SMBUS__I2cRxSel1_MASK 0x00000200L 859 + #define SMUSBI_SMBUS__PdEn0_MASK 0x00000400L 860 + #define SMUSBI_SMBUS__PdEn1_MASK 0x00000800L 861 + #define SMUSBI_SMBUS__FallSlewSel0_MASK 0x00001000L 862 + #define SMUSBI_SMBUS__FallSlewSel1_MASK 0x00002000L 863 + #define SMUSBI_SMBUS__Slewn_MASK 0x00004000L 864 + #define SMUSBI_SMBUS__SpikeRcEn_MASK 0x00008000L 865 + #define SMUSBI_SMBUS__SpikeRcSel_MASK 0x00010000L 866 + #define SMUSBI_SMBUS__CSel0p9_MASK 0x00020000L 867 + #define SMUSBI_SMBUS__CSel1p1_MASK 0x00040000L 868 + #define SMUSBI_SMBUS__RSel0p9_MASK 0x00080000L 869 + #define SMUSBI_SMBUS__RSel1p1_MASK 0x00100000L 870 + #define SMUSBI_SMBUS__BiasCrtEn_MASK 0x00200000L 871 + #define SMUSBI_SMBUS__DI2C0_MASK 0x00400000L 872 + #define SMUSBI_SMBUS__DI2C1_MASK 0x00800000L 873 + #define SMUSBI_SMBUS__DI2C0_OVERRIDE_MASK 0x01000000L 874 + #define SMUSBI_SMBUS__DI2C1_OVERRIDE_MASK 0x02000000L 875 + #define SMUSBI_SMBUS__Y0_MASK 0x40000000L 876 + #define SMUSBI_SMBUS__Y1_MASK 0x80000000L 877 + //SMUSBI_ALERT 878 + #define SMUSBI_ALERT__TXIMPSEL__SHIFT 0x0 879 + #define SMUSBI_ALERT__PD__SHIFT 0x1 880 + #define SMUSBI_ALERT__PU__SHIFT 0x2 881 + #define SMUSBI_ALERT__SCHMEN__SHIFT 0x3 882 + #define SMUSBI_ALERT__S0__SHIFT 0x4 883 + #define SMUSBI_ALERT__S1__SHIFT 0x5 884 + #define SMUSBI_ALERT__RXEN__SHIFT 0x6 885 + #define SMUSBI_ALERT__RXSEL0__SHIFT 0x7 886 + #define SMUSBI_ALERT__RXSEL1__SHIFT 0x8 887 + #define SMUSBI_ALERT__OE_OVERRIDE__SHIFT 0x10 888 + #define SMUSBI_ALERT__OE__SHIFT 0x11 889 + #define SMUSBI_ALERT__A_OVERRIDE__SHIFT 0x12 890 + #define SMUSBI_ALERT__A__SHIFT 0x13 891 + #define SMUSBI_ALERT__Y__SHIFT 0x1f 892 + #define SMUSBI_ALERT__TXIMPSEL_MASK 0x00000001L 893 + #define SMUSBI_ALERT__PD_MASK 0x00000002L 894 + #define SMUSBI_ALERT__PU_MASK 0x00000004L 895 + #define SMUSBI_ALERT__SCHMEN_MASK 0x00000008L 896 + #define SMUSBI_ALERT__S0_MASK 0x00000010L 897 + #define SMUSBI_ALERT__S1_MASK 0x00000020L 898 + #define SMUSBI_ALERT__RXEN_MASK 0x00000040L 899 + #define SMUSBI_ALERT__RXSEL0_MASK 0x00000080L 900 + #define SMUSBI_ALERT__RXSEL1_MASK 0x00000100L 901 + #define SMUSBI_ALERT__OE_OVERRIDE_MASK 0x00010000L 902 + #define SMUSBI_ALERT__OE_MASK 0x00020000L 903 + #define SMUSBI_ALERT__A_OVERRIDE_MASK 0x00040000L 904 + #define SMUSBI_ALERT__A_MASK 0x00080000L 905 + #define SMUSBI_ALERT__Y_MASK 0x80000000L 906 + //SMBUS_BACO_DUMMY 907 + #define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT 0x0 908 + #define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK 0xFFFFFFFFL 909 + //SMBUS_BACO_ADDR_RANGE0_LOW 910 + #define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT 0x0 911 + #define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK 0xFFFFFFFFL 912 + //SMBUS_BACO_ADDR_RANGE0_HIGH 913 + #define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT 0x0 914 + #define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK 0xFFFFFFFFL 915 + //SMBUS_BACO_ADDR_RANGE1_LOW 916 + #define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT 0x0 917 + #define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK 0xFFFFFFFFL 918 + //SMBUS_BACO_ADDR_RANGE1_HIGH 919 + #define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT 0x0 920 + #define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK 0xFFFFFFFFL 921 + //SMBUS_BACO_ADDR_RANGE2_LOW 922 + #define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT 0x0 923 + #define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK 0xFFFFFFFFL 924 + //SMBUS_BACO_ADDR_RANGE2_HIGH 925 + #define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT 0x0 926 + #define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK 0xFFFFFFFFL 927 + //SMBUS_BACO_ADDR_RANGE3_LOW 928 + #define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT 0x0 929 + #define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK 0xFFFFFFFFL 930 + //SMBUS_BACO_ADDR_RANGE3_HIGH 931 + #define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT 0x0 932 + #define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK 0xFFFFFFFFL 933 + //SMBUS_BACO_ADDR_RANGE4_LOW 934 + #define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT 0x0 935 + #define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK 0xFFFFFFFFL 936 + //SMBUS_BACO_ADDR_RANGE4_HIGH 937 + #define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT 0x0 938 + #define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK 0xFFFFFFFFL 939 + 940 + #endif