tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
[MIPS] Put an end to <asm/serial.h>'s long and annyoing existence
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+371
-151
-1
arch/mips/Kconfig
-1
arch/mips/Kconfig
+2
-1
arch/mips/ddb5xxx/ddb5477/Makefile
+2
-1
arch/mips/ddb5xxx/ddb5477/Makefile
+49
arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
+49
arch/mips/ddb5xxx/ddb5477/ddb5477-platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7
+
*/
8
+
#include <linux/init.h>
9
+
#include <linux/module.h>
10
+
#include <linux/serial_8250.h>
11
+
12
+
#include <asm/ddb5xxx/ddb5477.h>
13
+
14
+
#define DDB_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
15
+
16
+
#define DDB5477_PORT(base, int) \
17
+
{ \
18
+
.mapbase = base, \
19
+
.irq = int, \
20
+
.uartclk = 1843200, \
21
+
.iotype = UPIO_MEM, \
22
+
.flags = DDB_UART_FLAGS, \
23
+
.regshift = 3, \
24
+
}
25
+
26
+
static struct plat_serial8250_port uart8250_data[] = {
27
+
DDB5477_PORT(0xbfa04200, VRC5477_IRQ_UART0),
28
+
DDB5477_PORT(0xbfa04240, VRC5477_IRQ_UART1),
29
+
{ },
30
+
};
31
+
32
+
static struct platform_device uart8250_device = {
33
+
.name = "serial8250",
34
+
.id = PLAT8250_DEV_PLATFORM,
35
+
.dev = {
36
+
.platform_data = uart8250_data,
37
+
},
38
+
};
39
+
40
+
static int __init uart8250_init(void)
41
+
{
42
+
return platform_device_register(&uart8250_device);
43
+
}
44
+
45
+
module_init(uart8250_init);
46
+
47
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
48
+
MODULE_LICENSE("GPL");
49
+
MODULE_DESCRIPTION("8250 UART probe driver for the NEC DDB5477");
+1
-1
arch/mips/gt64120/momenco_ocelot/Makefile
+1
-1
arch/mips/gt64120/momenco_ocelot/Makefile
+46
arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
+46
arch/mips/gt64120/momenco_ocelot/ocelot-platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7
+
*
8
+
* A NS16552 DUART with a 20MHz crystal.
9
+
*
10
+
*/
11
+
#include <linux/module.h>
12
+
#include <linux/init.h>
13
+
#include <linux/serial_8250.h>
14
+
15
+
#define OCELOT_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
16
+
17
+
static struct plat_serial8250_port uart8250_data[] = {
18
+
{
19
+
.mapbase = 0xe0001020,
20
+
.irq = 4,
21
+
.uartclk = 20000000,
22
+
.iotype = UPIO_MEM,
23
+
.flags = OCELOT_UART_FLAGS,
24
+
.regshift = 2,
25
+
},
26
+
{ },
27
+
};
28
+
29
+
static struct platform_device uart8250_device = {
30
+
.name = "serial8250",
31
+
.id = PLAT8250_DEV_PLATFORM,
32
+
.dev = {
33
+
.platform_data = uart8250_data,
34
+
},
35
+
};
36
+
37
+
static int __init uart8250_init(void)
38
+
{
39
+
return platform_device_register(&uart8250_device);
40
+
}
41
+
42
+
module_init(uart8250_init);
43
+
44
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
45
+
MODULE_LICENSE("GPL");
46
+
MODULE_DESCRIPTION("8250 UART probe driver for the Momenco Ocelot");
+1
-1
arch/mips/jazz/Makefile
+1
-1
arch/mips/jazz/Makefile
+60
arch/mips/jazz/jazz-platform.c
+60
arch/mips/jazz/jazz-platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7
+
*/
8
+
#include <linux/init.h>
9
+
#include <linux/module.h>
10
+
#include <linux/serial_8250.h>
11
+
12
+
#include <asm/jazz.h>
13
+
14
+
/*
15
+
* Confusion ... It seems the original Microsoft Jazz machine used to have a
16
+
* 4.096MHz clock for its UART while the MIPS Magnum and Millenium systems
17
+
* had 8MHz. The Olivetti M700-10 and the Acer PICA have 1.8432MHz like PCs.
18
+
*/
19
+
#ifdef CONFIG_OLIVETTI_M700
20
+
#define JAZZ_BASE_BAUD 1843200
21
+
#else
22
+
#define JAZZ_BASE_BAUD 8000000 /* 3072000 */
23
+
#endif
24
+
25
+
#define JAZZ_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
26
+
27
+
#define JAZZ_PORT(base, int) \
28
+
{ \
29
+
.mapbase = base, \
30
+
.irq = int, \
31
+
.uartclk = JAZZ_BASE_BAUD, \
32
+
.iotype = UPIO_MEM, \
33
+
.flags = JAZZ_UART_FLAGS, \
34
+
.regshift = 0, \
35
+
}
36
+
37
+
static struct plat_serial8250_port uart8250_data[] = {
38
+
JAZZ_PORT(JAZZ_SERIAL1_BASE, JAZZ_SERIAL1_IRQ),
39
+
JAZZ_PORT(JAZZ_SERIAL2_BASE, JAZZ_SERIAL2_IRQ),
40
+
{ },
41
+
};
42
+
43
+
static struct platform_device uart8250_device = {
44
+
.name = "serial8250",
45
+
.id = PLAT8250_DEV_PLATFORM,
46
+
.dev = {
47
+
.platform_data = uart8250_data,
48
+
},
49
+
};
50
+
51
+
static int __init uart8250_init(void)
52
+
{
53
+
return platform_device_register(&uart8250_device);
54
+
}
55
+
56
+
module_init(uart8250_init);
57
+
58
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
59
+
MODULE_LICENSE("GPL");
60
+
MODULE_DESCRIPTION("8250 UART probe driver for the Jazz family");
+47
arch/mips/kernel/8250-platform.c
+47
arch/mips/kernel/8250-platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7
+
*/
8
+
#include <linux/module.h>
9
+
#include <linux/init.h>
10
+
#include <linux/serial_8250.h>
11
+
12
+
#define PORT(base, int) \
13
+
{ \
14
+
.iobase = base, \
15
+
.irq = int, \
16
+
.uartclk = 1843200, \
17
+
.iotype = UPIO_PORT, \
18
+
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
19
+
.regshift = 0, \
20
+
}
21
+
22
+
static struct plat_serial8250_port uart8250_data[] = {
23
+
PORT(0x3F8, 4),
24
+
PORT(0x2F8, 3),
25
+
PORT(0x3E8, 4),
26
+
PORT(0x2E8, 3),
27
+
{ },
28
+
};
29
+
30
+
static struct platform_device uart8250_device = {
31
+
.name = "serial8250",
32
+
.id = PLAT8250_DEV_PLATFORM,
33
+
.dev = {
34
+
.platform_data = uart8250_data,
35
+
},
36
+
};
37
+
38
+
static int __init uart8250_init(void)
39
+
{
40
+
return platform_device_register(&uart8250_device);
41
+
}
42
+
43
+
module_init(uart8250_init);
44
+
45
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
46
+
MODULE_LICENSE("GPL");
47
+
MODULE_DESCRIPTION("Generic 8250 UART probe driver");
+2
arch/mips/kernel/Makefile
+2
arch/mips/kernel/Makefile
+2
-1
arch/mips/mips-boards/malta/Makefile
+2
-1
arch/mips/mips-boards/malta/Makefile
+65
arch/mips/mips-boards/malta/malta_platform.c
+65
arch/mips/mips-boards/malta/malta_platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 MIPS Technologies, Inc.
7
+
* written by Ralf Baechle (ralf@linux-mips.org)
8
+
*
9
+
* Probe driver for the Malta's UART ports:
10
+
*
11
+
* o 2 ports in the SMC SuperIO
12
+
* o 1 port in the CBUS UART, a discrete 16550 which normally is only used
13
+
* for bringups.
14
+
*
15
+
* We don't use 8250_platform.c on Malta as it would result in the CBUS
16
+
* UART becoming ttyS0.
17
+
*/
18
+
#include <linux/module.h>
19
+
#include <linux/init.h>
20
+
#include <linux/serial_8250.h>
21
+
22
+
#define SMC_PORT(base, int) \
23
+
{ \
24
+
.iobase = base, \
25
+
.irq = int, \
26
+
.uartclk = 1843200, \
27
+
.iotype = UPIO_PORT, \
28
+
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \
29
+
.regshift = 0, \
30
+
}
31
+
32
+
#define CBUS_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
33
+
34
+
static struct plat_serial8250_port uart8250_data[] = {
35
+
SMC_PORT(0x3F8, 4),
36
+
SMC_PORT(0x2F8, 3),
37
+
{
38
+
.mapbase = 0x1f000900, /* The CBUS UART */
39
+
.irq = MIPS_CPU_IRQ_BASE + 2,
40
+
.uartclk = 3686400, /* Twice the usual clk! */
41
+
.iotype = UPIO_MEM32,
42
+
.flags = CBUS_UART_FLAGS,
43
+
.regshift = 3,
44
+
},
45
+
{ },
46
+
};
47
+
48
+
static struct platform_device uart8250_device = {
49
+
.name = "serial8250",
50
+
.id = PLAT8250_DEV_PLATFORM2,
51
+
.dev = {
52
+
.platform_data = uart8250_data,
53
+
},
54
+
};
55
+
56
+
static int __init uart8250_init(void)
57
+
{
58
+
return platform_device_register(&uart8250_device);
59
+
}
60
+
61
+
module_init(uart8250_init);
62
+
63
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
64
+
MODULE_LICENSE("GPL");
65
+
MODULE_DESCRIPTION("8250 UART probe driver for the Malta CBUS UART");
+44
arch/mips/momentum/ocelot_3/platform.c
+44
arch/mips/momentum/ocelot_3/platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
7
+
* Copyright (C) 2007 Dale Farnsworth (dale@farnsworth.org)
8
+
*/
1
9
#include <linux/delay.h>
2
10
#include <linux/if_ether.h>
11
+
#include <linux/init.h>
3
12
#include <linux/ioport.h>
13
+
#include <linux/module.h>
4
14
#include <linux/mv643xx.h>
5
15
#include <linux/platform_device.h>
16
+
#include <linux/serial_8250.h>
6
17
7
18
#include "ocelot_3_fpga.h"
8
19
···
217
206
device_initcall(mv643xx_eth_add_pds);
218
207
219
208
#endif /* defined(CONFIG_MV643XX_ETH) || defined(CONFIG_MV643XX_ETH_MODULE) */
209
+
210
+
#define OCELOT3_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST)
211
+
212
+
static struct plat_serial8250_port uart8250_data[] = {
213
+
{
214
+
.membase = (signed long) 0xfd000020,
215
+
.irq = 6,
216
+
.uartclk = 20000000,
217
+
.iotype = UPIO_MEM,
218
+
.flags = OCELOT3_UART_FLAGS,
219
+
.regshift = 2,
220
+
},
221
+
{ },
222
+
};
223
+
224
+
static struct platform_device uart8250_device = {
225
+
.name = "serial8250",
226
+
.id = PLAT8250_DEV_PLATFORM,
227
+
.dev = {
228
+
.platform_data = uart8250_data,
229
+
},
230
+
};
231
+
232
+
static int __init uart8250_init(void)
233
+
{
234
+
return platform_device_register(&uart8250_device);
235
+
}
236
+
237
+
module_init(uart8250_init);
238
+
239
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
240
+
MODULE_LICENSE("GPL");
241
+
MODULE_DESCRIPTION("8250 UART probe driver for the Ocelot 3");
+52
arch/mips/sgi-ip32/ip32-platform.c
+52
arch/mips/sgi-ip32/ip32-platform.c
···
1
+
/*
2
+
* This file is subject to the terms and conditions of the GNU General Public
3
+
* License. See the file "COPYING" in the main directory of this archive
4
+
* for more details.
5
+
*
6
+
* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
7
+
*/
8
+
#include <linux/module.h>
1
9
#include <linux/init.h>
2
10
#include <linux/platform_device.h>
11
+
#include <linux/serial_8250.h>
12
+
13
+
#include <asm/ip32/mace.h>
14
+
#include <asm/ip32/ip32_ints.h>
15
+
16
+
/*
17
+
* .iobase isn't a constant (in the sense of C) so we fill it in at runtime.
18
+
*/
19
+
#define MACE_PORT(int) \
20
+
{ \
21
+
.irq = int, \
22
+
.uartclk = 1843200, \
23
+
.iotype = UPIO_MEM, \
24
+
.flags = UPF_SKIP_TEST, \
25
+
.regshift = 8, \
26
+
}
27
+
28
+
static struct plat_serial8250_port uart8250_data[] = {
29
+
MACE_PORT(MACEISA_SERIAL1_IRQ),
30
+
MACE_PORT(MACEISA_SERIAL2_IRQ),
31
+
{ },
32
+
};
33
+
34
+
static struct platform_device uart8250_device = {
35
+
.name = "serial8250",
36
+
.id = PLAT8250_DEV_PLATFORM,
37
+
.dev = {
38
+
.platform_data = uart8250_data,
39
+
},
40
+
};
41
+
42
+
static int __init uart8250_init(void)
43
+
{
44
+
uart8250_data[0].iobase = (unsigned long) &mace->isa.serial1;
45
+
uart8250_data[1].iobase = (unsigned long) &mace->isa.serial1;
46
+
47
+
return platform_device_register(&uart8250_device);
48
+
}
49
+
50
+
device_initcall(uart8250_init);
3
51
4
52
static __init int meth_devinit(void)
5
53
{
···
66
18
}
67
19
68
20
device_initcall(meth_devinit);
21
+
22
+
MODULE_AUTHOR("Ralf Baechle <ralf@linux-mips.org>");
23
+
MODULE_LICENSE("GPL");
24
+
MODULE_DESCRIPTION("8250 UART probe driver for SGI IP32 aka O2");
-36
arch/mips/sgi-ip32/ip32-setup.c
-36
arch/mips/sgi-ip32/ip32-setup.c
···
62
62
}
63
63
#endif
64
64
65
-
#ifdef CONFIG_SERIAL_8250
66
-
#include <linux/tty.h>
67
-
#include <linux/serial.h>
68
-
#include <linux/serial_core.h>
69
-
#endif /* CONFIG_SERIAL_8250 */
70
-
71
65
/* An arbitrary time; this can be decreased if reliability looks good */
72
66
#define WAIT_MS 10
73
67
···
90
96
91
97
board_time_init = ip32_time_init;
92
98
93
-
#ifdef CONFIG_SERIAL_8250
94
-
{
95
-
static struct uart_port o2_serial[2];
96
-
97
-
memset(o2_serial, 0, sizeof(o2_serial));
98
-
o2_serial[0].type = PORT_16550A;
99
-
o2_serial[0].line = 0;
100
-
o2_serial[0].irq = MACEISA_SERIAL1_IRQ;
101
-
o2_serial[0].flags = UPF_SKIP_TEST;
102
-
o2_serial[0].uartclk = 1843200;
103
-
o2_serial[0].iotype = UPIO_MEM;
104
-
o2_serial[0].membase = (char *)&mace->isa.serial1;
105
-
o2_serial[0].fifosize = 14;
106
-
/* How much to shift register offset by. Each UART register
107
-
* is replicated over 256 byte space */
108
-
o2_serial[0].regshift = 8;
109
-
o2_serial[1].type = PORT_16550A;
110
-
o2_serial[1].line = 1;
111
-
o2_serial[1].irq = MACEISA_SERIAL2_IRQ;
112
-
o2_serial[1].flags = UPF_SKIP_TEST;
113
-
o2_serial[1].uartclk = 1843200;
114
-
o2_serial[1].iotype = UPIO_MEM;
115
-
o2_serial[1].membase = (char *)&mace->isa.serial2;
116
-
o2_serial[1].fifosize = 14;
117
-
o2_serial[1].regshift = 8;
118
-
119
-
early_serial_setup(&o2_serial[0]);
120
-
early_serial_setup(&o2_serial[1]);
121
-
}
122
-
#endif
123
99
#ifdef CONFIG_SGI_O2MACE_ETH
124
100
{
125
101
char *mac = ArcGetEnvironmentVariable("eaddr");
-110
include/asm-mips/serial.h
-110
include/asm-mips/serial.h
···
19
19
*/
20
20
#define BASE_BAUD (1843200 / 16)
21
21
22
-
/* Standard COM flags (except for COM4, because of the 8514 problem) */
23
-
#ifdef CONFIG_SERIAL_DETECT_IRQ
24
-
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
25
-
#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
26
-
#else
27
-
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
28
-
#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
29
-
#endif
30
-
31
-
#ifdef CONFIG_MACH_JAZZ
32
-
#include <asm/jazz.h>
33
-
34
-
#ifndef CONFIG_OLIVETTI_M700
35
-
/* Some Jazz machines seem to have an 8MHz crystal clock but I don't know
36
-
exactly which ones ... XXX */
37
-
#define JAZZ_BASE_BAUD ( 8000000 / 16 ) /* ( 3072000 / 16) */
38
-
#else
39
-
/* but the M700 isn't such a strange beast */
40
-
#define JAZZ_BASE_BAUD BASE_BAUD
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#endif
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#define _JAZZ_SERIAL_INIT(int, base) \
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{ .baud_base = JAZZ_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 0, \
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.io_type = SERIAL_IO_MEM }
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#define JAZZ_SERIAL_PORT_DEFNS \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL1_IRQ, JAZZ_SERIAL1_BASE), \
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_JAZZ_SERIAL_INIT(JAZZ_SERIAL2_IRQ, JAZZ_SERIAL2_BASE),
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#else
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#define JAZZ_SERIAL_PORT_DEFNS
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#endif
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#ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
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#define STD_SERIAL_PORT_DEFNS \
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/* UART CLK PORT IRQ FLAGS */ \
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{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
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{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \
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{ 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \
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{ 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */
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62
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#else /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
63
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#define STD_SERIAL_PORT_DEFNS
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#endif /* CONFIG_HAVE_STD_PC_SERIAL_PORTS */
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#ifdef CONFIG_MOMENCO_OCELOT_3
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#define OCELOT_3_BASE_BAUD ( 20000000 / 16 )
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#define OCELOT_3_SERIAL_IRQ 6
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#define OCELOT_3_SERIAL_BASE (signed)0xfd000020
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#define _OCELOT_3_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_3_BASE_BAUD, irq: int, \
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.flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, iomem_reg_shift: 2, \
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io_type: SERIAL_IO_MEM }
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-
77
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS \
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_OCELOT_3_SERIAL_INIT(OCELOT_3_SERIAL_IRQ, OCELOT_3_SERIAL_BASE)
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#else
80
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#define MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
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#endif
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-
83
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#ifdef CONFIG_MOMENCO_OCELOT
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/* Ordinary NS16552 duart with a 20MHz crystal. */
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#define OCELOT_BASE_BAUD ( 20000000 / 16 )
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87
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#define OCELOT_SERIAL1_IRQ 4
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#define OCELOT_SERIAL1_BASE 0xe0001020
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90
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#define _OCELOT_SERIAL_INIT(int, base) \
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{ .baud_base = OCELOT_BASE_BAUD, .irq = int, .flags = STD_COM_FLAGS, \
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.iomem_base = (u8 *) base, .iomem_reg_shift = 2, \
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.io_type = SERIAL_IO_MEM }
94
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
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_OCELOT_SERIAL_INIT(OCELOT_SERIAL1_IRQ, OCELOT_SERIAL1_BASE)
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#else
97
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#define MOMENCO_OCELOT_SERIAL_PORT_DEFNS
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-
#endif
99
-
100
-
#ifdef CONFIG_DDB5477
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#include <asm/ddb5xxx/ddb5477.h>
102
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#define DDB5477_SERIAL_PORT_DEFNS \
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{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART0, \
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.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04200, \
105
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.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM}, \
106
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{ .baud_base = BASE_BAUD, .irq = VRC5477_IRQ_UART1, \
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.flags = STD_COM_FLAGS, .iomem_base = (u8*)0xbfa04240, \
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-
.iomem_reg_shift = 3, .io_type = SERIAL_IO_MEM},
109
-
#else
110
-
#define DDB5477_SERIAL_PORT_DEFNS
111
-
#endif
112
-
113
-
#ifdef CONFIG_SGI_IP32
114
-
/*
115
-
* The IP32 (SGI O2) has standard serial ports (UART 16550A) mapped in memory
116
-
* They are initialized in ip32_setup
117
-
*/
118
-
#define IP32_SERIAL_PORT_DEFNS \
119
-
{},{},
120
-
#else
121
-
#define IP32_SERIAL_PORT_DEFNS
122
-
#endif /* CONFIG_SGI_IP32 */
123
-
124
-
#define SERIAL_PORT_DFNS \
125
-
DDB5477_SERIAL_PORT_DEFNS \
126
-
IP32_SERIAL_PORT_DEFNS \
127
-
JAZZ_SERIAL_PORT_DEFNS \
128
-
STD_SERIAL_PORT_DEFNS \
129
-
MOMENCO_OCELOT_SERIAL_PORT_DEFNS \
130
-
MOMENCO_OCELOT_3_SERIAL_PORT_DEFNS
131
-
132
22
#endif /* _ASM_SERIAL_H */