Merge branch 'for-arm-soc' of http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm into next/cleanup

+1

arch/arm/include/asm/suspend.h

··· 7 7 }; 8 8 9 9 extern void cpu_resume(void); 10 + extern void cpu_resume_arm(void); 10 11 extern int cpu_suspend(unsigned long, int (*)(unsigned long)); 11 12 12 13 #endif

+14

arch/arm/kernel/sleep.S

··· 118 118 119 119 .text 120 120 .align 121 + 122 + #ifdef CONFIG_MMU 123 + .arm 124 + ENTRY(cpu_resume_arm) 125 + THUMB( adr r9, BSYM(1f) ) @ Kernel is entered in ARM. 126 + THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 127 + THUMB( .thumb ) @ switch to Thumb now. 128 + THUMB(1: ) 129 + #endif 130 + 121 131 ENTRY(cpu_resume) 122 132 ARM_BE8(setend be) @ ensure we are in BE mode 123 133 #ifdef CONFIG_ARM_VIRT_EXT ··· 159 149 THUMB( mov sp, r2 ) 160 150 THUMB( bx r3 ) 161 151 ENDPROC(cpu_resume) 152 + 153 + #ifdef CONFIG_MMU 154 + ENDPROC(cpu_resume_arm) 155 + #endif 162 156 163 157 .align 2 164 158 _sleep_save_sp:

+1 -1

arch/arm/mach-bcm/Makefile

··· 43 43 ifeq ($(CONFIG_ARCH_BRCMSTB),y) 44 44 CFLAGS_platsmp-brcmstb.o += -march=armv7-a 45 45 obj-y += brcmstb.o 46 - obj-$(CONFIG_SMP) += headsmp-brcmstb.o platsmp-brcmstb.o 46 + obj-$(CONFIG_SMP) += platsmp-brcmstb.o 47 47 endif

-19

arch/arm/mach-bcm/brcmstb.h

··· 1 - /* 2 - * Copyright (C) 2013-2014 Broadcom Corporation 3 - * 4 - * This program is free software; you can redistribute it and/or 5 - * modify it under the terms of the GNU General Public License as 6 - * published by the Free Software Foundation version 2. 7 - * 8 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 - * kind, whether express or implied; without even the implied warranty 10 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 - * GNU General Public License for more details. 12 - */ 13 - 14 - #ifndef __BRCMSTB_H__ 15 - #define __BRCMSTB_H__ 16 - 17 - void brcmstb_secondary_startup(void); 18 - 19 - #endif /* __BRCMSTB_H__ */

-33

arch/arm/mach-bcm/headsmp-brcmstb.S

··· 1 - /* 2 - * SMP boot code for secondary CPUs 3 - * Based on arch/arm/mach-tegra/headsmp.S 4 - * 5 - * Copyright (C) 2010 NVIDIA, Inc. 6 - * Copyright (C) 2013-2014 Broadcom Corporation 7 - * 8 - * This program is free software; you can redistribute it and/or 9 - * modify it under the terms of the GNU General Public License as 10 - * published by the Free Software Foundation version 2. 11 - * 12 - * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 - * kind, whether express or implied; without even the implied warranty 14 - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 - * GNU General Public License for more details. 16 - */ 17 - 18 - #include <asm/assembler.h> 19 - #include <linux/linkage.h> 20 - #include <linux/init.h> 21 - 22 - .section ".text.head", "ax" 23 - 24 - ENTRY(brcmstb_secondary_startup) 25 - /* 26 - * Ensure CPU is in a sane state by disabling all IRQs and switching 27 - * into SVC mode. 28 - */ 29 - setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r0 30 - 31 - bl v7_invalidate_l1 32 - b secondary_startup 33 - ENDPROC(brcmstb_secondary_startup)

+1 -3

arch/arm/mach-bcm/platsmp-brcmstb.c

··· 30 30 #include <asm/mach-types.h> 31 31 #include <asm/smp_plat.h> 32 32 33 - #include "brcmstb.h" 34 - 35 33 enum { 36 34 ZONE_MAN_CLKEN_MASK = BIT(0), 37 35 ZONE_MAN_RESET_CNTL_MASK = BIT(1), ··· 151 153 * Set the reset vector to point to the secondary_startup 152 154 * routine 153 155 */ 154 - cpu_set_boot_addr(cpu, virt_to_phys(brcmstb_secondary_startup)); 156 + cpu_set_boot_addr(cpu, virt_to_phys(secondary_startup)); 155 157 156 158 /* Unhalt the cpu */ 157 159 cpu_rst_cfg_set(cpu, 0);

-6

arch/arm/mach-berlin/headsmp.S

··· 12 12 #include <linux/init.h> 13 13 #include <asm/assembler.h> 14 14 15 - ENTRY(berlin_secondary_startup) 16 - ARM_BE8(setend be) 17 - bl v7_invalidate_l1 18 - b secondary_startup 19 - ENDPROC(berlin_secondary_startup) 20 - 21 15 /* 22 16 * If the following instruction is set in the reset exception vector, CPUs 23 17 * will fetch the value of the software reset address vector when being

+1 -2

arch/arm/mach-berlin/platsmp.c

··· 22 22 #define RESET_VECT 0x00 23 23 #define SW_RESET_ADDR 0x94 24 24 25 - extern void berlin_secondary_startup(void); 26 25 extern u32 boot_inst; 27 26 28 27 static void __iomem *cpu_ctrl; ··· 84 85 * Write the secondary startup address into the SW reset address 85 86 * vector. This is used by boot_inst. 86 87 */ 87 - writel(virt_to_phys(berlin_secondary_startup), vectors_base + SW_RESET_ADDR); 88 + writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR); 88 89 89 90 iounmap(vectors_base); 90 91 unmap_scu:

+1 -1

arch/arm/mach-hisi/Makefile

··· 6 6 7 7 obj-y += hisilicon.o 8 8 obj-$(CONFIG_MCPM) += platmcpm.o 9 - obj-$(CONFIG_SMP) += platsmp.o hotplug.o headsmp.o 9 + obj-$(CONFIG_SMP) += platsmp.o hotplug.o

-1

arch/arm/mach-hisi/core.h

··· 12 12 extern int hi3xxx_cpu_kill(unsigned int cpu); 13 13 extern void hi3xxx_set_cpu(int cpu, bool enable); 14 14 15 - extern void hisi_secondary_startup(void); 16 15 extern struct smp_operations hix5hd2_smp_ops; 17 16 extern void hix5hd2_set_cpu(int cpu, bool enable); 18 17 extern void hix5hd2_cpu_die(unsigned int cpu);

-16

arch/arm/mach-hisi/headsmp.S

··· 1 - /* 2 - * Copyright (c) 2014 Hisilicon Limited. 3 - * Copyright (c) 2014 Linaro Ltd. 4 - * 5 - * This program is free software; you can redistribute it and/or modify 6 - * it under the terms of the GNU General Public License version 2 as 7 - * published by the Free Software Foundation. 8 - */ 9 - #include <linux/linkage.h> 10 - #include <linux/init.h> 11 - 12 - __CPUINIT 13 - 14 - ENTRY(hisi_secondary_startup) 15 - bl v7_invalidate_l1 16 - b secondary_startup

+2 -2

arch/arm/mach-hisi/platsmp.c

··· 118 118 { 119 119 phys_addr_t jumpaddr; 120 120 121 - jumpaddr = virt_to_phys(hisi_secondary_startup); 121 + jumpaddr = virt_to_phys(secondary_startup); 122 122 hix5hd2_set_scu_boot_addr(HIX5HD2_BOOT_ADDRESS, jumpaddr); 123 123 hix5hd2_set_cpu(cpu, true); 124 124 arch_send_wakeup_ipi_mask(cpumask_of(cpu)); ··· 156 156 struct device_node *node; 157 157 158 158 159 - jumpaddr = virt_to_phys(hisi_secondary_startup); 159 + jumpaddr = virt_to_phys(secondary_startup); 160 160 hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr); 161 161 162 162 node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");

-1

arch/arm/mach-imx/headsmp.S

··· 25 25 .endm 26 26 27 27 ENTRY(v7_secondary_startup) 28 - bl v7_invalidate_l1 29 28 set_diag_reg 30 29 b secondary_startup 31 30 ENDPROC(v7_secondary_startup)

-1

arch/arm/mach-mvebu/headsmp-a9.S

··· 21 21 22 22 ENTRY(mvebu_cortex_a9_secondary_startup) 23 23 ARM_BE8(setend be) 24 - bl v7_invalidate_l1 25 24 bl armada_38x_scu_power_up 26 25 b secondary_startup 27 26 ENDPROC(mvebu_cortex_a9_secondary_startup)

-1

arch/arm/mach-prima2/headsmp.S

··· 15 15 * ready for them to initialise. 16 16 */ 17 17 ENTRY(sirfsoc_secondary_startup) 18 - bl v7_invalidate_l1 19 18 mrc p15, 0, r0, c0, c0, 5 20 19 and r0, r0, #15 21 20 adr r4, 1f

-1

arch/arm/mach-rockchip/core.h

··· 17 17 extern char rockchip_secondary_trampoline_end; 18 18 19 19 extern unsigned long rockchip_boot_fn; 20 - extern void rockchip_secondary_startup(void);

-8

arch/arm/mach-rockchip/headsmp.S

··· 15 15 #include <linux/linkage.h> 16 16 #include <linux/init.h> 17 17 18 - ENTRY(rockchip_secondary_startup) 19 - mrc p15, 0, r0, c0, c0, 0 @ read main ID register 20 - ldr r1, =0x00000c09 @ Cortex-A9 primary part number 21 - teq r0, r1 22 - beq v7_invalidate_l1 23 - b secondary_startup 24 - ENDPROC(rockchip_secondary_startup) 25 - 26 18 ENTRY(rockchip_secondary_trampoline) 27 19 ldr pc, 1f 28 20 ENDPROC(rockchip_secondary_trampoline)

+2 -3

arch/arm/mach-rockchip/platsmp.c

··· 149 149 * sram_base_addr + 8: start address for pc 150 150 * */ 151 151 udelay(10); 152 - writel(virt_to_phys(rockchip_secondary_startup), 153 - sram_base_addr + 8); 152 + writel(virt_to_phys(secondary_startup), sram_base_addr + 8); 154 153 writel(0xDEADBEAF, sram_base_addr + 4); 155 154 dsb_sev(); 156 155 } ··· 188 189 } 189 190 190 191 /* set the boot function for the sram code */ 191 - rockchip_boot_fn = virt_to_phys(rockchip_secondary_startup); 192 + rockchip_boot_fn = virt_to_phys(secondary_startup); 192 193 193 194 /* copy the trampoline to sram, that runs during startup of the core */ 194 195 memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);

-1

arch/arm/mach-shmobile/common.h

··· 14 14 extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn, 15 15 unsigned long arg); 16 16 extern int shmobile_smp_cpu_disable(unsigned int cpu); 17 - extern void shmobile_invalidate_start(void); 18 17 extern void shmobile_boot_scu(void); 19 18 extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus); 20 19 extern void shmobile_smp_scu_cpu_die(unsigned int cpu);

+2 -2

arch/arm/mach-shmobile/headsmp-scu.S

··· 22 22 * Boot code for secondary CPUs. 23 23 * 24 24 * First we turn on L1 cache coherency for our CPU. Then we jump to 25 - * shmobile_invalidate_start that invalidates the cache and hands over control 25 + * secondary_startup that invalidates the cache and hands over control 26 26 * to the common ARM startup code. 27 27 */ 28 28 ENTRY(shmobile_boot_scu) ··· 36 36 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) 37 37 str r2, [r0, #8] @ write back 38 38 39 - b shmobile_invalidate_start 39 + b secondary_startup 40 40 ENDPROC(shmobile_boot_scu) 41 41 42 42 .text

-7

arch/arm/mach-shmobile/headsmp.S

··· 16 16 #include <asm/assembler.h> 17 17 #include <asm/memory.h> 18 18 19 - #ifdef CONFIG_SMP 20 - ENTRY(shmobile_invalidate_start) 21 - bl v7_invalidate_l1 22 - b secondary_startup 23 - ENDPROC(shmobile_invalidate_start) 24 - #endif 25 - 26 19 /* 27 20 * Reset vector for secondary CPUs. 28 21 * This will be mapped at address 0 by SBAR register.

+1 -1

arch/arm/mach-shmobile/platsmp-apmu.c

··· 133 133 int shmobile_smp_apmu_boot_secondary(unsigned int cpu, struct task_struct *idle) 134 134 { 135 135 /* For this particular CPU register boot vector */ 136 - shmobile_smp_hook(cpu, virt_to_phys(shmobile_invalidate_start), 0); 136 + shmobile_smp_hook(cpu, virt_to_phys(secondary_startup), 0); 137 137 138 138 return apmu_wrap(cpu, apmu_power_on); 139 139 }

-1

arch/arm/mach-socfpga/core.h

··· 31 31 32 32 #define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */ 33 33 34 - extern void socfpga_secondary_startup(void); 35 34 extern void __iomem *socfpga_scu_base_addr; 36 35 37 36 extern void socfpga_init_clocks(void);

-5

arch/arm/mach-socfpga/headsmp.S

··· 30 30 1: .long . 31 31 .long socfpga_cpu1start_addr 32 32 ENTRY(secondary_trampoline_end) 33 - 34 - ENTRY(socfpga_secondary_startup) 35 - bl v7_invalidate_l1 36 - b secondary_startup 37 - ENDPROC(socfpga_secondary_startup)

+1 -1

arch/arm/mach-socfpga/platsmp.c

··· 40 40 41 41 memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size); 42 42 43 - writel(virt_to_phys(socfpga_secondary_startup), 43 + writel(virt_to_phys(secondary_startup), 44 44 sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff)); 45 45 46 46 flush_cache_all();

+1 -1

arch/arm/mach-tegra/Makefile

··· 19 19 ifeq ($(CONFIG_CPU_IDLE),y) 20 20 obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o 21 21 endif 22 - obj-$(CONFIG_SMP) += platsmp.o headsmp.o 22 + obj-$(CONFIG_SMP) += platsmp.o 23 23 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 24 24 25 25 obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o

-12

arch/arm/mach-tegra/headsmp.S

··· 1 - #include <linux/linkage.h> 2 - #include <linux/init.h> 3 - 4 - #include "sleep.h" 5 - 6 - .section ".text.head", "ax" 7 - 8 - ENTRY(tegra_secondary_startup) 9 - check_cpu_part_num 0xc09, r8, r9 10 - bleq v7_invalidate_l1 11 - b secondary_startup 12 - ENDPROC(tegra_secondary_startup)

+1 -1

arch/arm/mach-tegra/reset.c

··· 94 94 __tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] = 95 95 *((u32 *)cpu_possible_mask); 96 96 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] = 97 - virt_to_phys((void *)tegra_secondary_startup); 97 + virt_to_phys((void *)secondary_startup); 98 98 #endif 99 99 100 100 #ifdef CONFIG_PM_SLEEP

-1

arch/arm/mach-tegra/reset.h

··· 36 36 void __tegra_cpu_reset_handler_start(void); 37 37 void __tegra_cpu_reset_handler(void); 38 38 void __tegra_cpu_reset_handler_end(void); 39 - void tegra_secondary_startup(void); 40 39 41 40 #ifdef CONFIG_PM_SLEEP 42 41 #define tegra_cpu_lp1_mask \

-2

arch/arm/mach-zynq/common.h

··· 17 17 #ifndef __MACH_ZYNQ_COMMON_H__ 18 18 #define __MACH_ZYNQ_COMMON_H__ 19 19 20 - void zynq_secondary_startup(void); 21 - 22 20 extern int zynq_slcr_init(void); 23 21 extern int zynq_early_slcr_init(void); 24 22 extern void zynq_slcr_system_reset(void);

-5

arch/arm/mach-zynq/headsmp.S

··· 22 22 .globl zynq_secondary_trampoline_end 23 23 zynq_secondary_trampoline_end: 24 24 ENDPROC(zynq_secondary_trampoline) 25 - 26 - ENTRY(zynq_secondary_startup) 27 - bl v7_invalidate_l1 28 - b secondary_startup 29 - ENDPROC(zynq_secondary_startup)

+2 -3

arch/arm/mach-zynq/platsmp.c

··· 87 87 } 88 88 EXPORT_SYMBOL(zynq_cpun_start); 89 89 90 - static int zynq_boot_secondary(unsigned int cpu, 91 - struct task_struct *idle) 90 + static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) 92 91 { 93 - return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); 92 + return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); 94 93 } 95 94 96 95 /*

+1 -1

arch/arm/mm/proc-v7.S

··· 336 336 __v7_setup: 337 337 adr r12, __v7_setup_stack @ the local stack 338 338 stmia r12, {r0-r5, r7, r9, r11, lr} 339 - bl v7_flush_dcache_louis 339 + bl v7_invalidate_l1 340 340 ldmia r12, {r0-r5, r7, r9, r11, lr} 341 341 342 342 mrc p15, 0, r0, c0, c0, 0 @ read main ID register