tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel
Selector (ISPCS), and video capture (VIN) clocks on R-Car V4H
- Add video capture (VIN) clocks on R-Car V3H
- Add Cortex-A53 System CPU (Z2) clocks on R-Car V3M and V3H
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.4-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: Convert to platform remove callback returning void
clk: renesas: r9a06g032: Improve clock tables
clk: renesas: r9a06g032: Document structs
clk: renesas: r9a06g032: Drop unused fields
clk: renesas: r9a06g032: Improve readability
clk: renesas: r8a77980: Add Z2 clock
clk: renesas: r8a77970: Add Z2 clock
clk: renesas: r8a77995: Fix VIN parent clock
clk: renesas: r8a77980: Add VIN clocks
clk: renesas: r8a779g0: Add VIN clocks
clk: renesas: r8a779g0: Add ISPCS clocks
clk: renesas: r8a779g0: Add CSI-2 clocks
clk: renesas: r8a779g0: Add thermal clock
clk: renesas: r8a779g0: Add Audio clocks
clk: renesas: cpg-mssr: Update MSSR register range for R-Car V4H
+591
-205
+1
drivers/clk/renesas/r8a77970-cpg-mssr.c
+1
drivers/clk/renesas/r8a77970-cpg-mssr.c
···
76
76
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
77
77
78
78
/* Core Clock Outputs */
79
+
DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
79
80
DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
80
81
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
81
82
DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
+17
drivers/clk/renesas/r8a77980-cpg-mssr.c
+17
drivers/clk/renesas/r8a77980-cpg-mssr.c
···
72
72
DEF_RATE(".oco", CLK_OCO, 32768),
73
73
74
74
/* Core Clock Outputs */
75
+
DEF_FIXED("z2", R8A77980_CLK_Z2, CLK_PLL2, 4, 1),
75
76
DEF_FIXED("ztr", R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
76
77
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
77
78
DEF_FIXED("zt", R8A77980_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
···
151
150
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
152
151
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
153
152
DEF_MOD("fcpvd0", 603, R8A77980_CLK_S3D1),
153
+
DEF_MOD("vin15", 604, R8A77980_CLK_S2D1),
154
+
DEF_MOD("vin14", 605, R8A77980_CLK_S2D1),
155
+
DEF_MOD("vin13", 608, R8A77980_CLK_S2D1),
156
+
DEF_MOD("vin12", 612, R8A77980_CLK_S2D1),
157
+
DEF_MOD("vin11", 618, R8A77980_CLK_S2D1),
154
158
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
159
+
DEF_MOD("vin10", 625, R8A77980_CLK_S2D1),
160
+
DEF_MOD("vin9", 627, R8A77980_CLK_S2D1),
161
+
DEF_MOD("vin8", 628, R8A77980_CLK_S2D1),
155
162
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
156
163
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
157
164
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
158
165
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
166
+
DEF_MOD("vin7", 804, R8A77980_CLK_S2D1),
167
+
DEF_MOD("vin6", 805, R8A77980_CLK_S2D1),
168
+
DEF_MOD("vin5", 806, R8A77980_CLK_S2D1),
169
+
DEF_MOD("vin4", 807, R8A77980_CLK_S2D1),
170
+
DEF_MOD("vin3", 808, R8A77980_CLK_S2D1),
171
+
DEF_MOD("vin2", 809, R8A77980_CLK_S2D1),
172
+
DEF_MOD("vin1", 810, R8A77980_CLK_S2D1),
173
+
DEF_MOD("vin0", 811, R8A77980_CLK_S2D1),
159
174
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
160
175
DEF_MOD("gether", 813, R8A77980_CLK_S3D2),
161
176
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
+1
-1
drivers/clk/renesas/r8a77995-cpg-mssr.c
+1
-1
drivers/clk/renesas/r8a77995-cpg-mssr.c
···
167
167
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
168
168
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
169
169
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
170
-
DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
170
+
DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
171
171
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
172
172
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
173
173
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
+24
drivers/clk/renesas/r8a779g0-cpg-mssr.c
+24
drivers/clk/renesas/r8a779g0-cpg-mssr.c
···
146
146
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
147
147
DEF_FIXED("vcbusd2", R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
148
148
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
149
+
DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
149
150
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF, CLK_PLL5_DIV4, 48, 1),
150
151
DEF_DIV6P1("dsiext", R8A779G0_CLK_DSIEXT, CLK_PLL5_DIV4, 0x884),
151
152
···
166
165
DEF_MOD("avb1", 212, R8A779G0_CLK_S0D4_HSC),
167
166
DEF_MOD("avb2", 213, R8A779G0_CLK_S0D4_HSC),
168
167
DEF_MOD("canfd0", 328, R8A779G0_CLK_SASYNCPERD2),
168
+
DEF_MOD("csi40", 331, R8A779G0_CLK_CSI),
169
+
DEF_MOD("csi41", 400, R8A779G0_CLK_CSI),
169
170
DEF_MOD("dis0", 411, R8A779G0_CLK_VIOBUSD2),
170
171
DEF_MOD("dsitxlink0", 415, R8A779G0_CLK_VIOBUSD2),
171
172
DEF_MOD("dsitxlink1", 416, R8A779G0_CLK_VIOBUSD2),
···
184
181
DEF_MOD("i2c4", 522, R8A779G0_CLK_S0D6_PER),
185
182
DEF_MOD("i2c5", 523, R8A779G0_CLK_S0D6_PER),
186
183
DEF_MOD("irqc", 611, R8A779G0_CLK_CL16M),
184
+
DEF_MOD("ispcs0", 612, R8A779G0_CLK_S0D2_VIO),
185
+
DEF_MOD("ispcs1", 613, R8A779G0_CLK_S0D2_VIO),
187
186
DEF_MOD("msi0", 618, R8A779G0_CLK_MSO),
188
187
DEF_MOD("msi1", 619, R8A779G0_CLK_MSO),
189
188
DEF_MOD("msi2", 620, R8A779G0_CLK_MSO),
···
207
202
DEF_MOD("tmu3", 716, R8A779G0_CLK_SASYNCPERD2),
208
203
DEF_MOD("tmu4", 717, R8A779G0_CLK_SASYNCPERD2),
209
204
DEF_MOD("tpu0", 718, R8A779G0_CLK_SASYNCPERD4),
205
+
DEF_MOD("vin00", 730, R8A779G0_CLK_S0D4_VIO),
206
+
DEF_MOD("vin01", 731, R8A779G0_CLK_S0D4_VIO),
207
+
DEF_MOD("vin02", 800, R8A779G0_CLK_S0D4_VIO),
208
+
DEF_MOD("vin03", 801, R8A779G0_CLK_S0D4_VIO),
209
+
DEF_MOD("vin04", 802, R8A779G0_CLK_S0D4_VIO),
210
+
DEF_MOD("vin05", 803, R8A779G0_CLK_S0D4_VIO),
211
+
DEF_MOD("vin06", 804, R8A779G0_CLK_S0D4_VIO),
212
+
DEF_MOD("vin07", 805, R8A779G0_CLK_S0D4_VIO),
213
+
DEF_MOD("vin10", 806, R8A779G0_CLK_S0D4_VIO),
214
+
DEF_MOD("vin11", 807, R8A779G0_CLK_S0D4_VIO),
215
+
DEF_MOD("vin12", 808, R8A779G0_CLK_S0D4_VIO),
216
+
DEF_MOD("vin13", 809, R8A779G0_CLK_S0D4_VIO),
217
+
DEF_MOD("vin14", 810, R8A779G0_CLK_S0D4_VIO),
218
+
DEF_MOD("vin15", 811, R8A779G0_CLK_S0D4_VIO),
219
+
DEF_MOD("vin16", 812, R8A779G0_CLK_S0D4_VIO),
220
+
DEF_MOD("vin17", 813, R8A779G0_CLK_S0D4_VIO),
210
221
DEF_MOD("vspd0", 830, R8A779G0_CLK_VIOBUSD2),
211
222
DEF_MOD("vspd1", 831, R8A779G0_CLK_VIOBUSD2),
212
223
DEF_MOD("wdt1:wdt0", 907, R8A779G0_CLK_R),
···
234
213
DEF_MOD("pfc1", 916, R8A779G0_CLK_CL16M),
235
214
DEF_MOD("pfc2", 917, R8A779G0_CLK_CL16M),
236
215
DEF_MOD("pfc3", 918, R8A779G0_CLK_CL16M),
216
+
DEF_MOD("tsc", 919, R8A779G0_CLK_CL16M),
217
+
DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
218
+
DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
237
219
};
238
220
239
221
/*
+542
-196
drivers/clk/renesas/r9a06g032-clocks.c
+542
-196
drivers/clk/renesas/r9a06g032-clocks.c
···
29
29
#define R9A06G032_SYSCTRL_USB_H2MODE (1<<1)
30
30
#define R9A06G032_SYSCTRL_DMAMUX 0xA0
31
31
32
-
struct r9a06g032_gate {
33
-
u16 gate, reset, ready, midle,
34
-
scon, mirack, mistat;
32
+
/**
33
+
* struct regbit - describe one bit in a register
34
+
* @reg: offset of register relative to base address,
35
+
* expressed in units of 32-bit words (not bytes),
36
+
* @bit: which bit (0 to 31) in the register
37
+
*
38
+
* This structure is used to compactly encode the location
39
+
* of a single bit in a register. Five bits are needed to
40
+
* encode the bit number. With uint16_t data type, this
41
+
* leaves 11 bits to encode a register offset up to 2047.
42
+
*
43
+
* Since registers are aligned on 32-bit boundaries, the
44
+
* offset will be specified in 32-bit words rather than bytes.
45
+
* This allows encoding an offset up to 0x1FFC (8188) bytes.
46
+
*
47
+
* Helper macro RB() takes care of converting the register
48
+
* offset from bytes to 32-bit words.
49
+
*/
50
+
struct regbit {
51
+
u16 bit:5;
52
+
u16 reg:11;
35
53
};
36
54
37
-
/* This is used to describe a clock for instantiation */
55
+
#define RB(_reg, _bit) ((struct regbit) { \
56
+
.reg = (_reg) / 4, \
57
+
.bit = (_bit) \
58
+
})
59
+
60
+
/**
61
+
* struct r9a06g032_gate - clock-related control bits
62
+
* @gate: clock enable/disable
63
+
* @reset: clock module reset (active low)
64
+
* @ready: enables NoC forwarding of read/write requests to device,
65
+
* (eg. device is ready to handle read/write requests)
66
+
* @midle: request to idle the NoC interconnect
67
+
*
68
+
* Each of these fields describes a single bit in a register,
69
+
* which controls some aspect of clock gating. The @gate field
70
+
* is mandatory, this one enables/disables the clock. The
71
+
* other fields are optional, with zero indicating "not used".
72
+
*
73
+
* In most cases there is a @reset bit which needs to be
74
+
* de-asserted to bring the module out of reset.
75
+
*
76
+
* Modules may also need to signal when they are @ready to
77
+
* handle requests (read/writes) from the NoC interconnect.
78
+
*
79
+
* Similarly, the @midle bit is used to idle the master.
80
+
*/
81
+
struct r9a06g032_gate {
82
+
struct regbit gate, reset, ready, midle;
83
+
/* Unused fields omitted to save space */
84
+
/* struct regbit scon, mirack, mistat */;
85
+
};
86
+
87
+
enum gate_type {
88
+
K_GATE = 0, /* gate which enable/disable */
89
+
K_FFC, /* fixed factor clock */
90
+
K_DIV, /* divisor */
91
+
K_BITSEL, /* special for UARTs */
92
+
K_DUALGATE /* special for UARTs */
93
+
};
94
+
95
+
/**
96
+
* struct r9a06g032_clkdesc - describe a single clock
97
+
* @name: string describing this clock
98
+
* @managed: boolean indicating if this clock should be
99
+
* started/stopped as part of power management
100
+
* @type: see enum @gate_type
101
+
* @index: the ID of this clock element
102
+
* @source: the ID+1 of the parent clock element.
103
+
* Root clock uses ID of ~0 (PARENT_ID);
104
+
* @gate: clock enable/disable
105
+
* @div_min: smallest permitted clock divider
106
+
* @div_max: largest permitted clock divider
107
+
* @reg: clock divider register offset, in 32-bit words
108
+
* @div_table: optional list of fixed clock divider values;
109
+
* must be in ascending order, zero for unused
110
+
* @div: divisor for fixed-factor clock
111
+
* @mul: multiplier for fixed-factor clock
112
+
* @group: UART group, 0=UART0/1/2, 1=UART3/4/5/6/7
113
+
* @sel: select either g1/r1 or g2/r2 as clock source
114
+
* @g1: 1st source gate (clock enable/disable)
115
+
* @r1: 1st source reset (module reset)
116
+
* @g2: 2nd source gate (clock enable/disable)
117
+
* @r2: 2nd source reset (module reset)
118
+
*
119
+
* Describes a single element in the clock tree hierarchy.
120
+
* As there are quite a large number of clock elements, this
121
+
* structure is packed tightly to conserve space.
122
+
*/
38
123
struct r9a06g032_clkdesc {
39
124
const char *name;
40
-
uint32_t managed: 1;
41
-
uint32_t type: 3;
42
-
uint32_t index: 8;
43
-
uint32_t source : 8; /* source index + 1 (0 == none) */
44
-
/* these are used to populate the bitsel struct */
125
+
uint32_t managed:1;
126
+
enum gate_type type:3;
127
+
uint32_t index:8;
128
+
uint32_t source:8; /* source index + 1 (0 == none) */
45
129
union {
130
+
/* type = K_GATE */
46
131
struct r9a06g032_gate gate;
47
-
/* for dividers */
132
+
/* type = K_DIV */
48
133
struct {
49
-
unsigned int div_min : 10, div_max : 10, reg: 10;
134
+
unsigned int div_min:10, div_max:10, reg:10;
50
135
u16 div_table[4];
51
136
};
52
-
/* For fixed-factor ones */
137
+
/* type = K_FFC */
53
138
struct {
54
139
u16 div, mul;
55
140
};
56
-
/* for dual gate */
141
+
/* type = K_DUALGATE */
57
142
struct {
58
-
uint16_t group : 1;
59
-
u16 sel, g1, r1, g2, r2;
143
+
uint16_t group:1;
144
+
struct regbit sel, g1, r1, g2, r2;
60
145
} dual;
61
146
};
62
147
};
63
148
64
-
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
65
-
{ .gate = _clk, .reset = _rst, \
66
-
.ready = _rdy, .midle = _midle, \
67
-
.scon = _scon, .mirack = _mirack, .mistat = _mistat }
68
-
#define D_GATE(_idx, _n, _src, ...) \
69
-
{ .type = K_GATE, .index = R9A06G032_##_idx, \
70
-
.source = 1 + R9A06G032_##_src, .name = _n, \
71
-
.gate = I_GATE(__VA_ARGS__) }
72
-
#define D_MODULE(_idx, _n, _src, ...) \
73
-
{ .type = K_GATE, .index = R9A06G032_##_idx, \
74
-
.source = 1 + R9A06G032_##_src, .name = _n, \
75
-
.managed = 1, .gate = I_GATE(__VA_ARGS__) }
76
-
#define D_ROOT(_idx, _n, _mul, _div) \
77
-
{ .type = K_FFC, .index = R9A06G032_##_idx, .name = _n, \
78
-
.div = _div, .mul = _mul }
79
-
#define D_FFC(_idx, _n, _src, _div) \
80
-
{ .type = K_FFC, .index = R9A06G032_##_idx, \
81
-
.source = 1 + R9A06G032_##_src, .name = _n, \
82
-
.div = _div, .mul = 1}
83
-
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
84
-
{ .type = K_DIV, .index = R9A06G032_##_idx, \
85
-
.source = 1 + R9A06G032_##_src, .name = _n, \
86
-
.reg = _reg, .div_min = _min, .div_max = _max, \
87
-
.div_table = { __VA_ARGS__ } }
88
-
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) \
89
-
{ .type = K_DUALGATE, .index = R9A06G032_##_idx, \
90
-
.source = 1 + R9A06G032_##_src, .name = _n, \
91
-
.dual = { .group = _g, \
92
-
.g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
93
-
94
-
enum { K_GATE = 0, K_FFC, K_DIV, K_BITSEL, K_DUALGATE };
149
+
/*
150
+
* The last three arguments are not currently used,
151
+
* but are kept in the r9a06g032_clocks table below.
152
+
*/
153
+
#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) { \
154
+
.gate = _clk, \
155
+
.reset = _rst, \
156
+
.ready = _rdy, \
157
+
.midle = _midle, \
158
+
/* .scon = _scon, */ \
159
+
/* .mirack = _mirack, */ \
160
+
/* .mistat = _mistat */ \
161
+
}
162
+
#define D_GATE(_idx, _n, _src, ...) { \
163
+
.type = K_GATE, \
164
+
.index = R9A06G032_##_idx, \
165
+
.source = 1 + R9A06G032_##_src, \
166
+
.name = _n, \
167
+
.gate = I_GATE(__VA_ARGS__) \
168
+
}
169
+
#define D_MODULE(_idx, _n, _src, ...) { \
170
+
.type = K_GATE, \
171
+
.index = R9A06G032_##_idx, \
172
+
.source = 1 + R9A06G032_##_src, \
173
+
.name = _n, \
174
+
.managed = 1, \
175
+
.gate = I_GATE(__VA_ARGS__) \
176
+
}
177
+
#define D_ROOT(_idx, _n, _mul, _div) { \
178
+
.type = K_FFC, \
179
+
.index = R9A06G032_##_idx, \
180
+
.name = _n, \
181
+
.div = _div, \
182
+
.mul = _mul \
183
+
}
184
+
#define D_FFC(_idx, _n, _src, _div) { \
185
+
.type = K_FFC, \
186
+
.index = R9A06G032_##_idx, \
187
+
.source = 1 + R9A06G032_##_src, \
188
+
.name = _n, \
189
+
.div = _div, \
190
+
.mul = 1 \
191
+
}
192
+
#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) { \
193
+
.type = K_DIV, \
194
+
.index = R9A06G032_##_idx, \
195
+
.source = 1 + R9A06G032_##_src, \
196
+
.name = _n, \
197
+
.reg = _reg, \
198
+
.div_min = _min, \
199
+
.div_max = _max, \
200
+
.div_table = { __VA_ARGS__ } \
201
+
}
202
+
#define D_UGATE(_idx, _n, _src, _g, _g1, _r1, _g2, _r2) { \
203
+
.type = K_DUALGATE, \
204
+
.index = R9A06G032_##_idx, \
205
+
.source = 1 + R9A06G032_##_src, \
206
+
.name = _n, \
207
+
.dual = { \
208
+
.group = _g, \
209
+
.g1 = _g1, \
210
+
.r1 = _r1, \
211
+
.g2 = _g2, \
212
+
.r2 = _r2 \
213
+
}, \
214
+
}
95
215
96
216
/* Internal clock IDs */
97
217
#define R9A06G032_CLKOUT 0
···
280
160
D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
281
161
D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
282
162
D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
283
-
D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
284
-
D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
285
-
D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
286
-
D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
287
-
D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
288
-
D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
289
-
D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
290
-
D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
291
-
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
292
-
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
293
-
D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
294
-
D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
295
-
D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
296
-
D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
297
-
D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
298
-
D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
299
-
D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
300
-
D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
301
-
D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
302
-
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
303
-
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
304
-
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
305
-
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, 0xe6, 0, 0, 0, 0, 0, 0),
306
-
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
307
-
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
308
-
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
309
-
D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
310
-
D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
311
-
D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
312
-
D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
313
-
D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
314
-
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
315
-
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
316
-
D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
317
-
D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
318
-
D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
319
-
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
320
-
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
163
+
D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, RB(0xe8, 9),
164
+
RB(0xe8, 10), RB(0xe8, 11), RB(0x00, 0),
165
+
RB(0x15c, 3), RB(0x00, 0), RB(0x00, 0)),
166
+
D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, RB(0xe8, 12),
167
+
RB(0xe8, 13), RB(0xe8, 14), RB(0x00, 0),
168
+
RB(0x15c, 4), RB(0x00, 0), RB(0x00, 0)),
169
+
D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, RB(0xe8, 15),
170
+
RB(0xe8, 16), RB(0xe8, 17), RB(0x00, 0),
171
+
RB(0x15c, 5), RB(0x00, 0), RB(0x00, 0)),
172
+
D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, RB(0xe8, 18),
173
+
RB(0xe8, 19), RB(0xe8, 20), RB(0x00, 0),
174
+
RB(0x15c, 6), RB(0x00, 0), RB(0x00, 0)),
175
+
D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, RB(0xe8, 21),
176
+
RB(0xe8, 22), RB(0xe8, 23), RB(0x00, 0),
177
+
RB(0x15c, 7), RB(0x00, 0), RB(0x00, 0)),
178
+
D_GATE(CLK_ADC, "clk_adc", DIV_ADC, RB(0x3c, 10),
179
+
RB(0x3c, 11), RB(0x00, 0), RB(0x00, 0),
180
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
181
+
D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, RB(0x80, 5),
182
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
183
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
184
+
D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, RB(0x90, 3),
185
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
186
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
187
+
D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, RB(0x3c, 6),
188
+
RB(0x3c, 7), RB(0x00, 0), RB(0x00, 0),
189
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
190
+
D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, RB(0x3c, 8),
191
+
RB(0x3c, 9), RB(0x00, 0), RB(0x00, 0),
192
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
193
+
D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, RB(0x68, 2),
194
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
195
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
196
+
D_GATE(CLK_NAND, "clk_nand", DIV_NAND, RB(0x50, 4),
197
+
RB(0x50, 5), RB(0x00, 0), RB(0x00, 0),
198
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
199
+
D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, RB(0xec, 20),
200
+
RB(0xec, 21), RB(0x00, 0), RB(0x00, 0),
201
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
202
+
D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, RB(0x10c, 2),
203
+
RB(0x10c, 3), RB(0x00, 0), RB(0x00, 0),
204
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
205
+
D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, RB(0x10c, 4),
206
+
RB(0x10c, 5), RB(0x00, 0), RB(0x00, 0),
207
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
208
+
D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, RB(0x10c, 6),
209
+
RB(0x10c, 7), RB(0x00, 0), RB(0x00, 0),
210
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
211
+
D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, RB(0x104, 4),
212
+
RB(0x104, 5), RB(0x00, 0), RB(0x00, 0),
213
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
214
+
D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, RB(0x104, 6),
215
+
RB(0x104, 7), RB(0x00, 0), RB(0x00, 0),
216
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
217
+
D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, RB(0x114, 0),
218
+
RB(0x114, 1), RB(0x114, 2), RB(0x00, 0),
219
+
RB(0x16c, 0), RB(0x00, 0), RB(0x00, 0)),
220
+
D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, RB(0x114, 3),
221
+
RB(0x114, 4), RB(0x114, 5), RB(0x00, 0),
222
+
RB(0x16c, 1), RB(0x00, 0), RB(0x00, 0)),
223
+
D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, RB(0x114, 6),
224
+
RB(0x114, 7), RB(0x114, 8), RB(0x00, 0),
225
+
RB(0x16c, 2), RB(0x00, 0), RB(0x00, 0)),
226
+
D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, RB(0x114, 9),
227
+
RB(0x114, 10), RB(0x114, 11), RB(0x00, 0),
228
+
RB(0x16c, 3), RB(0x00, 0), RB(0x00, 0)),
229
+
D_MODULE(CLK_PCI_USB, "clk_pci_usb", CLKOUT_D40, RB(0x1c, 6),
230
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
231
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
232
+
D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, RB(0x54, 4),
233
+
RB(0x54, 5), RB(0x00, 0), RB(0x00, 0),
234
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
235
+
D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, RB(0x90, 4),
236
+
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
237
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
238
+
D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, RB(0x68, 0),
239
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
240
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
241
+
D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, RB(0x68, 1),
242
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
243
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
244
+
D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, RB(0x0c, 4),
245
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
246
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
247
+
D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, RB(0xc8, 4),
248
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
249
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
250
+
D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, RB(0x84, 5),
251
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
252
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
253
+
D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, RB(0x10c, 0),
254
+
RB(0x10c, 1), RB(0x00, 0), RB(0x00, 0),
255
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
256
+
D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, RB(0xfc, 0),
257
+
RB(0xfc, 1), RB(0x00, 0), RB(0x00, 0),
258
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
259
+
D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, RB(0xfc, 2),
260
+
RB(0xfc, 3), RB(0x00, 0), RB(0x00, 0),
261
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
262
+
D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, RB(0xfc, 4),
263
+
RB(0xfc, 5), RB(0x00, 0), RB(0x00, 0),
264
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
265
+
D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, RB(0xfc, 6),
266
+
RB(0xfc, 7), RB(0x00, 0), RB(0x00, 0),
267
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
268
+
D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, RB(0x104, 0),
269
+
RB(0x104, 1), RB(0x00, 0), RB(0x00, 0),
270
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
271
+
D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, RB(0x104, 2),
272
+
RB(0x104, 3), RB(0x00, 0), RB(0x00, 0),
273
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
274
+
D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, RB(0x130, 2),
275
+
RB(0x130, 3), RB(0x00, 0), RB(0x00, 0),
276
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
321
277
D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
322
-
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
323
-
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
324
-
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
325
-
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
326
-
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
327
-
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
328
-
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
329
-
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
330
-
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
331
-
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
332
-
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
333
-
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
334
-
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
278
+
D_MODULE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, RB(0x80, 0),
279
+
RB(0x80, 1), RB(0x00, 0), RB(0x80, 2),
280
+
RB(0x00, 0), RB(0x88, 0), RB(0x88, 1)),
281
+
D_MODULE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, RB(0xe8, 0),
282
+
RB(0xe8, 1), RB(0xe8, 2), RB(0x00, 0),
283
+
RB(0x15c, 0), RB(0x00, 0), RB(0x00, 0)),
284
+
D_MODULE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, RB(0x84, 0),
285
+
RB(0x84, 2), RB(0x00, 0), RB(0x84, 1),
286
+
RB(0x00, 0), RB(0x8c, 0), RB(0x8c, 1)),
287
+
D_MODULE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, RB(0x118, 3),
288
+
RB(0x118, 4), RB(0x118, 5), RB(0x00, 0),
289
+
RB(0x168, 1), RB(0x00, 0), RB(0x00, 0)),
290
+
D_MODULE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, RB(0x118, 6),
291
+
RB(0x118, 7), RB(0x118, 8), RB(0x00, 0),
292
+
RB(0x168, 2), RB(0x00, 0), RB(0x00, 0)),
293
+
D_MODULE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, RB(0x118, 9),
294
+
RB(0x118, 10), RB(0x118, 11), RB(0x00, 0),
295
+
RB(0x168, 3), RB(0x00, 0), RB(0x00, 0)),
296
+
D_MODULE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, RB(0xe8, 3),
297
+
RB(0xe8, 4), RB(0xe8, 5), RB(0x00, 0),
298
+
RB(0x15c, 1), RB(0x00, 0), RB(0x00, 0)),
299
+
D_MODULE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, RB(0xe8, 6),
300
+
RB(0xe8, 7), RB(0xe8, 8), RB(0x00, 0),
301
+
RB(0x15c, 2), RB(0x00, 0), RB(0x00, 0)),
302
+
D_MODULE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, RB(0x1c, 3),
303
+
RB(0x00, 0), RB(0x00, 0), RB(0x1c, 4),
304
+
RB(0x00, 0), RB(0x20, 2), RB(0x20, 3)),
305
+
D_MODULE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, RB(0x1c, 0),
306
+
RB(0x1c, 1), RB(0x00, 0), RB(0x1c, 2),
307
+
RB(0x00, 0), RB(0x20, 0), RB(0x20, 1)),
308
+
D_MODULE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, RB(0x1c, 5),
309
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0),
310
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
311
+
D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, RB(0xf0, 12),
312
+
RB(0xf0, 13), RB(0x00, 0), RB(0xf0, 14),
313
+
RB(0x00, 0), RB(0x160, 4), RB(0x160, 5)),
314
+
D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, RB(0xf0, 9),
315
+
RB(0xf0, 10), RB(0xf0, 11), RB(0x00, 0),
316
+
RB(0x160, 3), RB(0x00, 0), RB(0x00, 0)),
335
317
D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
336
318
D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
337
319
D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
···
441
219
D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
442
220
D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
443
221
D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
444
-
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
445
-
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
446
-
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
447
-
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
448
-
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
449
-
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
450
-
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
222
+
D_MODULE(HCLK_CAN0, "hclk_can0", CLK_48, RB(0xf0, 3),
223
+
RB(0xf0, 4), RB(0xf0, 5), RB(0x00, 0),
224
+
RB(0x160, 1), RB(0x00, 0), RB(0x00, 0)),
225
+
D_MODULE(HCLK_CAN1, "hclk_can1", CLK_48, RB(0xf0, 6),
226
+
RB(0xf0, 7), RB(0xf0, 8), RB(0x00, 0),
227
+
RB(0x160, 2), RB(0x00, 0), RB(0x00, 0)),
228
+
D_MODULE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, RB(0x3c, 15),
229
+
RB(0x3c, 16), RB(0x3c, 17), RB(0x00, 0),
230
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
231
+
D_MODULE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, RB(0x3c, 12),
232
+
RB(0x3c, 13), RB(0x3c, 14), RB(0x00, 0),
233
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
234
+
D_MODULE(HCLK_RSV, "hclk_rsv", CLK_48, RB(0xf0, 0),
235
+
RB(0xf0, 1), RB(0xf0, 2), RB(0x00, 0),
236
+
RB(0x160, 0), RB(0x00, 0), RB(0x00, 0)),
237
+
D_MODULE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, RB(0x3c, 0),
238
+
RB(0x3c, 1), RB(0x3c, 2), RB(0x00, 0),
239
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
240
+
D_MODULE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, RB(0x3c, 3),
241
+
RB(0x3c, 4), RB(0x3c, 5), RB(0x00, 0),
242
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
451
243
D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
452
-
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
453
-
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
454
-
D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
455
-
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
456
-
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
457
-
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
458
-
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
459
-
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
460
-
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
461
-
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
462
-
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
463
-
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
464
-
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
465
-
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
466
-
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
467
-
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
468
-
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
469
-
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
470
-
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
471
-
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
472
-
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
473
-
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
474
-
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
475
-
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
476
-
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
477
-
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
478
-
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
479
-
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
480
-
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
481
-
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
482
-
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
483
-
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
484
-
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
485
-
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0xa03, 0, 0xa02, 0, 0, 0),
486
-
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
487
-
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
488
-
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
489
-
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
490
-
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
491
-
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
492
-
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
493
-
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
494
-
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
495
-
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
496
-
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
497
-
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
498
-
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
499
-
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
500
-
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
501
-
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
502
-
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
503
-
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
504
-
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
244
+
D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, RB(0x174, 0),
245
+
RB(0x174, 1), RB(0x00, 0), RB(0x174, 2),
246
+
RB(0x00, 0), RB(0x178, 0), RB(0x178, 1)),
247
+
D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, RB(0x64, 3),
248
+
RB(0x64, 4), RB(0x00, 0), RB(0x00, 0),
249
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
250
+
D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, RB(0x80, 3),
251
+
RB(0x80, 4), RB(0x00, 0), RB(0x00, 0),
252
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
253
+
D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, RB(0x90, 4),
254
+
RB(0x90, 5), RB(0x00, 0), RB(0x00, 0),
255
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
256
+
D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, RB(0x18c, 0),
257
+
RB(0x18c, 1), RB(0x00, 0), RB(0x00, 0),
258
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
259
+
D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, RB(0x84, 4),
260
+
RB(0x84, 3), RB(0x00, 0), RB(0x00, 0),
261
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
262
+
D_MODULE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, RB(0x34, 15),
263
+
RB(0x34, 16), RB(0x34, 17), RB(0x00, 0),
264
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
265
+
D_MODULE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, RB(0x184, 0),
266
+
RB(0x184, 1), RB(0x184, 2), RB(0x00, 0),
267
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
268
+
D_MODULE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, RB(0x24, 3),
269
+
RB(0x24, 4), RB(0x24, 5), RB(0x00, 0),
270
+
RB(0x28, 2), RB(0x00, 0), RB(0x00, 0)),
271
+
D_MODULE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, RB(0x24, 0),
272
+
RB(0x24, 1), RB(0x00, 0), RB(0x24, 2),
273
+
RB(0x00, 0), RB(0x28, 0), RB(0x28, 1)),
274
+
D_MODULE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, RB(0x64, 0),
275
+
RB(0x64, 2), RB(0x00, 0), RB(0x64, 1),
276
+
RB(0x00, 0), RB(0x74, 0), RB(0x74, 1)),
277
+
D_MODULE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, RB(0x4c, 0),
278
+
RB(0x4c, 1), RB(0x4c, 2), RB(0x4c, 3),
279
+
RB(0x58, 0), RB(0x58, 1), RB(0x58, 2)),
280
+
D_MODULE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, RB(0x4c, 4),
281
+
RB(0x4c, 5), RB(0x4c, 6), RB(0x4c, 7),
282
+
RB(0x58, 3), RB(0x58, 4), RB(0x58, 5)),
283
+
D_MODULE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, RB(0x6c, 0),
284
+
RB(0x6c, 1), RB(0x6c, 2), RB(0x6c, 3),
285
+
RB(0x78, 0), RB(0x78, 1), RB(0x78, 2)),
286
+
D_MODULE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, RB(0x70, 0),
287
+
RB(0x70, 1), RB(0x70, 2), RB(0x70, 3),
288
+
RB(0x7c, 0), RB(0x7c, 1), RB(0x7c, 2)),
289
+
D_MODULE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, RB(0x40, 18),
290
+
RB(0x40, 19), RB(0x40, 20), RB(0x00, 0),
291
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
292
+
D_MODULE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, RB(0x40, 21),
293
+
RB(0x40, 22), RB(0x40, 23), RB(0x00, 0),
294
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
295
+
D_MODULE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, RB(0x44, 9),
296
+
RB(0x44, 10), RB(0x44, 11), RB(0x00, 0),
297
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
298
+
D_MODULE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, RB(0x90, 0),
299
+
RB(0x90, 2), RB(0x00, 0), RB(0x90, 1),
300
+
RB(0x00, 0), RB(0x98, 0), RB(0x98, 1)),
301
+
D_MODULE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, RB(0x34, 9),
302
+
RB(0x34, 10), RB(0x34, 11), RB(0x00, 0),
303
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
304
+
D_MODULE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, RB(0x34, 12),
305
+
RB(0x34, 13), RB(0x34, 14), RB(0x00, 0),
306
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
307
+
D_MODULE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, RB(0xf4, 0),
308
+
RB(0xf4, 1), RB(0xf4, 2), RB(0x00, 0),
309
+
RB(0x164, 0), RB(0x00, 0), RB(0x00, 0)),
310
+
D_MODULE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, RB(0x2c, 4),
311
+
RB(0x2c, 5), RB(0x2c, 6), RB(0x00, 0),
312
+
RB(0x30, 3), RB(0x00, 0), RB(0x00, 0)),
313
+
D_MODULE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, RB(0x2c, 0),
314
+
RB(0x2c, 1), RB(0x2c, 2), RB(0x2c, 3),
315
+
RB(0x30, 0), RB(0x30, 1), RB(0x30, 2)),
316
+
D_MODULE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, RB(0x50, 0),
317
+
RB(0x50, 1), RB(0x50, 2), RB(0x50, 3),
318
+
RB(0x5c, 0), RB(0x5c, 1), RB(0x5c, 2)),
319
+
D_MODULE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, RB(0xf4, 12),
320
+
RB(0xf4, 13), RB(0x00, 0), RB(0xf4, 14),
321
+
RB(0x00, 0), RB(0x164, 4), RB(0x164, 5)),
322
+
D_MODULE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, RB(0x44, 12),
323
+
RB(0x44, 13), RB(0x44, 14), RB(0x00, 0),
324
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
325
+
D_MODULE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, RB(0x44, 15),
326
+
RB(0x44, 16), RB(0x44, 17), RB(0x00, 0),
327
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
328
+
D_MODULE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, RB(0xf4, 6),
329
+
RB(0xf4, 7), RB(0xf4, 8), RB(0x00, 0),
330
+
RB(0x164, 2), RB(0x00, 0), RB(0x00, 0)),
331
+
D_MODULE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, RB(0xf4, 9),
332
+
RB(0xf4, 10), RB(0xf4, 11), RB(0x00, 0),
333
+
RB(0x164, 3), RB(0x00, 0), RB(0x00, 0)),
334
+
D_MODULE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, RB(0x54, 0),
335
+
RB(0x54, 1), RB(0x54, 2), RB(0x54, 3),
336
+
RB(0x60, 0), RB(0x60, 1), RB(0x60, 2)),
337
+
D_MODULE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, RB(0x90, 0),
338
+
RB(0x90, 1), RB(0x90, 2), RB(0x90, 3),
339
+
RB(0x98, 0), RB(0x98, 1), RB(0x98, 2)),
340
+
D_MODULE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, RB(0x154, 0),
341
+
RB(0x154, 1), RB(0x154, 2), RB(0x00, 0),
342
+
RB(0x170, 0), RB(0x00, 0), RB(0x00, 0)),
343
+
D_MODULE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, RB(0x140, 0),
344
+
RB(0x140, 3), RB(0x00, 0), RB(0x140, 2),
345
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
346
+
D_MODULE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, RB(0x0c, 0),
347
+
RB(0x0c, 1), RB(0x0c, 2), RB(0x0c, 3),
348
+
RB(0x10, 0), RB(0x10, 1), RB(0x10, 2)),
349
+
D_MODULE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, RB(0xc8, 0),
350
+
RB(0xc8, 1), RB(0xc8, 2), RB(0xc8, 3),
351
+
RB(0xcc, 0), RB(0xcc, 1), RB(0xcc, 2)),
352
+
D_MODULE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, RB(0xf4, 3),
353
+
RB(0xf4, 4), RB(0xf4, 5), RB(0x00, 0),
354
+
RB(0x164, 1), RB(0x00, 0), RB(0x00, 0)),
355
+
D_MODULE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, RB(0x40, 0),
356
+
RB(0x40, 1), RB(0x40, 2), RB(0x00, 0),
357
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
358
+
D_MODULE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, RB(0x40, 3),
359
+
RB(0x40, 4), RB(0x40, 5), RB(0x00, 0),
360
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
361
+
D_MODULE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, RB(0x40, 6),
362
+
RB(0x40, 7), RB(0x40, 8), RB(0x00, 0),
363
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
364
+
D_MODULE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, RB(0x40, 9),
365
+
RB(0x40, 10), RB(0x40, 11), RB(0x00, 0),
366
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
367
+
D_MODULE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, RB(0x40, 12),
368
+
RB(0x40, 13), RB(0x40, 14), RB(0x00, 0),
369
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
370
+
D_MODULE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, RB(0x40, 15),
371
+
RB(0x40, 16), RB(0x40, 17), RB(0x00, 0),
372
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
373
+
D_MODULE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, RB(0x130, 0),
374
+
RB(0x00, 0), RB(0x130, 1), RB(0x00, 0),
375
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
376
+
D_MODULE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, RB(0x188, 0),
377
+
RB(0x188, 1), RB(0x188, 2), RB(0x00, 0),
378
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
379
+
D_MODULE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, RB(0x34, 0),
380
+
RB(0x34, 1), RB(0x34, 2), RB(0x00, 0),
381
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
382
+
D_MODULE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, RB(0x34, 3),
383
+
RB(0x34, 4), RB(0x34, 5), RB(0x00, 0),
384
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
385
+
D_MODULE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, RB(0x34, 6),
386
+
RB(0x34, 7), RB(0x34, 8), RB(0x00, 0),
387
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
388
+
D_MODULE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, RB(0x40, 24),
389
+
RB(0x40, 25), RB(0x40, 26), RB(0x00, 0),
390
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
391
+
D_MODULE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, RB(0x40, 27),
392
+
RB(0x40, 28), RB(0x40, 29), RB(0x00, 0),
393
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
394
+
D_MODULE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, RB(0x44, 0),
395
+
RB(0x44, 1), RB(0x44, 2), RB(0x00, 0),
396
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
397
+
D_MODULE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, RB(0x44, 3),
398
+
RB(0x44, 4), RB(0x44, 5), RB(0x00, 0),
399
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
400
+
D_MODULE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, RB(0x44, 6),
401
+
RB(0x44, 7), RB(0x44, 8), RB(0x00, 0),
402
+
RB(0x00, 0), RB(0x00, 0), RB(0x00, 0)),
505
403
/*
506
404
* These are not hardware clocks, but are needed to handle the special
507
405
* case where we have a 'selector bit' that doesn't just change the
···
633
291
.type = K_BITSEL,
634
292
.source = 1 + R9A06G032_DIV_UART,
635
293
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG0_0 */
636
-
.dual.sel = ((0x34 / 4) << 5) | 30,
294
+
.dual.sel = RB(0x34, 30),
637
295
.dual.group = 0,
638
296
},
639
297
{
···
642
300
.type = K_BITSEL,
643
301
.source = 1 + R9A06G032_DIV_P2_PG,
644
302
/* R9A06G032_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
645
-
.dual.sel = ((0xec / 4) << 5) | 24,
303
+
.dual.sel = RB(0xec, 24),
646
304
.dual.group = 1,
647
305
},
648
-
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
649
-
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
650
-
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
651
-
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0x760, 0x761, 0x762, 0x763),
652
-
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 0x764, 0x765, 0x766, 0x767),
653
-
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 0x768, 0x769, 0x76a, 0x76b),
654
-
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 0x76c, 0x76d, 0x76e, 0x76f),
655
-
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 0x770, 0x771, 0x772, 0x773),
306
+
D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0,
307
+
RB(0x34, 18), RB(0x34, 19), RB(0x34, 20), RB(0x34, 21)),
308
+
D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0,
309
+
RB(0x34, 22), RB(0x34, 23), RB(0x34, 24), RB(0x34, 25)),
310
+
D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0,
311
+
RB(0x34, 26), RB(0x34, 27), RB(0x34, 28), RB(0x34, 29)),
312
+
D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1,
313
+
RB(0xec, 0), RB(0xec, 1), RB(0xec, 2), RB(0xec, 3)),
314
+
D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1,
315
+
RB(0xec, 4), RB(0xec, 5), RB(0xec, 6), RB(0xec, 7)),
316
+
D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1,
317
+
RB(0xec, 8), RB(0xec, 9), RB(0xec, 10), RB(0xec, 11)),
318
+
D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1,
319
+
RB(0xec, 12), RB(0xec, 13), RB(0xec, 14), RB(0xec, 15)),
320
+
D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1,
321
+
RB(0xec, 16), RB(0xec, 17), RB(0xec, 18), RB(0xec, 19)),
656
322
};
657
323
658
324
struct r9a06g032_priv {
···
693
343
}
694
344
EXPORT_SYMBOL_GPL(r9a06g032_sysctrl_set_dmamux);
695
345
696
-
/* register/bit pairs are encoded as an uint16_t */
697
-
static void
698
-
clk_rdesc_set(struct r9a06g032_priv *clocks,
699
-
u16 one, unsigned int on)
346
+
static void clk_rdesc_set(struct r9a06g032_priv *clocks,
347
+
struct regbit rb, unsigned int on)
700
348
{
701
-
u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
702
-
u32 val = readl(reg);
349
+
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
350
+
u32 val;
703
351
704
-
val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
352
+
if (!rb.reg && !rb.bit)
353
+
return;
354
+
355
+
val = readl(reg);
356
+
val = (val & ~BIT(rb.bit)) | ((!!on) << rb.bit);
705
357
writel(val, reg);
706
358
}
707
359
708
-
static int
709
-
clk_rdesc_get(struct r9a06g032_priv *clocks,
710
-
uint16_t one)
360
+
static int clk_rdesc_get(struct r9a06g032_priv *clocks, struct regbit rb)
711
361
{
712
-
u32 __iomem *reg = clocks->reg + (4 * (one >> 5));
362
+
u32 __iomem *reg = clocks->reg + (rb.reg * 4);
713
363
u32 val = readl(reg);
714
364
715
-
return !!(val & (1U << (one & 0x1f)));
365
+
return !!(val & BIT(rb.bit));
716
366
}
717
367
718
368
/*
···
814
464
{
815
465
unsigned long flags;
816
466
817
-
WARN_ON(!g->gate);
467
+
WARN_ON(!g->gate.reg && !g->gate.bit);
818
468
819
469
spin_lock_irqsave(&clocks->lock, flags);
820
470
clk_rdesc_set(clocks, g->gate, on);
821
471
/* De-assert reset */
822
-
if (g->reset)
823
-
clk_rdesc_set(clocks, g->reset, 1);
472
+
clk_rdesc_set(clocks, g->reset, 1);
824
473
spin_unlock_irqrestore(&clocks->lock, flags);
825
474
826
475
/* Hardware manual recommends 5us delay after enabling clock & reset */
···
829
480
* associated SLVRDY bit in the System Controller that needs to be set
830
481
* so that the FlexWAY bus fabric passes on the read/write requests.
831
482
*/
832
-
if (g->ready || g->midle) {
833
-
spin_lock_irqsave(&clocks->lock, flags);
834
-
if (g->ready)
835
-
clk_rdesc_set(clocks, g->ready, on);
836
-
/* Clear 'Master Idle Request' bit */
837
-
if (g->midle)
838
-
clk_rdesc_set(clocks, g->midle, !on);
839
-
spin_unlock_irqrestore(&clocks->lock, flags);
840
-
}
483
+
spin_lock_irqsave(&clocks->lock, flags);
484
+
clk_rdesc_set(clocks, g->ready, on);
485
+
/* Clear 'Master Idle Request' bit */
486
+
clk_rdesc_set(clocks, g->midle, !on);
487
+
spin_unlock_irqrestore(&clocks->lock, flags);
488
+
841
489
/* Note: We don't wait for FlexWAY Socket Connection signal */
842
490
}
843
491
···
858
512
struct r9a06g032_clk_gate *g = to_r9a06g032_gate(hw);
859
513
860
514
/* if clock is in reset, the gate might be on, and still not 'be' on */
861
-
if (g->gate.reset && !clk_rdesc_get(g->clocks, g->gate.reset))
515
+
if (g->gate.reset.reg && !clk_rdesc_get(g->clocks, g->gate.reset))
862
516
return 0;
863
517
864
518
return clk_rdesc_get(g->clocks, g->gate.gate);
···
1097
751
struct clk_hw hw;
1098
752
struct r9a06g032_priv *clocks;
1099
753
u16 index;
1100
-
u16 selector; /* selector register + bit */
754
+
struct regbit selector; /* selector register + bit */
1101
755
};
1102
756
1103
757
#define to_clk_bitselect(_hw) \
···
1166
820
struct clk_hw hw;
1167
821
struct r9a06g032_priv *clocks;
1168
822
u16 index;
1169
-
u16 selector; /* selector register + bit */
823
+
struct regbit selector; /* selector register + bit */
1170
824
struct r9a06g032_gate gate[2];
1171
825
};
1172
826
···
1219
873
r9a06g032_register_dualgate(struct r9a06g032_priv *clocks,
1220
874
const char *parent_name,
1221
875
const struct r9a06g032_clkdesc *desc,
1222
-
uint16_t sel)
876
+
struct regbit sel)
1223
877
{
1224
878
struct r9a06g032_clk_dualgate *g;
1225
879
struct clk *clk;
···
1297
951
struct clk **clks;
1298
952
struct clk *mclk;
1299
953
unsigned int i;
1300
-
u16 uart_group_sel[2];
954
+
struct regbit uart_group_sel[2];
1301
955
int error;
1302
956
1303
957
clocks = devm_kzalloc(dev, sizeof(*clocks), GFP_KERNEL);
+2
-4
drivers/clk/renesas/rcar-usb2-clock-sel.c
+2
-4
drivers/clk/renesas/rcar-usb2-clock-sel.c
···
125
125
return 0;
126
126
}
127
127
128
-
static int rcar_usb2_clock_sel_remove(struct platform_device *pdev)
128
+
static void rcar_usb2_clock_sel_remove(struct platform_device *pdev)
129
129
{
130
130
struct device *dev = &pdev->dev;
131
131
132
132
of_clk_del_provider(dev->of_node);
133
133
pm_runtime_put(dev);
134
134
pm_runtime_disable(dev);
135
-
136
-
return 0;
137
135
}
138
136
139
137
static int rcar_usb2_clock_sel_probe(struct platform_device *pdev)
···
213
215
.pm = &rcar_usb2_clock_sel_pm_ops,
214
216
},
215
217
.probe = rcar_usb2_clock_sel_probe,
216
-
.remove = rcar_usb2_clock_sel_remove,
218
+
.remove_new = rcar_usb2_clock_sel_remove,
217
219
};
218
220
builtin_platform_driver(rcar_usb2_clock_sel_driver);
219
221
+4
-4
drivers/clk/renesas/renesas-cpg-mssr.c
+4
-4
drivers/clk/renesas/renesas-cpg-mssr.c
···
61
61
0x2E00, 0x2E04, 0x2E08, 0x2E0C, 0x2E10, 0x2E14, 0x2E18, 0x2E1C,
62
62
0x2E20, 0x2E24, 0x2E28, 0x2E2C, 0x2E30, 0x2E34, 0x2E38, 0x2E3C,
63
63
0x2E40, 0x2E44, 0x2E48, 0x2E4C, 0x2E50, 0x2E54, 0x2E58, 0x2E5C,
64
-
0x2E60, 0x2E64, 0x2E68, 0x2E6C,
64
+
0x2E60, 0x2E64, 0x2E68, 0x2E6C, 0x2E70, 0x2E74,
65
65
};
66
66
67
67
/*
···
77
77
0x2D00, 0x2D04, 0x2D08, 0x2D0C, 0x2D10, 0x2D14, 0x2D18, 0x2D1C,
78
78
0x2D20, 0x2D24, 0x2D28, 0x2D2C, 0x2D30, 0x2D34, 0x2D38, 0x2D3C,
79
79
0x2D40, 0x2D44, 0x2D48, 0x2D4C, 0x2D50, 0x2D54, 0x2D58, 0x2D5C,
80
-
0x2D60, 0x2D64, 0x2D68, 0x2D6C,
80
+
0x2D60, 0x2D64, 0x2D68, 0x2D6C, 0x2D70, 0x2D74,
81
81
};
82
82
83
83
/*
···
103
103
0x2C00, 0x2C04, 0x2C08, 0x2C0C, 0x2C10, 0x2C14, 0x2C18, 0x2C1C,
104
104
0x2C20, 0x2C24, 0x2C28, 0x2C2C, 0x2C30, 0x2C34, 0x2C38, 0x2C3C,
105
105
0x2C40, 0x2C44, 0x2C48, 0x2C4C, 0x2C50, 0x2C54, 0x2C58, 0x2C5C,
106
-
0x2C60, 0x2C64, 0x2C68, 0x2C6C,
106
+
0x2C60, 0x2C64, 0x2C68, 0x2C6C, 0x2C70, 0x2C74,
107
107
};
108
108
109
109
/*
···
119
119
0x2C80, 0x2C84, 0x2C88, 0x2C8C, 0x2C90, 0x2C94, 0x2C98, 0x2C9C,
120
120
0x2CA0, 0x2CA4, 0x2CA8, 0x2CAC, 0x2CB0, 0x2CB4, 0x2CB8, 0x2CBC,
121
121
0x2CC0, 0x2CC4, 0x2CC8, 0x2CCC, 0x2CD0, 0x2CD4, 0x2CD8, 0x2CDC,
122
-
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC,
122
+
0x2CE0, 0x2CE4, 0x2CE8, 0x2CEC, 0x2CF0, 0x2CF4,
123
123
};
124
124
125
125
/**