tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
gpu: host1x: Add Tegra124 support
Tegra124 has 192 syncpoints whereas its predecessors had 32 syncpoints.
This required changes to the hardware register layout.
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
+768
-1
+2
-1
drivers/gpu/host1x/Makefile
+2
-1
drivers/gpu/host1x/Makefile
+11
drivers/gpu/host1x/dev.c
+11
drivers/gpu/host1x/dev.c
···
34
34
#include "debug.h"
35
35
#include "hw/host1x01.h"
36
36
#include "hw/host1x02.h"
37
+
#include "hw/host1x04.h"
37
38
38
39
void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)
39
40
{
···
78
77
.sync_offset = 0x3000,
79
78
};
80
79
80
+
static const struct host1x_info host1x04_info = {
81
+
.nb_channels = 12,
82
+
.nb_pts = 192,
83
+
.nb_mlocks = 16,
84
+
.nb_bases = 64,
85
+
.init = host1x04_init,
86
+
.sync_offset = 0x2100,
87
+
};
88
+
81
89
static struct of_device_id host1x_of_match[] = {
90
+
{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
82
91
{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
83
92
{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
84
93
{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
+42
drivers/gpu/host1x/hw/host1x04.c
+42
drivers/gpu/host1x/hw/host1x04.c
···
1
+
/*
2
+
* Host1x init for Tegra124 SoCs
3
+
*
4
+
* Copyright (c) 2013 NVIDIA Corporation.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
/* include hw specification */
20
+
#include "host1x04.h"
21
+
#include "host1x04_hardware.h"
22
+
23
+
/* include code */
24
+
#include "cdma_hw.c"
25
+
#include "channel_hw.c"
26
+
#include "debug_hw.c"
27
+
#include "intr_hw.c"
28
+
#include "syncpt_hw.c"
29
+
30
+
#include "../dev.h"
31
+
32
+
int host1x04_init(struct host1x *host)
33
+
{
34
+
host->channel_op = &host1x_channel_ops;
35
+
host->cdma_op = &host1x_cdma_ops;
36
+
host->cdma_pb_op = &host1x_pushbuffer_ops;
37
+
host->syncpt_op = &host1x_syncpt_ops;
38
+
host->intr_op = &host1x_intr_ops;
39
+
host->debug_op = &host1x_debug_ops;
40
+
41
+
return 0;
42
+
}
+26
drivers/gpu/host1x/hw/host1x04.h
+26
drivers/gpu/host1x/hw/host1x04.h
···
1
+
/*
2
+
* Host1x init for Tegra124 SoCs
3
+
*
4
+
* Copyright (c) 2013 NVIDIA Corporation.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
#ifndef HOST1X_HOST1X04_H
20
+
#define HOST1X_HOST1X04_H
21
+
22
+
struct host1x;
23
+
24
+
int host1x04_init(struct host1x *host);
25
+
26
+
#endif
+142
drivers/gpu/host1x/hw/host1x04_hardware.h
+142
drivers/gpu/host1x/hw/host1x04_hardware.h
···
1
+
/*
2
+
* Tegra host1x Register Offsets for Tegra124
3
+
*
4
+
* Copyright (c) 2010-2013 NVIDIA Corporation.
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify it
7
+
* under the terms and conditions of the GNU General Public License,
8
+
* version 2, as published by the Free Software Foundation.
9
+
*
10
+
* This program is distributed in the hope it will be useful, but WITHOUT
11
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13
+
* more details.
14
+
*
15
+
* You should have received a copy of the GNU General Public License
16
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
17
+
*/
18
+
19
+
#ifndef __HOST1X_HOST1X04_HARDWARE_H
20
+
#define __HOST1X_HOST1X04_HARDWARE_H
21
+
22
+
#include <linux/types.h>
23
+
#include <linux/bitops.h>
24
+
25
+
#include "hw_host1x04_channel.h"
26
+
#include "hw_host1x04_sync.h"
27
+
#include "hw_host1x04_uclass.h"
28
+
29
+
static inline u32 host1x_class_host_wait_syncpt(
30
+
unsigned indx, unsigned threshold)
31
+
{
32
+
return host1x_uclass_wait_syncpt_indx_f(indx)
33
+
| host1x_uclass_wait_syncpt_thresh_f(threshold);
34
+
}
35
+
36
+
static inline u32 host1x_class_host_load_syncpt_base(
37
+
unsigned indx, unsigned threshold)
38
+
{
39
+
return host1x_uclass_load_syncpt_base_base_indx_f(indx)
40
+
| host1x_uclass_load_syncpt_base_value_f(threshold);
41
+
}
42
+
43
+
static inline u32 host1x_class_host_wait_syncpt_base(
44
+
unsigned indx, unsigned base_indx, unsigned offset)
45
+
{
46
+
return host1x_uclass_wait_syncpt_base_indx_f(indx)
47
+
| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
48
+
| host1x_uclass_wait_syncpt_base_offset_f(offset);
49
+
}
50
+
51
+
static inline u32 host1x_class_host_incr_syncpt_base(
52
+
unsigned base_indx, unsigned offset)
53
+
{
54
+
return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
55
+
| host1x_uclass_incr_syncpt_base_offset_f(offset);
56
+
}
57
+
58
+
static inline u32 host1x_class_host_incr_syncpt(
59
+
unsigned cond, unsigned indx)
60
+
{
61
+
return host1x_uclass_incr_syncpt_cond_f(cond)
62
+
| host1x_uclass_incr_syncpt_indx_f(indx);
63
+
}
64
+
65
+
static inline u32 host1x_class_host_indoff_reg_write(
66
+
unsigned mod_id, unsigned offset, bool auto_inc)
67
+
{
68
+
u32 v = host1x_uclass_indoff_indbe_f(0xf)
69
+
| host1x_uclass_indoff_indmodid_f(mod_id)
70
+
| host1x_uclass_indoff_indroffset_f(offset);
71
+
if (auto_inc)
72
+
v |= host1x_uclass_indoff_autoinc_f(1);
73
+
return v;
74
+
}
75
+
76
+
static inline u32 host1x_class_host_indoff_reg_read(
77
+
unsigned mod_id, unsigned offset, bool auto_inc)
78
+
{
79
+
u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
80
+
| host1x_uclass_indoff_indroffset_f(offset)
81
+
| host1x_uclass_indoff_rwn_read_v();
82
+
if (auto_inc)
83
+
v |= host1x_uclass_indoff_autoinc_f(1);
84
+
return v;
85
+
}
86
+
87
+
/* cdma opcodes */
88
+
static inline u32 host1x_opcode_setclass(
89
+
unsigned class_id, unsigned offset, unsigned mask)
90
+
{
91
+
return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
92
+
}
93
+
94
+
static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
95
+
{
96
+
return (1 << 28) | (offset << 16) | count;
97
+
}
98
+
99
+
static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
100
+
{
101
+
return (2 << 28) | (offset << 16) | count;
102
+
}
103
+
104
+
static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
105
+
{
106
+
return (3 << 28) | (offset << 16) | mask;
107
+
}
108
+
109
+
static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
110
+
{
111
+
return (4 << 28) | (offset << 16) | value;
112
+
}
113
+
114
+
static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
115
+
{
116
+
return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
117
+
host1x_class_host_incr_syncpt(cond, indx));
118
+
}
119
+
120
+
static inline u32 host1x_opcode_restart(unsigned address)
121
+
{
122
+
return (5 << 28) | (address >> 4);
123
+
}
124
+
125
+
static inline u32 host1x_opcode_gather(unsigned count)
126
+
{
127
+
return (6 << 28) | count;
128
+
}
129
+
130
+
static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
131
+
{
132
+
return (6 << 28) | (offset << 16) | BIT(15) | count;
133
+
}
134
+
135
+
static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
136
+
{
137
+
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
138
+
}
139
+
140
+
#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
141
+
142
+
#endif
+121
drivers/gpu/host1x/hw/hw_host1x04_channel.h
+121
drivers/gpu/host1x/hw/hw_host1x04_channel.h
···
1
+
/*
2
+
* Copyright (c) 2013 NVIDIA Corporation.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify it
5
+
* under the terms and conditions of the GNU General Public License,
6
+
* version 2, as published by the Free Software Foundation.
7
+
*
8
+
* This program is distributed in the hope it will be useful, but WITHOUT
9
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
+
* more details.
12
+
*
13
+
* You should have received a copy of the GNU General Public License
14
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
15
+
*
16
+
*/
17
+
18
+
/*
19
+
* Function naming determines intended use:
20
+
*
21
+
* <x>_r(void) : Returns the offset for register <x>.
22
+
*
23
+
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24
+
*
25
+
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26
+
*
27
+
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28
+
* and masked to place it at field <y> of register <x>. This value
29
+
* can be |'d with others to produce a full register value for
30
+
* register <x>.
31
+
*
32
+
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33
+
* value can be ~'d and then &'d to clear the value of field <y> for
34
+
* register <x>.
35
+
*
36
+
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37
+
* to place it at field <y> of register <x>. This value can be |'d
38
+
* with others to produce a full register value for <x>.
39
+
*
40
+
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41
+
* <x> value 'r' after being shifted to place its LSB at bit 0.
42
+
* This value is suitable for direct comparison with other unshifted
43
+
* values appropriate for use in field <y> of register <x>.
44
+
*
45
+
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46
+
* field <y> of register <x>. This value is suitable for direct
47
+
* comparison with unshifted values appropriate for use in field <y>
48
+
* of register <x>.
49
+
*/
50
+
51
+
#ifndef HOST1X_HW_HOST1X04_CHANNEL_H
52
+
#define HOST1X_HW_HOST1X04_CHANNEL_H
53
+
54
+
static inline u32 host1x_channel_fifostat_r(void)
55
+
{
56
+
return 0x0;
57
+
}
58
+
#define HOST1X_CHANNEL_FIFOSTAT \
59
+
host1x_channel_fifostat_r()
60
+
static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
61
+
{
62
+
return (r >> 11) & 0x1;
63
+
}
64
+
#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \
65
+
host1x_channel_fifostat_cfempty_v(r)
66
+
static inline u32 host1x_channel_dmastart_r(void)
67
+
{
68
+
return 0x14;
69
+
}
70
+
#define HOST1X_CHANNEL_DMASTART \
71
+
host1x_channel_dmastart_r()
72
+
static inline u32 host1x_channel_dmaput_r(void)
73
+
{
74
+
return 0x18;
75
+
}
76
+
#define HOST1X_CHANNEL_DMAPUT \
77
+
host1x_channel_dmaput_r()
78
+
static inline u32 host1x_channel_dmaget_r(void)
79
+
{
80
+
return 0x1c;
81
+
}
82
+
#define HOST1X_CHANNEL_DMAGET \
83
+
host1x_channel_dmaget_r()
84
+
static inline u32 host1x_channel_dmaend_r(void)
85
+
{
86
+
return 0x20;
87
+
}
88
+
#define HOST1X_CHANNEL_DMAEND \
89
+
host1x_channel_dmaend_r()
90
+
static inline u32 host1x_channel_dmactrl_r(void)
91
+
{
92
+
return 0x24;
93
+
}
94
+
#define HOST1X_CHANNEL_DMACTRL \
95
+
host1x_channel_dmactrl_r()
96
+
static inline u32 host1x_channel_dmactrl_dmastop(void)
97
+
{
98
+
return 1 << 0;
99
+
}
100
+
#define HOST1X_CHANNEL_DMACTRL_DMASTOP \
101
+
host1x_channel_dmactrl_dmastop()
102
+
static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
103
+
{
104
+
return (r >> 0) & 0x1;
105
+
}
106
+
#define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \
107
+
host1x_channel_dmactrl_dmastop_v(r)
108
+
static inline u32 host1x_channel_dmactrl_dmagetrst(void)
109
+
{
110
+
return 1 << 1;
111
+
}
112
+
#define HOST1X_CHANNEL_DMACTRL_DMAGETRST \
113
+
host1x_channel_dmactrl_dmagetrst()
114
+
static inline u32 host1x_channel_dmactrl_dmainitget(void)
115
+
{
116
+
return 1 << 2;
117
+
}
118
+
#define HOST1X_CHANNEL_DMACTRL_DMAINITGET \
119
+
host1x_channel_dmactrl_dmainitget()
120
+
121
+
#endif
+243
drivers/gpu/host1x/hw/hw_host1x04_sync.h
+243
drivers/gpu/host1x/hw/hw_host1x04_sync.h
···
1
+
/*
2
+
* Copyright (c) 2013 NVIDIA Corporation.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify it
5
+
* under the terms and conditions of the GNU General Public License,
6
+
* version 2, as published by the Free Software Foundation.
7
+
*
8
+
* This program is distributed in the hope it will be useful, but WITHOUT
9
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
+
* more details.
12
+
*
13
+
* You should have received a copy of the GNU General Public License
14
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
15
+
*
16
+
*/
17
+
18
+
/*
19
+
* Function naming determines intended use:
20
+
*
21
+
* <x>_r(void) : Returns the offset for register <x>.
22
+
*
23
+
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24
+
*
25
+
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26
+
*
27
+
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28
+
* and masked to place it at field <y> of register <x>. This value
29
+
* can be |'d with others to produce a full register value for
30
+
* register <x>.
31
+
*
32
+
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33
+
* value can be ~'d and then &'d to clear the value of field <y> for
34
+
* register <x>.
35
+
*
36
+
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37
+
* to place it at field <y> of register <x>. This value can be |'d
38
+
* with others to produce a full register value for <x>.
39
+
*
40
+
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41
+
* <x> value 'r' after being shifted to place its LSB at bit 0.
42
+
* This value is suitable for direct comparison with other unshifted
43
+
* values appropriate for use in field <y> of register <x>.
44
+
*
45
+
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46
+
* field <y> of register <x>. This value is suitable for direct
47
+
* comparison with unshifted values appropriate for use in field <y>
48
+
* of register <x>.
49
+
*/
50
+
51
+
#ifndef HOST1X_HW_HOST1X04_SYNC_H
52
+
#define HOST1X_HW_HOST1X04_SYNC_H
53
+
54
+
#define REGISTER_STRIDE 4
55
+
56
+
static inline u32 host1x_sync_syncpt_r(unsigned int id)
57
+
{
58
+
return 0xf80 + id * REGISTER_STRIDE;
59
+
}
60
+
#define HOST1X_SYNC_SYNCPT(id) \
61
+
host1x_sync_syncpt_r(id)
62
+
static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
63
+
{
64
+
return 0xe80 + id * REGISTER_STRIDE;
65
+
}
66
+
#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
67
+
host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
68
+
static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
69
+
{
70
+
return 0xf00 + id * REGISTER_STRIDE;
71
+
}
72
+
#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
73
+
host1x_sync_syncpt_thresh_int_disable_r(id)
74
+
static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
75
+
{
76
+
return 0xf20 + id * REGISTER_STRIDE;
77
+
}
78
+
#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
79
+
host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
80
+
static inline u32 host1x_sync_cf_setup_r(unsigned int channel)
81
+
{
82
+
return 0xc00 + channel * REGISTER_STRIDE;
83
+
}
84
+
#define HOST1X_SYNC_CF_SETUP(channel) \
85
+
host1x_sync_cf_setup_r(channel)
86
+
static inline u32 host1x_sync_cf_setup_base_v(u32 r)
87
+
{
88
+
return (r >> 0) & 0x3ff;
89
+
}
90
+
#define HOST1X_SYNC_CF_SETUP_BASE_V(r) \
91
+
host1x_sync_cf_setup_base_v(r)
92
+
static inline u32 host1x_sync_cf_setup_limit_v(u32 r)
93
+
{
94
+
return (r >> 16) & 0x3ff;
95
+
}
96
+
#define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \
97
+
host1x_sync_cf_setup_limit_v(r)
98
+
static inline u32 host1x_sync_cmdproc_stop_r(void)
99
+
{
100
+
return 0xac;
101
+
}
102
+
#define HOST1X_SYNC_CMDPROC_STOP \
103
+
host1x_sync_cmdproc_stop_r()
104
+
static inline u32 host1x_sync_ch_teardown_r(void)
105
+
{
106
+
return 0xb0;
107
+
}
108
+
#define HOST1X_SYNC_CH_TEARDOWN \
109
+
host1x_sync_ch_teardown_r()
110
+
static inline u32 host1x_sync_usec_clk_r(void)
111
+
{
112
+
return 0x1a4;
113
+
}
114
+
#define HOST1X_SYNC_USEC_CLK \
115
+
host1x_sync_usec_clk_r()
116
+
static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
117
+
{
118
+
return 0x1a8;
119
+
}
120
+
#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
121
+
host1x_sync_ctxsw_timeout_cfg_r()
122
+
static inline u32 host1x_sync_ip_busy_timeout_r(void)
123
+
{
124
+
return 0x1bc;
125
+
}
126
+
#define HOST1X_SYNC_IP_BUSY_TIMEOUT \
127
+
host1x_sync_ip_busy_timeout_r()
128
+
static inline u32 host1x_sync_mlock_owner_r(unsigned int id)
129
+
{
130
+
return 0x340 + id * REGISTER_STRIDE;
131
+
}
132
+
#define HOST1X_SYNC_MLOCK_OWNER(id) \
133
+
host1x_sync_mlock_owner_r(id)
134
+
static inline u32 host1x_sync_mlock_owner_chid_f(u32 v)
135
+
{
136
+
return (v & 0xf) << 8;
137
+
}
138
+
#define HOST1X_SYNC_MLOCK_OWNER_CHID_F(v) \
139
+
host1x_sync_mlock_owner_chid_f(v)
140
+
static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r)
141
+
{
142
+
return (r >> 1) & 0x1;
143
+
}
144
+
#define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \
145
+
host1x_sync_mlock_owner_cpu_owns_v(r)
146
+
static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r)
147
+
{
148
+
return (r >> 0) & 0x1;
149
+
}
150
+
#define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \
151
+
host1x_sync_mlock_owner_ch_owns_v(r)
152
+
static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
153
+
{
154
+
return 0x1380 + id * REGISTER_STRIDE;
155
+
}
156
+
#define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
157
+
host1x_sync_syncpt_int_thresh_r(id)
158
+
static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
159
+
{
160
+
return 0x600 + id * REGISTER_STRIDE;
161
+
}
162
+
#define HOST1X_SYNC_SYNCPT_BASE(id) \
163
+
host1x_sync_syncpt_base_r(id)
164
+
static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
165
+
{
166
+
return 0xf60 + id * REGISTER_STRIDE;
167
+
}
168
+
#define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
169
+
host1x_sync_syncpt_cpu_incr_r(id)
170
+
static inline u32 host1x_sync_cbread_r(unsigned int channel)
171
+
{
172
+
return 0xc80 + channel * REGISTER_STRIDE;
173
+
}
174
+
#define HOST1X_SYNC_CBREAD(channel) \
175
+
host1x_sync_cbread_r(channel)
176
+
static inline u32 host1x_sync_cfpeek_ctrl_r(void)
177
+
{
178
+
return 0x74c;
179
+
}
180
+
#define HOST1X_SYNC_CFPEEK_CTRL \
181
+
host1x_sync_cfpeek_ctrl_r()
182
+
static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
183
+
{
184
+
return (v & 0x3ff) << 0;
185
+
}
186
+
#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
187
+
host1x_sync_cfpeek_ctrl_addr_f(v)
188
+
static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
189
+
{
190
+
return (v & 0xf) << 16;
191
+
}
192
+
#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
193
+
host1x_sync_cfpeek_ctrl_channr_f(v)
194
+
static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
195
+
{
196
+
return (v & 0x1) << 31;
197
+
}
198
+
#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
199
+
host1x_sync_cfpeek_ctrl_ena_f(v)
200
+
static inline u32 host1x_sync_cfpeek_read_r(void)
201
+
{
202
+
return 0x750;
203
+
}
204
+
#define HOST1X_SYNC_CFPEEK_READ \
205
+
host1x_sync_cfpeek_read_r()
206
+
static inline u32 host1x_sync_cfpeek_ptrs_r(void)
207
+
{
208
+
return 0x754;
209
+
}
210
+
#define HOST1X_SYNC_CFPEEK_PTRS \
211
+
host1x_sync_cfpeek_ptrs_r()
212
+
static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
213
+
{
214
+
return (r >> 0) & 0x3ff;
215
+
}
216
+
#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \
217
+
host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r)
218
+
static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
219
+
{
220
+
return (r >> 16) & 0x3ff;
221
+
}
222
+
#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \
223
+
host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r)
224
+
static inline u32 host1x_sync_cbstat_r(unsigned int channel)
225
+
{
226
+
return 0xcc0 + channel * REGISTER_STRIDE;
227
+
}
228
+
#define HOST1X_SYNC_CBSTAT(channel) \
229
+
host1x_sync_cbstat_r(channel)
230
+
static inline u32 host1x_sync_cbstat_cboffset_v(u32 r)
231
+
{
232
+
return (r >> 0) & 0xffff;
233
+
}
234
+
#define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \
235
+
host1x_sync_cbstat_cboffset_v(r)
236
+
static inline u32 host1x_sync_cbstat_cbclass_v(u32 r)
237
+
{
238
+
return (r >> 16) & 0x3ff;
239
+
}
240
+
#define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \
241
+
host1x_sync_cbstat_cbclass_v(r)
242
+
243
+
#endif
+181
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
+181
drivers/gpu/host1x/hw/hw_host1x04_uclass.h
···
1
+
/*
2
+
* Copyright (c) 2013 NVIDIA Corporation.
3
+
*
4
+
* This program is free software; you can redistribute it and/or modify it
5
+
* under the terms and conditions of the GNU General Public License,
6
+
* version 2, as published by the Free Software Foundation.
7
+
*
8
+
* This program is distributed in the hope it will be useful, but WITHOUT
9
+
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10
+
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11
+
* more details.
12
+
*
13
+
* You should have received a copy of the GNU General Public License
14
+
* along with this program. If not, see <http://www.gnu.org/licenses/>.
15
+
*
16
+
*/
17
+
18
+
/*
19
+
* Function naming determines intended use:
20
+
*
21
+
* <x>_r(void) : Returns the offset for register <x>.
22
+
*
23
+
* <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24
+
*
25
+
* <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26
+
*
27
+
* <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28
+
* and masked to place it at field <y> of register <x>. This value
29
+
* can be |'d with others to produce a full register value for
30
+
* register <x>.
31
+
*
32
+
* <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33
+
* value can be ~'d and then &'d to clear the value of field <y> for
34
+
* register <x>.
35
+
*
36
+
* <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37
+
* to place it at field <y> of register <x>. This value can be |'d
38
+
* with others to produce a full register value for <x>.
39
+
*
40
+
* <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41
+
* <x> value 'r' after being shifted to place its LSB at bit 0.
42
+
* This value is suitable for direct comparison with other unshifted
43
+
* values appropriate for use in field <y> of register <x>.
44
+
*
45
+
* <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46
+
* field <y> of register <x>. This value is suitable for direct
47
+
* comparison with unshifted values appropriate for use in field <y>
48
+
* of register <x>.
49
+
*/
50
+
51
+
#ifndef HOST1X_HW_HOST1X04_UCLASS_H
52
+
#define HOST1X_HW_HOST1X04_UCLASS_H
53
+
54
+
static inline u32 host1x_uclass_incr_syncpt_r(void)
55
+
{
56
+
return 0x0;
57
+
}
58
+
#define HOST1X_UCLASS_INCR_SYNCPT \
59
+
host1x_uclass_incr_syncpt_r()
60
+
static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
61
+
{
62
+
return (v & 0xff) << 8;
63
+
}
64
+
#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
65
+
host1x_uclass_incr_syncpt_cond_f(v)
66
+
static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
67
+
{
68
+
return (v & 0xff) << 0;
69
+
}
70
+
#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
71
+
host1x_uclass_incr_syncpt_indx_f(v)
72
+
static inline u32 host1x_uclass_wait_syncpt_r(void)
73
+
{
74
+
return 0x8;
75
+
}
76
+
#define HOST1X_UCLASS_WAIT_SYNCPT \
77
+
host1x_uclass_wait_syncpt_r()
78
+
static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
79
+
{
80
+
return (v & 0xff) << 24;
81
+
}
82
+
#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
83
+
host1x_uclass_wait_syncpt_indx_f(v)
84
+
static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
85
+
{
86
+
return (v & 0xffffff) << 0;
87
+
}
88
+
#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
89
+
host1x_uclass_wait_syncpt_thresh_f(v)
90
+
static inline u32 host1x_uclass_wait_syncpt_base_r(void)
91
+
{
92
+
return 0x9;
93
+
}
94
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
95
+
host1x_uclass_wait_syncpt_base_r()
96
+
static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
97
+
{
98
+
return (v & 0xff) << 24;
99
+
}
100
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
101
+
host1x_uclass_wait_syncpt_base_indx_f(v)
102
+
static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
103
+
{
104
+
return (v & 0xff) << 16;
105
+
}
106
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
107
+
host1x_uclass_wait_syncpt_base_base_indx_f(v)
108
+
static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
109
+
{
110
+
return (v & 0xffff) << 0;
111
+
}
112
+
#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
113
+
host1x_uclass_wait_syncpt_base_offset_f(v)
114
+
static inline u32 host1x_uclass_load_syncpt_base_r(void)
115
+
{
116
+
return 0xb;
117
+
}
118
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
119
+
host1x_uclass_load_syncpt_base_r()
120
+
static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
121
+
{
122
+
return (v & 0xff) << 24;
123
+
}
124
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
125
+
host1x_uclass_load_syncpt_base_base_indx_f(v)
126
+
static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
127
+
{
128
+
return (v & 0xffffff) << 0;
129
+
}
130
+
#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
131
+
host1x_uclass_load_syncpt_base_value_f(v)
132
+
static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
133
+
{
134
+
return (v & 0xff) << 24;
135
+
}
136
+
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
137
+
host1x_uclass_incr_syncpt_base_base_indx_f(v)
138
+
static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
139
+
{
140
+
return (v & 0xffffff) << 0;
141
+
}
142
+
#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
143
+
host1x_uclass_incr_syncpt_base_offset_f(v)
144
+
static inline u32 host1x_uclass_indoff_r(void)
145
+
{
146
+
return 0x2d;
147
+
}
148
+
#define HOST1X_UCLASS_INDOFF \
149
+
host1x_uclass_indoff_r()
150
+
static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
151
+
{
152
+
return (v & 0xf) << 28;
153
+
}
154
+
#define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
155
+
host1x_uclass_indoff_indbe_f(v)
156
+
static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
157
+
{
158
+
return (v & 0x1) << 27;
159
+
}
160
+
#define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
161
+
host1x_uclass_indoff_autoinc_f(v)
162
+
static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
163
+
{
164
+
return (v & 0xff) << 18;
165
+
}
166
+
#define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
167
+
host1x_uclass_indoff_indmodid_f(v)
168
+
static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
169
+
{
170
+
return (v & 0xffff) << 2;
171
+
}
172
+
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
173
+
host1x_uclass_indoff_indroffset_f(v)
174
+
static inline u32 host1x_uclass_indoff_rwn_read_v(void)
175
+
{
176
+
return 1;
177
+
}
178
+
#define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
179
+
host1x_uclass_indoff_indroffset_f(v)
180
+
181
+
#endif