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[media] dt-bindings: Add a binding for Mediatek Video Encoder
Add a DT binding documentation of Video Encoder for the
MT8173 SoC from Mediatek.
Signed-off-by: Tiffany Lin <tiffany.lin@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
authored by
Tiffany Lin
and committed by
Mauro Carvalho Chehab
e6d28fd6
404b2819
+59
+59
Documentation/devicetree/bindings/media/mediatek-vcodec.txt
+59
Documentation/devicetree/bindings/media/mediatek-vcodec.txt
···
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Mediatek Video Codec
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Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
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supports high resolution encoding functionalities.
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Required properties:
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- compatible : "mediatek,mt8173-vcodec-enc" for encoder
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- reg : Physical base address of the video codec registers and length of
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memory mapped region.
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- interrupts : interrupt number to the cpu.
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- mediatek,larb : must contain the local arbiters in the current Socs.
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- clocks : list of clock specifiers, corresponding to entries in
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the clock-names property.
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- clock-names: encoder must contain "venc_sel_src", "venc_sel",
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- "venc_lt_sel_src", "venc_lt_sel".
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- iommus : should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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for details.
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- mediatek,vpu : the node of video processor unit
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Example:
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vcodec_enc: vcodec@0x18002000 {
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compatible = "mediatek,mt8173-vcodec-enc";
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reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
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<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
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mediatek,larb = <&larb3>,
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<&larb5>;
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iommus = <&iommu M4U_PORT_VENC_RCPU>,
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<&iommu M4U_PORT_VENC_REC>,
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<&iommu M4U_PORT_VENC_BSDMA>,
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<&iommu M4U_PORT_VENC_SV_COMV>,
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<&iommu M4U_PORT_VENC_RD_COMV>,
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<&iommu M4U_PORT_VENC_CUR_LUMA>,
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<&iommu M4U_PORT_VENC_CUR_CHROMA>,
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<&iommu M4U_PORT_VENC_REF_LUMA>,
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<&iommu M4U_PORT_VENC_REF_CHROMA>,
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<&iommu M4U_PORT_VENC_NBM_RDMA>,
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<&iommu M4U_PORT_VENC_NBM_WDMA>,
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<&iommu M4U_PORT_VENC_RCPU_SET2>,
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<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
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<&iommu M4U_PORT_VENC_BSDMA_SET2>,
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<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
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<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
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<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
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<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
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<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
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<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
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mediatek,vpu = <&vpu>;
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clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "venc_sel_src",
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"venc_sel",
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"venc_lt_sel_src",
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"venc_lt_sel";
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};