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Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: clk-u300: Add some spaces for better code readability
Use space characters at some source code places according to the
Linux coding style convention.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
authored by
Markus Elfring
and committed by
Stephen Boyd
e6b332ab
27f8a53a
+32
-32
+32
-32
drivers/clk/clk-u300.c
+32
-32
drivers/clk/clk-u300.c
···
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#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK (0x01E0)
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#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK (0x001E)
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#define U300_SYSCON_S0CCR_CLOCK_ENABLE (0x0001)
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-
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8<<1)
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-
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA<<1)
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-
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC<<1)
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#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD<<1)
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#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE<<1)
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-
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0<<1)
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#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2<<1)
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#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4<<1)
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-
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6<<1)
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+
#define U300_SYSCON_S0CCR_SEL_MCLK (0x8 << 1)
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+
#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK (0xA << 1)
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+
#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK (0xC << 1)
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+
#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK (0xD << 1)
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+
#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK (0xE << 1)
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+
#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK (0x0 << 1)
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+
#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK (0x2 << 1)
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+
#define U300_SYSCON_S0CCR_SEL_RTC_CLK (0x4 << 1)
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+
#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK (0x6 << 1)
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/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
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#define U300_SYSCON_S1CCR (0x124)
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#define U300_SYSCON_S1CCR_FIELD_MASK (0x43FF)
···
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#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK (0x01E0)
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#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK (0x001E)
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#define U300_SYSCON_S1CCR_CLOCK_ENABLE (0x0001)
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#define U300_SYSCON_S1CCR_SEL_MCLK (0x8<<1)
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-
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA<<1)
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-
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC<<1)
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-
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD<<1)
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-
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE<<1)
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-
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0<<1)
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-
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2<<1)
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-
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4<<1)
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-
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6<<1)
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+
#define U300_SYSCON_S1CCR_SEL_MCLK (0x8 << 1)
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+
#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK (0xA << 1)
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+
#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK (0xC << 1)
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+
#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK (0xD << 1)
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+
#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK (0xE << 1)
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+
#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
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+
#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK (0x2 << 1)
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+
#define U300_SYSCON_S1CCR_SEL_RTC_CLK (0x4 << 1)
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+
#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK (0x6 << 1)
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/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
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#define U300_SYSCON_S2CCR (0x128)
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#define U300_SYSCON_S2CCR_FIELD_MASK (0xC3FF)
···
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#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK (0x01E0)
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#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK (0x001E)
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#define U300_SYSCON_S2CCR_CLOCK_ENABLE (0x0001)
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-
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8<<1)
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-
#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA<<1)
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#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC<<1)
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#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD<<1)
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#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE<<1)
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#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0<<1)
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#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2<<1)
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-
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4<<1)
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-
#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6<<1)
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+
#define U300_SYSCON_S2CCR_SEL_MCLK (0x8 << 1)
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#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK (0xA << 1)
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#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK (0xC << 1)
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+
#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK (0xD << 1)
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#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK (0xE << 1)
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+
#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK (0x0 << 1)
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+
#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK (0x2 << 1)
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+
#define U300_SYSCON_S2CCR_SEL_RTC_CLK (0x4 << 1)
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#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK (0x6 << 1)
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/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
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#define U300_SYSCON_PICR (0x0130)
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#define U300_SYSCON_PICR_MASK (0x00FF)
···
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struct clk_syscon *sclk = to_syscon(hw);
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u16 perf = syscon_get_perf();
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-
switch(sclk->clk_val) {
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+
switch (sclk->clk_val) {
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case U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN:
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case U300_SYSCON_SBCER_I2C0_CLK_EN:
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case U300_SYSCON_SBCER_I2C1_CLK_EN:
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case U300_SYSCON_SBCER_MMC_CLK_EN:
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case U300_SYSCON_SBCER_SPI_CLK_EN:
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/* The FAST clocks have one progression */
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switch(perf) {
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+
switch (perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;
···
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case U300_SYSCON_SBCER_NANDIF_CLK_EN:
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case U300_SYSCON_SBCER_XGAM_CLK_EN:
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/* AMBA interconnect peripherals */
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-
switch(perf) {
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+
switch (perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 6500000;
···
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case U300_SYSCON_SBCER_SEMI_CLK_EN:
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case U300_SYSCON_SBCER_EMIF_CLK_EN:
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/* EMIF speeds */
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-
switch(perf) {
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+
switch (perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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603
case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;
···
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}
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case U300_SYSCON_SBCER_CPU_CLK_EN:
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/* And the fast CPU clock */
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-
switch(perf) {
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+
switch (perf) {
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
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case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
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return 13000000;