tjh.dev
Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: uniphier: remove sLD3 SoC support
This SoC is too old. It is difficult to maintain any longer.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
authored by
Masahiro Yamada
and committed by
Stephen Boyd
e66d57a9
8e7be401
+20
-50
-5
Documentation/devicetree/bindings/clock/uniphier-clock.txt
-5
Documentation/devicetree/bindings/clock/uniphier-clock.txt
···
6
6
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7
Required properties:
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8
- compatible: should be one of the following:
9
-
"socionext,uniphier-sld3-clock" - for sLD3 SoC.
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9
"socionext,uniphier-ld4-clock" - for LD4 SoC.
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10
"socionext,uniphier-pro4-clock" - for Pro4 SoC.
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11
"socionext,uniphier-sld8-clock" - for sLD8 SoC.
···
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Required properties:
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- compatible: should be one of the following:
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-
"socionext,uniphier-sld3-mio-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-mio-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-mio-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-mio-clock" - for sLD8 SoC.
···
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8: USB2 ch0 host
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9: USB2 ch1 host
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10: USB2 ch2 host
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-
11: USB2 ch3 host
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12: USB2 ch0 PHY
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13: USB2 ch1 PHY
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14: USB2 ch2 PHY
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-
15: USB2 ch3 PHY
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Peripheral clock
···
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Required properties:
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- compatible: should be one of the following:
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-
"socionext,uniphier-sld3-peri-clock" - for sLD3 SoC.
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"socionext,uniphier-ld4-peri-clock" - for LD4 SoC.
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"socionext,uniphier-pro4-peri-clock" - for Pro4 SoC.
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"socionext,uniphier-sld8-peri-clock" - for sLD8 SoC.
+4
-12
drivers/clk/uniphier/clk-uniphier-core.c
+4
-12
drivers/clk/uniphier/clk-uniphier-core.c
···
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111
static const struct of_device_id uniphier_clk_match[] = {
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/* System clock */
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{
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-
.compatible = "socionext,uniphier-sld3-clock",
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-
.data = uniphier_sld3_sys_clk_data,
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-
},
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-
{
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.compatible = "socionext,uniphier-ld4-clock",
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.data = uniphier_ld4_sys_clk_data,
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},
···
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},
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/* Media I/O clock, SD clock */
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{
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-
.compatible = "socionext,uniphier-sld3-mio-clock",
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-
.data = uniphier_sld3_mio_clk_data,
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-
},
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-
{
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.compatible = "socionext,uniphier-ld4-mio-clock",
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-
.data = uniphier_sld3_mio_clk_data,
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+
.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro4-mio-clock",
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-
.data = uniphier_sld3_mio_clk_data,
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+
.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-sld8-mio-clock",
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-
.data = uniphier_sld3_mio_clk_data,
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+
.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-pro5-sd-clock",
···
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},
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{
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.compatible = "socionext,uniphier-ld11-mio-clock",
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-
.data = uniphier_sld3_mio_clk_data,
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+
.data = uniphier_ld4_mio_clk_data,
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},
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{
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.compatible = "socionext,uniphier-ld20-sd-clock",
+1
-3
drivers/clk/uniphier/clk-uniphier-mio.c
+1
-3
drivers/clk/uniphier/clk-uniphier-mio.c
···
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#define UNIPHIER_MIO_CLK_DMAC(idx) \
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UNIPHIER_CLK_GATE("miodmac", (idx), "stdmac", 0x20, 25)
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-
const struct uniphier_clk_data uniphier_sld3_mio_clk_data[] = {
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+
const struct uniphier_clk_data uniphier_ld4_mio_clk_data[] = {
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UNIPHIER_MIO_CLK_SD_FIXED,
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UNIPHIER_MIO_CLK_SD(0, 0),
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UNIPHIER_MIO_CLK_SD(1, 1),
···
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UNIPHIER_MIO_CLK_USB2(8, 0),
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UNIPHIER_MIO_CLK_USB2(9, 1),
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UNIPHIER_MIO_CLK_USB2(10, 2),
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-
UNIPHIER_MIO_CLK_USB2(11, 3),
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UNIPHIER_MIO_CLK_USB2_PHY(12, 0),
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UNIPHIER_MIO_CLK_USB2_PHY(13, 1),
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UNIPHIER_MIO_CLK_USB2_PHY(14, 2),
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-
UNIPHIER_MIO_CLK_USB2_PHY(15, 3),
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{ /* sentinel */ }
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};
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+14
-28
drivers/clk/uniphier/clk-uniphier-sys.c
+14
-28
drivers/clk/uniphier/clk-uniphier-sys.c
···
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#include "clk-uniphier.h"
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-
#define UNIPHIER_SLD3_SYS_CLK_SD \
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+
#define UNIPHIER_LD4_SYS_CLK_SD \
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UNIPHIER_CLK_FACTOR("sd-200m", -1, "spll", 1, 8), \
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UNIPHIER_CLK_FACTOR("sd-133m", -1, "vpll27a", 1, 2)
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···
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UNIPHIER_CLK_FACTOR("sd-133m", -1, "spll", 1, 15)
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/* Denali driver requires clk_x rate (clk: 50MHz, clk_x & ecc_clk: 200MHz) */
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-
#define UNIPHIER_SLD3_SYS_CLK_NAND(idx) \
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+
#define UNIPHIER_LD4_SYS_CLK_NAND(idx) \
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UNIPHIER_CLK_FACTOR("nand-200m", -1, "spll", 1, 8), \
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UNIPHIER_CLK_GATE("nand", (idx), "nand-200m", 0x2104, 2)
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···
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#define UNIPHIER_LD11_SYS_CLK_EMMC(idx) \
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UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
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-
#define UNIPHIER_SLD3_SYS_CLK_STDMAC(idx) \
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+
#define UNIPHIER_LD4_SYS_CLK_STDMAC(idx) \
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UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
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#define UNIPHIER_LD11_SYS_CLK_STDMAC(idx) \
···
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#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
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UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
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-
const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
61
-
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
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-
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
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-
UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
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-
UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
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UNIPHIER_SLD3_SYS_CLK_NAND(2),
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-
UNIPHIER_SLD3_SYS_CLK_SD,
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-
UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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UNIPHIER_SLD3_SYS_CLK_STDMAC(8),
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-
{ /* sentinel */ }
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-
};
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-
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const struct uniphier_clk_data uniphier_ld4_sys_clk_data[] = {
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UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
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UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
···
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
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-
UNIPHIER_SLD3_SYS_CLK_NAND(2),
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-
UNIPHIER_SLD3_SYS_CLK_SD,
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+
UNIPHIER_LD4_SYS_CLK_NAND(2),
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+
UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
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+
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
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{ /* sentinel */ }
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};
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···
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 32),
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-
UNIPHIER_SLD3_SYS_CLK_NAND(2),
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-
UNIPHIER_SLD3_SYS_CLK_SD,
95
+
UNIPHIER_LD4_SYS_CLK_NAND(2),
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+
UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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-
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
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+
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, MIO, RLE */
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* Ether, SATA, USB3 */
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
···
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UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 270, 25), /* 270 MHz */
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UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
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110
UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 16),
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-
UNIPHIER_SLD3_SYS_CLK_NAND(2),
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-
UNIPHIER_SLD3_SYS_CLK_SD,
111
+
UNIPHIER_LD4_SYS_CLK_NAND(2),
112
+
UNIPHIER_LD4_SYS_CLK_SD,
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UNIPHIER_CLK_FACTOR("usb2", -1, "upll", 1, 12),
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-
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
114
+
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* Ether, HSC, MIO */
101
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{ /* sentinel */ }
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};
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···
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
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UNIPHIER_PRO5_SYS_CLK_NAND(2),
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UNIPHIER_PRO5_SYS_CLK_SD,
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-
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC */
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+
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC */
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UNIPHIER_PRO4_SYS_CLK_GIO(12), /* PCIe, USB3 */
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128
UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
···
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UNIPHIER_CLK_FACTOR("i2c", 1, "spll", 1, 48),
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UNIPHIER_PRO5_SYS_CLK_NAND(2),
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UNIPHIER_PRO5_SYS_CLK_SD,
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-
UNIPHIER_SLD3_SYS_CLK_STDMAC(8), /* HSC, RLE */
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+
UNIPHIER_LD4_SYS_CLK_STDMAC(8), /* HSC, RLE */
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/* GIO is always clock-enabled: no function for 0x2104 bit6 */
127
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UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
128
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UNIPHIER_PRO4_SYS_CLK_USB3(15, 1),
+1
-2
drivers/clk/uniphier/clk-uniphier.h
+1
-2
drivers/clk/uniphier/clk-uniphier.h
···
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const char *name,
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const struct uniphier_clk_mux_data *data);
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-
extern const struct uniphier_clk_data uniphier_sld3_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld4_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro4_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_sld8_sys_clk_data[];
···
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extern const struct uniphier_clk_data uniphier_pxs2_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld11_sys_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld20_sys_clk_data[];
157
-
extern const struct uniphier_clk_data uniphier_sld3_mio_clk_data[];
158
+
extern const struct uniphier_clk_data uniphier_ld4_mio_clk_data[];
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extern const struct uniphier_clk_data uniphier_pro5_sd_clk_data[];
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extern const struct uniphier_clk_data uniphier_ld4_peri_clk_data[];
160
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extern const struct uniphier_clk_data uniphier_pro4_peri_clk_data[];